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dmaengine, async_tx: add a "no channel switch" allocator
[net-next-2.6.git] / drivers / dma / dmaengine.c
CommitLineData
c13c8260
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1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21
22/*
23 * This code implements the DMA subsystem. It provides a HW-neutral interface
24 * for other kernel code to use asynchronous memory copy capabilities,
25 * if present, and allows different HW DMA drivers to register as providing
26 * this capability.
27 *
28 * Due to the fact we are accelerating what is already a relatively fast
29 * operation, the code goes to great lengths to avoid additional overhead,
30 * such as locking.
31 *
32 * LOCKING:
33 *
aa1e6f1a
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34 * The subsystem keeps a global list of dma_device structs it is protected by a
35 * mutex, dma_list_mutex.
c13c8260 36 *
f27c580c
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37 * A subsystem can get access to a channel by calling dmaengine_get() followed
38 * by dma_find_channel(), or if it has need for an exclusive channel it can call
39 * dma_request_channel(). Once a channel is allocated a reference is taken
40 * against its corresponding driver to disable removal.
41 *
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42 * Each device has a channels list, which runs unlocked but is never modified
43 * once the device is registered, it's just setup by the driver.
44 *
f27c580c 45 * See Documentation/dmaengine.txt for more details
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46 */
47
48#include <linux/init.h>
49#include <linux/module.h>
7405f74b 50#include <linux/mm.h>
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51#include <linux/device.h>
52#include <linux/dmaengine.h>
53#include <linux/hardirq.h>
54#include <linux/spinlock.h>
55#include <linux/percpu.h>
56#include <linux/rcupdate.h>
57#include <linux/mutex.h>
7405f74b 58#include <linux/jiffies.h>
2ba05622 59#include <linux/rculist.h>
864498aa 60#include <linux/idr.h>
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61
62static DEFINE_MUTEX(dma_list_mutex);
63static LIST_HEAD(dma_device_list);
6f49a57a 64static long dmaengine_ref_count;
864498aa 65static struct idr dma_idr;
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66
67/* --- sysfs implementation --- */
68
41d5e59c
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69/**
70 * dev_to_dma_chan - convert a device pointer to the its sysfs container object
71 * @dev - device node
72 *
73 * Must be called under dma_list_mutex
74 */
75static struct dma_chan *dev_to_dma_chan(struct device *dev)
76{
77 struct dma_chan_dev *chan_dev;
78
79 chan_dev = container_of(dev, typeof(*chan_dev), device);
80 return chan_dev->chan;
81}
82
891f78ea 83static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
c13c8260 84{
41d5e59c 85 struct dma_chan *chan;
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86 unsigned long count = 0;
87 int i;
41d5e59c 88 int err;
c13c8260 89
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90 mutex_lock(&dma_list_mutex);
91 chan = dev_to_dma_chan(dev);
92 if (chan) {
93 for_each_possible_cpu(i)
94 count += per_cpu_ptr(chan->local, i)->memcpy_count;
95 err = sprintf(buf, "%lu\n", count);
96 } else
97 err = -ENODEV;
98 mutex_unlock(&dma_list_mutex);
c13c8260 99
41d5e59c 100 return err;
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101}
102
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103static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
104 char *buf)
c13c8260 105{
41d5e59c 106 struct dma_chan *chan;
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107 unsigned long count = 0;
108 int i;
41d5e59c 109 int err;
c13c8260 110
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111 mutex_lock(&dma_list_mutex);
112 chan = dev_to_dma_chan(dev);
113 if (chan) {
114 for_each_possible_cpu(i)
115 count += per_cpu_ptr(chan->local, i)->bytes_transferred;
116 err = sprintf(buf, "%lu\n", count);
117 } else
118 err = -ENODEV;
119 mutex_unlock(&dma_list_mutex);
c13c8260 120
41d5e59c 121 return err;
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122}
123
891f78ea 124static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
c13c8260 125{
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126 struct dma_chan *chan;
127 int err;
c13c8260 128
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129 mutex_lock(&dma_list_mutex);
130 chan = dev_to_dma_chan(dev);
131 if (chan)
132 err = sprintf(buf, "%d\n", chan->client_count);
133 else
134 err = -ENODEV;
135 mutex_unlock(&dma_list_mutex);
136
137 return err;
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138}
139
891f78ea 140static struct device_attribute dma_attrs[] = {
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141 __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
142 __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
143 __ATTR(in_use, S_IRUGO, show_in_use, NULL),
144 __ATTR_NULL
145};
146
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147static void chan_dev_release(struct device *dev)
148{
149 struct dma_chan_dev *chan_dev;
150
151 chan_dev = container_of(dev, typeof(*chan_dev), device);
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152 if (atomic_dec_and_test(chan_dev->idr_ref)) {
153 mutex_lock(&dma_list_mutex);
154 idr_remove(&dma_idr, chan_dev->dev_id);
155 mutex_unlock(&dma_list_mutex);
156 kfree(chan_dev->idr_ref);
157 }
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158 kfree(chan_dev);
159}
160
c13c8260 161static struct class dma_devclass = {
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162 .name = "dma",
163 .dev_attrs = dma_attrs,
41d5e59c 164 .dev_release = chan_dev_release,
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165};
166
167/* --- client and device registration --- */
168
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169#define dma_device_satisfies_mask(device, mask) \
170 __dma_device_satisfies_mask((device), &(mask))
d379b01e 171static int
59b5ec21 172__dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
d379b01e
DW
173{
174 dma_cap_mask_t has;
175
59b5ec21 176 bitmap_and(has.bits, want->bits, device->cap_mask.bits,
d379b01e
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177 DMA_TX_TYPE_END);
178 return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
179}
180
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181static struct module *dma_chan_to_owner(struct dma_chan *chan)
182{
183 return chan->device->dev->driver->owner;
184}
185
186/**
187 * balance_ref_count - catch up the channel reference count
188 * @chan - channel to balance ->client_count versus dmaengine_ref_count
189 *
190 * balance_ref_count must be called under dma_list_mutex
191 */
192static void balance_ref_count(struct dma_chan *chan)
193{
194 struct module *owner = dma_chan_to_owner(chan);
195
196 while (chan->client_count < dmaengine_ref_count) {
197 __module_get(owner);
198 chan->client_count++;
199 }
200}
201
202/**
203 * dma_chan_get - try to grab a dma channel's parent driver module
204 * @chan - channel to grab
205 *
206 * Must be called under dma_list_mutex
207 */
208static int dma_chan_get(struct dma_chan *chan)
209{
210 int err = -ENODEV;
211 struct module *owner = dma_chan_to_owner(chan);
212
213 if (chan->client_count) {
214 __module_get(owner);
215 err = 0;
216 } else if (try_module_get(owner))
217 err = 0;
218
219 if (err == 0)
220 chan->client_count++;
221
222 /* allocate upon first client reference */
223 if (chan->client_count == 1 && err == 0) {
aa1e6f1a 224 int desc_cnt = chan->device->device_alloc_chan_resources(chan);
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DW
225
226 if (desc_cnt < 0) {
227 err = desc_cnt;
228 chan->client_count = 0;
229 module_put(owner);
59b5ec21 230 } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
6f49a57a
DW
231 balance_ref_count(chan);
232 }
233
234 return err;
235}
236
237/**
238 * dma_chan_put - drop a reference to a dma channel's parent driver module
239 * @chan - channel to release
240 *
241 * Must be called under dma_list_mutex
242 */
243static void dma_chan_put(struct dma_chan *chan)
244{
245 if (!chan->client_count)
246 return; /* this channel failed alloc_chan_resources */
247 chan->client_count--;
248 module_put(dma_chan_to_owner(chan));
249 if (chan->client_count == 0)
250 chan->device->device_free_chan_resources(chan);
251}
252
7405f74b
DW
253enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
254{
255 enum dma_status status;
256 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
257
258 dma_async_issue_pending(chan);
259 do {
260 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
261 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
262 printk(KERN_ERR "dma_sync_wait_timeout!\n");
263 return DMA_ERROR;
264 }
265 } while (status == DMA_IN_PROGRESS);
266
267 return status;
268}
269EXPORT_SYMBOL(dma_sync_wait);
270
bec08513
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271/**
272 * dma_cap_mask_all - enable iteration over all operation types
273 */
274static dma_cap_mask_t dma_cap_mask_all;
275
276/**
277 * dma_chan_tbl_ent - tracks channel allocations per core/operation
278 * @chan - associated channel for this entry
279 */
280struct dma_chan_tbl_ent {
281 struct dma_chan *chan;
282};
283
284/**
285 * channel_table - percpu lookup table for memory-to-memory offload providers
286 */
287static struct dma_chan_tbl_ent *channel_table[DMA_TX_TYPE_END];
288
289static int __init dma_channel_table_init(void)
290{
291 enum dma_transaction_type cap;
292 int err = 0;
293
294 bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
295
59b5ec21
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296 /* 'interrupt', 'private', and 'slave' are channel capabilities,
297 * but are not associated with an operation so they do not need
298 * an entry in the channel_table
bec08513
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299 */
300 clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
59b5ec21 301 clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
bec08513
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302 clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
303
304 for_each_dma_cap_mask(cap, dma_cap_mask_all) {
305 channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
306 if (!channel_table[cap]) {
307 err = -ENOMEM;
308 break;
309 }
310 }
311
312 if (err) {
313 pr_err("dmaengine: initialization failure\n");
314 for_each_dma_cap_mask(cap, dma_cap_mask_all)
315 if (channel_table[cap])
316 free_percpu(channel_table[cap]);
317 }
318
319 return err;
320}
652afc27 321arch_initcall(dma_channel_table_init);
bec08513
DW
322
323/**
324 * dma_find_channel - find a channel to carry out the operation
325 * @tx_type: transaction type
326 */
327struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
328{
329 struct dma_chan *chan;
330 int cpu;
331
bec08513
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332 cpu = get_cpu();
333 chan = per_cpu_ptr(channel_table[tx_type], cpu)->chan;
334 put_cpu();
335
336 return chan;
337}
338EXPORT_SYMBOL(dma_find_channel);
339
2ba05622
DW
340/**
341 * dma_issue_pending_all - flush all pending operations across all channels
342 */
343void dma_issue_pending_all(void)
344{
345 struct dma_device *device;
346 struct dma_chan *chan;
347
2ba05622 348 rcu_read_lock();
59b5ec21
DW
349 list_for_each_entry_rcu(device, &dma_device_list, global_node) {
350 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
351 continue;
2ba05622
DW
352 list_for_each_entry(chan, &device->channels, device_node)
353 if (chan->client_count)
354 device->device_issue_pending(chan);
59b5ec21 355 }
2ba05622
DW
356 rcu_read_unlock();
357}
358EXPORT_SYMBOL(dma_issue_pending_all);
359
bec08513
DW
360/**
361 * nth_chan - returns the nth channel of the given capability
362 * @cap: capability to match
363 * @n: nth channel desired
364 *
365 * Defaults to returning the channel with the desired capability and the
366 * lowest reference count when 'n' cannot be satisfied. Must be called
367 * under dma_list_mutex.
368 */
369static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
370{
371 struct dma_device *device;
372 struct dma_chan *chan;
373 struct dma_chan *ret = NULL;
374 struct dma_chan *min = NULL;
375
376 list_for_each_entry(device, &dma_device_list, global_node) {
59b5ec21
DW
377 if (!dma_has_cap(cap, device->cap_mask) ||
378 dma_has_cap(DMA_PRIVATE, device->cap_mask))
bec08513
DW
379 continue;
380 list_for_each_entry(chan, &device->channels, device_node) {
381 if (!chan->client_count)
382 continue;
383 if (!min)
384 min = chan;
385 else if (chan->table_count < min->table_count)
386 min = chan;
387
388 if (n-- == 0) {
389 ret = chan;
390 break; /* done */
391 }
392 }
393 if (ret)
394 break; /* done */
395 }
396
397 if (!ret)
398 ret = min;
399
400 if (ret)
401 ret->table_count++;
402
403 return ret;
404}
405
406/**
407 * dma_channel_rebalance - redistribute the available channels
408 *
409 * Optimize for cpu isolation (each cpu gets a dedicated channel for an
410 * operation type) in the SMP case, and operation isolation (avoid
411 * multi-tasking channels) in the non-SMP case. Must be called under
412 * dma_list_mutex.
413 */
414static void dma_channel_rebalance(void)
415{
416 struct dma_chan *chan;
417 struct dma_device *device;
418 int cpu;
419 int cap;
420 int n;
421
422 /* undo the last distribution */
423 for_each_dma_cap_mask(cap, dma_cap_mask_all)
424 for_each_possible_cpu(cpu)
425 per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
426
59b5ec21
DW
427 list_for_each_entry(device, &dma_device_list, global_node) {
428 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
429 continue;
bec08513
DW
430 list_for_each_entry(chan, &device->channels, device_node)
431 chan->table_count = 0;
59b5ec21 432 }
bec08513
DW
433
434 /* don't populate the channel_table if no clients are available */
435 if (!dmaengine_ref_count)
436 return;
437
438 /* redistribute available channels */
439 n = 0;
440 for_each_dma_cap_mask(cap, dma_cap_mask_all)
441 for_each_online_cpu(cpu) {
442 if (num_possible_cpus() > 1)
443 chan = nth_chan(cap, n++);
444 else
445 chan = nth_chan(cap, -1);
446
447 per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
448 }
449}
450
e2346677
DW
451static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
452 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
453{
454 struct dma_chan *chan;
59b5ec21
DW
455
456 if (!__dma_device_satisfies_mask(dev, mask)) {
457 pr_debug("%s: wrong capabilities\n", __func__);
458 return NULL;
459 }
460 /* devices with multiple channels need special handling as we need to
461 * ensure that all channels are either private or public.
462 */
463 if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
464 list_for_each_entry(chan, &dev->channels, device_node) {
465 /* some channels are already publicly allocated */
466 if (chan->client_count)
467 return NULL;
468 }
469
470 list_for_each_entry(chan, &dev->channels, device_node) {
471 if (chan->client_count) {
472 pr_debug("%s: %s busy\n",
41d5e59c 473 __func__, dma_chan_name(chan));
59b5ec21
DW
474 continue;
475 }
e2346677
DW
476 if (fn && !fn(chan, fn_param)) {
477 pr_debug("%s: %s filter said false\n",
478 __func__, dma_chan_name(chan));
479 continue;
480 }
481 return chan;
59b5ec21
DW
482 }
483
e2346677 484 return NULL;
59b5ec21
DW
485}
486
487/**
488 * dma_request_channel - try to allocate an exclusive channel
489 * @mask: capabilities that the channel must satisfy
490 * @fn: optional callback to disposition available channels
491 * @fn_param: opaque parameter to pass to dma_filter_fn
492 */
493struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
494{
495 struct dma_device *device, *_d;
496 struct dma_chan *chan = NULL;
59b5ec21
DW
497 int err;
498
499 /* Find a channel */
500 mutex_lock(&dma_list_mutex);
501 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
e2346677
DW
502 chan = private_candidate(mask, device, fn, fn_param);
503 if (chan) {
59b5ec21
DW
504 /* Found a suitable channel, try to grab, prep, and
505 * return it. We first set DMA_PRIVATE to disable
506 * balance_ref_count as this channel will not be
507 * published in the general-purpose allocator
508 */
509 dma_cap_set(DMA_PRIVATE, device->cap_mask);
0f571515 510 device->privatecnt++;
59b5ec21
DW
511 err = dma_chan_get(chan);
512
513 if (err == -ENODEV) {
514 pr_debug("%s: %s module removed\n", __func__,
41d5e59c 515 dma_chan_name(chan));
59b5ec21
DW
516 list_del_rcu(&device->global_node);
517 } else if (err)
518 pr_err("dmaengine: failed to get %s: (%d)\n",
41d5e59c 519 dma_chan_name(chan), err);
59b5ec21
DW
520 else
521 break;
0f571515
AN
522 if (--device->privatecnt == 0)
523 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
287d8592 524 chan->private = NULL;
e2346677
DW
525 chan = NULL;
526 }
59b5ec21
DW
527 }
528 mutex_unlock(&dma_list_mutex);
529
530 pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
41d5e59c 531 chan ? dma_chan_name(chan) : NULL);
59b5ec21
DW
532
533 return chan;
534}
535EXPORT_SYMBOL_GPL(__dma_request_channel);
536
537void dma_release_channel(struct dma_chan *chan)
538{
539 mutex_lock(&dma_list_mutex);
540 WARN_ONCE(chan->client_count != 1,
541 "chan reference count %d != 1\n", chan->client_count);
542 dma_chan_put(chan);
0f571515
AN
543 /* drop PRIVATE cap enabled by __dma_request_channel() */
544 if (--chan->device->privatecnt == 0)
545 dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
287d8592 546 chan->private = NULL;
59b5ec21
DW
547 mutex_unlock(&dma_list_mutex);
548}
549EXPORT_SYMBOL_GPL(dma_release_channel);
550
d379b01e 551/**
209b84a8 552 * dmaengine_get - register interest in dma_channels
d379b01e 553 */
209b84a8 554void dmaengine_get(void)
d379b01e 555{
6f49a57a
DW
556 struct dma_device *device, *_d;
557 struct dma_chan *chan;
558 int err;
559
c13c8260 560 mutex_lock(&dma_list_mutex);
6f49a57a
DW
561 dmaengine_ref_count++;
562
563 /* try to grab channels */
59b5ec21
DW
564 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
565 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
566 continue;
6f49a57a
DW
567 list_for_each_entry(chan, &device->channels, device_node) {
568 err = dma_chan_get(chan);
569 if (err == -ENODEV) {
570 /* module removed before we could use it */
2ba05622 571 list_del_rcu(&device->global_node);
6f49a57a
DW
572 break;
573 } else if (err)
574 pr_err("dmaengine: failed to get %s: (%d)\n",
41d5e59c 575 dma_chan_name(chan), err);
6f49a57a 576 }
59b5ec21 577 }
6f49a57a 578
bec08513
DW
579 /* if this is the first reference and there were channels
580 * waiting we need to rebalance to get those channels
581 * incorporated into the channel table
582 */
583 if (dmaengine_ref_count == 1)
584 dma_channel_rebalance();
c13c8260 585 mutex_unlock(&dma_list_mutex);
c13c8260 586}
209b84a8 587EXPORT_SYMBOL(dmaengine_get);
c13c8260
CL
588
589/**
209b84a8 590 * dmaengine_put - let dma drivers be removed when ref_count == 0
c13c8260 591 */
209b84a8 592void dmaengine_put(void)
c13c8260 593{
d379b01e 594 struct dma_device *device;
c13c8260
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595 struct dma_chan *chan;
596
c13c8260 597 mutex_lock(&dma_list_mutex);
6f49a57a
DW
598 dmaengine_ref_count--;
599 BUG_ON(dmaengine_ref_count < 0);
600 /* drop channel references */
59b5ec21
DW
601 list_for_each_entry(device, &dma_device_list, global_node) {
602 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
603 continue;
6f49a57a
DW
604 list_for_each_entry(chan, &device->channels, device_node)
605 dma_chan_put(chan);
59b5ec21 606 }
c13c8260 607 mutex_unlock(&dma_list_mutex);
c13c8260 608}
209b84a8 609EXPORT_SYMBOL(dmaengine_put);
c13c8260 610
138f4c35
DW
611static bool device_has_all_tx_types(struct dma_device *device)
612{
613 /* A device that satisfies this test has channels that will never cause
614 * an async_tx channel switch event as all possible operation types can
615 * be handled.
616 */
617 #ifdef CONFIG_ASYNC_TX_DMA
618 if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
619 return false;
620 #endif
621
622 #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
623 if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
624 return false;
625 #endif
626
627 #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
628 if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
629 return false;
630 #endif
631
632 #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
633 if (!dma_has_cap(DMA_XOR, device->cap_mask))
634 return false;
635 #endif
636
637 #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
638 if (!dma_has_cap(DMA_PQ, device->cap_mask))
639 return false;
640 #endif
641
642 return true;
643}
644
257b17ca
DW
645static int get_dma_id(struct dma_device *device)
646{
647 int rc;
648
649 idr_retry:
650 if (!idr_pre_get(&dma_idr, GFP_KERNEL))
651 return -ENOMEM;
652 mutex_lock(&dma_list_mutex);
653 rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
654 mutex_unlock(&dma_list_mutex);
655 if (rc == -EAGAIN)
656 goto idr_retry;
657 else if (rc != 0)
658 return rc;
659
660 return 0;
661}
662
c13c8260 663/**
6508871e 664 * dma_async_device_register - registers DMA devices found
c13c8260
CL
665 * @device: &dma_device
666 */
667int dma_async_device_register(struct dma_device *device)
668{
ff487fb7 669 int chancnt = 0, rc;
c13c8260 670 struct dma_chan* chan;
864498aa 671 atomic_t *idr_ref;
c13c8260
CL
672
673 if (!device)
674 return -ENODEV;
675
7405f74b
DW
676 /* validate device routines */
677 BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
678 !device->device_prep_dma_memcpy);
679 BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
680 !device->device_prep_dma_xor);
099f53cb
DW
681 BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
682 !device->device_prep_dma_xor_val);
b2f46fd8
DW
683 BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
684 !device->device_prep_dma_pq);
685 BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
686 !device->device_prep_dma_pq_val);
7405f74b
DW
687 BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
688 !device->device_prep_dma_memset);
9b941c66 689 BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
7405f74b 690 !device->device_prep_dma_interrupt);
dc0ee643
HS
691 BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
692 !device->device_prep_slave_sg);
693 BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
694 !device->device_terminate_all);
7405f74b
DW
695
696 BUG_ON(!device->device_alloc_chan_resources);
697 BUG_ON(!device->device_free_chan_resources);
7405f74b
DW
698 BUG_ON(!device->device_is_tx_complete);
699 BUG_ON(!device->device_issue_pending);
700 BUG_ON(!device->dev);
701
138f4c35
DW
702 /* note: this only matters in the
703 * CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH=y case
704 */
705 if (device_has_all_tx_types(device))
706 dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
707
864498aa
DW
708 idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
709 if (!idr_ref)
710 return -ENOMEM;
257b17ca
DW
711 rc = get_dma_id(device);
712 if (rc != 0) {
713 kfree(idr_ref);
864498aa 714 return rc;
257b17ca
DW
715 }
716
717 atomic_set(idr_ref, 0);
c13c8260
CL
718
719 /* represent channels in sysfs. Probably want devs too */
720 list_for_each_entry(chan, &device->channels, device_node) {
257b17ca 721 rc = -ENOMEM;
c13c8260
CL
722 chan->local = alloc_percpu(typeof(*chan->local));
723 if (chan->local == NULL)
257b17ca 724 goto err_out;
41d5e59c
DW
725 chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
726 if (chan->dev == NULL) {
727 free_percpu(chan->local);
257b17ca
DW
728 chan->local = NULL;
729 goto err_out;
41d5e59c 730 }
c13c8260
CL
731
732 chan->chan_id = chancnt++;
41d5e59c
DW
733 chan->dev->device.class = &dma_devclass;
734 chan->dev->device.parent = device->dev;
735 chan->dev->chan = chan;
864498aa
DW
736 chan->dev->idr_ref = idr_ref;
737 chan->dev->dev_id = device->dev_id;
738 atomic_inc(idr_ref);
41d5e59c 739 dev_set_name(&chan->dev->device, "dma%dchan%d",
06190d84 740 device->dev_id, chan->chan_id);
c13c8260 741
41d5e59c 742 rc = device_register(&chan->dev->device);
ff487fb7 743 if (rc) {
ff487fb7
JG
744 free_percpu(chan->local);
745 chan->local = NULL;
257b17ca
DW
746 kfree(chan->dev);
747 atomic_dec(idr_ref);
ff487fb7
JG
748 goto err_out;
749 }
7cc5bf9a 750 chan->client_count = 0;
c13c8260 751 }
59b5ec21 752 device->chancnt = chancnt;
c13c8260
CL
753
754 mutex_lock(&dma_list_mutex);
59b5ec21
DW
755 /* take references on public channels */
756 if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
6f49a57a
DW
757 list_for_each_entry(chan, &device->channels, device_node) {
758 /* if clients are already waiting for channels we need
759 * to take references on their behalf
760 */
761 if (dma_chan_get(chan) == -ENODEV) {
762 /* note we can only get here for the first
763 * channel as the remaining channels are
764 * guaranteed to get a reference
765 */
766 rc = -ENODEV;
767 mutex_unlock(&dma_list_mutex);
768 goto err_out;
769 }
770 }
2ba05622 771 list_add_tail_rcu(&device->global_node, &dma_device_list);
0f571515
AN
772 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
773 device->privatecnt++; /* Always private */
bec08513 774 dma_channel_rebalance();
c13c8260
CL
775 mutex_unlock(&dma_list_mutex);
776
c13c8260 777 return 0;
ff487fb7
JG
778
779err_out:
257b17ca
DW
780 /* if we never registered a channel just release the idr */
781 if (atomic_read(idr_ref) == 0) {
782 mutex_lock(&dma_list_mutex);
783 idr_remove(&dma_idr, device->dev_id);
784 mutex_unlock(&dma_list_mutex);
785 kfree(idr_ref);
786 return rc;
787 }
788
ff487fb7
JG
789 list_for_each_entry(chan, &device->channels, device_node) {
790 if (chan->local == NULL)
791 continue;
41d5e59c
DW
792 mutex_lock(&dma_list_mutex);
793 chan->dev->chan = NULL;
794 mutex_unlock(&dma_list_mutex);
795 device_unregister(&chan->dev->device);
ff487fb7
JG
796 free_percpu(chan->local);
797 }
798 return rc;
c13c8260 799}
765e3d8a 800EXPORT_SYMBOL(dma_async_device_register);
c13c8260 801
6508871e 802/**
6f49a57a 803 * dma_async_device_unregister - unregister a DMA device
6508871e 804 * @device: &dma_device
f27c580c
DW
805 *
806 * This routine is called by dma driver exit routines, dmaengine holds module
807 * references to prevent it being called while channels are in use.
6508871e
RD
808 */
809void dma_async_device_unregister(struct dma_device *device)
c13c8260
CL
810{
811 struct dma_chan *chan;
c13c8260
CL
812
813 mutex_lock(&dma_list_mutex);
2ba05622 814 list_del_rcu(&device->global_node);
bec08513 815 dma_channel_rebalance();
c13c8260
CL
816 mutex_unlock(&dma_list_mutex);
817
818 list_for_each_entry(chan, &device->channels, device_node) {
6f49a57a
DW
819 WARN_ONCE(chan->client_count,
820 "%s called while %d clients hold a reference\n",
821 __func__, chan->client_count);
41d5e59c
DW
822 mutex_lock(&dma_list_mutex);
823 chan->dev->chan = NULL;
824 mutex_unlock(&dma_list_mutex);
825 device_unregister(&chan->dev->device);
c13c8260 826 }
c13c8260 827}
765e3d8a 828EXPORT_SYMBOL(dma_async_device_unregister);
c13c8260 829
7405f74b
DW
830/**
831 * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
832 * @chan: DMA channel to offload copy to
833 * @dest: destination address (virtual)
834 * @src: source address (virtual)
835 * @len: length
836 *
837 * Both @dest and @src must be mappable to a bus address according to the
838 * DMA mapping API rules for streaming mappings.
839 * Both @dest and @src must stay memory resident (kernel memory or locked
840 * user space pages).
841 */
842dma_cookie_t
843dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
844 void *src, size_t len)
845{
846 struct dma_device *dev = chan->device;
847 struct dma_async_tx_descriptor *tx;
0036731c 848 dma_addr_t dma_dest, dma_src;
7405f74b
DW
849 dma_cookie_t cookie;
850 int cpu;
4f005dbe 851 unsigned long flags;
7405f74b 852
0036731c
DW
853 dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
854 dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
4f005dbe
MS
855 flags = DMA_CTRL_ACK |
856 DMA_COMPL_SRC_UNMAP_SINGLE |
857 DMA_COMPL_DEST_UNMAP_SINGLE;
858 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
0036731c
DW
859
860 if (!tx) {
861 dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
862 dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 863 return -ENOMEM;
0036731c 864 }
7405f74b 865
7405f74b 866 tx->callback = NULL;
7405f74b
DW
867 cookie = tx->tx_submit(tx);
868
869 cpu = get_cpu();
870 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
871 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
872 put_cpu();
873
874 return cookie;
875}
876EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
877
878/**
879 * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
880 * @chan: DMA channel to offload copy to
881 * @page: destination page
882 * @offset: offset in page to copy to
883 * @kdata: source address (virtual)
884 * @len: length
885 *
886 * Both @page/@offset and @kdata must be mappable to a bus address according
887 * to the DMA mapping API rules for streaming mappings.
888 * Both @page/@offset and @kdata must stay memory resident (kernel memory or
889 * locked user space pages)
890 */
891dma_cookie_t
892dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
893 unsigned int offset, void *kdata, size_t len)
894{
895 struct dma_device *dev = chan->device;
896 struct dma_async_tx_descriptor *tx;
0036731c 897 dma_addr_t dma_dest, dma_src;
7405f74b
DW
898 dma_cookie_t cookie;
899 int cpu;
4f005dbe 900 unsigned long flags;
7405f74b 901
0036731c
DW
902 dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
903 dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
4f005dbe
MS
904 flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
905 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
0036731c
DW
906
907 if (!tx) {
908 dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
909 dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 910 return -ENOMEM;
0036731c 911 }
7405f74b 912
7405f74b 913 tx->callback = NULL;
7405f74b
DW
914 cookie = tx->tx_submit(tx);
915
916 cpu = get_cpu();
917 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
918 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
919 put_cpu();
920
921 return cookie;
922}
923EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
924
925/**
926 * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
927 * @chan: DMA channel to offload copy to
928 * @dest_pg: destination page
929 * @dest_off: offset in page to copy to
930 * @src_pg: source page
931 * @src_off: offset in page to copy from
932 * @len: length
933 *
934 * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
935 * address according to the DMA mapping API rules for streaming mappings.
936 * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
937 * (kernel memory or locked user space pages).
938 */
939dma_cookie_t
940dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
941 unsigned int dest_off, struct page *src_pg, unsigned int src_off,
942 size_t len)
943{
944 struct dma_device *dev = chan->device;
945 struct dma_async_tx_descriptor *tx;
0036731c 946 dma_addr_t dma_dest, dma_src;
7405f74b
DW
947 dma_cookie_t cookie;
948 int cpu;
4f005dbe 949 unsigned long flags;
7405f74b 950
0036731c
DW
951 dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
952 dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
953 DMA_FROM_DEVICE);
4f005dbe
MS
954 flags = DMA_CTRL_ACK;
955 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
0036731c
DW
956
957 if (!tx) {
958 dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
959 dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 960 return -ENOMEM;
0036731c 961 }
7405f74b 962
7405f74b 963 tx->callback = NULL;
7405f74b
DW
964 cookie = tx->tx_submit(tx);
965
966 cpu = get_cpu();
967 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
968 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
969 put_cpu();
970
971 return cookie;
972}
973EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
974
975void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
976 struct dma_chan *chan)
977{
978 tx->chan = chan;
979 spin_lock_init(&tx->lock);
ccccce22 980 INIT_LIST_HEAD(&tx->tx_list);
7405f74b
DW
981}
982EXPORT_SYMBOL(dma_async_tx_descriptor_init);
983
07f2211e
DW
984/* dma_wait_for_async_tx - spin wait for a transaction to complete
985 * @tx: in-flight transaction to wait on
07f2211e
DW
986 */
987enum dma_status
988dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
989{
95475e57 990 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
07f2211e
DW
991
992 if (!tx)
993 return DMA_SUCCESS;
994
95475e57
DW
995 while (tx->cookie == -EBUSY) {
996 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
997 pr_err("%s timeout waiting for descriptor submission\n",
998 __func__);
999 return DMA_ERROR;
1000 }
1001 cpu_relax();
1002 }
1003 return dma_sync_wait(tx->chan, tx->cookie);
07f2211e
DW
1004}
1005EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
1006
1007/* dma_run_dependencies - helper routine for dma drivers to process
1008 * (start) dependent operations on their target channel
1009 * @tx: transaction with dependencies
1010 */
1011void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
1012{
1013 struct dma_async_tx_descriptor *dep = tx->next;
1014 struct dma_async_tx_descriptor *dep_next;
1015 struct dma_chan *chan;
1016
1017 if (!dep)
1018 return;
1019
dd59b853
YT
1020 /* we'll submit tx->next now, so clear the link */
1021 tx->next = NULL;
07f2211e
DW
1022 chan = dep->chan;
1023
1024 /* keep submitting up until a channel switch is detected
1025 * in that case we will be called again as a result of
1026 * processing the interrupt from async_tx_channel_switch
1027 */
1028 for (; dep; dep = dep_next) {
1029 spin_lock_bh(&dep->lock);
1030 dep->parent = NULL;
1031 dep_next = dep->next;
1032 if (dep_next && dep_next->chan == chan)
1033 dep->next = NULL; /* ->next will be submitted */
1034 else
1035 dep_next = NULL; /* submit current dep and terminate */
1036 spin_unlock_bh(&dep->lock);
1037
1038 dep->tx_submit(dep);
1039 }
1040
1041 chan->device->device_issue_pending(chan);
1042}
1043EXPORT_SYMBOL_GPL(dma_run_dependencies);
1044
c13c8260
CL
1045static int __init dma_bus_init(void)
1046{
864498aa 1047 idr_init(&dma_idr);
c13c8260
CL
1048 mutex_init(&dma_list_mutex);
1049 return class_register(&dma_devclass);
1050}
652afc27 1051arch_initcall(dma_bus_init);
c13c8260 1052
bec08513 1053