[net-next-2.6.git] / drivers / clocksource / acpi_pm.c

/*
 * linux/drivers/clocksource/acpi_pm.c
 *
 * This file contains the ACPI PM based clocksource.
 *
 * This code was largely moved from the i386 timer_pm.c file
 * which was (C) Dominik Brodowski <linux@brodo.de> 2003
 * and contained the following comments:
 *
 * Driver to use the Power Management Timer (PMTMR) available in some
 * southbridges as primary timing source for the Linux kernel.
 *
 * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
 * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
 *
 * This file is licensed under the GPL v2.
 */

#include <linux/acpi_pmtmr.h>
#include <linux/clocksource.h>
#include <linux/timex.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <asm/io.h>

/*
 * The I/O port the PMTMR resides at.
 * The location is detected during setup_arch(),
 * in arch/i386/kernel/acpi/boot.c
 */
u32 pmtmr_ioport __read_mostly;

static inline u32 read_pmtmr(void)
{
	/* mask the output to 24 bits */
	return inl(pmtmr_ioport) & ACPI_PM_MASK;
}

u32 acpi_pm_read_verified(void)
{
	u32 v1 = 0, v2 = 0, v3 = 0;

	/*
	 * It has been reported that because of various broken
	 * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
	 * source is not latched, you must read it multiple
	 * times to ensure a safe value is read:
	 */
	do {
		v1 = read_pmtmr();
		v2 = read_pmtmr();
		v3 = read_pmtmr();
	} while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
			  || (v3 > v1 && v3 < v2)));

	return v2;
}

static cycle_t acpi_pm_read(struct clocksource *cs)
{
	return (cycle_t)read_pmtmr();
}

static struct clocksource clocksource_acpi_pm = {
	.name		= "acpi_pm",
	.rating		= 200,
	.read		= acpi_pm_read,
	.mask		= (cycle_t)ACPI_PM_MASK,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};


#ifdef CONFIG_PCI
static int __devinitdata acpi_pm_good;
static int __init acpi_pm_good_setup(char *__str)
{
	acpi_pm_good = 1;
	return 1;
}
__setup("acpi_pm_good", acpi_pm_good_setup);

static cycle_t acpi_pm_read_slow(struct clocksource *cs)
{
	return (cycle_t)acpi_pm_read_verified();
}

static inline void acpi_pm_need_workaround(void)
{
	clocksource_acpi_pm.read = acpi_pm_read_slow;
	clocksource_acpi_pm.rating = 120;
}

/*
 * PIIX4 Errata:
 *
 * The power management timer may return improper results when read.
 * Although the timer value settles properly after incrementing,
 * while incrementing there is a 3 ns window every 69.8 ns where the
 * timer value is indeterminate (a 4.2% chance that the data will be
 * incorrect when read). As a result, the ACPI free running count up
 * timer specification is violated due to erroneous reads.
 */
static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
{
	if (acpi_pm_good)
		return;

	/* the bug has been fixed in PIIX4M */
	if (dev->revision < 3) {
		printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
		       " Due to workarounds for a bug,\n"
		       "* this clock source is slow. Consider trying"
		       " other clock sources\n");

		acpi_pm_need_workaround();
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
			acpi_pm_check_blacklist);

static void __devinit acpi_pm_check_graylist(struct pci_dev *dev)
{
	if (acpi_pm_good)
		return;

	printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to"
	       " workarounds for a bug,\n"
	       "* this clock source is slow. If you are sure your timer"
	       " does not have\n"
	       "* this bug, please use \"acpi_pm_good\" to disable the"
	       " workaround\n");

	acpi_pm_need_workaround();
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
			acpi_pm_check_graylist);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
			acpi_pm_check_graylist);
#endif

#ifndef CONFIG_X86_64
#include <asm/mach_timer.h>
#define PMTMR_EXPECTED_RATE \
  ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
/*
 * Some boards have the PMTMR running way too fast. We check
 * the PMTMR rate against PIT channel 2 to catch these cases.
 */
static int verify_pmtmr_rate(void)
{
	cycle_t value1, value2;
	unsigned long count, delta;

	mach_prepare_counter();
	value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
	mach_countup(&count);
	value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
	delta = (value2 - value1) & ACPI_PM_MASK;

	/* Check that the PMTMR delta is within 5% of what we expect */
	if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 ||
	    delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
		printk(KERN_INFO "PM-Timer running at invalid rate: %lu%% "
			"of normal - aborting.\n",
			100UL * delta / PMTMR_EXPECTED_RATE);
		return -1;
	}

	return 0;
}
#else
#define verify_pmtmr_rate() (0)
#endif

/* Number of monotonicity checks to perform during initialization */
#define ACPI_PM_MONOTONICITY_CHECKS 10
/* Number of reads we try to get two different values */
#define ACPI_PM_READ_CHECKS 10000

static int __init init_acpi_pm_clocksource(void)
{
	cycle_t value1, value2;
	unsigned int i, j = 0;

	if (!pmtmr_ioport)
		return -ENODEV;

	/* "verify" this timing source: */
	for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
		udelay(100 * j);
		value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
		for (i = 0; i < ACPI_PM_READ_CHECKS; i++) {
			value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
			if (value2 == value1)
				continue;
			if (value2 > value1)
				break;
			if ((value2 < value1) && ((value2) < 0xFFF))
				break;
			printk(KERN_INFO "PM-Timer had inconsistent results:"
			       " 0x%#llx, 0x%#llx - aborting.\n",
			       value1, value2);
			return -EINVAL;
		}
		if (i == ACPI_PM_READ_CHECKS) {
			printk(KERN_INFO "PM-Timer failed consistency check "
			       " (0x%#llx) - aborting.\n", value1);
			return -ENODEV;
		}
	}

	if (verify_pmtmr_rate() != 0)
		return -ENODEV;

	return clocksource_register_hz(&clocksource_acpi_pm,
						PMTMR_TICKS_PER_SEC);
}

/* We use fs_initcall because we want the PCI fixups to have run
 * but we still need to load before device_initcall
 */
fs_initcall(init_acpi_pm_clocksource);

/*
 * Allow an override of the IOPort. Stupid BIOSes do not tell us about
 * the PMTimer, but we might know where it is.
 */
static int __init parse_pmtmr(char *arg)
{
	unsigned long base;

	if (strict_strtoul(arg, 16, &base))
		return -EINVAL;
#ifdef CONFIG_X86_64
	if (base > UINT_MAX)
		return -ERANGE;
#endif
	printk(KERN_INFO "PMTMR IOPort override: 0x%04x -> 0x%04lx\n",
	       pmtmr_ioport, base);
	pmtmr_ioport = base;

	return 1;
}
__setup("pmtmr=", parse_pmtmr);
Commit	Line	Data
5d0cf410 JS	1	/*
	2	* linux/drivers/clocksource/acpi_pm.c
	3	*
	4	* This file contains the ACPI PM based clocksource.
	5	*
	6	* This code was largely moved from the i386 timer_pm.c file
	7	* which was (C) Dominik Brodowski <linux@brodo.de> 2003
	8	* and contained the following comments:
	9	*
	10	* Driver to use the Power Management Timer (PMTMR) available in some
	11	* southbridges as primary timing source for the Linux kernel.
	12	*
	13	* Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
	14	* timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
	15	*
	16	* This file is licensed under the GPL v2.
	17	*/
	18
d66bea57	19	#include <linux/acpi_pmtmr.h>
5d0cf410	20	#include <linux/clocksource.h>
08604bd9	21	#include <linux/timex.h>
5d0cf410 JS	22	#include <linux/errno.h>
	23	#include <linux/init.h>
	24	#include <linux/pci.h>
4ab6a219	25	#include <linux/delay.h>
5d0cf410 JS	26	#include <asm/io.h>
5d0cf410 JS	27
5d0cf410 JS	28	/*
	29	* The I/O port the PMTMR resides at.
	30	* The location is detected during setup_arch(),
8ce8e2f9	31	* in arch/i386/kernel/acpi/boot.c
5d0cf410	32	*/
7d622d47	33	u32 pmtmr_ioport __read_mostly;
5d0cf410	34
5d0cf410 JS	35	static inline u32 read_pmtmr(void)
	36	{
	37	/* mask the output to 24 bits */
	38	return inl(pmtmr_ioport) & ACPI_PM_MASK;
	39	}
	40
d66bea57	41	u32 acpi_pm_read_verified(void)
5d0cf410 JS	42	{
	43	u32 v1 = 0, v2 = 0, v3 = 0;
	44
	45	/*
	46	* It has been reported that because of various broken
	47	* chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
7d622d47	48	* source is not latched, you must read it multiple
5d0cf410 JS	49	* times to ensure a safe value is read:
	50	*/
	51	do {
	52	v1 = read_pmtmr();
	53	v2 = read_pmtmr();
	54	v3 = read_pmtmr();
78f32668 DW	55	} while (unlikely((v1 > v2 && v1 < v3) \|\| (v2 > v3 && v2 < v1)
78f32668 DW	56	\|\| (v3 > v1 && v3 < v2)));
5d0cf410	57
d66bea57 TG	58	return v2;
	59	}
	60
8e19608e	61	static cycle_t acpi_pm_read(struct clocksource *cs)
5d0cf410 JS	62	{
	63	return (cycle_t)read_pmtmr();
	64	}
	65
	66	static struct clocksource clocksource_acpi_pm = {
	67	.name = "acpi_pm",
	68	.rating = 200,
	69	.read = acpi_pm_read,
	70	.mask = (cycle_t)ACPI_PM_MASK,
73b08d2a	71	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
5d0cf410 JS	72	};
	73
	74
	75	#ifdef CONFIG_PCI
f5f1a24a	76	static int __devinitdata acpi_pm_good;
5d0cf410 JS	77	static int __init acpi_pm_good_setup(char *__str)
5d0cf410 JS	78	{
f5f1a24a DW	79	acpi_pm_good = 1;
f5f1a24a DW	80	return 1;
5d0cf410 JS	81	}
	82	__setup("acpi_pm_good", acpi_pm_good_setup);
	83
8e19608e	84	static cycle_t acpi_pm_read_slow(struct clocksource *cs)
0a57b783 BH	85	{
	86	return (cycle_t)acpi_pm_read_verified();
	87	}
	88
5d0cf410 JS	89	static inline void acpi_pm_need_workaround(void)
5d0cf410 JS	90	{
d66bea57	91	clocksource_acpi_pm.read = acpi_pm_read_slow;
1ff100d7	92	clocksource_acpi_pm.rating = 120;
5d0cf410 JS	93	}
	94
	95	/*
	96	* PIIX4 Errata:
	97	*
	98	* The power management timer may return improper results when read.
	99	* Although the timer value settles properly after incrementing,
	100	* while incrementing there is a 3 ns window every 69.8 ns where the
	101	* timer value is indeterminate (a 4.2% chance that the data will be
	102	* incorrect when read). As a result, the ACPI free running count up
	103	* timer specification is violated due to erroneous reads.
	104	*/
	105	static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
	106	{
5d0cf410 JS	107	if (acpi_pm_good)
	108	return;
	109
5d0cf410	110	/* the bug has been fixed in PIIX4M */
44c10138	111	if (dev->revision < 3) {
5d0cf410 JS	112	printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
	113	" Due to workarounds for a bug,\n"
	114	"* this clock source is slow. Consider trying"
	115	" other clock sources\n");
	116
	117	acpi_pm_need_workaround();
	118	}
	119	}
	120	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
	121	acpi_pm_check_blacklist);
	122
	123	static void __devinit acpi_pm_check_graylist(struct pci_dev *dev)
	124	{
	125	if (acpi_pm_good)
	126	return;
	127
	128	printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to"
	129	" workarounds for a bug,\n"
	130	"* this clock source is slow. If you are sure your timer"
	131	" does not have\n"
	132	"* this bug, please use \"acpi_pm_good\" to disable the"
	133	" workaround\n");
	134
	135	acpi_pm_need_workaround();
	136	}
	137	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
	138	acpi_pm_check_graylist);
78f32668 DW	139	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
78f32668 DW	140	acpi_pm_check_graylist);
5d0cf410 JS	141	#endif
5d0cf410 JS	142
562f9c57	143	#ifndef CONFIG_X86_64
1164dd00	144	#include <asm/mach_timer.h>
562f9c57 JS	145	#define PMTMR_EXPECTED_RATE \
	146	((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
	147	/*
	148	* Some boards have the PMTMR running way too fast. We check
	149	* the PMTMR rate against PIT channel 2 to catch these cases.
	150	*/
	151	static int verify_pmtmr_rate(void)
	152	{
dfdf748a	153	cycle_t value1, value2;
562f9c57 JS	154	unsigned long count, delta;
	155
	156	mach_prepare_counter();
8e19608e	157	value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
562f9c57	158	mach_countup(&count);
8e19608e	159	value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
562f9c57 JS	160	delta = (value2 - value1) & ACPI_PM_MASK;
	161
	162	/* Check that the PMTMR delta is within 5% of what we expect */
	163	if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 \|\|
	164	delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
	165	printk(KERN_INFO "PM-Timer running at invalid rate: %lu%% "
	166	"of normal - aborting.\n",
	167	100UL * delta / PMTMR_EXPECTED_RATE);
	168	return -1;
	169	}
	170
	171	return 0;
	172	}
	173	#else
	174	#define verify_pmtmr_rate() (0)
	175	#endif
5d0cf410	176
4ab6a219 DB	177	/* Number of monotonicity checks to perform during initialization */
4ab6a219 DB	178	#define ACPI_PM_MONOTONICITY_CHECKS 10
f1926ce6 DB	179	/* Number of reads we try to get two different values */
f1926ce6 DB	180	#define ACPI_PM_READ_CHECKS 10000
4ab6a219	181
5d0cf410 JS	182	static int __init init_acpi_pm_clocksource(void)
5d0cf410 JS	183	{
dfdf748a	184	cycle_t value1, value2;
f1926ce6	185	unsigned int i, j = 0;
5d0cf410 JS	186
	187	if (!pmtmr_ioport)
	188	return -ENODEV;
	189
5d0cf410	190	/* "verify" this timing source: */
4ab6a219	191	for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
f1926ce6	192	udelay(100 * j);
8e19608e	193	value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
f1926ce6	194	for (i = 0; i < ACPI_PM_READ_CHECKS; i++) {
8e19608e	195	value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
4ab6a219 DB	196	if (value2 == value1)
	197	continue;
	198	if (value2 > value1)
4ab6a219 DB	199	break;
4ab6a219 DB	200	if ((value2 < value1) && ((value2) < 0xFFF))
4ab6a219 DB	201	break;
	202	printk(KERN_INFO "PM-Timer had inconsistent results:"
	203	" 0x%#llx, 0x%#llx - aborting.\n",
	204	value1, value2);
	205	return -EINVAL;
	206	}
f1926ce6 DB	207	if (i == ACPI_PM_READ_CHECKS) {
	208	printk(KERN_INFO "PM-Timer failed consistency check "
	209	" (0x%#llx) - aborting.\n", value1);
	210	return -ENODEV;
	211	}
5d0cf410	212	}
5d0cf410	213
562f9c57 JS	214	if (verify_pmtmr_rate() != 0)
	215	return -ENODEV;
	216
f12a15be JS	217	return clocksource_register_hz(&clocksource_acpi_pm,
f12a15be JS	218	PMTMR_TICKS_PER_SEC);
5d0cf410 JS	219	}
5d0cf410 JS	220
6bb74df4 JS	221	/* We use fs_initcall because we want the PCI fixups to have run
	222	* but we still need to load before device_initcall
	223	*/
	224	fs_initcall(init_acpi_pm_clocksource);
6b148507 TG	225
	226	/*
	227	* Allow an override of the IOPort. Stupid BIOSes do not tell us about
	228	* the PMTimer, but we might know where it is.
	229	*/
	230	static int __init parse_pmtmr(char *arg)
	231	{
	232	unsigned long base;
	233
	234	if (strict_strtoul(arg, 16, &base))
	235	return -EINVAL;
ee974e01 DH	236	#ifdef CONFIG_X86_64
	237	if (base > UINT_MAX)
	238	return -ERANGE;
	239	#endif
14351760	240	printk(KERN_INFO "PMTMR IOPort override: 0x%04x -> 0x%04lx\n",
ee974e01	241	pmtmr_ioport, base);
6b148507 TG	242	pmtmr_ioport = base;
	243
	244	return 1;
	245	}
	246	__setup("pmtmr=", parse_pmtmr);