[net-next-2.6.git] / drivers / char / hw_random / intel-rng.c

/*
 * RNG driver for Intel RNGs
 *
 * Copyright 2005 (c) MontaVista Software, Inc.
 *
 * with the majority of the code coming from:
 *
 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
 *
 * derived from
 *
 * Hardware driver for the AMD 768 Random Number Generator (RNG)
 * (c) Copyright 2001 Red Hat Inc <alan@redhat.com>
 *
 * derived from
 *
 * Hardware driver for Intel i810 Random Number Generator (RNG)
 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
 *
 * This file is licensed under  the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/hw_random.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/stop_machine.h>
#include <linux/delay.h>
#include <asm/io.h>


#define PFX	KBUILD_MODNAME ": "

/*
 * RNG registers
 */
#define INTEL_RNG_HW_STATUS			0
#define         INTEL_RNG_PRESENT		0x40
#define         INTEL_RNG_ENABLED		0x01
#define INTEL_RNG_STATUS			1
#define         INTEL_RNG_DATA_PRESENT		0x01
#define INTEL_RNG_DATA				2

/*
 * Magic address at which Intel PCI bridges locate the RNG
 */
#define INTEL_RNG_ADDR				0xFFBC015F
#define INTEL_RNG_ADDR_LEN			3

/*
 * LPC bridge PCI config space registers
 */
#define FWH_DEC_EN1_REG_OLD			0xe3
#define FWH_DEC_EN1_REG_NEW			0xd9 /* high byte of 16-bit register */
#define FWH_F8_EN_MASK				0x80

#define BIOS_CNTL_REG_OLD			0x4e
#define BIOS_CNTL_REG_NEW			0xdc
#define BIOS_CNTL_WRITE_ENABLE_MASK		0x01
#define BIOS_CNTL_LOCK_ENABLE_MASK		0x02

/*
 * Magic address at which Intel Firmware Hubs get accessed
 */
#define INTEL_FWH_ADDR				0xffff0000
#define INTEL_FWH_ADDR_LEN			2

/*
 * Intel Firmware Hub command codes (write to any address inside the device)
 */
#define INTEL_FWH_RESET_CMD			0xff /* aka READ_ARRAY */
#define INTEL_FWH_READ_ID_CMD			0x90

/*
 * Intel Firmware Hub Read ID command result addresses
 */
#define INTEL_FWH_MANUFACTURER_CODE_ADDRESS	0x000000
#define INTEL_FWH_DEVICE_CODE_ADDRESS		0x000001

/*
 * Intel Firmware Hub Read ID command result values
 */
#define INTEL_FWH_MANUFACTURER_CODE		0x89
#define INTEL_FWH_DEVICE_CODE_8M		0xac
#define INTEL_FWH_DEVICE_CODE_4M		0xad

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because someone else might one day
 * want to register another driver on the same PCI id.
 */
static const struct pci_device_id pci_tbl[] = {
/* AA
	{ PCI_DEVICE(0x8086, 0x2418) }, */
	{ PCI_DEVICE(0x8086, 0x2410) }, /* AA */
/* AB
	{ PCI_DEVICE(0x8086, 0x2428) }, */
	{ PCI_DEVICE(0x8086, 0x2420) }, /* AB */
/* ??
	{ PCI_DEVICE(0x8086, 0x2430) }, */
/* BAM, CAM, DBM, FBM, GxM
	{ PCI_DEVICE(0x8086, 0x2448) }, */
	{ PCI_DEVICE(0x8086, 0x244c) }, /* BAM */
	{ PCI_DEVICE(0x8086, 0x248c) }, /* CAM */
	{ PCI_DEVICE(0x8086, 0x24cc) }, /* DBM */
	{ PCI_DEVICE(0x8086, 0x2641) }, /* FBM */
	{ PCI_DEVICE(0x8086, 0x27b9) }, /* GxM */
	{ PCI_DEVICE(0x8086, 0x27bd) }, /* GxM DH */
/* BA, CA, DB, Ex, 6300, Fx, 631x/632x, Gx
	{ PCI_DEVICE(0x8086, 0x244e) }, */
	{ PCI_DEVICE(0x8086, 0x2440) }, /* BA */
	{ PCI_DEVICE(0x8086, 0x2480) }, /* CA */
	{ PCI_DEVICE(0x8086, 0x24c0) }, /* DB */
	{ PCI_DEVICE(0x8086, 0x24d0) }, /* Ex */
	{ PCI_DEVICE(0x8086, 0x25a1) }, /* 6300 */
	{ PCI_DEVICE(0x8086, 0x2640) }, /* Fx */
	{ PCI_DEVICE(0x8086, 0x2670) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2671) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2672) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2673) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2674) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2675) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2676) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2677) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2678) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x2679) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x267a) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x267b) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x267c) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x267d) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x267e) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x267f) }, /* 631x/632x */
	{ PCI_DEVICE(0x8086, 0x27b8) }, /* Gx */
/* E
	{ PCI_DEVICE(0x8086, 0x245e) }, */
	{ PCI_DEVICE(0x8086, 0x2450) }, /* E  */
	{ 0, },	/* terminate list */
};
MODULE_DEVICE_TABLE(pci, pci_tbl);

static __initdata int no_fwh_detect;
module_param(no_fwh_detect, int, 0);
MODULE_PARM_DESC(no_fwh_detect, "Skip FWH detection:\n"
                                " positive value - skip if FWH space locked read-only\n"
                                " negative value - skip always");

static inline u8 hwstatus_get(void __iomem *mem)
{
	return readb(mem + INTEL_RNG_HW_STATUS);
}

static inline u8 hwstatus_set(void __iomem *mem,
			      u8 hw_status)
{
	writeb(hw_status, mem + INTEL_RNG_HW_STATUS);
	return hwstatus_get(mem);
}

static int intel_rng_data_present(struct hwrng *rng, int wait)
{
	void __iomem *mem = (void __iomem *)rng->priv;
	int data, i;

	for (i = 0; i < 20; i++) {
		data = !!(readb(mem + INTEL_RNG_STATUS) &
			  INTEL_RNG_DATA_PRESENT);
		if (data || !wait)
			break;
		udelay(10);
	}
	return data;
}

static int intel_rng_data_read(struct hwrng *rng, u32 *data)
{
	void __iomem *mem = (void __iomem *)rng->priv;

	*data = readb(mem + INTEL_RNG_DATA);

	return 1;
}

static int intel_rng_init(struct hwrng *rng)
{
	void __iomem *mem = (void __iomem *)rng->priv;
	u8 hw_status;
	int err = -EIO;

	hw_status = hwstatus_get(mem);
	/* turn RNG h/w on, if it's off */
	if ((hw_status & INTEL_RNG_ENABLED) == 0)
		hw_status = hwstatus_set(mem, hw_status | INTEL_RNG_ENABLED);
	if ((hw_status & INTEL_RNG_ENABLED) == 0) {
		printk(KERN_ERR PFX "cannot enable RNG, aborting\n");
		goto out;
	}
	err = 0;
out:
	return err;
}

static void intel_rng_cleanup(struct hwrng *rng)
{
	void __iomem *mem = (void __iomem *)rng->priv;
	u8 hw_status;

	hw_status = hwstatus_get(mem);
	if (hw_status & INTEL_RNG_ENABLED)
		hwstatus_set(mem, hw_status & ~INTEL_RNG_ENABLED);
	else
		printk(KERN_WARNING PFX "unusual: RNG already disabled\n");
}


static struct hwrng intel_rng = {
	.name		= "intel",
	.init		= intel_rng_init,
	.cleanup	= intel_rng_cleanup,
	.data_present	= intel_rng_data_present,
	.data_read	= intel_rng_data_read,
};

struct intel_rng_hw {
	struct pci_dev *dev;
	void __iomem *mem;
	u8 bios_cntl_off;
	u8 bios_cntl_val;
	u8 fwh_dec_en1_off;
	u8 fwh_dec_en1_val;
};

static int __init intel_rng_hw_init(void *_intel_rng_hw)
{
	struct intel_rng_hw *intel_rng_hw = _intel_rng_hw;
	u8 mfc, dvc;

	/* interrupts disabled in stop_machine call */

	if (!(intel_rng_hw->fwh_dec_en1_val & FWH_F8_EN_MASK))
		pci_write_config_byte(intel_rng_hw->dev,
		                      intel_rng_hw->fwh_dec_en1_off,
		                      intel_rng_hw->fwh_dec_en1_val |
				      FWH_F8_EN_MASK);
	if (!(intel_rng_hw->bios_cntl_val & BIOS_CNTL_WRITE_ENABLE_MASK))
		pci_write_config_byte(intel_rng_hw->dev,
		                      intel_rng_hw->bios_cntl_off,
		                      intel_rng_hw->bios_cntl_val |
				      BIOS_CNTL_WRITE_ENABLE_MASK);

	writeb(INTEL_FWH_RESET_CMD, intel_rng_hw->mem);
	writeb(INTEL_FWH_READ_ID_CMD, intel_rng_hw->mem);
	mfc = readb(intel_rng_hw->mem + INTEL_FWH_MANUFACTURER_CODE_ADDRESS);
	dvc = readb(intel_rng_hw->mem + INTEL_FWH_DEVICE_CODE_ADDRESS);
	writeb(INTEL_FWH_RESET_CMD, intel_rng_hw->mem);

	if (!(intel_rng_hw->bios_cntl_val &
	      (BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK)))
		pci_write_config_byte(intel_rng_hw->dev,
				      intel_rng_hw->bios_cntl_off,
				      intel_rng_hw->bios_cntl_val);
	if (!(intel_rng_hw->fwh_dec_en1_val & FWH_F8_EN_MASK))
		pci_write_config_byte(intel_rng_hw->dev,
				      intel_rng_hw->fwh_dec_en1_off,
				      intel_rng_hw->fwh_dec_en1_val);

	if (mfc != INTEL_FWH_MANUFACTURER_CODE ||
	    (dvc != INTEL_FWH_DEVICE_CODE_8M &&
	     dvc != INTEL_FWH_DEVICE_CODE_4M)) {
		printk(KERN_NOTICE PFX "FWH not detected\n");
		return -ENODEV;
	}

	return 0;
}

static int __init intel_init_hw_struct(struct intel_rng_hw *intel_rng_hw,
					struct pci_dev *dev)
{
	intel_rng_hw->bios_cntl_val = 0xff;
	intel_rng_hw->fwh_dec_en1_val = 0xff;
	intel_rng_hw->dev = dev;

	/* Check for Intel 82802 */
	if (dev->device < 0x2640) {
		intel_rng_hw->fwh_dec_en1_off = FWH_DEC_EN1_REG_OLD;
		intel_rng_hw->bios_cntl_off = BIOS_CNTL_REG_OLD;
	} else {
		intel_rng_hw->fwh_dec_en1_off = FWH_DEC_EN1_REG_NEW;
		intel_rng_hw->bios_cntl_off = BIOS_CNTL_REG_NEW;
	}

	pci_read_config_byte(dev, intel_rng_hw->fwh_dec_en1_off,
			     &intel_rng_hw->fwh_dec_en1_val);
	pci_read_config_byte(dev, intel_rng_hw->bios_cntl_off,
			     &intel_rng_hw->bios_cntl_val);

	if ((intel_rng_hw->bios_cntl_val &
	     (BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK))
	    == BIOS_CNTL_LOCK_ENABLE_MASK) {
		static __initdata /*const*/ char warning[] =
			KERN_WARNING PFX "Firmware space is locked read-only. If you can't or\n"
			KERN_WARNING PFX "don't want to disable this in firmware setup, and if\n"
			KERN_WARNING PFX "you are certain that your system has a functional\n"
			KERN_WARNING PFX "RNG, try using the 'no_fwh_detect' option.\n";

		if (no_fwh_detect)
			return -ENODEV;
		printk(warning);
		return -EBUSY;
	}

	intel_rng_hw->mem = ioremap_nocache(INTEL_FWH_ADDR, INTEL_FWH_ADDR_LEN);
	if (intel_rng_hw->mem == NULL)
		return -EBUSY;

	return 0;
}


static int __init mod_init(void)
{
	int err = -ENODEV;
	int i;
	struct pci_dev *dev = NULL;
	void __iomem *mem = mem;
	u8 hw_status;
	struct intel_rng_hw *intel_rng_hw;

	for (i = 0; !dev && pci_tbl[i].vendor; ++i)
		dev = pci_get_device(pci_tbl[i].vendor, pci_tbl[i].device,
				     NULL);

	if (!dev)
		goto out; /* Device not found. */

	if (no_fwh_detect < 0) {
		pci_dev_put(dev);
		goto fwh_done;
	}

	intel_rng_hw = kmalloc(sizeof(*intel_rng_hw), GFP_KERNEL);
	if (!intel_rng_hw) {
		pci_dev_put(dev);
		goto out;
	}

	err = intel_init_hw_struct(intel_rng_hw, dev);
	if (err) {
		pci_dev_put(dev);
		kfree(intel_rng_hw);
		if (err == -ENODEV)
			goto fwh_done;
		goto out;
	}

	/*
	 * Since the BIOS code/data is going to disappear from its normal
	 * location with the Read ID command, all activity on the system
	 * must be stopped until the state is back to normal.
	 *
	 * Use stop_machine because IPIs can be blocked by disabling
	 * interrupts.
	 */
	err = stop_machine(intel_rng_hw_init, intel_rng_hw, NULL);
	pci_dev_put(dev);
	iounmap(intel_rng_hw->mem);
	kfree(intel_rng_hw);
	if (err)
		goto out;

fwh_done:
	err = -ENOMEM;
	mem = ioremap(INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
	if (!mem)
		goto out;
	intel_rng.priv = (unsigned long)mem;

	/* Check for Random Number Generator */
	err = -ENODEV;
	hw_status = hwstatus_get(mem);
	if ((hw_status & INTEL_RNG_PRESENT) == 0) {
		iounmap(mem);
		goto out;
	}

	printk(KERN_INFO "Intel 82802 RNG detected\n");
	err = hwrng_register(&intel_rng);
	if (err) {
		printk(KERN_ERR PFX "RNG registering failed (%d)\n",
		       err);
		iounmap(mem);
	}
out:
	return err;

}

static void __exit mod_exit(void)
{
	void __iomem *mem = (void __iomem *)intel_rng.priv;

	hwrng_unregister(&intel_rng);
	iounmap(mem);
}

module_init(mod_init);
module_exit(mod_exit);

MODULE_DESCRIPTION("H/W RNG driver for Intel chipsets");
MODULE_LICENSE("GPL");
Commit	Line	Data
ca644bd5 MB	1	/*
	2	* RNG driver for Intel RNGs
	3	*
	4	* Copyright 2005 (c) MontaVista Software, Inc.
	5	*
	6	* with the majority of the code coming from:
	7	*
	8	* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
	9	* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
	10	*
	11	* derived from
	12	*
	13	* Hardware driver for the AMD 768 Random Number Generator (RNG)
	14	* (c) Copyright 2001 Red Hat Inc <alan@redhat.com>
	15	*
	16	* derived from
	17	*
	18	* Hardware driver for Intel i810 Random Number Generator (RNG)
	19	* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
	20	* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
	21	*
	22	* This file is licensed under the terms of the GNU General Public
	23	* License version 2. This program is licensed "as is" without any
	24	* warranty of any kind, whether express or implied.
	25	*/
	26
ee527cd3	27	#include <linux/hw_random.h>
ca644bd5	28	#include <linux/kernel.h>
ee527cd3	29	#include <linux/module.h>
ca644bd5	30	#include <linux/pci.h>
ee527cd3	31	#include <linux/stop_machine.h>
984e976f	32	#include <linux/delay.h>
ca644bd5 MB	33	#include <asm/io.h>
	34
	35
	36	#define PFX KBUILD_MODNAME ": "
	37
	38	/*
	39	* RNG registers
	40	*/
	41	#define INTEL_RNG_HW_STATUS 0
	42	#define INTEL_RNG_PRESENT 0x40
	43	#define INTEL_RNG_ENABLED 0x01
	44	#define INTEL_RNG_STATUS 1
	45	#define INTEL_RNG_DATA_PRESENT 0x01
	46	#define INTEL_RNG_DATA 2
	47
	48	/*
	49	* Magic address at which Intel PCI bridges locate the RNG
	50	*/
	51	#define INTEL_RNG_ADDR 0xFFBC015F
	52	#define INTEL_RNG_ADDR_LEN 3
	53
c24c95a0 JB	54	/*
	55	* LPC bridge PCI config space registers
	56	*/
	57	#define FWH_DEC_EN1_REG_OLD 0xe3
	58	#define FWH_DEC_EN1_REG_NEW 0xd9 /* high byte of 16-bit register */
	59	#define FWH_F8_EN_MASK 0x80
	60
	61	#define BIOS_CNTL_REG_OLD 0x4e
	62	#define BIOS_CNTL_REG_NEW 0xdc
	63	#define BIOS_CNTL_WRITE_ENABLE_MASK 0x01
	64	#define BIOS_CNTL_LOCK_ENABLE_MASK 0x02
	65
	66	/*
	67	* Magic address at which Intel Firmware Hubs get accessed
	68	*/
	69	#define INTEL_FWH_ADDR 0xffff0000
	70	#define INTEL_FWH_ADDR_LEN 2
	71
	72	/*
	73	* Intel Firmware Hub command codes (write to any address inside the device)
	74	*/
	75	#define INTEL_FWH_RESET_CMD 0xff /* aka READ_ARRAY */
	76	#define INTEL_FWH_READ_ID_CMD 0x90
	77
	78	/*
	79	* Intel Firmware Hub Read ID command result addresses
	80	*/
	81	#define INTEL_FWH_MANUFACTURER_CODE_ADDRESS 0x000000
	82	#define INTEL_FWH_DEVICE_CODE_ADDRESS 0x000001
	83
	84	/*
	85	* Intel Firmware Hub Read ID command result values
	86	*/
	87	#define INTEL_FWH_MANUFACTURER_CODE 0x89
	88	#define INTEL_FWH_DEVICE_CODE_8M 0xac
	89	#define INTEL_FWH_DEVICE_CODE_4M 0xad
	90
ca644bd5 MB	91	/*
	92	* Data for PCI driver interface
	93	*
	94	* This data only exists for exporting the supported
	95	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
	96	* register a pci_driver, because someone else might one day
	97	* want to register another driver on the same PCI id.
	98	*/
	99	static const struct pci_device_id pci_tbl[] = {
c24c95a0	100	/* AA
29d73aab JS	101	{ PCI_DEVICE(0x8086, 0x2418) }, */
29d73aab JS	102	{ PCI_DEVICE(0x8086, 0x2410) }, /* AA */
c24c95a0	103	/* AB
29d73aab JS	104	{ PCI_DEVICE(0x8086, 0x2428) }, */
29d73aab JS	105	{ PCI_DEVICE(0x8086, 0x2420) }, /* AB */
c24c95a0	106	/* ??
29d73aab	107	{ PCI_DEVICE(0x8086, 0x2430) }, */
c24c95a0	108	/* BAM, CAM, DBM, FBM, GxM
29d73aab JS	109	{ PCI_DEVICE(0x8086, 0x2448) }, */
	110	{ PCI_DEVICE(0x8086, 0x244c) }, /* BAM */
	111	{ PCI_DEVICE(0x8086, 0x248c) }, /* CAM */
	112	{ PCI_DEVICE(0x8086, 0x24cc) }, /* DBM */
	113	{ PCI_DEVICE(0x8086, 0x2641) }, /* FBM */
	114	{ PCI_DEVICE(0x8086, 0x27b9) }, /* GxM */
	115	{ PCI_DEVICE(0x8086, 0x27bd) }, /* GxM DH */
c24c95a0	116	/* BA, CA, DB, Ex, 6300, Fx, 631x/632x, Gx
29d73aab JS	117	{ PCI_DEVICE(0x8086, 0x244e) }, */
	118	{ PCI_DEVICE(0x8086, 0x2440) }, /* BA */
	119	{ PCI_DEVICE(0x8086, 0x2480) }, /* CA */
	120	{ PCI_DEVICE(0x8086, 0x24c0) }, /* DB */
	121	{ PCI_DEVICE(0x8086, 0x24d0) }, /* Ex */
	122	{ PCI_DEVICE(0x8086, 0x25a1) }, /* 6300 */
	123	{ PCI_DEVICE(0x8086, 0x2640) }, /* Fx */
	124	{ PCI_DEVICE(0x8086, 0x2670) }, /* 631x/632x */
	125	{ PCI_DEVICE(0x8086, 0x2671) }, /* 631x/632x */
	126	{ PCI_DEVICE(0x8086, 0x2672) }, /* 631x/632x */
	127	{ PCI_DEVICE(0x8086, 0x2673) }, /* 631x/632x */
	128	{ PCI_DEVICE(0x8086, 0x2674) }, /* 631x/632x */
	129	{ PCI_DEVICE(0x8086, 0x2675) }, /* 631x/632x */
	130	{ PCI_DEVICE(0x8086, 0x2676) }, /* 631x/632x */
	131	{ PCI_DEVICE(0x8086, 0x2677) }, /* 631x/632x */
	132	{ PCI_DEVICE(0x8086, 0x2678) }, /* 631x/632x */
	133	{ PCI_DEVICE(0x8086, 0x2679) }, /* 631x/632x */
	134	{ PCI_DEVICE(0x8086, 0x267a) }, /* 631x/632x */
	135	{ PCI_DEVICE(0x8086, 0x267b) }, /* 631x/632x */
	136	{ PCI_DEVICE(0x8086, 0x267c) }, /* 631x/632x */
	137	{ PCI_DEVICE(0x8086, 0x267d) }, /* 631x/632x */
	138	{ PCI_DEVICE(0x8086, 0x267e) }, /* 631x/632x */
	139	{ PCI_DEVICE(0x8086, 0x267f) }, /* 631x/632x */
	140	{ PCI_DEVICE(0x8086, 0x27b8) }, /* Gx */
c24c95a0	141	/* E
29d73aab JS	142	{ PCI_DEVICE(0x8086, 0x245e) }, */
29d73aab JS	143	{ PCI_DEVICE(0x8086, 0x2450) }, /* E */
ca644bd5 MB	144	{ 0, }, /* terminate list */
	145	};
	146	MODULE_DEVICE_TABLE(pci, pci_tbl);
	147
9863be59 JB	148	static __initdata int no_fwh_detect;
	149	module_param(no_fwh_detect, int, 0);
	150	MODULE_PARM_DESC(no_fwh_detect, "Skip FWH detection:\n"
	151	" positive value - skip if FWH space locked read-only\n"
	152	" negative value - skip always");
ca644bd5 MB	153
	154	static inline u8 hwstatus_get(void __iomem *mem)
	155	{
	156	return readb(mem + INTEL_RNG_HW_STATUS);
	157	}
	158
	159	static inline u8 hwstatus_set(void __iomem *mem,
	160	u8 hw_status)
	161	{
	162	writeb(hw_status, mem + INTEL_RNG_HW_STATUS);
	163	return hwstatus_get(mem);
	164	}
	165
984e976f	166	static int intel_rng_data_present(struct hwrng *rng, int wait)
ca644bd5 MB	167	{
ca644bd5 MB	168	void __iomem mem = (void __iomem )rng->priv;
984e976f PM	169	int data, i;
	170
	171	for (i = 0; i < 20; i++) {
	172	data = !!(readb(mem + INTEL_RNG_STATUS) &
	173	INTEL_RNG_DATA_PRESENT);
	174	if (data \|\| !wait)
	175	break;
	176	udelay(10);
	177	}
	178	return data;
ca644bd5 MB	179	}
	180
	181	static int intel_rng_data_read(struct hwrng rng, u32 data)
	182	{
	183	void __iomem mem = (void __iomem )rng->priv;
	184
	185	*data = readb(mem + INTEL_RNG_DATA);
	186
	187	return 1;
	188	}
	189
	190	static int intel_rng_init(struct hwrng *rng)
	191	{
	192	void __iomem mem = (void __iomem )rng->priv;
	193	u8 hw_status;
	194	int err = -EIO;
	195
	196	hw_status = hwstatus_get(mem);
	197	/* turn RNG h/w on, if it's off */
	198	if ((hw_status & INTEL_RNG_ENABLED) == 0)
	199	hw_status = hwstatus_set(mem, hw_status \| INTEL_RNG_ENABLED);
	200	if ((hw_status & INTEL_RNG_ENABLED) == 0) {
	201	printk(KERN_ERR PFX "cannot enable RNG, aborting\n");
	202	goto out;
	203	}
	204	err = 0;
	205	out:
	206	return err;
	207	}
	208
	209	static void intel_rng_cleanup(struct hwrng *rng)
	210	{
	211	void __iomem mem = (void __iomem )rng->priv;
	212	u8 hw_status;
	213
	214	hw_status = hwstatus_get(mem);
	215	if (hw_status & INTEL_RNG_ENABLED)
	216	hwstatus_set(mem, hw_status & ~INTEL_RNG_ENABLED);
	217	else
	218	printk(KERN_WARNING PFX "unusual: RNG already disabled\n");
	219	}
	220
	221
	222	static struct hwrng intel_rng = {
	223	.name = "intel",
	224	.init = intel_rng_init,
	225	.cleanup = intel_rng_cleanup,
	226	.data_present = intel_rng_data_present,
	227	.data_read = intel_rng_data_read,
	228	};
	229
ee527cd3 PB	230	struct intel_rng_hw {
	231	struct pci_dev *dev;
	232	void __iomem *mem;
	233	u8 bios_cntl_off;
	234	u8 bios_cntl_val;
	235	u8 fwh_dec_en1_off;
	236	u8 fwh_dec_en1_val;
	237	};
ca644bd5	238
ee527cd3 PB	239	static int __init intel_rng_hw_init(void *_intel_rng_hw)
	240	{
	241	struct intel_rng_hw *intel_rng_hw = _intel_rng_hw;
	242	u8 mfc, dvc;
	243
9b1a4d38	244	/* interrupts disabled in stop_machine call */
ee527cd3 PB	245
	246	if (!(intel_rng_hw->fwh_dec_en1_val & FWH_F8_EN_MASK))
	247	pci_write_config_byte(intel_rng_hw->dev,
	248	intel_rng_hw->fwh_dec_en1_off,
	249	intel_rng_hw->fwh_dec_en1_val \|
	250	FWH_F8_EN_MASK);
	251	if (!(intel_rng_hw->bios_cntl_val & BIOS_CNTL_WRITE_ENABLE_MASK))
	252	pci_write_config_byte(intel_rng_hw->dev,
	253	intel_rng_hw->bios_cntl_off,
	254	intel_rng_hw->bios_cntl_val \|
	255	BIOS_CNTL_WRITE_ENABLE_MASK);
	256
	257	writeb(INTEL_FWH_RESET_CMD, intel_rng_hw->mem);
	258	writeb(INTEL_FWH_READ_ID_CMD, intel_rng_hw->mem);
	259	mfc = readb(intel_rng_hw->mem + INTEL_FWH_MANUFACTURER_CODE_ADDRESS);
	260	dvc = readb(intel_rng_hw->mem + INTEL_FWH_DEVICE_CODE_ADDRESS);
	261	writeb(INTEL_FWH_RESET_CMD, intel_rng_hw->mem);
	262
	263	if (!(intel_rng_hw->bios_cntl_val &
	264	(BIOS_CNTL_LOCK_ENABLE_MASK\|BIOS_CNTL_WRITE_ENABLE_MASK)))
	265	pci_write_config_byte(intel_rng_hw->dev,
	266	intel_rng_hw->bios_cntl_off,
	267	intel_rng_hw->bios_cntl_val);
	268	if (!(intel_rng_hw->fwh_dec_en1_val & FWH_F8_EN_MASK))
	269	pci_write_config_byte(intel_rng_hw->dev,
	270	intel_rng_hw->fwh_dec_en1_off,
	271	intel_rng_hw->fwh_dec_en1_val);
c24c95a0	272
ee527cd3 PB	273	if (mfc != INTEL_FWH_MANUFACTURER_CODE \|\|
	274	(dvc != INTEL_FWH_DEVICE_CODE_8M &&
	275	dvc != INTEL_FWH_DEVICE_CODE_4M)) {
c97aee9b	276	printk(KERN_NOTICE PFX "FWH not detected\n");
ee527cd3 PB	277	return -ENODEV;
	278	}
	279
	280	return 0;
	281	}
	282
	283	static int __init intel_init_hw_struct(struct intel_rng_hw *intel_rng_hw,
	284	struct pci_dev *dev)
c24c95a0	285	{
ee527cd3 PB	286	intel_rng_hw->bios_cntl_val = 0xff;
	287	intel_rng_hw->fwh_dec_en1_val = 0xff;
	288	intel_rng_hw->dev = dev;
	289
	290	/* Check for Intel 82802 */
	291	if (dev->device < 0x2640) {
	292	intel_rng_hw->fwh_dec_en1_off = FWH_DEC_EN1_REG_OLD;
	293	intel_rng_hw->bios_cntl_off = BIOS_CNTL_REG_OLD;
	294	} else {
	295	intel_rng_hw->fwh_dec_en1_off = FWH_DEC_EN1_REG_NEW;
	296	intel_rng_hw->bios_cntl_off = BIOS_CNTL_REG_NEW;
	297	}
	298
	299	pci_read_config_byte(dev, intel_rng_hw->fwh_dec_en1_off,
	300	&intel_rng_hw->fwh_dec_en1_val);
	301	pci_read_config_byte(dev, intel_rng_hw->bios_cntl_off,
	302	&intel_rng_hw->bios_cntl_val);
	303
	304	if ((intel_rng_hw->bios_cntl_val &
	305	(BIOS_CNTL_LOCK_ENABLE_MASK\|BIOS_CNTL_WRITE_ENABLE_MASK))
	306	== BIOS_CNTL_LOCK_ENABLE_MASK) {
	307	static __initdata /const/ char warning[] =
f3dc8c18 AC	308	KERN_WARNING PFX "Firmware space is locked read-only. If you can't or\n"
	309	KERN_WARNING PFX "don't want to disable this in firmware setup, and if\n"
	310	KERN_WARNING PFX "you are certain that your system has a functional\n"
	311	KERN_WARNING PFX "RNG, try using the 'no_fwh_detect' option.\n";
ee527cd3 PB	312
	313	if (no_fwh_detect)
	314	return -ENODEV;
	315	printk(warning);
	316	return -EBUSY;
	317	}
	318
	319	intel_rng_hw->mem = ioremap_nocache(INTEL_FWH_ADDR, INTEL_FWH_ADDR_LEN);
	320	if (intel_rng_hw->mem == NULL)
	321	return -EBUSY;
	322
	323	return 0;
c24c95a0	324	}
ee527cd3	325
c24c95a0	326
ca644bd5 MB	327	static int __init mod_init(void)
	328	{
	329	int err = -ENODEV;
ee527cd3	330	int i;
c24c95a0	331	struct pci_dev *dev = NULL;
ee527cd3 PB	332	void __iomem *mem = mem;
	333	u8 hw_status;
	334	struct intel_rng_hw *intel_rng_hw;
ca644bd5	335
c24c95a0	336	for (i = 0; !dev && pci_tbl[i].vendor; ++i)
ee527cd3 PB	337	dev = pci_get_device(pci_tbl[i].vendor, pci_tbl[i].device,
ee527cd3 PB	338	NULL);
c24c95a0 JB	339
c24c95a0 JB	340	if (!dev)
ca644bd5 MB	341	goto out; /* Device not found. */
ca644bd5 MB	342
9863be59 JB	343	if (no_fwh_detect < 0) {
	344	pci_dev_put(dev);
	345	goto fwh_done;
	346	}
	347
ee527cd3 PB	348	intel_rng_hw = kmalloc(sizeof(*intel_rng_hw), GFP_KERNEL);
ee527cd3 PB	349	if (!intel_rng_hw) {
9863be59	350	pci_dev_put(dev);
9863be59 JB	351	goto out;
	352	}
	353
ee527cd3 PB	354	err = intel_init_hw_struct(intel_rng_hw, dev);
ee527cd3 PB	355	if (err) {
c24c95a0	356	pci_dev_put(dev);
ee527cd3 PB	357	kfree(intel_rng_hw);
	358	if (err == -ENODEV)
	359	goto fwh_done;
c24c95a0 JB	360	goto out;
	361	}
	362
	363	/*
	364	* Since the BIOS code/data is going to disappear from its normal
	365	* location with the Read ID command, all activity on the system
	366	* must be stopped until the state is back to normal.
ee527cd3	367	*
9b1a4d38	368	* Use stop_machine because IPIs can be blocked by disabling
ee527cd3	369	* interrupts.
c24c95a0	370	*/
9b1a4d38	371	err = stop_machine(intel_rng_hw_init, intel_rng_hw, NULL);
c24c95a0	372	pci_dev_put(dev);
ee527cd3 PB	373	iounmap(intel_rng_hw->mem);
	374	kfree(intel_rng_hw);
	375	if (err)
c24c95a0	376	goto out;
c24c95a0	377
9863be59	378	fwh_done:
ca644bd5 MB	379	err = -ENOMEM;
	380	mem = ioremap(INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
	381	if (!mem)
	382	goto out;
	383	intel_rng.priv = (unsigned long)mem;
	384
c24c95a0	385	/* Check for Random Number Generator */
ca644bd5 MB	386	err = -ENODEV;
ca644bd5 MB	387	hw_status = hwstatus_get(mem);
ee527cd3 PB	388	if ((hw_status & INTEL_RNG_PRESENT) == 0) {
	389	iounmap(mem);
	390	goto out;
	391	}
ca644bd5 MB	392
	393	printk(KERN_INFO "Intel 82802 RNG detected\n");
	394	err = hwrng_register(&intel_rng);
	395	if (err) {
	396	printk(KERN_ERR PFX "RNG registering failed (%d)\n",
	397	err);
ee527cd3	398	iounmap(mem);
ca644bd5 MB	399	}
	400	out:
	401	return err;
	402
ca644bd5 MB	403	}
	404
	405	static void __exit mod_exit(void)
	406	{
	407	void __iomem mem = (void __iomem )intel_rng.priv;
	408
	409	hwrng_unregister(&intel_rng);
	410	iounmap(mem);
	411	}
	412
56fb5fe9	413	module_init(mod_init);
ca644bd5 MB	414	module_exit(mod_exit);
	415
	416	MODULE_DESCRIPTION("H/W RNG driver for Intel chipsets");
	417	MODULE_LICENSE("GPL");