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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel & MS High Precision Event Timer Implementation. | |
3 | * | |
4 | * Copyright (C) 2003 Intel Corporation | |
5 | * Venki Pallipadi | |
6 | * (c) Copyright 2004 Hewlett-Packard Development Company, L.P. | |
7 | * Bob Picco <robert.picco@hp.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
1da177e4 LT |
14 | #include <linux/interrupt.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
48b81880 | 17 | #include <linux/smp_lock.h> |
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/miscdevice.h> | |
20 | #include <linux/major.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/fcntl.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/poll.h> | |
f23f6e08 | 25 | #include <linux/mm.h> |
1da177e4 LT |
26 | #include <linux/proc_fs.h> |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/sysctl.h> | |
29 | #include <linux/wait.h> | |
30 | #include <linux/bcd.h> | |
31 | #include <linux/seq_file.h> | |
32 | #include <linux/bitops.h> | |
54066a57 | 33 | #include <linux/compat.h> |
0aa366f3 | 34 | #include <linux/clocksource.h> |
0ca01763 | 35 | #include <linux/uaccess.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
0ca01763 | 37 | #include <linux/io.h> |
1da177e4 LT |
38 | |
39 | #include <asm/current.h> | |
1da177e4 | 40 | #include <asm/system.h> |
1da177e4 LT |
41 | #include <asm/irq.h> |
42 | #include <asm/div64.h> | |
43 | ||
44 | #include <linux/acpi.h> | |
45 | #include <acpi/acpi_bus.h> | |
46 | #include <linux/hpet.h> | |
47 | ||
48 | /* | |
49 | * The High Precision Event Timer driver. | |
50 | * This driver is closely modelled after the rtc.c driver. | |
e45f2c07 | 51 | * http://www.intel.com/hardwaredesign/hpetspec_1.pdf |
1da177e4 LT |
52 | */ |
53 | #define HPET_USER_FREQ (64) | |
54 | #define HPET_DRIFT (500) | |
55 | ||
757c4724 RD |
56 | #define HPET_RANGE_SIZE 1024 /* from HPET spec */ |
57 | ||
64a76f66 DB |
58 | |
59 | /* WARNING -- don't get confused. These macros are never used | |
60 | * to write the (single) counter, and rarely to read it. | |
61 | * They're badly named; to fix, someday. | |
62 | */ | |
0aa366f3 TL |
63 | #if BITS_PER_LONG == 64 |
64 | #define write_counter(V, MC) writeq(V, MC) | |
65 | #define read_counter(MC) readq(MC) | |
66 | #else | |
67 | #define write_counter(V, MC) writel(V, MC) | |
68 | #define read_counter(MC) readl(MC) | |
69 | #endif | |
70 | ||
54066a57 | 71 | static DEFINE_MUTEX(hpet_mutex); /* replaces BKL */ |
642d30bb | 72 | static u32 hpet_nhpet, hpet_max_freq = HPET_USER_FREQ; |
1da177e4 | 73 | |
3dffec45 ÇO |
74 | /* This clocksource driver currently only works on ia64 */ |
75 | #ifdef CONFIG_IA64 | |
0aa366f3 TL |
76 | static void __iomem *hpet_mctr; |
77 | ||
8e19608e | 78 | static cycle_t read_hpet(struct clocksource *cs) |
0aa366f3 TL |
79 | { |
80 | return (cycle_t)read_counter((void __iomem *)hpet_mctr); | |
81 | } | |
82 | ||
83 | static struct clocksource clocksource_hpet = { | |
0ca01763 JSR |
84 | .name = "hpet", |
85 | .rating = 250, | |
86 | .read = read_hpet, | |
87 | .mask = CLOCKSOURCE_MASK(64), | |
88 | .mult = 0, /* to be calculated */ | |
89 | .shift = 10, | |
90 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
0aa366f3 TL |
91 | }; |
92 | static struct clocksource *hpet_clocksource; | |
3dffec45 | 93 | #endif |
0aa366f3 | 94 | |
1da177e4 LT |
95 | /* A lock for concurrent access by app and isr hpet activity. */ |
96 | static DEFINE_SPINLOCK(hpet_lock); | |
1da177e4 LT |
97 | |
98 | #define HPET_DEV_NAME (7) | |
99 | ||
100 | struct hpet_dev { | |
101 | struct hpets *hd_hpets; | |
102 | struct hpet __iomem *hd_hpet; | |
103 | struct hpet_timer __iomem *hd_timer; | |
104 | unsigned long hd_ireqfreq; | |
105 | unsigned long hd_irqdata; | |
106 | wait_queue_head_t hd_waitqueue; | |
107 | struct fasync_struct *hd_async_queue; | |
1da177e4 LT |
108 | unsigned int hd_flags; |
109 | unsigned int hd_irq; | |
110 | unsigned int hd_hdwirq; | |
111 | char hd_name[HPET_DEV_NAME]; | |
112 | }; | |
113 | ||
114 | struct hpets { | |
115 | struct hpets *hp_next; | |
116 | struct hpet __iomem *hp_hpet; | |
117 | unsigned long hp_hpet_phys; | |
0aa366f3 | 118 | struct clocksource *hp_clocksource; |
ba3f213f | 119 | unsigned long long hp_tick_freq; |
1da177e4 LT |
120 | unsigned long hp_delta; |
121 | unsigned int hp_ntimer; | |
122 | unsigned int hp_which; | |
123 | struct hpet_dev hp_dev[1]; | |
124 | }; | |
125 | ||
126 | static struct hpets *hpets; | |
127 | ||
128 | #define HPET_OPEN 0x0001 | |
129 | #define HPET_IE 0x0002 /* interrupt enabled */ | |
130 | #define HPET_PERIODIC 0x0004 | |
0d290861 | 131 | #define HPET_SHARED_IRQ 0x0008 |
1da177e4 | 132 | |
1da177e4 LT |
133 | |
134 | #ifndef readq | |
887c27f3 | 135 | static inline unsigned long long readq(void __iomem *addr) |
1da177e4 LT |
136 | { |
137 | return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL); | |
138 | } | |
139 | #endif | |
140 | ||
141 | #ifndef writeq | |
887c27f3 | 142 | static inline void writeq(unsigned long long v, void __iomem *addr) |
1da177e4 LT |
143 | { |
144 | writel(v & 0xffffffff, addr); | |
145 | writel(v >> 32, addr + 4); | |
146 | } | |
147 | #endif | |
148 | ||
7d12e780 | 149 | static irqreturn_t hpet_interrupt(int irq, void *data) |
1da177e4 LT |
150 | { |
151 | struct hpet_dev *devp; | |
152 | unsigned long isr; | |
153 | ||
154 | devp = data; | |
0d290861 CL |
155 | isr = 1 << (devp - devp->hd_hpets->hp_dev); |
156 | ||
157 | if ((devp->hd_flags & HPET_SHARED_IRQ) && | |
158 | !(isr & readl(&devp->hd_hpet->hpet_isr))) | |
159 | return IRQ_NONE; | |
1da177e4 LT |
160 | |
161 | spin_lock(&hpet_lock); | |
162 | devp->hd_irqdata++; | |
163 | ||
164 | /* | |
165 | * For non-periodic timers, increment the accumulator. | |
166 | * This has the effect of treating non-periodic like periodic. | |
167 | */ | |
168 | if ((devp->hd_flags & (HPET_IE | HPET_PERIODIC)) == HPET_IE) { | |
169 | unsigned long m, t; | |
170 | ||
171 | t = devp->hd_ireqfreq; | |
ae21cf92 NC |
172 | m = read_counter(&devp->hd_timer->hpet_compare); |
173 | write_counter(t + m, &devp->hd_timer->hpet_compare); | |
1da177e4 LT |
174 | } |
175 | ||
0d290861 CL |
176 | if (devp->hd_flags & HPET_SHARED_IRQ) |
177 | writel(isr, &devp->hd_hpet->hpet_isr); | |
1da177e4 LT |
178 | spin_unlock(&hpet_lock); |
179 | ||
1da177e4 LT |
180 | wake_up_interruptible(&devp->hd_waitqueue); |
181 | ||
182 | kill_fasync(&devp->hd_async_queue, SIGIO, POLL_IN); | |
183 | ||
184 | return IRQ_HANDLED; | |
185 | } | |
186 | ||
70ef6d59 KH |
187 | static void hpet_timer_set_irq(struct hpet_dev *devp) |
188 | { | |
189 | unsigned long v; | |
190 | int irq, gsi; | |
191 | struct hpet_timer __iomem *timer; | |
192 | ||
193 | spin_lock_irq(&hpet_lock); | |
194 | if (devp->hd_hdwirq) { | |
195 | spin_unlock_irq(&hpet_lock); | |
196 | return; | |
197 | } | |
198 | ||
199 | timer = devp->hd_timer; | |
200 | ||
201 | /* we prefer level triggered mode */ | |
202 | v = readl(&timer->hpet_config); | |
203 | if (!(v & Tn_INT_TYPE_CNF_MASK)) { | |
204 | v |= Tn_INT_TYPE_CNF_MASK; | |
205 | writel(v, &timer->hpet_config); | |
206 | } | |
207 | spin_unlock_irq(&hpet_lock); | |
208 | ||
209 | v = (readq(&timer->hpet_config) & Tn_INT_ROUTE_CAP_MASK) >> | |
210 | Tn_INT_ROUTE_CAP_SHIFT; | |
211 | ||
212 | /* | |
213 | * In PIC mode, skip IRQ0-4, IRQ6-9, IRQ12-15 which is always used by | |
214 | * legacy device. In IO APIC mode, we skip all the legacy IRQS. | |
215 | */ | |
216 | if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) | |
217 | v &= ~0xf3df; | |
218 | else | |
219 | v &= ~0xffff; | |
220 | ||
e5d61511 | 221 | for_each_set_bit(irq, &v, HPET_MAX_IRQ) { |
1f45f562 | 222 | if (irq >= nr_irqs) { |
70ef6d59 KH |
223 | irq = HPET_MAX_IRQ; |
224 | break; | |
225 | } | |
226 | ||
a2f809b0 | 227 | gsi = acpi_register_gsi(NULL, irq, ACPI_LEVEL_SENSITIVE, |
70ef6d59 KH |
228 | ACPI_ACTIVE_LOW); |
229 | if (gsi > 0) | |
230 | break; | |
231 | ||
232 | /* FIXME: Setup interrupt source table */ | |
233 | } | |
234 | ||
235 | if (irq < HPET_MAX_IRQ) { | |
236 | spin_lock_irq(&hpet_lock); | |
237 | v = readl(&timer->hpet_config); | |
238 | v |= irq << Tn_INT_ROUTE_CNF_SHIFT; | |
239 | writel(v, &timer->hpet_config); | |
240 | devp->hd_hdwirq = gsi; | |
241 | spin_unlock_irq(&hpet_lock); | |
242 | } | |
243 | return; | |
244 | } | |
245 | ||
1da177e4 LT |
246 | static int hpet_open(struct inode *inode, struct file *file) |
247 | { | |
248 | struct hpet_dev *devp; | |
249 | struct hpets *hpetp; | |
250 | int i; | |
251 | ||
252 | if (file->f_mode & FMODE_WRITE) | |
253 | return -EINVAL; | |
254 | ||
54066a57 | 255 | mutex_lock(&hpet_mutex); |
1da177e4 LT |
256 | spin_lock_irq(&hpet_lock); |
257 | ||
258 | for (devp = NULL, hpetp = hpets; hpetp && !devp; hpetp = hpetp->hp_next) | |
259 | for (i = 0; i < hpetp->hp_ntimer; i++) | |
64a76f66 | 260 | if (hpetp->hp_dev[i].hd_flags & HPET_OPEN) |
1da177e4 LT |
261 | continue; |
262 | else { | |
263 | devp = &hpetp->hp_dev[i]; | |
264 | break; | |
265 | } | |
266 | ||
267 | if (!devp) { | |
268 | spin_unlock_irq(&hpet_lock); | |
54066a57 | 269 | mutex_unlock(&hpet_mutex); |
1da177e4 LT |
270 | return -EBUSY; |
271 | } | |
272 | ||
273 | file->private_data = devp; | |
274 | devp->hd_irqdata = 0; | |
275 | devp->hd_flags |= HPET_OPEN; | |
276 | spin_unlock_irq(&hpet_lock); | |
54066a57 | 277 | mutex_unlock(&hpet_mutex); |
1da177e4 | 278 | |
70ef6d59 KH |
279 | hpet_timer_set_irq(devp); |
280 | ||
1da177e4 LT |
281 | return 0; |
282 | } | |
283 | ||
284 | static ssize_t | |
285 | hpet_read(struct file *file, char __user *buf, size_t count, loff_t * ppos) | |
286 | { | |
287 | DECLARE_WAITQUEUE(wait, current); | |
288 | unsigned long data; | |
289 | ssize_t retval; | |
290 | struct hpet_dev *devp; | |
291 | ||
292 | devp = file->private_data; | |
293 | if (!devp->hd_ireqfreq) | |
294 | return -EIO; | |
295 | ||
296 | if (count < sizeof(unsigned long)) | |
297 | return -EINVAL; | |
298 | ||
299 | add_wait_queue(&devp->hd_waitqueue, &wait); | |
300 | ||
301 | for ( ; ; ) { | |
302 | set_current_state(TASK_INTERRUPTIBLE); | |
303 | ||
304 | spin_lock_irq(&hpet_lock); | |
305 | data = devp->hd_irqdata; | |
306 | devp->hd_irqdata = 0; | |
307 | spin_unlock_irq(&hpet_lock); | |
308 | ||
309 | if (data) | |
310 | break; | |
311 | else if (file->f_flags & O_NONBLOCK) { | |
312 | retval = -EAGAIN; | |
313 | goto out; | |
314 | } else if (signal_pending(current)) { | |
315 | retval = -ERESTARTSYS; | |
316 | goto out; | |
317 | } | |
318 | schedule(); | |
319 | } | |
320 | ||
321 | retval = put_user(data, (unsigned long __user *)buf); | |
322 | if (!retval) | |
323 | retval = sizeof(unsigned long); | |
324 | out: | |
325 | __set_current_state(TASK_RUNNING); | |
326 | remove_wait_queue(&devp->hd_waitqueue, &wait); | |
327 | ||
328 | return retval; | |
329 | } | |
330 | ||
331 | static unsigned int hpet_poll(struct file *file, poll_table * wait) | |
332 | { | |
333 | unsigned long v; | |
334 | struct hpet_dev *devp; | |
335 | ||
336 | devp = file->private_data; | |
337 | ||
338 | if (!devp->hd_ireqfreq) | |
339 | return 0; | |
340 | ||
341 | poll_wait(file, &devp->hd_waitqueue, wait); | |
342 | ||
343 | spin_lock_irq(&hpet_lock); | |
344 | v = devp->hd_irqdata; | |
345 | spin_unlock_irq(&hpet_lock); | |
346 | ||
347 | if (v != 0) | |
348 | return POLLIN | POLLRDNORM; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static int hpet_mmap(struct file *file, struct vm_area_struct *vma) | |
354 | { | |
355 | #ifdef CONFIG_HPET_MMAP | |
356 | struct hpet_dev *devp; | |
357 | unsigned long addr; | |
358 | ||
359 | if (((vma->vm_end - vma->vm_start) != PAGE_SIZE) || vma->vm_pgoff) | |
360 | return -EINVAL; | |
361 | ||
362 | devp = file->private_data; | |
363 | addr = devp->hd_hpets->hp_hpet_phys; | |
364 | ||
365 | if (addr & (PAGE_SIZE - 1)) | |
366 | return -ENOSYS; | |
367 | ||
368 | vma->vm_flags |= VM_IO; | |
369 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
1da177e4 LT |
370 | |
371 | if (io_remap_pfn_range(vma, vma->vm_start, addr >> PAGE_SHIFT, | |
372 | PAGE_SIZE, vma->vm_page_prot)) { | |
3e6716e7 | 373 | printk(KERN_ERR "%s: io_remap_pfn_range failed\n", |
bf9d8929 | 374 | __func__); |
1da177e4 LT |
375 | return -EAGAIN; |
376 | } | |
377 | ||
378 | return 0; | |
379 | #else | |
380 | return -ENOSYS; | |
381 | #endif | |
382 | } | |
383 | ||
384 | static int hpet_fasync(int fd, struct file *file, int on) | |
385 | { | |
386 | struct hpet_dev *devp; | |
387 | ||
388 | devp = file->private_data; | |
389 | ||
390 | if (fasync_helper(fd, file, on, &devp->hd_async_queue) >= 0) | |
391 | return 0; | |
392 | else | |
393 | return -EIO; | |
394 | } | |
395 | ||
396 | static int hpet_release(struct inode *inode, struct file *file) | |
397 | { | |
398 | struct hpet_dev *devp; | |
399 | struct hpet_timer __iomem *timer; | |
400 | int irq = 0; | |
401 | ||
402 | devp = file->private_data; | |
403 | timer = devp->hd_timer; | |
404 | ||
405 | spin_lock_irq(&hpet_lock); | |
406 | ||
407 | writeq((readq(&timer->hpet_config) & ~Tn_INT_ENB_CNF_MASK), | |
408 | &timer->hpet_config); | |
409 | ||
410 | irq = devp->hd_irq; | |
411 | devp->hd_irq = 0; | |
412 | ||
413 | devp->hd_ireqfreq = 0; | |
414 | ||
415 | if (devp->hd_flags & HPET_PERIODIC | |
416 | && readq(&timer->hpet_config) & Tn_TYPE_CNF_MASK) { | |
417 | unsigned long v; | |
418 | ||
419 | v = readq(&timer->hpet_config); | |
420 | v ^= Tn_TYPE_CNF_MASK; | |
421 | writeq(v, &timer->hpet_config); | |
422 | } | |
423 | ||
424 | devp->hd_flags &= ~(HPET_OPEN | HPET_IE | HPET_PERIODIC); | |
425 | spin_unlock_irq(&hpet_lock); | |
426 | ||
427 | if (irq) | |
428 | free_irq(irq, devp); | |
429 | ||
1da177e4 LT |
430 | file->private_data = NULL; |
431 | return 0; | |
432 | } | |
433 | ||
1da177e4 LT |
434 | static int hpet_ioctl_ieon(struct hpet_dev *devp) |
435 | { | |
436 | struct hpet_timer __iomem *timer; | |
437 | struct hpet __iomem *hpet; | |
438 | struct hpets *hpetp; | |
439 | int irq; | |
440 | unsigned long g, v, t, m; | |
441 | unsigned long flags, isr; | |
442 | ||
443 | timer = devp->hd_timer; | |
444 | hpet = devp->hd_hpet; | |
445 | hpetp = devp->hd_hpets; | |
446 | ||
9090e6db CL |
447 | if (!devp->hd_ireqfreq) |
448 | return -EIO; | |
449 | ||
1da177e4 LT |
450 | spin_lock_irq(&hpet_lock); |
451 | ||
452 | if (devp->hd_flags & HPET_IE) { | |
453 | spin_unlock_irq(&hpet_lock); | |
454 | return -EBUSY; | |
455 | } | |
456 | ||
457 | devp->hd_flags |= HPET_IE; | |
0d290861 CL |
458 | |
459 | if (readl(&timer->hpet_config) & Tn_INT_TYPE_CNF_MASK) | |
460 | devp->hd_flags |= HPET_SHARED_IRQ; | |
1da177e4 LT |
461 | spin_unlock_irq(&hpet_lock); |
462 | ||
1da177e4 LT |
463 | irq = devp->hd_hdwirq; |
464 | ||
465 | if (irq) { | |
0d290861 | 466 | unsigned long irq_flags; |
1da177e4 | 467 | |
96e9694d CL |
468 | if (devp->hd_flags & HPET_SHARED_IRQ) { |
469 | /* | |
470 | * To prevent the interrupt handler from seeing an | |
471 | * unwanted interrupt status bit, program the timer | |
472 | * so that it will not fire in the near future ... | |
473 | */ | |
474 | writel(readl(&timer->hpet_config) & ~Tn_TYPE_CNF_MASK, | |
475 | &timer->hpet_config); | |
476 | write_counter(read_counter(&hpet->hpet_mc), | |
477 | &timer->hpet_compare); | |
478 | /* ... and clear any left-over status. */ | |
479 | isr = 1 << (devp - devp->hd_hpets->hp_dev); | |
480 | writel(isr, &hpet->hpet_isr); | |
481 | } | |
482 | ||
0d290861 CL |
483 | sprintf(devp->hd_name, "hpet%d", (int)(devp - hpetp->hp_dev)); |
484 | irq_flags = devp->hd_flags & HPET_SHARED_IRQ | |
0f2ed4c6 | 485 | ? IRQF_SHARED : IRQF_DISABLED; |
0d290861 CL |
486 | if (request_irq(irq, hpet_interrupt, irq_flags, |
487 | devp->hd_name, (void *)devp)) { | |
1da177e4 LT |
488 | printk(KERN_ERR "hpet: IRQ %d is not free\n", irq); |
489 | irq = 0; | |
490 | } | |
491 | } | |
492 | ||
493 | if (irq == 0) { | |
494 | spin_lock_irq(&hpet_lock); | |
495 | devp->hd_flags ^= HPET_IE; | |
496 | spin_unlock_irq(&hpet_lock); | |
497 | return -EIO; | |
498 | } | |
499 | ||
500 | devp->hd_irq = irq; | |
501 | t = devp->hd_ireqfreq; | |
502 | v = readq(&timer->hpet_config); | |
64a76f66 DB |
503 | |
504 | /* 64-bit comparators are not yet supported through the ioctls, | |
505 | * so force this into 32-bit mode if it supports both modes | |
506 | */ | |
507 | g = v | Tn_32MODE_CNF_MASK | Tn_INT_ENB_CNF_MASK; | |
1da177e4 LT |
508 | |
509 | if (devp->hd_flags & HPET_PERIODIC) { | |
1da177e4 | 510 | g |= Tn_TYPE_CNF_MASK; |
ae21cf92 | 511 | v |= Tn_TYPE_CNF_MASK | Tn_VAL_SET_CNF_MASK; |
1da177e4 LT |
512 | writeq(v, &timer->hpet_config); |
513 | local_irq_save(flags); | |
64a76f66 | 514 | |
ae21cf92 NC |
515 | /* |
516 | * NOTE: First we modify the hidden accumulator | |
64a76f66 DB |
517 | * register supported by periodic-capable comparators. |
518 | * We never want to modify the (single) counter; that | |
ae21cf92 NC |
519 | * would affect all the comparators. The value written |
520 | * is the counter value when the first interrupt is due. | |
64a76f66 | 521 | */ |
1da177e4 LT |
522 | m = read_counter(&hpet->hpet_mc); |
523 | write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare); | |
ae21cf92 NC |
524 | /* |
525 | * Then we modify the comparator, indicating the period | |
526 | * for subsequent interrupt. | |
527 | */ | |
528 | write_counter(t, &timer->hpet_compare); | |
1da177e4 LT |
529 | } else { |
530 | local_irq_save(flags); | |
531 | m = read_counter(&hpet->hpet_mc); | |
532 | write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare); | |
533 | } | |
534 | ||
0d290861 | 535 | if (devp->hd_flags & HPET_SHARED_IRQ) { |
3d5640d1 | 536 | isr = 1 << (devp - devp->hd_hpets->hp_dev); |
0d290861 CL |
537 | writel(isr, &hpet->hpet_isr); |
538 | } | |
1da177e4 LT |
539 | writeq(g, &timer->hpet_config); |
540 | local_irq_restore(flags); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
ba3f213f CL |
545 | /* converts Hz to number of timer ticks */ |
546 | static inline unsigned long hpet_time_div(struct hpets *hpets, | |
547 | unsigned long dis) | |
1da177e4 | 548 | { |
ba3f213f | 549 | unsigned long long m; |
1da177e4 | 550 | |
ba3f213f | 551 | m = hpets->hp_tick_freq + (dis >> 1); |
1da177e4 | 552 | do_div(m, dis); |
1da177e4 LT |
553 | return (unsigned long)m; |
554 | } | |
555 | ||
556 | static int | |
54066a57 AB |
557 | hpet_ioctl_common(struct hpet_dev *devp, int cmd, unsigned long arg, |
558 | struct hpet_info *info) | |
1da177e4 LT |
559 | { |
560 | struct hpet_timer __iomem *timer; | |
561 | struct hpet __iomem *hpet; | |
562 | struct hpets *hpetp; | |
563 | int err; | |
564 | unsigned long v; | |
565 | ||
566 | switch (cmd) { | |
567 | case HPET_IE_OFF: | |
568 | case HPET_INFO: | |
569 | case HPET_EPI: | |
570 | case HPET_DPI: | |
571 | case HPET_IRQFREQ: | |
572 | timer = devp->hd_timer; | |
573 | hpet = devp->hd_hpet; | |
574 | hpetp = devp->hd_hpets; | |
575 | break; | |
576 | case HPET_IE_ON: | |
577 | return hpet_ioctl_ieon(devp); | |
578 | default: | |
579 | return -EINVAL; | |
580 | } | |
581 | ||
582 | err = 0; | |
583 | ||
584 | switch (cmd) { | |
585 | case HPET_IE_OFF: | |
586 | if ((devp->hd_flags & HPET_IE) == 0) | |
587 | break; | |
588 | v = readq(&timer->hpet_config); | |
589 | v &= ~Tn_INT_ENB_CNF_MASK; | |
590 | writeq(v, &timer->hpet_config); | |
591 | if (devp->hd_irq) { | |
592 | free_irq(devp->hd_irq, devp); | |
593 | devp->hd_irq = 0; | |
594 | } | |
595 | devp->hd_flags ^= HPET_IE; | |
596 | break; | |
597 | case HPET_INFO: | |
598 | { | |
dae512ed | 599 | memset(info, 0, sizeof(*info)); |
af95eade | 600 | if (devp->hd_ireqfreq) |
54066a57 | 601 | info->hi_ireqfreq = |
af95eade | 602 | hpet_time_div(hpetp, devp->hd_ireqfreq); |
54066a57 | 603 | info->hi_flags = |
1da177e4 | 604 | readq(&timer->hpet_config) & Tn_PER_INT_CAP_MASK; |
54066a57 AB |
605 | info->hi_hpet = hpetp->hp_which; |
606 | info->hi_timer = devp - hpetp->hp_dev; | |
1da177e4 LT |
607 | break; |
608 | } | |
609 | case HPET_EPI: | |
610 | v = readq(&timer->hpet_config); | |
611 | if ((v & Tn_PER_INT_CAP_MASK) == 0) { | |
612 | err = -ENXIO; | |
613 | break; | |
614 | } | |
615 | devp->hd_flags |= HPET_PERIODIC; | |
616 | break; | |
617 | case HPET_DPI: | |
618 | v = readq(&timer->hpet_config); | |
619 | if ((v & Tn_PER_INT_CAP_MASK) == 0) { | |
620 | err = -ENXIO; | |
621 | break; | |
622 | } | |
623 | if (devp->hd_flags & HPET_PERIODIC && | |
624 | readq(&timer->hpet_config) & Tn_TYPE_CNF_MASK) { | |
625 | v = readq(&timer->hpet_config); | |
626 | v ^= Tn_TYPE_CNF_MASK; | |
627 | writeq(v, &timer->hpet_config); | |
628 | } | |
629 | devp->hd_flags &= ~HPET_PERIODIC; | |
630 | break; | |
631 | case HPET_IRQFREQ: | |
54066a57 | 632 | if ((arg > hpet_max_freq) && |
1da177e4 LT |
633 | !capable(CAP_SYS_RESOURCE)) { |
634 | err = -EACCES; | |
635 | break; | |
636 | } | |
637 | ||
189e2dd1 | 638 | if (!arg) { |
1da177e4 LT |
639 | err = -EINVAL; |
640 | break; | |
641 | } | |
642 | ||
ba3f213f | 643 | devp->hd_ireqfreq = hpet_time_div(hpetp, arg); |
1da177e4 LT |
644 | } |
645 | ||
646 | return err; | |
647 | } | |
648 | ||
54066a57 AB |
649 | static long |
650 | hpet_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
651 | { | |
652 | struct hpet_info info; | |
653 | int err; | |
654 | ||
655 | mutex_lock(&hpet_mutex); | |
656 | err = hpet_ioctl_common(file->private_data, cmd, arg, &info); | |
657 | mutex_unlock(&hpet_mutex); | |
658 | ||
659 | if ((cmd == HPET_INFO) && !err && | |
660 | (copy_to_user((void __user *)arg, &info, sizeof(info)))) | |
661 | err = -EFAULT; | |
662 | ||
663 | return err; | |
664 | } | |
665 | ||
666 | #ifdef CONFIG_COMPAT | |
667 | struct compat_hpet_info { | |
668 | compat_ulong_t hi_ireqfreq; /* Hz */ | |
669 | compat_ulong_t hi_flags; /* information */ | |
670 | unsigned short hi_hpet; | |
671 | unsigned short hi_timer; | |
672 | }; | |
673 | ||
674 | static long | |
675 | hpet_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
676 | { | |
677 | struct hpet_info info; | |
678 | int err; | |
679 | ||
680 | mutex_lock(&hpet_mutex); | |
681 | err = hpet_ioctl_common(file->private_data, cmd, arg, &info); | |
682 | mutex_unlock(&hpet_mutex); | |
683 | ||
684 | if ((cmd == HPET_INFO) && !err) { | |
685 | struct compat_hpet_info __user *u = compat_ptr(arg); | |
686 | if (put_user(info.hi_ireqfreq, &u->hi_ireqfreq) || | |
687 | put_user(info.hi_flags, &u->hi_flags) || | |
688 | put_user(info.hi_hpet, &u->hi_hpet) || | |
689 | put_user(info.hi_timer, &u->hi_timer)) | |
690 | err = -EFAULT; | |
691 | } | |
692 | ||
693 | return err; | |
694 | } | |
695 | #endif | |
696 | ||
62322d25 | 697 | static const struct file_operations hpet_fops = { |
1da177e4 LT |
698 | .owner = THIS_MODULE, |
699 | .llseek = no_llseek, | |
700 | .read = hpet_read, | |
701 | .poll = hpet_poll, | |
55929332 | 702 | .unlocked_ioctl = hpet_ioctl, |
54066a57 AB |
703 | #ifdef CONFIG_COMPAT |
704 | .compat_ioctl = hpet_compat_ioctl, | |
705 | #endif | |
1da177e4 LT |
706 | .open = hpet_open, |
707 | .release = hpet_release, | |
708 | .fasync = hpet_fasync, | |
709 | .mmap = hpet_mmap, | |
710 | }; | |
711 | ||
3e6716e7 RD |
712 | static int hpet_is_known(struct hpet_data *hdp) |
713 | { | |
714 | struct hpets *hpetp; | |
715 | ||
716 | for (hpetp = hpets; hpetp; hpetp = hpetp->hp_next) | |
717 | if (hpetp->hp_hpet_phys == hdp->hd_phys_address) | |
718 | return 1; | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
1da177e4 LT |
723 | static ctl_table hpet_table[] = { |
724 | { | |
1da177e4 LT |
725 | .procname = "max-user-freq", |
726 | .data = &hpet_max_freq, | |
727 | .maxlen = sizeof(int), | |
728 | .mode = 0644, | |
6d456111 | 729 | .proc_handler = proc_dointvec, |
1da177e4 | 730 | }, |
894d2491 | 731 | {} |
1da177e4 LT |
732 | }; |
733 | ||
734 | static ctl_table hpet_root[] = { | |
735 | { | |
1da177e4 LT |
736 | .procname = "hpet", |
737 | .maxlen = 0, | |
738 | .mode = 0555, | |
739 | .child = hpet_table, | |
740 | }, | |
894d2491 | 741 | {} |
1da177e4 LT |
742 | }; |
743 | ||
744 | static ctl_table dev_root[] = { | |
745 | { | |
1da177e4 LT |
746 | .procname = "dev", |
747 | .maxlen = 0, | |
748 | .mode = 0555, | |
749 | .child = hpet_root, | |
750 | }, | |
894d2491 | 751 | {} |
1da177e4 LT |
752 | }; |
753 | ||
754 | static struct ctl_table_header *sysctl_header; | |
755 | ||
1da177e4 LT |
756 | /* |
757 | * Adjustment for when arming the timer with | |
758 | * initial conditions. That is, main counter | |
759 | * ticks expired before interrupts are enabled. | |
760 | */ | |
761 | #define TICK_CALIBRATE (1000UL) | |
762 | ||
303d379c | 763 | static unsigned long __hpet_calibrate(struct hpets *hpetp) |
1da177e4 LT |
764 | { |
765 | struct hpet_timer __iomem *timer = NULL; | |
766 | unsigned long t, m, count, i, flags, start; | |
767 | struct hpet_dev *devp; | |
768 | int j; | |
769 | struct hpet __iomem *hpet; | |
770 | ||
771 | for (j = 0, devp = hpetp->hp_dev; j < hpetp->hp_ntimer; j++, devp++) | |
772 | if ((devp->hd_flags & HPET_OPEN) == 0) { | |
773 | timer = devp->hd_timer; | |
774 | break; | |
775 | } | |
776 | ||
777 | if (!timer) | |
778 | return 0; | |
779 | ||
3d5640d1 | 780 | hpet = hpetp->hp_hpet; |
1da177e4 LT |
781 | t = read_counter(&timer->hpet_compare); |
782 | ||
783 | i = 0; | |
ba3f213f | 784 | count = hpet_time_div(hpetp, TICK_CALIBRATE); |
1da177e4 LT |
785 | |
786 | local_irq_save(flags); | |
787 | ||
788 | start = read_counter(&hpet->hpet_mc); | |
789 | ||
790 | do { | |
791 | m = read_counter(&hpet->hpet_mc); | |
792 | write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare); | |
793 | } while (i++, (m - start) < count); | |
794 | ||
795 | local_irq_restore(flags); | |
796 | ||
797 | return (m - start) / i; | |
798 | } | |
799 | ||
303d379c YG |
800 | static unsigned long hpet_calibrate(struct hpets *hpetp) |
801 | { | |
802 | unsigned long ret = -1; | |
803 | unsigned long tmp; | |
804 | ||
805 | /* | |
806 | * Try to calibrate until return value becomes stable small value. | |
807 | * If SMI interruption occurs in calibration loop, the return value | |
808 | * will be big. This avoids its impact. | |
809 | */ | |
810 | for ( ; ; ) { | |
811 | tmp = __hpet_calibrate(hpetp); | |
812 | if (ret <= tmp) | |
813 | break; | |
814 | ret = tmp; | |
815 | } | |
816 | ||
817 | return ret; | |
818 | } | |
819 | ||
1da177e4 LT |
820 | int hpet_alloc(struct hpet_data *hdp) |
821 | { | |
5761d64b | 822 | u64 cap, mcfg; |
1da177e4 | 823 | struct hpet_dev *devp; |
5761d64b | 824 | u32 i, ntimer; |
1da177e4 LT |
825 | struct hpets *hpetp; |
826 | size_t siz; | |
827 | struct hpet __iomem *hpet; | |
0ca01763 | 828 | static struct hpets *last; |
5761d64b | 829 | unsigned long period; |
ba3f213f | 830 | unsigned long long temp; |
f92a789d | 831 | u32 remainder; |
1da177e4 LT |
832 | |
833 | /* | |
834 | * hpet_alloc can be called by platform dependent code. | |
3e6716e7 RD |
835 | * If platform dependent code has allocated the hpet that |
836 | * ACPI has also reported, then we catch it here. | |
1da177e4 | 837 | */ |
3e6716e7 RD |
838 | if (hpet_is_known(hdp)) { |
839 | printk(KERN_DEBUG "%s: duplicate HPET ignored\n", | |
bf9d8929 | 840 | __func__); |
3e6716e7 RD |
841 | return 0; |
842 | } | |
1da177e4 LT |
843 | |
844 | siz = sizeof(struct hpets) + ((hdp->hd_nirqs - 1) * | |
845 | sizeof(struct hpet_dev)); | |
846 | ||
3e6716e7 | 847 | hpetp = kzalloc(siz, GFP_KERNEL); |
1da177e4 LT |
848 | |
849 | if (!hpetp) | |
850 | return -ENOMEM; | |
851 | ||
1da177e4 LT |
852 | hpetp->hp_which = hpet_nhpet++; |
853 | hpetp->hp_hpet = hdp->hd_address; | |
854 | hpetp->hp_hpet_phys = hdp->hd_phys_address; | |
855 | ||
856 | hpetp->hp_ntimer = hdp->hd_nirqs; | |
e3f37a54 | 857 | |
5761d64b TG |
858 | for (i = 0; i < hdp->hd_nirqs; i++) |
859 | hpetp->hp_dev[i].hd_hdwirq = hdp->hd_irq[i]; | |
37a47db8 | 860 | |
5761d64b | 861 | hpet = hpetp->hp_hpet; |
e3f37a54 | 862 | |
1da177e4 LT |
863 | cap = readq(&hpet->hpet_cap); |
864 | ||
865 | ntimer = ((cap & HPET_NUM_TIM_CAP_MASK) >> HPET_NUM_TIM_CAP_SHIFT) + 1; | |
866 | ||
867 | if (hpetp->hp_ntimer != ntimer) { | |
868 | printk(KERN_WARNING "hpet: number irqs doesn't agree" | |
869 | " with number of timers\n"); | |
870 | kfree(hpetp); | |
871 | return -ENODEV; | |
872 | } | |
873 | ||
874 | if (last) | |
875 | last->hp_next = hpetp; | |
876 | else | |
877 | hpets = hpetp; | |
878 | ||
879 | last = hpetp; | |
880 | ||
ba3f213f CL |
881 | period = (cap & HPET_COUNTER_CLK_PERIOD_MASK) >> |
882 | HPET_COUNTER_CLK_PERIOD_SHIFT; /* fs, 10^-15 */ | |
883 | temp = 1000000000000000uLL; /* 10^15 femtoseconds per second */ | |
884 | temp += period >> 1; /* round */ | |
885 | do_div(temp, period); | |
886 | hpetp->hp_tick_freq = temp; /* ticks per second */ | |
1da177e4 | 887 | |
3034d11c AK |
888 | printk(KERN_INFO "hpet%d: at MMIO 0x%lx, IRQ%s", |
889 | hpetp->hp_which, hdp->hd_phys_address, | |
1da177e4 LT |
890 | hpetp->hp_ntimer > 1 ? "s" : ""); |
891 | for (i = 0; i < hpetp->hp_ntimer; i++) | |
5761d64b | 892 | printk("%s %d", i > 0 ? "," : "", hdp->hd_irq[i]); |
1da177e4 LT |
893 | printk("\n"); |
894 | ||
f92a789d DB |
895 | temp = hpetp->hp_tick_freq; |
896 | remainder = do_div(temp, 1000000); | |
64a76f66 DB |
897 | printk(KERN_INFO |
898 | "hpet%u: %u comparators, %d-bit %u.%06u MHz counter\n", | |
899 | hpetp->hp_which, hpetp->hp_ntimer, | |
900 | cap & HPET_COUNTER_SIZE_MASK ? 64 : 32, | |
f92a789d | 901 | (unsigned) temp, remainder); |
1da177e4 LT |
902 | |
903 | mcfg = readq(&hpet->hpet_config); | |
904 | if ((mcfg & HPET_ENABLE_CNF_MASK) == 0) { | |
905 | write_counter(0L, &hpet->hpet_mc); | |
906 | mcfg |= HPET_ENABLE_CNF_MASK; | |
907 | writeq(mcfg, &hpet->hpet_config); | |
908 | } | |
909 | ||
642d30bb | 910 | for (i = 0, devp = hpetp->hp_dev; i < hpetp->hp_ntimer; i++, devp++) { |
1da177e4 LT |
911 | struct hpet_timer __iomem *timer; |
912 | ||
913 | timer = &hpet->hpet_timers[devp - hpetp->hp_dev]; | |
1da177e4 LT |
914 | |
915 | devp->hd_hpets = hpetp; | |
916 | devp->hd_hpet = hpet; | |
917 | devp->hd_timer = timer; | |
918 | ||
919 | /* | |
920 | * If the timer was reserved by platform code, | |
921 | * then make timer unavailable for opens. | |
922 | */ | |
923 | if (hdp->hd_state & (1 << i)) { | |
924 | devp->hd_flags = HPET_OPEN; | |
925 | continue; | |
926 | } | |
927 | ||
928 | init_waitqueue_head(&devp->hd_waitqueue); | |
929 | } | |
930 | ||
931 | hpetp->hp_delta = hpet_calibrate(hpetp); | |
0aa366f3 | 932 | |
3b2b64fd LT |
933 | /* This clocksource driver currently only works on ia64 */ |
934 | #ifdef CONFIG_IA64 | |
0aa366f3 TL |
935 | if (!hpet_clocksource) { |
936 | hpet_mctr = (void __iomem *)&hpetp->hp_hpet->hpet_mc; | |
937 | CLKSRC_FSYS_MMIO_SET(clocksource_hpet.fsys_mmio, hpet_mctr); | |
938 | clocksource_hpet.mult = clocksource_hz2mult(hpetp->hp_tick_freq, | |
939 | clocksource_hpet.shift); | |
940 | clocksource_register(&clocksource_hpet); | |
941 | hpetp->hp_clocksource = &clocksource_hpet; | |
942 | hpet_clocksource = &clocksource_hpet; | |
943 | } | |
3b2b64fd | 944 | #endif |
1da177e4 LT |
945 | |
946 | return 0; | |
947 | } | |
948 | ||
949 | static acpi_status hpet_resources(struct acpi_resource *res, void *data) | |
950 | { | |
951 | struct hpet_data *hdp; | |
952 | acpi_status status; | |
953 | struct acpi_resource_address64 addr; | |
1da177e4 LT |
954 | |
955 | hdp = data; | |
956 | ||
957 | status = acpi_resource_to_address64(res, &addr); | |
958 | ||
959 | if (ACPI_SUCCESS(status)) { | |
50eca3eb | 960 | hdp->hd_phys_address = addr.minimum; |
9224a867 | 961 | hdp->hd_address = ioremap(addr.minimum, addr.address_length); |
1da177e4 | 962 | |
3e6716e7 | 963 | if (hpet_is_known(hdp)) { |
3e6716e7 | 964 | iounmap(hdp->hd_address); |
78e1ca49 | 965 | return AE_ALREADY_EXISTS; |
3e6716e7 | 966 | } |
50eca3eb BM |
967 | } else if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { |
968 | struct acpi_resource_fixed_memory32 *fixmem32; | |
757c4724 RD |
969 | |
970 | fixmem32 = &res->data.fixed_memory32; | |
971 | if (!fixmem32) | |
78e1ca49 | 972 | return AE_NO_MEMORY; |
757c4724 | 973 | |
50eca3eb BM |
974 | hdp->hd_phys_address = fixmem32->address; |
975 | hdp->hd_address = ioremap(fixmem32->address, | |
757c4724 RD |
976 | HPET_RANGE_SIZE); |
977 | ||
3e6716e7 | 978 | if (hpet_is_known(hdp)) { |
3e6716e7 | 979 | iounmap(hdp->hd_address); |
78e1ca49 | 980 | return AE_ALREADY_EXISTS; |
3e6716e7 | 981 | } |
50eca3eb BM |
982 | } else if (res->type == ACPI_RESOURCE_TYPE_EXTENDED_IRQ) { |
983 | struct acpi_resource_extended_irq *irqp; | |
be5efffb | 984 | int i, irq; |
1da177e4 LT |
985 | |
986 | irqp = &res->data.extended_irq; | |
987 | ||
be5efffb | 988 | for (i = 0; i < irqp->interrupt_count; i++) { |
a2f809b0 | 989 | irq = acpi_register_gsi(NULL, irqp->interrupts[i], |
be5efffb BH |
990 | irqp->triggering, irqp->polarity); |
991 | if (irq < 0) | |
992 | return AE_ERROR; | |
993 | ||
994 | hdp->hd_irq[hdp->hd_nirqs] = irq; | |
995 | hdp->hd_nirqs++; | |
1da177e4 LT |
996 | } |
997 | } | |
998 | ||
999 | return AE_OK; | |
1000 | } | |
1001 | ||
1002 | static int hpet_acpi_add(struct acpi_device *device) | |
1003 | { | |
1004 | acpi_status result; | |
1005 | struct hpet_data data; | |
1006 | ||
1007 | memset(&data, 0, sizeof(data)); | |
1008 | ||
1009 | result = | |
1010 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, | |
1011 | hpet_resources, &data); | |
1012 | ||
1013 | if (ACPI_FAILURE(result)) | |
1014 | return -ENODEV; | |
1015 | ||
1016 | if (!data.hd_address || !data.hd_nirqs) { | |
a56d5318 JS |
1017 | if (data.hd_address) |
1018 | iounmap(data.hd_address); | |
bf9d8929 | 1019 | printk("%s: no address or irqs in _CRS\n", __func__); |
1da177e4 LT |
1020 | return -ENODEV; |
1021 | } | |
1022 | ||
1023 | return hpet_alloc(&data); | |
1024 | } | |
1025 | ||
1026 | static int hpet_acpi_remove(struct acpi_device *device, int type) | |
1027 | { | |
0aa366f3 | 1028 | /* XXX need to unregister clocksource, dealloc mem, etc */ |
1da177e4 LT |
1029 | return -EINVAL; |
1030 | } | |
1031 | ||
1ba90e3a TR |
1032 | static const struct acpi_device_id hpet_device_ids[] = { |
1033 | {"PNP0103", 0}, | |
1034 | {"", 0}, | |
1035 | }; | |
1036 | MODULE_DEVICE_TABLE(acpi, hpet_device_ids); | |
1037 | ||
1da177e4 LT |
1038 | static struct acpi_driver hpet_acpi_driver = { |
1039 | .name = "hpet", | |
1ba90e3a | 1040 | .ids = hpet_device_ids, |
1da177e4 LT |
1041 | .ops = { |
1042 | .add = hpet_acpi_add, | |
1043 | .remove = hpet_acpi_remove, | |
1044 | }, | |
1045 | }; | |
1046 | ||
1047 | static struct miscdevice hpet_misc = { HPET_MINOR, "hpet", &hpet_fops }; | |
1048 | ||
1049 | static int __init hpet_init(void) | |
1050 | { | |
1051 | int result; | |
1052 | ||
1053 | result = misc_register(&hpet_misc); | |
1054 | if (result < 0) | |
1055 | return -ENODEV; | |
1056 | ||
0b4d4147 | 1057 | sysctl_header = register_sysctl_table(dev_root); |
1da177e4 LT |
1058 | |
1059 | result = acpi_bus_register_driver(&hpet_acpi_driver); | |
1060 | if (result < 0) { | |
1061 | if (sysctl_header) | |
1062 | unregister_sysctl_table(sysctl_header); | |
1063 | misc_deregister(&hpet_misc); | |
1064 | return result; | |
1065 | } | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static void __exit hpet_exit(void) | |
1071 | { | |
1072 | acpi_bus_unregister_driver(&hpet_acpi_driver); | |
1073 | ||
1074 | if (sysctl_header) | |
1075 | unregister_sysctl_table(sysctl_header); | |
1076 | misc_deregister(&hpet_misc); | |
1077 | ||
1078 | return; | |
1079 | } | |
1080 | ||
1081 | module_init(hpet_init); | |
1082 | module_exit(hpet_exit); | |
1083 | MODULE_AUTHOR("Bob Picco <Robert.Picco@hp.com>"); | |
1084 | MODULE_LICENSE("GPL"); |