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radeon: setup the ring buffer fetcher to be less agressive.
[net-next-2.6.git] / drivers / char / drm / radeon_drv.h
CommitLineData
1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
d6fece05 41#define DRIVER_DATE "20060524"
1da177e4
LT		 42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
b5e89ed5 71 * clients use to tell the DRM where they think the framebuffer is
1da177e4
LT		 72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
d985c108 76 * (No 3D support yet - just microcode loading).
1da177e4
LT		 77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
414ed537 85 * 1.17- Add initial support for R300 (3D).
9d17601c
DA		 86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
ea98a92f 90 * 1.19- Add support for gart table in FB memory and PCIE r300
d985c108
DA		 91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
4e5e2e25 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
d5ea702f 94 * 1.23- Add new radeon memory map work from benh
ee4621f0 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
d6fece05
DA		 96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
f2b04cd2
DA		 98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
ddbee333 100 * 1.28- Add support for VBL on CRTC2
1da177e4
LT		 101 */
102#define DRIVER_MAJOR 1
ddbee333 103#define DRIVER_MINOR 28
1da177e4
LT		 104#define DRIVER_PATCHLEVEL 0
105
1da177e4
LT		 106/*
107 * Radeon chip families
108 */
109enum radeon_family {
110 CHIP_R100,
1da177e4 111 CHIP_RV100,
dfab1154 112 CHIP_RS100,
1da177e4
LT		 113 CHIP_RV200,
114 CHIP_RS200,
dfab1154 115 CHIP_R200,
1da177e4 116 CHIP_RV250,
dfab1154 117 CHIP_RS300,
1da177e4
LT		 118 CHIP_RV280,
119 CHIP_R300,
414ed537 120 CHIP_R350,
1da177e4 121 CHIP_RV350,
dfab1154 122 CHIP_RV380,
414ed537 123 CHIP_R420,
dfab1154
DA		 124 CHIP_RV410,
125 CHIP_RS400,
1da177e4
LT		 126 CHIP_LAST,
127};
128
129enum radeon_cp_microcode_version {
130 UCODE_R100,
131 UCODE_R200,
132 UCODE_R300,
133};
134
135/*
136 * Chip flags
137 */
138enum radeon_chip_flags {
54a56ac5
DA		 139 RADEON_FAMILY_MASK = 0x0000ffffUL,
140 RADEON_FLAGS_MASK = 0xffff0000UL,
141 RADEON_IS_MOBILITY = 0x00010000UL,
142 RADEON_IS_IGP = 0x00020000UL,
143 RADEON_SINGLE_CRTC = 0x00040000UL,
144 RADEON_IS_AGP = 0x00080000UL,
145 RADEON_HAS_HIERZ = 0x00100000UL,
146 RADEON_IS_PCIE = 0x00200000UL,
147 RADEON_NEW_MEMMAP = 0x00400000UL,
148 RADEON_IS_PCI = 0x00800000UL,
f2b04cd2 149 RADEON_IS_IGPGART = 0x01000000UL,
1da177e4
LT		 150};
151
d5ea702f
DA		 152#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
153 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
d985c108
DA		 154#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
155
1da177e4 156typedef struct drm_radeon_freelist {
b5e89ed5 157 unsigned int age;
056219e2 158 struct drm_buf *buf;
b5e89ed5
DA		 159 struct drm_radeon_freelist *next;
160 struct drm_radeon_freelist *prev;
1da177e4
LT		 161} drm_radeon_freelist_t;
162
163typedef struct drm_radeon_ring_buffer {
164 u32 *start;
165 u32 *end;
166 int size;
167 int size_l2qw;
168
576cc458
RS		 169 int rptr_update; /* Double Words */
170 int rptr_update_l2qw; /* log2 Quad Words */
171
172 int fetch_size; /* Double Words */
173 int fetch_size_l2ow; /* log2 Oct Words */
174
1da177e4
LT		 175 u32 tail;
176 u32 tail_mask;
177 int space;
178
179 int high_mark;
180} drm_radeon_ring_buffer_t;
181
182typedef struct drm_radeon_depth_clear_t {
183 u32 rb3d_cntl;
184 u32 rb3d_zstencilcntl;
185 u32 se_cntl;
186} drm_radeon_depth_clear_t;
187
188struct drm_radeon_driver_file_fields {
189 int64_t radeon_fb_delta;
190};
191
192struct mem_block {
193 struct mem_block *next;
194 struct mem_block *prev;
195 int start;
196 int size;
6c340eac 197 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 198};
199
200struct radeon_surface {
201 int refcount;
202 u32 lower;
203 u32 upper;
204 u32 flags;
205};
206
207struct radeon_virt_surface {
208 int surface_index;
209 u32 lower;
210 u32 upper;
211 u32 flags;
6c340eac 212 struct drm_file *file_priv;
1da177e4
LT		 213};
214
215typedef struct drm_radeon_private {
216 drm_radeon_ring_buffer_t ring;
217 drm_radeon_sarea_t *sarea_priv;
218
219 u32 fb_location;
d5ea702f
DA		 220 u32 fb_size;
221 int new_memmap;
1da177e4
LT		 222
223 int gart_size;
224 u32 gart_vm_start;
225 unsigned long gart_buffers_offset;
226
227 int cp_mode;
228 int cp_running;
229
b5e89ed5
DA		 230 drm_radeon_freelist_t *head;
231 drm_radeon_freelist_t *tail;
1da177e4
LT		 232 int last_buf;
233 volatile u32 *scratch;
234 int writeback_works;
235
236 int usec_timeout;
237
238 int microcode_version;
239
1da177e4
LT		 240 struct {
241 u32 boxes;
242 int freelist_timeouts;
243 int freelist_loops;
244 int requested_bufs;
245 int last_frame_reads;
246 int last_clear_reads;
247 int clears;
248 int texture_uploads;
249 } stats;
250
251 int do_boxes;
252 int page_flipping;
1da177e4
LT		 253
254 u32 color_fmt;
255 unsigned int front_offset;
256 unsigned int front_pitch;
257 unsigned int back_offset;
258 unsigned int back_pitch;
259
260 u32 depth_fmt;
261 unsigned int depth_offset;
262 unsigned int depth_pitch;
263
264 u32 front_pitch_offset;
265 u32 back_pitch_offset;
266 u32 depth_pitch_offset;
267
268 drm_radeon_depth_clear_t depth_clear;
b5e89ed5 269
1da177e4
LT		 270 unsigned long ring_offset;
271 unsigned long ring_rptr_offset;
272 unsigned long buffers_offset;
273 unsigned long gart_textures_offset;
274
275 drm_local_map_t *sarea;
276 drm_local_map_t *mmio;
277 drm_local_map_t *cp_ring;
278 drm_local_map_t *ring_rptr;
279 drm_local_map_t *gart_textures;
280
281 struct mem_block *gart_heap;
282 struct mem_block *fb_heap;
283
284 /* SW interrupt */
b5e89ed5
DA		 285 wait_queue_head_t swi_queue;
286 atomic_t swi_emitted;
ddbee333
DA		 287 int vblank_crtc;
288 uint32_t irq_enable_reg;
289 int irq_enabled;
1da177e4
LT		 290
291 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
b5e89ed5 292 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
1da177e4 293
b5e89ed5 294 unsigned long pcigart_offset;
f2b04cd2 295 unsigned int pcigart_offset_set;
55910517 296 struct drm_ati_pcigart_info gart_info;
ea98a92f 297
ee4621f0
DA		 298 u32 scratch_ages[5];
299
1da177e4
LT		 300 /* starting from here on, data is preserved accross an open */
301 uint32_t flags; /* see radeon_chip_flags */
7fc86860 302 unsigned long fb_aper_offset;
1da177e4
LT		 303} drm_radeon_private_t;
304
305typedef struct drm_radeon_buf_priv {
306 u32 age;
307} drm_radeon_buf_priv_t;
308
b3a83639
DA		 309typedef struct drm_radeon_kcmd_buffer {
310 int bufsz;
311 char *buf;
312 int nbox;
c60ce623 313 struct drm_clip_rect __user *boxes;
b3a83639
DA		 314} drm_radeon_kcmd_buffer_t;
315
689b9d74 316extern int radeon_no_wb;
c153f45f 317extern struct drm_ioctl_desc radeon_ioctls[];
b3a83639
DA		 318extern int radeon_max_ioctl;
319
1d6bb8e5
MD		 320/* Check whether the given hardware address is inside the framebuffer or the
321 * GART area.
322 */
323static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
324 u64 off)
325{
326 u32 fb_start = dev_priv->fb_location;
327 u32 fb_end = fb_start + dev_priv->fb_size - 1;
328 u32 gart_start = dev_priv->gart_vm_start;
329 u32 gart_end = gart_start + dev_priv->gart_size - 1;
330
331 return ((off >= fb_start && off <= fb_end) ||
332 (off >= gart_start && off <= gart_end));
333}
334
1da177e4 335 /* radeon_cp.c */
c153f45f
EA		 336extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
337extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
338extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
339extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
340extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
341extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
342extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
343extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
344extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
1da177e4 345
84b1fd10 346extern void radeon_freelist_reset(struct drm_device * dev);
056219e2 347extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
1da177e4 348
b5e89ed5 349extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
1da177e4 350
b5e89ed5 351extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
1da177e4
LT		 352
353extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 354extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 355extern int radeon_driver_postcleanup(struct drm_device *dev);
356
c153f45f
EA		 357extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
358extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
359extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
b5e89ed5 360extern void radeon_mem_takedown(struct mem_block **heap);
6c340eac
EA		 361extern void radeon_mem_release(struct drm_file *file_priv,
362 struct mem_block *heap);
1da177e4
LT		 363
364 /* radeon_irq.c */
c153f45f
EA		 365extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
366extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
b5e89ed5 367
84b1fd10
DA		 368extern void radeon_do_release(struct drm_device * dev);
369extern int radeon_driver_vblank_wait(struct drm_device * dev,
b5e89ed5 370 unsigned int *sequence);
84b1fd10 371extern int radeon_driver_vblank_wait2(struct drm_device * dev,
ddbee333 372 unsigned int *sequence);
b5e89ed5 373extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10
DA		 374extern void radeon_driver_irq_preinstall(struct drm_device * dev);
375extern void radeon_driver_irq_postinstall(struct drm_device * dev);
376extern void radeon_driver_irq_uninstall(struct drm_device * dev);
377extern int radeon_vblank_crtc_get(struct drm_device *dev);
378extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
1da177e4 379
22eae947
DA		 380extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
381extern int radeon_driver_unload(struct drm_device *dev);
382extern int radeon_driver_firstopen(struct drm_device *dev);
6c340eac 383extern void radeon_driver_preclose(struct drm_device * dev, struct drm_file *file_priv);
84b1fd10
DA		 384extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp);
385extern void radeon_driver_lastclose(struct drm_device * dev);
386extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv);
9a186645
DA		 387extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
388 unsigned long arg);
389
414ed537
DA		 390/* r300_cmdbuf.c */
391extern void r300_init_reg_flags(void);
392
6c340eac
EA		 393extern int r300_do_cp_cmdbuf(struct drm_device * dev,
394 struct drm_file *file_priv,
b3a83639 395 drm_radeon_kcmd_buffer_t * cmdbuf);
414ed537 396
1da177e4
LT		 397/* Flags for stats.boxes
398 */
399#define RADEON_BOX_DMA_IDLE 0x1
400#define RADEON_BOX_RING_FULL 0x2
401#define RADEON_BOX_FLIP 0x4
402#define RADEON_BOX_WAIT_IDLE 0x8
403#define RADEON_BOX_TEXTURE_LOAD 0x10
404
1da177e4
LT		 405/* Register definitions, register access macros and drmAddMap constants
406 * for Radeon kernel driver.
407 */
408
409#define RADEON_AGP_COMMAND 0x0f60
d985c108
DA		 410#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
411# define RADEON_AGP_ENABLE (1<<8)
1da177e4
LT		 412#define RADEON_AUX_SCISSOR_CNTL 0x26f0
413# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
414# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
415# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
416# define RADEON_SCISSOR_0_ENABLE (1 << 28)
417# define RADEON_SCISSOR_1_ENABLE (1 << 29)
418# define RADEON_SCISSOR_2_ENABLE (1 << 30)
419
420#define RADEON_BUS_CNTL 0x0030
421# define RADEON_BUS_MASTER_DIS (1 << 6)
422
423#define RADEON_CLOCK_CNTL_DATA 0x000c
424# define RADEON_PLL_WR_EN (1 << 7)
425#define RADEON_CLOCK_CNTL_INDEX 0x0008
426#define RADEON_CONFIG_APER_SIZE 0x0108
d985c108 427#define RADEON_CONFIG_MEMSIZE 0x00f8
1da177e4
LT		 428#define RADEON_CRTC_OFFSET 0x0224
429#define RADEON_CRTC_OFFSET_CNTL 0x0228
430# define RADEON_CRTC_TILE_EN (1 << 15)
431# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
432#define RADEON_CRTC2_OFFSET 0x0324
433#define RADEON_CRTC2_OFFSET_CNTL 0x0328
434
ea98a92f
DA		 435#define RADEON_PCIE_INDEX 0x0030
436#define RADEON_PCIE_DATA 0x0034
437#define RADEON_PCIE_TX_GART_CNTL 0x10
bc5f4523 438# define RADEON_PCIE_TX_GART_EN (1 << 0)
ea98a92f
DA		 439# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
440# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
441# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
442# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
443# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
444# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
445# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
446#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
447#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
bc5f4523 448#define RADEON_PCIE_TX_GART_BASE 0x13
ea98a92f
DA		 449#define RADEON_PCIE_TX_GART_START_LO 0x14
450#define RADEON_PCIE_TX_GART_START_HI 0x15
451#define RADEON_PCIE_TX_GART_END_LO 0x16
452#define RADEON_PCIE_TX_GART_END_HI 0x17
453
f2b04cd2
DA		 454#define RADEON_IGPGART_INDEX 0x168
455#define RADEON_IGPGART_DATA 0x16c
456#define RADEON_IGPGART_UNK_18 0x18
457#define RADEON_IGPGART_CTRL 0x2b
458#define RADEON_IGPGART_BASE_ADDR 0x2c
459#define RADEON_IGPGART_FLUSH 0x2e
460#define RADEON_IGPGART_ENABLE 0x38
461#define RADEON_IGPGART_UNK_39 0x39
462
414ed537
DA		 463#define RADEON_MPP_TB_CONFIG 0x01c0
464#define RADEON_MEM_CNTL 0x0140
465#define RADEON_MEM_SDRAM_MODE_REG 0x0158
466#define RADEON_AGP_BASE 0x0170
467
1da177e4
LT		 468#define RADEON_RB3D_COLOROFFSET 0x1c40
469#define RADEON_RB3D_COLORPITCH 0x1c48
470
3e14a286
MD		 471#define RADEON_SRC_X_Y 0x1590
472
1da177e4
LT		 473#define RADEON_DP_GUI_MASTER_CNTL 0x146c
474# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
475# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
476# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
477# define RADEON_GMC_BRUSH_NONE (15 << 4)
478# define RADEON_GMC_DST_16BPP (4 << 8)
479# define RADEON_GMC_DST_24BPP (5 << 8)
480# define RADEON_GMC_DST_32BPP (6 << 8)
481# define RADEON_GMC_DST_DATATYPE_SHIFT 8
482# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
483# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
484# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
485# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
486# define RADEON_GMC_WR_MSK_DIS (1 << 30)
487# define RADEON_ROP3_S 0x00cc0000
488# define RADEON_ROP3_P 0x00f00000
489#define RADEON_DP_WRITE_MASK 0x16cc
3e14a286 490#define RADEON_SRC_PITCH_OFFSET 0x1428
1da177e4
LT		 491#define RADEON_DST_PITCH_OFFSET 0x142c
492#define RADEON_DST_PITCH_OFFSET_C 0x1c80
493# define RADEON_DST_TILE_LINEAR (0 << 30)
494# define RADEON_DST_TILE_MACRO (1 << 30)
495# define RADEON_DST_TILE_MICRO (2 << 30)
496# define RADEON_DST_TILE_BOTH (3 << 30)
497
498#define RADEON_SCRATCH_REG0 0x15e0
499#define RADEON_SCRATCH_REG1 0x15e4
500#define RADEON_SCRATCH_REG2 0x15e8
501#define RADEON_SCRATCH_REG3 0x15ec
502#define RADEON_SCRATCH_REG4 0x15f0
503#define RADEON_SCRATCH_REG5 0x15f4
504#define RADEON_SCRATCH_UMSK 0x0770
505#define RADEON_SCRATCH_ADDR 0x0774
506
507#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
508
509#define GET_SCRATCH( x ) (dev_priv->writeback_works \
510 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
511 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
512
1da177e4
LT		 513#define RADEON_GEN_INT_CNTL 0x0040
514# define RADEON_CRTC_VBLANK_MASK (1 << 0)
ddbee333 515# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
1da177e4
LT		 516# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
517# define RADEON_SW_INT_ENABLE (1 << 25)
518
519#define RADEON_GEN_INT_STATUS 0x0044
520# define RADEON_CRTC_VBLANK_STAT (1 << 0)
bc5f4523 521# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
ddbee333 522# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
bc5f4523 523# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
1da177e4
LT		 524# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
525# define RADEON_SW_INT_TEST (1 << 25)
bc5f4523 526# define RADEON_SW_INT_TEST_ACK (1 << 25)
1da177e4
LT		 527# define RADEON_SW_INT_FIRE (1 << 26)
528
529#define RADEON_HOST_PATH_CNTL 0x0130
530# define RADEON_HDP_SOFT_RESET (1 << 26)
531# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
532# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
533
534#define RADEON_ISYNC_CNTL 0x1724
535# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
536# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
537# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
538# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
539# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
540# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
541
542#define RADEON_RBBM_GUICNTL 0x172c
543# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
544# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
545# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
546# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
547
548#define RADEON_MC_AGP_LOCATION 0x014c
549#define RADEON_MC_FB_LOCATION 0x0148
550#define RADEON_MCLK_CNTL 0x0012
551# define RADEON_FORCEON_MCLKA (1 << 16)
552# define RADEON_FORCEON_MCLKB (1 << 17)
553# define RADEON_FORCEON_YCLKA (1 << 18)
554# define RADEON_FORCEON_YCLKB (1 << 19)
555# define RADEON_FORCEON_MC (1 << 20)
556# define RADEON_FORCEON_AIC (1 << 21)
557
558#define RADEON_PP_BORDER_COLOR_0 0x1d40
559#define RADEON_PP_BORDER_COLOR_1 0x1d44
560#define RADEON_PP_BORDER_COLOR_2 0x1d48
561#define RADEON_PP_CNTL 0x1c38
562# define RADEON_SCISSOR_ENABLE (1 << 1)
563#define RADEON_PP_LUM_MATRIX 0x1d00
564#define RADEON_PP_MISC 0x1c14
565#define RADEON_PP_ROT_MATRIX_0 0x1d58
566#define RADEON_PP_TXFILTER_0 0x1c54
567#define RADEON_PP_TXOFFSET_0 0x1c5c
568#define RADEON_PP_TXFILTER_1 0x1c6c
569#define RADEON_PP_TXFILTER_2 0x1c84
570
571#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
572# define RADEON_RB2D_DC_FLUSH (3 << 0)
573# define RADEON_RB2D_DC_FREE (3 << 2)
574# define RADEON_RB2D_DC_FLUSH_ALL 0xf
575# define RADEON_RB2D_DC_BUSY (1 << 31)
576#define RADEON_RB3D_CNTL 0x1c3c
577# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
578# define RADEON_PLANE_MASK_ENABLE (1 << 1)
579# define RADEON_DITHER_ENABLE (1 << 2)
580# define RADEON_ROUND_ENABLE (1 << 3)
581# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
582# define RADEON_DITHER_INIT (1 << 5)
583# define RADEON_ROP_ENABLE (1 << 6)
584# define RADEON_STENCIL_ENABLE (1 << 7)
585# define RADEON_Z_ENABLE (1 << 8)
586# define RADEON_ZBLOCK16 (1 << 15)
587#define RADEON_RB3D_DEPTHOFFSET 0x1c24
588#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
589#define RADEON_RB3D_DEPTHPITCH 0x1c28
590#define RADEON_RB3D_PLANEMASK 0x1d84
591#define RADEON_RB3D_STENCILREFMASK 0x1d7c
592#define RADEON_RB3D_ZCACHE_MODE 0x3250
593#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
594# define RADEON_RB3D_ZC_FLUSH (1 << 0)
595# define RADEON_RB3D_ZC_FREE (1 << 2)
596# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
597# define RADEON_RB3D_ZC_BUSY (1 << 31)
b9b603dd
MD		 598#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
599# define RADEON_RB3D_DC_FLUSH (3 << 0)
600# define RADEON_RB3D_DC_FREE (3 << 2)
601# define RADEON_RB3D_DC_FLUSH_ALL 0xf
602# define RADEON_RB3D_DC_BUSY (1 << 31)
1da177e4
LT		 603#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
604# define RADEON_Z_TEST_MASK (7 << 4)
605# define RADEON_Z_TEST_ALWAYS (7 << 4)
606# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
607# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
608# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
609# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
610# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
611# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
612# define RADEON_FORCE_Z_DIRTY (1 << 29)
613# define RADEON_Z_WRITE_ENABLE (1 << 30)
614# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
615#define RADEON_RBBM_SOFT_RESET 0x00f0
616# define RADEON_SOFT_RESET_CP (1 << 0)
617# define RADEON_SOFT_RESET_HI (1 << 1)
618# define RADEON_SOFT_RESET_SE (1 << 2)
619# define RADEON_SOFT_RESET_RE (1 << 3)
620# define RADEON_SOFT_RESET_PP (1 << 4)
621# define RADEON_SOFT_RESET_E2 (1 << 5)
622# define RADEON_SOFT_RESET_RB (1 << 6)
623# define RADEON_SOFT_RESET_HDP (1 << 7)
576cc458
RS		 624/*
625 * 6:0 Available slots in the FIFO
626 * 8 Host Interface active
627 * 9 CP request active
628 * 10 FIFO request active
629 * 11 Host Interface retry active
630 * 12 CP retry active
631 * 13 FIFO retry active
632 * 14 FIFO pipeline busy
633 * 15 Event engine busy
634 * 16 CP command stream busy
635 * 17 2D engine busy
636 * 18 2D portion of render backend busy
637 * 20 3D setup engine busy
638 * 26 GA engine busy
639 * 27 CBA 2D engine busy
640 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
641 * command stream queue not empty or Ring Buffer not empty
642 */
1da177e4 643#define RADEON_RBBM_STATUS 0x0e40
576cc458
RS		 644/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
645/* #define RADEON_RBBM_STATUS 0x1740 */
646/* bits 6:0 are dword slots available in the cmd fifo */
1da177e4 647# define RADEON_RBBM_FIFOCNT_MASK 0x007f
576cc458
RS		 648# define RADEON_HIRQ_ON_RBB (1 << 8)
649# define RADEON_CPRQ_ON_RBB (1 << 9)
650# define RADEON_CFRQ_ON_RBB (1 << 10)
651# define RADEON_HIRQ_IN_RTBUF (1 << 11)
652# define RADEON_CPRQ_IN_RTBUF (1 << 12)
653# define RADEON_CFRQ_IN_RTBUF (1 << 13)
654# define RADEON_PIPE_BUSY (1 << 14)
655# define RADEON_ENG_EV_BUSY (1 << 15)
656# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
657# define RADEON_E2_BUSY (1 << 17)
658# define RADEON_RB2D_BUSY (1 << 18)
659# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
660# define RADEON_VAP_BUSY (1 << 20)
661# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
662# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
663# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
664# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
665# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
666# define RADEON_GA_BUSY (1 << 26)
667# define RADEON_CBA2D_BUSY (1 << 27)
668# define RADEON_RBBM_ACTIVE (1 << 31)
1da177e4
LT		 669#define RADEON_RE_LINE_PATTERN 0x1cd0
670#define RADEON_RE_MISC 0x26c4
671#define RADEON_RE_TOP_LEFT 0x26c0
672#define RADEON_RE_WIDTH_HEIGHT 0x1c44
673#define RADEON_RE_STIPPLE_ADDR 0x1cc8
674#define RADEON_RE_STIPPLE_DATA 0x1ccc
675
676#define RADEON_SCISSOR_TL_0 0x1cd8
677#define RADEON_SCISSOR_BR_0 0x1cdc
678#define RADEON_SCISSOR_TL_1 0x1ce0
679#define RADEON_SCISSOR_BR_1 0x1ce4
680#define RADEON_SCISSOR_TL_2 0x1ce8
681#define RADEON_SCISSOR_BR_2 0x1cec
682#define RADEON_SE_COORD_FMT 0x1c50
683#define RADEON_SE_CNTL 0x1c4c
684# define RADEON_FFACE_CULL_CW (0 << 0)
685# define RADEON_BFACE_SOLID (3 << 1)
686# define RADEON_FFACE_SOLID (3 << 3)
687# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
688# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
689# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
690# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
691# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
692# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
693# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
694# define RADEON_FOG_SHADE_FLAT (1 << 14)
695# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
696# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
697# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
698# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
699# define RADEON_ROUND_MODE_TRUNC (0 << 28)
700# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
701#define RADEON_SE_CNTL_STATUS 0x2140
702#define RADEON_SE_LINE_WIDTH 0x1db8
703#define RADEON_SE_VPORT_XSCALE 0x1d98
704#define RADEON_SE_ZBIAS_FACTOR 0x1db0
705#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
706#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
707#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
708# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
709# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
710#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
711#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
712# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
713#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
714#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
715#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
716#define RADEON_SURFACE_CNTL 0x0b00
717# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
718# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
719# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
720# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
721# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
722# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
723# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
724# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
725# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
726#define RADEON_SURFACE0_INFO 0x0b0c
727# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
728# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
729# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
730# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
731# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
732# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
733#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
734#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
735# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
736#define RADEON_SURFACE1_INFO 0x0b1c
737#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
738#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
739#define RADEON_SURFACE2_INFO 0x0b2c
740#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
741#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
742#define RADEON_SURFACE3_INFO 0x0b3c
743#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
744#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
745#define RADEON_SURFACE4_INFO 0x0b4c
746#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
747#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
748#define RADEON_SURFACE5_INFO 0x0b5c
749#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
750#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
751#define RADEON_SURFACE6_INFO 0x0b6c
752#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
753#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
754#define RADEON_SURFACE7_INFO 0x0b7c
755#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
756#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
757#define RADEON_SW_SEMAPHORE 0x013c
758
759#define RADEON_WAIT_UNTIL 0x1720
760# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
d985c108
DA		 761# define RADEON_WAIT_2D_IDLE (1 << 14)
762# define RADEON_WAIT_3D_IDLE (1 << 15)
1da177e4
LT		 763# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
764# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
765# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
766
767#define RADEON_RB3D_ZMASKOFFSET 0x3234
768#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
769# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
770# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
771
1da177e4
LT		 772/* CP registers */
773#define RADEON_CP_ME_RAM_ADDR 0x07d4
774#define RADEON_CP_ME_RAM_RADDR 0x07d8
775#define RADEON_CP_ME_RAM_DATAH 0x07dc
776#define RADEON_CP_ME_RAM_DATAL 0x07e0
777
778#define RADEON_CP_RB_BASE 0x0700
779#define RADEON_CP_RB_CNTL 0x0704
780# define RADEON_BUF_SWAP_32BIT (2 << 16)
ae1b1a48 781# define RADEON_RB_NO_UPDATE (1 << 27)
1da177e4
LT		 782#define RADEON_CP_RB_RPTR_ADDR 0x070c
783#define RADEON_CP_RB_RPTR 0x0710
784#define RADEON_CP_RB_WPTR 0x0714
785
786#define RADEON_CP_RB_WPTR_DELAY 0x0718
787# define RADEON_PRE_WRITE_TIMER_SHIFT 0
788# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
789
790#define RADEON_CP_IB_BASE 0x0738
791
792#define RADEON_CP_CSQ_CNTL 0x0740
793# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
794# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
795# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
796# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
797# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
798# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
799# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
800
801#define RADEON_AIC_CNTL 0x01d0
802# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
803#define RADEON_AIC_STAT 0x01d4
804#define RADEON_AIC_PT_BASE 0x01d8
805#define RADEON_AIC_LO_ADDR 0x01dc
806#define RADEON_AIC_HI_ADDR 0x01e0
807#define RADEON_AIC_TLB_ADDR 0x01e4
808#define RADEON_AIC_TLB_DATA 0x01e8
809
810/* CP command packets */
811#define RADEON_CP_PACKET0 0x00000000
812# define RADEON_ONE_REG_WR (1 << 15)
813#define RADEON_CP_PACKET1 0x40000000
814#define RADEON_CP_PACKET2 0x80000000
815#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 816# define RADEON_CP_NOP 0x00001000
817# define RADEON_CP_NEXT_CHAR 0x00001900
818# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
819# define RADEON_CP_SET_SCISSORS 0x00001E00
b5e89ed5 820 /* GEN_INDX_PRIM is unsupported starting with R300 */
1da177e4
LT		 821# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
822# define RADEON_WAIT_FOR_IDLE 0x00002600
823# define RADEON_3D_DRAW_VBUF 0x00002800
824# define RADEON_3D_DRAW_IMMD 0x00002900
825# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 826# define RADEON_CP_LOAD_PALETTE 0x00002C00
1da177e4
LT		 827# define RADEON_3D_LOAD_VBPNTR 0x00002F00
828# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
829# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
830# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 831# define RADEON_CP_INDX_BUFFER 0x00003300
832# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
833# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
834# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 835# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 836# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1da177e4
LT		 837# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
838# define RADEON_CNTL_PAINT_MULTI 0x00009A00
839# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
840# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
841
842#define RADEON_CP_PACKET_MASK 0xC0000000
843#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
844#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
845#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
846#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
847
848#define RADEON_VTX_Z_PRESENT (1 << 31)
849#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
850
851#define RADEON_PRIM_TYPE_NONE (0 << 0)
852#define RADEON_PRIM_TYPE_POINT (1 << 0)
853#define RADEON_PRIM_TYPE_LINE (2 << 0)
854#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
855#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
856#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
857#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
858#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
859#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
860#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
861#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
862#define RADEON_PRIM_TYPE_MASK 0xf
863#define RADEON_PRIM_WALK_IND (1 << 4)
864#define RADEON_PRIM_WALK_LIST (2 << 4)
865#define RADEON_PRIM_WALK_RING (3 << 4)
866#define RADEON_COLOR_ORDER_BGRA (0 << 6)
867#define RADEON_COLOR_ORDER_RGBA (1 << 6)
868#define RADEON_MAOS_ENABLE (1 << 7)
869#define RADEON_VTX_FMT_R128_MODE (0 << 8)
870#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
871#define RADEON_NUM_VERTICES_SHIFT 16
872
873#define RADEON_COLOR_FORMAT_CI8 2
874#define RADEON_COLOR_FORMAT_ARGB1555 3
875#define RADEON_COLOR_FORMAT_RGB565 4
876#define RADEON_COLOR_FORMAT_ARGB8888 6
877#define RADEON_COLOR_FORMAT_RGB332 7
878#define RADEON_COLOR_FORMAT_RGB8 9
879#define RADEON_COLOR_FORMAT_ARGB4444 15
880
881#define RADEON_TXFORMAT_I8 0
882#define RADEON_TXFORMAT_AI88 1
883#define RADEON_TXFORMAT_RGB332 2
884#define RADEON_TXFORMAT_ARGB1555 3
885#define RADEON_TXFORMAT_RGB565 4
886#define RADEON_TXFORMAT_ARGB4444 5
887#define RADEON_TXFORMAT_ARGB8888 6
888#define RADEON_TXFORMAT_RGBA8888 7
889#define RADEON_TXFORMAT_Y8 8
890#define RADEON_TXFORMAT_VYUY422 10
891#define RADEON_TXFORMAT_YVYU422 11
892#define RADEON_TXFORMAT_DXT1 12
893#define RADEON_TXFORMAT_DXT23 14
894#define RADEON_TXFORMAT_DXT45 15
895
896#define R200_PP_TXCBLEND_0 0x2f00
897#define R200_PP_TXCBLEND_1 0x2f10
898#define R200_PP_TXCBLEND_2 0x2f20
899#define R200_PP_TXCBLEND_3 0x2f30
900#define R200_PP_TXCBLEND_4 0x2f40
901#define R200_PP_TXCBLEND_5 0x2f50
902#define R200_PP_TXCBLEND_6 0x2f60
903#define R200_PP_TXCBLEND_7 0x2f70
b5e89ed5 904#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1da177e4
LT		 905#define R200_PP_TFACTOR_0 0x2ee0
906#define R200_SE_VTX_FMT_0 0x2088
907#define R200_SE_VAP_CNTL 0x2080
908#define R200_SE_TCL_MATRIX_SEL_0 0x2230
b5e89ed5
DA		 909#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
910#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
911#define R200_PP_TXFILTER_5 0x2ca0
912#define R200_PP_TXFILTER_4 0x2c80
913#define R200_PP_TXFILTER_3 0x2c60
914#define R200_PP_TXFILTER_2 0x2c40
915#define R200_PP_TXFILTER_1 0x2c20
916#define R200_PP_TXFILTER_0 0x2c00
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LT		 917#define R200_PP_TXOFFSET_5 0x2d78
918#define R200_PP_TXOFFSET_4 0x2d60
919#define R200_PP_TXOFFSET_3 0x2d48
920#define R200_PP_TXOFFSET_2 0x2d30
921#define R200_PP_TXOFFSET_1 0x2d18
922#define R200_PP_TXOFFSET_0 0x2d00
923
924#define R200_PP_CUBIC_FACES_0 0x2c18
925#define R200_PP_CUBIC_FACES_1 0x2c38
926#define R200_PP_CUBIC_FACES_2 0x2c58
927#define R200_PP_CUBIC_FACES_3 0x2c78
928#define R200_PP_CUBIC_FACES_4 0x2c98
929#define R200_PP_CUBIC_FACES_5 0x2cb8
930#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
931#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
932#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
933#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
934#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
935#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
936#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
937#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
938#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
939#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
940#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
941#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
942#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
943#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
944#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
945#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
946#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
947#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
948#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
949#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
950#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
951#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
952#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
953#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
954#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
955#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
956#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
957#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
958#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
959#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
960
961#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
962#define R200_SE_VTE_CNTL 0x20b0
963#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
964#define R200_PP_TAM_DEBUG3 0x2d9c
965#define R200_PP_CNTL_X 0x2cc4
966#define R200_SE_VAP_CNTL_STATUS 0x2140
967#define R200_RE_SCISSOR_TL_0 0x1cd8
968#define R200_RE_SCISSOR_TL_1 0x1ce0
969#define R200_RE_SCISSOR_TL_2 0x1ce8
b5e89ed5 970#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
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LT		 971#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
972#define R200_SE_VTX_STATE_CNTL 0x2180
973#define R200_RE_POINTSIZE 0x2648
974#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
975
b5e89ed5 976#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
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LT		 977#define RADEON_PP_TEX_SIZE_1 0x1d0c
978#define RADEON_PP_TEX_SIZE_2 0x1d14
979
980#define RADEON_PP_CUBIC_FACES_0 0x1d24
981#define RADEON_PP_CUBIC_FACES_1 0x1d28
982#define RADEON_PP_CUBIC_FACES_2 0x1d2c
983#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
984#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
985#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
986
f2a2279f
DA		 987#define RADEON_SE_TCL_STATE_FLUSH 0x2284
988
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LT		 989#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
990#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
991#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
992#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
993#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
994#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
995#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
996#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
997#define R200_3D_DRAW_IMMD_2 0xC0003500
998#define R200_SE_VTX_FMT_1 0x208c
b5e89ed5 999#define R200_RE_CNTL 0x1c50
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LT		 1000
1001#define R200_RB3D_BLENDCOLOR 0x3218
1002
1003#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1004
1005#define R200_PP_TRI_PERF 0x2cf8
1006
9d17601c 1007#define R200_PP_AFS_0 0x2f80
b5e89ed5 1008#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
9d17601c 1009
d6fece05
DA		 1010#define R200_VAP_PVS_CNTL_1 0x22D0
1011
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LT		 1012/* Constants */
1013#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1014
1015#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1016#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1017#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1018#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1019#define RADEON_LAST_DISPATCH 1
1020
1021#define RADEON_MAX_VB_AGE 0x7fffffff
1022#define RADEON_MAX_VB_VERTS (0xffff)
1023
1024#define RADEON_RING_HIGH_MARK 128
1025
ea98a92f
DA		 1026#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1027
1da177e4
LT		 1028#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1029#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1030#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1031#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1032
1033#define RADEON_WRITE_PLL( addr, val ) \
1034do { \
1035 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
1036 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1037 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
1038} while (0)
1039
f2b04cd2
DA		 1040#define RADEON_WRITE_IGPGART( addr, val ) \
1041do { \
1042 RADEON_WRITE( RADEON_IGPGART_INDEX, \
1043 ((addr) & 0x7f) | (1 << 8)); \
1044 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
1045 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
1046} while (0)
1047
ea98a92f
DA		 1048#define RADEON_WRITE_PCIE( addr, val ) \
1049do { \
1050 RADEON_WRITE8( RADEON_PCIE_INDEX, \
1051 ((addr) & 0xff)); \
1052 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
1053} while (0)
1054
1da177e4
LT		 1055#define CP_PACKET0( reg, n ) \
1056 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1057#define CP_PACKET0_TABLE( reg, n ) \
1058 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1059#define CP_PACKET1( reg0, reg1 ) \
1060 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1061#define CP_PACKET2() \
1062 (RADEON_CP_PACKET2)
1063#define CP_PACKET3( pkt, n ) \
1064 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1065
1da177e4
LT		 1066/* ================================================================
1067 * Engine control helper macros
1068 */
1069
1070#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1071 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1072 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1073 RADEON_WAIT_HOST_IDLECLEAN) ); \
1074} while (0)
1075
1076#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1077 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1078 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1079 RADEON_WAIT_HOST_IDLECLEAN) ); \
1080} while (0)
1081
1082#define RADEON_WAIT_UNTIL_IDLE() do { \
1083 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1084 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1085 RADEON_WAIT_3D_IDLECLEAN | \
1086 RADEON_WAIT_HOST_IDLECLEAN) ); \
1087} while (0)
1088
1089#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1090 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1091 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1092} while (0)
1093
1094#define RADEON_FLUSH_CACHE() do { \
b9b603dd 1095 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
b15ec368 1096 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1da177e4
LT		 1097} while (0)
1098
1099#define RADEON_PURGE_CACHE() do { \
b9b603dd 1100 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
b15ec368 1101 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1da177e4
LT		 1102} while (0)
1103
1104#define RADEON_FLUSH_ZCACHE() do { \
1105 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1106 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1107} while (0)
1108
1109#define RADEON_PURGE_ZCACHE() do { \
1110 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1111 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1112} while (0)
1113
1da177e4
LT		 1114/* ================================================================
1115 * Misc helper macros
1116 */
1117
b5e89ed5 1118/* Perfbox functionality only.
1da177e4
LT		 1119 */
1120#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1121do { \
1122 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1123 u32 head = GET_RING_HEAD( dev_priv ); \
1124 if (head == dev_priv->ring.tail) \
1125 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1126 } \
1127} while (0)
1128
1129#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1130do { \
1131 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1132 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1133 int __ret = radeon_do_cp_idle( dev_priv ); \
1134 if ( __ret ) return __ret; \
1135 sarea_priv->last_dispatch = 0; \
1136 radeon_freelist_reset( dev ); \
1137 } \
1138} while (0)
1139
1140#define RADEON_DISPATCH_AGE( age ) do { \
1141 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1142 OUT_RING( age ); \
1143} while (0)
1144
1145#define RADEON_FRAME_AGE( age ) do { \
1146 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1147 OUT_RING( age ); \
1148} while (0)
1149
1150#define RADEON_CLEAR_AGE( age ) do { \
1151 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1152 OUT_RING( age ); \
1153} while (0)
1154
1da177e4
LT		 1155/* ================================================================
1156 * Ring control
1157 */
1158
1159#define RADEON_VERBOSE 0
1160
1161#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1162
1163#define BEGIN_RING( n ) do { \
1164 if ( RADEON_VERBOSE ) { \
3e684eae 1165 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1da177e4
LT		 1166 } \
1167 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1168 COMMIT_RING(); \
1169 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1170 } \
1171 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1172 ring = dev_priv->ring.start; \
1173 write = dev_priv->ring.tail; \
1174 mask = dev_priv->ring.tail_mask; \
1175} while (0)
1176
1177#define ADVANCE_RING() do { \
1178 if ( RADEON_VERBOSE ) { \
1179 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1180 write, dev_priv->ring.tail ); \
1181 } \
1182 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
bc5f4523 1183 DRM_ERROR( \
1da177e4
LT		 1184 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1185 ((dev_priv->ring.tail + _nr) & mask), \
1186 write, __LINE__); \
1187 } else \
1188 dev_priv->ring.tail = write; \
1189} while (0)
1190
1191#define COMMIT_RING() do { \
1192 /* Flush writes to ring */ \
1193 DRM_MEMORYBARRIER(); \
1194 GET_RING_HEAD( dev_priv ); \
1195 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1196 /* read from PCI bus to ensure correct posting */ \
1197 RADEON_READ( RADEON_CP_RB_RPTR ); \
1198} while (0)
1199
1200#define OUT_RING( x ) do { \
1201 if ( RADEON_VERBOSE ) { \
1202 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1203 (unsigned int)(x), write ); \
1204 } \
1205 ring[write++] = (x); \
1206 write &= mask; \
1207} while (0)
1208
1209#define OUT_RING_REG( reg, val ) do { \
1210 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1211 OUT_RING( val ); \
1212} while (0)
1213
1da177e4
LT		 1214#define OUT_RING_TABLE( tab, sz ) do { \
1215 int _size = (sz); \
1216 int *_tab = (int *)(tab); \
1217 \
1218 if (write + _size > mask) { \
1219 int _i = (mask+1) - write; \
1220 _size -= _i; \
1221 while (_i > 0 ) { \
1222 *(int *)(ring + write) = *_tab++; \
1223 write++; \
1224 _i--; \
1225 } \
1226 write = 0; \
1227 _tab += _i; \
1228 } \
1da177e4
LT		 1229 while (_size > 0) { \
1230 *(ring + write) = *_tab++; \
1231 write++; \
1232 _size--; \
1233 } \
1234 write &= mask; \
1235} while (0)
1236
b5e89ed5 1237#endif /* __RADEON_DRV_H__ */
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