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Currently DRM depends on PCI this will need to change for ffb on Sparc to
[net-next-2.6.git] / drivers / char / drm / i915_drv.h
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1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/**************************************************************************
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 **************************************************************************/
9
10#ifndef _I915_DRV_H_
11#define _I915_DRV_H_
12
13/* General customization:
14 */
15
16#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
17
18#define DRIVER_NAME "i915"
19#define DRIVER_DESC "Intel Graphics"
20#define DRIVER_DATE "20040405"
21
22/* Interface history:
23 *
24 * 1.1: Original.
25 */
26#define DRIVER_MAJOR 1
27#define DRIVER_MINOR 1
28#define DRIVER_PATCHLEVEL 0
29
30/* We use our own dma mechanisms, not the drm template code. However,
31 * the shared IRQ code is useful to us:
32 */
33#define __HAVE_PM 1
34
35typedef struct _drm_i915_ring_buffer {
36 int tail_mask;
37 unsigned long Start;
38 unsigned long End;
39 unsigned long Size;
40 u8 *virtual_start;
41 int head;
42 int tail;
43 int space;
44 drm_local_map_t map;
45} drm_i915_ring_buffer_t;
46
47struct mem_block {
48 struct mem_block *next;
49 struct mem_block *prev;
50 int start;
51 int size;
52 DRMFILE filp; /* 0: free, -1: heap, other: real files */
53};
54
55typedef struct drm_i915_private {
56 drm_local_map_t *sarea;
57 drm_local_map_t *mmio_map;
58
59 drm_i915_sarea_t *sarea_priv;
60 drm_i915_ring_buffer_t ring;
61
62 void *hw_status_page;
63 unsigned long counter;
64 dma_addr_t dma_status_page;
65
66 int back_offset;
67 int front_offset;
68 int current_page;
69 int page_flipping;
70 int use_mi_batchbuffer_start;
71
72 wait_queue_head_t irq_queue;
73 atomic_t irq_received;
74 atomic_t irq_emitted;
75
76 int tex_lru_log_granularity;
77 int allow_batchbuffer;
78 struct mem_block *agp_heap;
79} drm_i915_private_t;
80
81 /* i915_dma.c */
82extern int i915_dma_init(DRM_IOCTL_ARGS);
83extern int i915_dma_cleanup(drm_device_t * dev);
84extern int i915_flush_ioctl(DRM_IOCTL_ARGS);
85extern int i915_batchbuffer(DRM_IOCTL_ARGS);
86extern int i915_flip_bufs(DRM_IOCTL_ARGS);
87extern int i915_getparam(DRM_IOCTL_ARGS);
88extern int i915_setparam(DRM_IOCTL_ARGS);
89extern int i915_cmdbuffer(DRM_IOCTL_ARGS);
90extern void i915_kernel_lost_context(drm_device_t * dev);
91extern void i915_driver_pretakedown(drm_device_t *dev);
92extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp);
93
94/* i915_irq.c */
95extern int i915_irq_emit(DRM_IOCTL_ARGS);
96extern int i915_irq_wait(DRM_IOCTL_ARGS);
97extern int i915_wait_irq(drm_device_t * dev, int irq_nr);
98extern int i915_emit_irq(drm_device_t * dev);
99
100extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
101extern void i915_driver_irq_preinstall(drm_device_t *dev);
102extern void i915_driver_irq_postinstall(drm_device_t *dev);
103extern void i915_driver_irq_uninstall(drm_device_t *dev);
104
105/* i915_mem.c */
106extern int i915_mem_alloc(DRM_IOCTL_ARGS);
107extern int i915_mem_free(DRM_IOCTL_ARGS);
108extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
109extern void i915_mem_takedown(struct mem_block **heap);
110extern void i915_mem_release(drm_device_t * dev,
111 DRMFILE filp, struct mem_block *heap);
112
113#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
114#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
115#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
116#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val)
117
118#define I915_VERBOSE 0
119
120#define RING_LOCALS unsigned int outring, ringmask, outcount; \
121 volatile char *virt;
122
123#define BEGIN_LP_RING(n) do { \
124 if (I915_VERBOSE) \
125 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
126 n, __FUNCTION__); \
127 if (dev_priv->ring.space < n*4) \
128 i915_wait_ring(dev, n*4, __FUNCTION__); \
129 outcount = 0; \
130 outring = dev_priv->ring.tail; \
131 ringmask = dev_priv->ring.tail_mask; \
132 virt = dev_priv->ring.virtual_start; \
133} while (0)
134
135#define OUT_RING(n) do { \
136 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
137 *(volatile unsigned int *)(virt + outring) = n; \
138 outcount++; \
139 outring += 4; \
140 outring &= ringmask; \
141} while (0)
142
143#define ADVANCE_LP_RING() do { \
144 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
145 dev_priv->ring.tail = outring; \
146 dev_priv->ring.space -= outcount * 4; \
147 I915_WRITE(LP_RING + RING_TAIL, outring); \
148} while(0)
149
150extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
151
152#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
153#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
154#define CMD_REPORT_HEAD (7<<23)
155#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
156#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
157
158#define INST_PARSER_CLIENT 0x00000000
159#define INST_OP_FLUSH 0x02000000
160#define INST_FLUSH_MAP_CACHE 0x00000001
161
162#define BB1_START_ADDR_MASK (~0x7)
163#define BB1_PROTECTED (1<<0)
164#define BB1_UNPROTECTED (0<<0)
165#define BB2_END_ADDR_MASK (~0x7)
166
167#define I915REG_HWSTAM 0x02098
168#define I915REG_INT_IDENTITY_R 0x020a4
169#define I915REG_INT_MASK_R 0x020a8
170#define I915REG_INT_ENABLE_R 0x020a0
171
172#define SRX_INDEX 0x3c4
173#define SRX_DATA 0x3c5
174#define SR01 1
175#define SR01_SCREEN_OFF (1<<5)
176
177#define PPCR 0x61204
178#define PPCR_ON (1<<0)
179
180#define ADPA 0x61100
181#define ADPA_DPMS_MASK (~(3<<10))
182#define ADPA_DPMS_ON (0<<10)
183#define ADPA_DPMS_SUSPEND (1<<10)
184#define ADPA_DPMS_STANDBY (2<<10)
185#define ADPA_DPMS_OFF (3<<10)
186
187#define NOPID 0x2094
188#define LP_RING 0x2030
189#define HP_RING 0x2040
190#define RING_TAIL 0x00
191#define TAIL_ADDR 0x001FFFF8
192#define RING_HEAD 0x04
193#define HEAD_WRAP_COUNT 0xFFE00000
194#define HEAD_WRAP_ONE 0x00200000
195#define HEAD_ADDR 0x001FFFFC
196#define RING_START 0x08
197#define START_ADDR 0x0xFFFFF000
198#define RING_LEN 0x0C
199#define RING_NR_PAGES 0x001FF000
200#define RING_REPORT_MASK 0x00000006
201#define RING_REPORT_64K 0x00000002
202#define RING_REPORT_128K 0x00000004
203#define RING_NO_REPORT 0x00000000
204#define RING_VALID_MASK 0x00000001
205#define RING_VALID 0x00000001
206#define RING_INVALID 0x00000000
207
208#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
209#define SC_UPDATE_SCISSOR (0x1<<1)
210#define SC_ENABLE_MASK (0x1<<0)
211#define SC_ENABLE (0x1<<0)
212
213#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
214#define SCI_YMIN_MASK (0xffff<<16)
215#define SCI_XMIN_MASK (0xffff<<0)
216#define SCI_YMAX_MASK (0xffff<<16)
217#define SCI_XMAX_MASK (0xffff<<0)
218
219#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
220#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
221#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
222#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
223#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
224#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
225#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
226
227#define MI_BATCH_BUFFER ((0x30<<23)|1)
228#define MI_BATCH_BUFFER_START (0x31<<23)
229#define MI_BATCH_BUFFER_END (0xA<<23)
230#define MI_BATCH_NON_SECURE (1)
231
232#define MI_WAIT_FOR_EVENT ((0x3<<23))
233#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
234#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
235
236#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
237
238#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
239#define ASYNC_FLIP (1<<22)
240
241#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
242
243#endif
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