[net-next-2.6.git] / drivers / char / drm / i915_drm.h

/**************************************************************************
 *
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/

#ifndef _I915_DRM_H_
#define _I915_DRM_H_

/* Please note that modifications to all structs defined here are
 * subject to backwards-compatibility constraints.
 */

#include "drm.h"

/* Each region is a minimum of 16k, and there are at most 255 of them.
 */
#define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
				 * of chars for next/prev indices */
#define I915_LOG_MIN_TEX_REGION_SIZE 14

typedef struct _drm_i915_init {
	enum {
		I915_INIT_DMA = 0x01,
		I915_CLEANUP_DMA = 0x02,
		I915_RESUME_DMA = 0x03
	} func;
	unsigned int mmio_offset;
	int sarea_priv_offset;
	unsigned int ring_start;
	unsigned int ring_end;
	unsigned int ring_size;
	unsigned int front_offset;
	unsigned int back_offset;
	unsigned int depth_offset;
	unsigned int w;
	unsigned int h;
	unsigned int pitch;
	unsigned int pitch_bits;
	unsigned int back_pitch;
	unsigned int depth_pitch;
	unsigned int cpp;
	unsigned int chipset;
} drm_i915_init_t;

typedef struct _drm_i915_sarea {
	drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
	int last_upload;	/* last time texture was uploaded */
	int last_enqueue;	/* last time a buffer was enqueued */
	int last_dispatch;	/* age of the most recently dispatched buffer */
	int ctxOwner;		/* last context to upload state */
	int texAge;
	int pf_enabled;		/* is pageflipping allowed? */
	int pf_active;
	int pf_current_page;	/* which buffer is being displayed? */
	int perf_boxes;		/* performance boxes to be displayed */
} drm_i915_sarea_t;

/* Flags for perf_boxes
 */
#define I915_BOX_RING_EMPTY    0x1
#define I915_BOX_FLIP          0x2
#define I915_BOX_WAIT          0x4
#define I915_BOX_TEXTURE_LOAD  0x8
#define I915_BOX_LOST_CONTEXT  0x10

/* I915 specific ioctls
 * The device specific ioctl range is 0x40 to 0x79.
 */
#define DRM_I915_INIT		0x00
#define DRM_I915_FLUSH		0x01
#define DRM_I915_FLIP		0x02
#define DRM_I915_BATCHBUFFER	0x03
#define DRM_I915_IRQ_EMIT	0x04
#define DRM_I915_IRQ_WAIT	0x05
#define DRM_I915_GETPARAM	0x06
#define DRM_I915_SETPARAM	0x07
#define DRM_I915_ALLOC		0x08
#define DRM_I915_FREE		0x09
#define DRM_I915_INIT_HEAP	0x0a
#define DRM_I915_CMDBUFFER	0x0b

#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
#define DRM_IOCTL_I915_BATCHBUFFER	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
#define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
#define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
#define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
#define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
#define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
#define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
#define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
#define DRM_IOCTL_I915_CMDBUFFER	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)

/* Allow drivers to submit batchbuffers directly to hardware, relying
 * on the security mechanisms provided by hardware.
 */
typedef struct _drm_i915_batchbuffer {
	int start;		/* agp offset */
	int used;		/* nr bytes in use */
	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */
	int num_cliprects;	/* mulitpass with multiple cliprects? */
	drm_clip_rect_t __user *cliprects;	/* pointer to userspace cliprects */
} drm_i915_batchbuffer_t;

/* As above, but pass a pointer to userspace buffer which can be
 * validated by the kernel prior to sending to hardware.
 */
typedef struct _drm_i915_cmdbuffer {
	char __user *buf;	/* pointer to userspace command buffer */
	int sz;			/* nr bytes in buf */
	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */
	int num_cliprects;	/* mulitpass with multiple cliprects? */
	drm_clip_rect_t __user *cliprects;	/* pointer to userspace cliprects */
} drm_i915_cmdbuffer_t;

/* Userspace can request & wait on irq's:
 */
typedef struct drm_i915_irq_emit {
	int __user *irq_seq;
} drm_i915_irq_emit_t;

typedef struct drm_i915_irq_wait {
	int irq_seq;
} drm_i915_irq_wait_t;

/* Ioctl to query kernel params:
 */
#define I915_PARAM_IRQ_ACTIVE            1
#define I915_PARAM_ALLOW_BATCHBUFFER     2

typedef struct drm_i915_getparam {
	int param;
	int __user *value;
} drm_i915_getparam_t;

/* Ioctl to set kernel params:
 */
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
#define I915_SETPARAM_ALLOW_BATCHBUFFER                   3

typedef struct drm_i915_setparam {
	int param;
	int value;
} drm_i915_setparam_t;

/* A memory manager for regions of shared memory:
 */
#define I915_MEM_REGION_AGP 1

typedef struct drm_i915_mem_alloc {
	int region;
	int alignment;
	int size;
	int __user *region_offset;	/* offset from start of fb or agp */
} drm_i915_mem_alloc_t;

typedef struct drm_i915_mem_free {
	int region;
	int region_offset;
} drm_i915_mem_free_t;

typedef struct drm_i915_mem_init_heap {
	int region;
	int size;
	int start;
} drm_i915_mem_init_heap_t;

#endif				/* _I915_DRM_H_ */
Commit	Line	Data
bc54fd1a DA	1	/**************************************************************************
	2	*
	3	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
	4	* All Rights Reserved.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sub license, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	19	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	20	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	21	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	22	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	23	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	24	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*
	26	**************************************************************************/
	27
1da177e4 LT	28	#ifndef _I915_DRM_H_
	29	#define _I915_DRM_H_
	30
	31	/* Please note that modifications to all structs defined here are
	32	* subject to backwards-compatibility constraints.
	33	*/
	34
	35	#include "drm.h"
	36
	37	/* Each region is a minimum of 16k, and there are at most 255 of them.
	38	*/
	39	#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
	40	* of chars for next/prev indices */
	41	#define I915_LOG_MIN_TEX_REGION_SIZE 14
	42
	43	typedef struct _drm_i915_init {
	44	enum {
	45	I915_INIT_DMA = 0x01,
	46	I915_CLEANUP_DMA = 0x02,
	47	I915_RESUME_DMA = 0x03
	48	} func;
	49	unsigned int mmio_offset;
	50	int sarea_priv_offset;
	51	unsigned int ring_start;
	52	unsigned int ring_end;
	53	unsigned int ring_size;
	54	unsigned int front_offset;
	55	unsigned int back_offset;
	56	unsigned int depth_offset;
	57	unsigned int w;
	58	unsigned int h;
	59	unsigned int pitch;
	60	unsigned int pitch_bits;
	61	unsigned int back_pitch;
	62	unsigned int depth_pitch;
	63	unsigned int cpp;
	64	unsigned int chipset;
	65	} drm_i915_init_t;
	66
	67	typedef struct _drm_i915_sarea {
	68	drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
	69	int last_upload; /* last time texture was uploaded */
	70	int last_enqueue; /* last time a buffer was enqueued */
	71	int last_dispatch; /* age of the most recently dispatched buffer */
	72	int ctxOwner; /* last context to upload state */
	73	int texAge;
	74	int pf_enabled; /* is pageflipping allowed? */
	75	int pf_active;
	76	int pf_current_page; /* which buffer is being displayed? */
	77	int perf_boxes; /* performance boxes to be displayed */
	78	} drm_i915_sarea_t;
	79
	80	/* Flags for perf_boxes
	81	*/
	82	#define I915_BOX_RING_EMPTY 0x1
	83	#define I915_BOX_FLIP 0x2
	84	#define I915_BOX_WAIT 0x4
	85	#define I915_BOX_TEXTURE_LOAD 0x8
	86	#define I915_BOX_LOST_CONTEXT 0x10
	87
	88	/* I915 specific ioctls
	89	* The device specific ioctl range is 0x40 to 0x79.
	90	*/
	91	#define DRM_I915_INIT 0x00
92	#define DRM_I915_FLUSH 0x01
93	#define DRM_I915_FLIP 0x02
94	#define DRM_I915_BATCHBUFFER 0x03
95	#define DRM_I915_IRQ_EMIT 0x04
96	#define DRM_I915_IRQ_WAIT 0x05
97	#define DRM_I915_GETPARAM 0x06
98	#define DRM_I915_SETPARAM 0x07
99	#define DRM_I915_ALLOC 0x08
100	#define DRM_I915_FREE 0x09
101	#define DRM_I915_INIT_HEAP 0x0a
102	#define DRM_I915_CMDBUFFER 0x0b
103
104	#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
105	#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
106	#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
107	#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
108	#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
109	#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
110	#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
111	#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
112	#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
113	#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
114	#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
115	#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
116
117	/* Allow drivers to submit batchbuffers directly to hardware, relying
118	* on the security mechanisms provided by hardware.
119	*/
120	typedef struct _drm_i915_batchbuffer {
121	int start; /* agp offset */
122	int used; /* nr bytes in use */
123	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
124	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
125	int num_cliprects; /* mulitpass with multiple cliprects? */
126	drm_clip_rect_t __user cliprects; / pointer to userspace cliprects */
127	} drm_i915_batchbuffer_t;
128
129	/* As above, but pass a pointer to userspace buffer which can be
130	* validated by the kernel prior to sending to hardware.
131	*/
132	typedef struct _drm_i915_cmdbuffer {
133	char __user buf; / pointer to userspace command buffer */
134	int sz; /* nr bytes in buf */
135	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
136	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
137	int num_cliprects; /* mulitpass with multiple cliprects? */
138	drm_clip_rect_t __user cliprects; / pointer to userspace cliprects */
139	} drm_i915_cmdbuffer_t;
140
141	/* Userspace can request & wait on irq's:
142	*/
143	typedef struct drm_i915_irq_emit {
144	int __user *irq_seq;
145	} drm_i915_irq_emit_t;
146
147	typedef struct drm_i915_irq_wait {
148	int irq_seq;
149	} drm_i915_irq_wait_t;
150
151	/* Ioctl to query kernel params:
152	*/
153	#define I915_PARAM_IRQ_ACTIVE 1
154	#define I915_PARAM_ALLOW_BATCHBUFFER 2
155
156	typedef struct drm_i915_getparam {
157	int param;
158	int __user *value;
159	} drm_i915_getparam_t;
160
161	/* Ioctl to set kernel params:
162	*/
163	#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
164	#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
165	#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
166
167	typedef struct drm_i915_setparam {
168	int param;
169	int value;
170	} drm_i915_setparam_t;
171
172	/* A memory manager for regions of shared memory:
173	*/
174	#define I915_MEM_REGION_AGP 1
175
176	typedef struct drm_i915_mem_alloc {
177	int region;
178	int alignment;
179	int size;
180	int __user region_offset; / offset from start of fb or agp */
181	} drm_i915_mem_alloc_t;
182
183	typedef struct drm_i915_mem_free {
184	int region;
185	int region_offset;
186	} drm_i915_mem_free_t;
187
188	typedef struct drm_i915_mem_init_heap {
189	int region;
190	int size;
191	int start;
192	} drm_i915_mem_init_heap_t;
193
194	#endif /* _I915_DRM_H_ */