[net-next-2.6.git] / drivers / char / drm / i915_drm.h

/*
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _I915_DRM_H_
#define _I915_DRM_H_

/* Please note that modifications to all structs defined here are
 * subject to backwards-compatibility constraints.
 */

#include "drm.h"

/* Each region is a minimum of 16k, and there are at most 255 of them.
 */
#define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
				 * of chars for next/prev indices */
#define I915_LOG_MIN_TEX_REGION_SIZE 14

typedef struct _drm_i915_init {
	enum {
		I915_INIT_DMA = 0x01,
		I915_CLEANUP_DMA = 0x02,
		I915_RESUME_DMA = 0x03
	} func;
	unsigned int mmio_offset;
	int sarea_priv_offset;
	unsigned int ring_start;
	unsigned int ring_end;
	unsigned int ring_size;
	unsigned int front_offset;
	unsigned int back_offset;
	unsigned int depth_offset;
	unsigned int w;
	unsigned int h;
	unsigned int pitch;
	unsigned int pitch_bits;
	unsigned int back_pitch;
	unsigned int depth_pitch;
	unsigned int cpp;
	unsigned int chipset;
} drm_i915_init_t;

typedef struct _drm_i915_sarea {
	drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
	int last_upload;	/* last time texture was uploaded */
	int last_enqueue;	/* last time a buffer was enqueued */
	int last_dispatch;	/* age of the most recently dispatched buffer */
	int ctxOwner;		/* last context to upload state */
	int texAge;
	int pf_enabled;		/* is pageflipping allowed? */
	int pf_active;
	int pf_current_page;	/* which buffer is being displayed? */
	int perf_boxes;		/* performance boxes to be displayed */
	int width, height;      /* screen size in pixels */

	drm_handle_t front_handle;
	int front_offset;
	int front_size;

	drm_handle_t back_handle;
	int back_offset;
	int back_size;

	drm_handle_t depth_handle;
	int depth_offset;
	int depth_size;

	drm_handle_t tex_handle;
	int tex_offset;
	int tex_size;
	int log_tex_granularity;
	int pitch;
	int rotation;           /* 0, 90, 180 or 270 */
	int rotated_offset;
	int rotated_size;
	int rotated_pitch;
	int virtualX, virtualY;

	unsigned int front_tiled;
	unsigned int back_tiled;
	unsigned int depth_tiled;
	unsigned int rotated_tiled;
	unsigned int rotated2_tiled;
} drm_i915_sarea_t;

/* Flags for perf_boxes
 */
#define I915_BOX_RING_EMPTY    0x1
#define I915_BOX_FLIP          0x2
#define I915_BOX_WAIT          0x4
#define I915_BOX_TEXTURE_LOAD  0x8
#define I915_BOX_LOST_CONTEXT  0x10

/* I915 specific ioctls
 * The device specific ioctl range is 0x40 to 0x79.
 */
#define DRM_I915_INIT		0x00
#define DRM_I915_FLUSH		0x01
#define DRM_I915_FLIP		0x02
#define DRM_I915_BATCHBUFFER	0x03
#define DRM_I915_IRQ_EMIT	0x04
#define DRM_I915_IRQ_WAIT	0x05
#define DRM_I915_GETPARAM	0x06
#define DRM_I915_SETPARAM	0x07
#define DRM_I915_ALLOC		0x08
#define DRM_I915_FREE		0x09
#define DRM_I915_INIT_HEAP	0x0a
#define DRM_I915_CMDBUFFER	0x0b
#define DRM_I915_DESTROY_HEAP	0x0c
#define DRM_I915_SET_VBLANK_PIPE	0x0d
#define DRM_I915_GET_VBLANK_PIPE	0x0e

#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
#define DRM_IOCTL_I915_FLIP		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
#define DRM_IOCTL_I915_BATCHBUFFER	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
#define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
#define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
#define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
#define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
#define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
#define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
#define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
#define DRM_IOCTL_I915_CMDBUFFER	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
#define DRM_IOCTL_I915_DESTROY_HEAP	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
#define DRM_IOCTL_I915_SET_VBLANK_PIPE	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
#define DRM_IOCTL_I915_GET_VBLANK_PIPE	DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

/* Allow drivers to submit batchbuffers directly to hardware, relying
 * on the security mechanisms provided by hardware.
 */
typedef struct _drm_i915_batchbuffer {
	int start;		/* agp offset */
	int used;		/* nr bytes in use */
	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */
	int num_cliprects;	/* mulitpass with multiple cliprects? */
	drm_clip_rect_t __user *cliprects;	/* pointer to userspace cliprects */
} drm_i915_batchbuffer_t;

/* As above, but pass a pointer to userspace buffer which can be
 * validated by the kernel prior to sending to hardware.
 */
typedef struct _drm_i915_cmdbuffer {
	char __user *buf;	/* pointer to userspace command buffer */
	int sz;			/* nr bytes in buf */
	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
	int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO */
	int num_cliprects;	/* mulitpass with multiple cliprects? */
	drm_clip_rect_t __user *cliprects;	/* pointer to userspace cliprects */
} drm_i915_cmdbuffer_t;

/* Userspace can request & wait on irq's:
 */
typedef struct drm_i915_irq_emit {
	int __user *irq_seq;
} drm_i915_irq_emit_t;

typedef struct drm_i915_irq_wait {
	int irq_seq;
} drm_i915_irq_wait_t;

/* Ioctl to query kernel params:
 */
#define I915_PARAM_IRQ_ACTIVE            1
#define I915_PARAM_ALLOW_BATCHBUFFER     2
#define I915_PARAM_LAST_DISPATCH         3

typedef struct drm_i915_getparam {
	int param;
	int __user *value;
} drm_i915_getparam_t;

/* Ioctl to set kernel params:
 */
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
#define I915_SETPARAM_ALLOW_BATCHBUFFER                   3

typedef struct drm_i915_setparam {
	int param;
	int value;
} drm_i915_setparam_t;

/* A memory manager for regions of shared memory:
 */
#define I915_MEM_REGION_AGP 1

typedef struct drm_i915_mem_alloc {
	int region;
	int alignment;
	int size;
	int __user *region_offset;	/* offset from start of fb or agp */
} drm_i915_mem_alloc_t;

typedef struct drm_i915_mem_free {
	int region;
	int region_offset;
} drm_i915_mem_free_t;

typedef struct drm_i915_mem_init_heap {
	int region;
	int size;
	int start;
} drm_i915_mem_init_heap_t;

/* Allow memory manager to be torn down and re-initialized (eg on
 * rotate):
 */
typedef struct drm_i915_mem_destroy_heap {
	int region;
} drm_i915_mem_destroy_heap_t;

/* Allow X server to configure which pipes to monitor for vblank signals
 */
#define	DRM_I915_VBLANK_PIPE_A	1
#define	DRM_I915_VBLANK_PIPE_B	2

typedef struct drm_i915_vblank_pipe {
	int pipe;
} drm_i915_vblank_pipe_t;

#endif				/* _I915_DRM_H_ */
Commit	Line	Data
0d6aa60b	1	/*
bc54fd1a DA	2	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial portions
	15	* of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	18	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	20	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	21	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	22	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	23	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
0d6aa60b	25	*/
bc54fd1a	26
1da177e4 LT	27	#ifndef _I915_DRM_H_
	28	#define _I915_DRM_H_
	29
	30	/* Please note that modifications to all structs defined here are
	31	* subject to backwards-compatibility constraints.
	32	*/
	33
	34	#include "drm.h"
	35
	36	/* Each region is a minimum of 16k, and there are at most 255 of them.
	37	*/
	38	#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
	39	* of chars for next/prev indices */
	40	#define I915_LOG_MIN_TEX_REGION_SIZE 14
	41
	42	typedef struct _drm_i915_init {
	43	enum {
	44	I915_INIT_DMA = 0x01,
	45	I915_CLEANUP_DMA = 0x02,
	46	I915_RESUME_DMA = 0x03
	47	} func;
	48	unsigned int mmio_offset;
	49	int sarea_priv_offset;
	50	unsigned int ring_start;
	51	unsigned int ring_end;
	52	unsigned int ring_size;
	53	unsigned int front_offset;
	54	unsigned int back_offset;
	55	unsigned int depth_offset;
	56	unsigned int w;
	57	unsigned int h;
	58	unsigned int pitch;
	59	unsigned int pitch_bits;
	60	unsigned int back_pitch;
	61	unsigned int depth_pitch;
	62	unsigned int cpp;
	63	unsigned int chipset;
	64	} drm_i915_init_t;
	65
	66	typedef struct _drm_i915_sarea {
	67	drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
	68	int last_upload; /* last time texture was uploaded */
	69	int last_enqueue; /* last time a buffer was enqueued */
	70	int last_dispatch; /* age of the most recently dispatched buffer */
	71	int ctxOwner; /* last context to upload state */
	72	int texAge;
	73	int pf_enabled; /* is pageflipping allowed? */
	74	int pf_active;
	75	int pf_current_page; /* which buffer is being displayed? */
	76	int perf_boxes; /* performance boxes to be displayed */
de227f5f DA	77	int width, height; /* screen size in pixels */
	78
	79	drm_handle_t front_handle;
	80	int front_offset;
	81	int front_size;
	82
	83	drm_handle_t back_handle;
	84	int back_offset;
	85	int back_size;
	86
	87	drm_handle_t depth_handle;
	88	int depth_offset;
	89	int depth_size;
	90
	91	drm_handle_t tex_handle;
	92	int tex_offset;
	93	int tex_size;
	94	int log_tex_granularity;
	95	int pitch;
	96	int rotation; /* 0, 90, 180 or 270 */
	97	int rotated_offset;
	98	int rotated_size;
	99	int rotated_pitch;
	100	int virtualX, virtualY;
c29b669c AH	101
	102	unsigned int front_tiled;
	103	unsigned int back_tiled;
	104	unsigned int depth_tiled;
	105	unsigned int rotated_tiled;
	106	unsigned int rotated2_tiled;
1da177e4 LT	107	} drm_i915_sarea_t;
	108
	109	/* Flags for perf_boxes
	110	*/
	111	#define I915_BOX_RING_EMPTY 0x1
	112	#define I915_BOX_FLIP 0x2
	113	#define I915_BOX_WAIT 0x4
	114	#define I915_BOX_TEXTURE_LOAD 0x8
	115	#define I915_BOX_LOST_CONTEXT 0x10
	116
	117	/* I915 specific ioctls
	118	* The device specific ioctl range is 0x40 to 0x79.
	119	*/
	120	#define DRM_I915_INIT 0x00
	121	#define DRM_I915_FLUSH 0x01
	122	#define DRM_I915_FLIP 0x02
	123	#define DRM_I915_BATCHBUFFER 0x03
	124	#define DRM_I915_IRQ_EMIT 0x04
	125	#define DRM_I915_IRQ_WAIT 0x05
	126	#define DRM_I915_GETPARAM 0x06
	127	#define DRM_I915_SETPARAM 0x07
	128	#define DRM_I915_ALLOC 0x08
	129	#define DRM_I915_FREE 0x09
	130	#define DRM_I915_INIT_HEAP 0x0a
	131	#define DRM_I915_CMDBUFFER 0x0b
de227f5f	132	#define DRM_I915_DESTROY_HEAP 0x0c
702880f2 DA	133	#define DRM_I915_SET_VBLANK_PIPE 0x0d
702880f2 DA	134	#define DRM_I915_GET_VBLANK_PIPE 0x0e
1da177e4 LT	135
	136	#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
	137	#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
	138	#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
	139	#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
	140	#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
	141	#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
	142	#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
	143	#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
	144	#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
	145	#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
	146	#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
	147	#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
de227f5f	148	#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
702880f2 DA	149	#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
702880f2 DA	150	#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
1da177e4 LT	151
	152	/* Allow drivers to submit batchbuffers directly to hardware, relying
	153	* on the security mechanisms provided by hardware.
	154	*/
	155	typedef struct _drm_i915_batchbuffer {
	156	int start; /* agp offset */
	157	int used; /* nr bytes in use */
	158	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
	159	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
	160	int num_cliprects; /* mulitpass with multiple cliprects? */
	161	drm_clip_rect_t __user cliprects; / pointer to userspace cliprects */
	162	} drm_i915_batchbuffer_t;
	163
	164	/* As above, but pass a pointer to userspace buffer which can be
	165	* validated by the kernel prior to sending to hardware.
	166	*/
	167	typedef struct _drm_i915_cmdbuffer {
	168	char __user buf; / pointer to userspace command buffer */
	169	int sz; /* nr bytes in buf */
	170	int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
	171	int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
	172	int num_cliprects; /* mulitpass with multiple cliprects? */
	173	drm_clip_rect_t __user cliprects; / pointer to userspace cliprects */
	174	} drm_i915_cmdbuffer_t;
	175
	176	/* Userspace can request & wait on irq's:
	177	*/
	178	typedef struct drm_i915_irq_emit {
	179	int __user *irq_seq;
	180	} drm_i915_irq_emit_t;
	181
	182	typedef struct drm_i915_irq_wait {
	183	int irq_seq;
	184	} drm_i915_irq_wait_t;
	185
	186	/* Ioctl to query kernel params:
	187	*/
	188	#define I915_PARAM_IRQ_ACTIVE 1
	189	#define I915_PARAM_ALLOW_BATCHBUFFER 2
0d6aa60b	190	#define I915_PARAM_LAST_DISPATCH 3
1da177e4 LT	191
	192	typedef struct drm_i915_getparam {
	193	int param;
	194	int __user *value;
	195	} drm_i915_getparam_t;
	196
	197	/* Ioctl to set kernel params:
	198	*/
	199	#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
	200	#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
	201	#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
	202
	203	typedef struct drm_i915_setparam {
	204	int param;
	205	int value;
	206	} drm_i915_setparam_t;
	207
	208	/* A memory manager for regions of shared memory:
	209	*/
	210	#define I915_MEM_REGION_AGP 1
	211
	212	typedef struct drm_i915_mem_alloc {
	213	int region;
	214	int alignment;
	215	int size;
	216	int __user region_offset; / offset from start of fb or agp */
	217	} drm_i915_mem_alloc_t;
	218
	219	typedef struct drm_i915_mem_free {
	220	int region;
	221	int region_offset;
	222	} drm_i915_mem_free_t;
	223
	224	typedef struct drm_i915_mem_init_heap {
	225	int region;
	226	int size;
	227	int start;
	228	} drm_i915_mem_init_heap_t;
	229
de227f5f DA	230	/* Allow memory manager to be torn down and re-initialized (eg on
	231	* rotate):
	232	*/
	233	typedef struct drm_i915_mem_destroy_heap {
	234	int region;
	235	} drm_i915_mem_destroy_heap_t;
	236
702880f2 DA	237	/* Allow X server to configure which pipes to monitor for vblank signals
	238	*/
	239	#define DRM_I915_VBLANK_PIPE_A 1
	240	#define DRM_I915_VBLANK_PIPE_B 2
	241
	242	typedef struct drm_i915_vblank_pipe {
	243	int pipe;
	244	} drm_i915_vblank_pipe_t;
	245
1da177e4	246	#endif /* _I915_DRM_H_ */