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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel AGPGART routines. | |
3 | */ | |
4 | ||
1da177e4 LT |
5 | #include <linux/module.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
1eaf122c | 8 | #include <linux/kernel.h> |
1da177e4 LT |
9 | #include <linux/pagemap.h> |
10 | #include <linux/agp_backend.h> | |
11 | #include "agp.h" | |
12 | ||
17661681 ZW |
13 | /* |
14 | * If we have Intel graphics, we're not going to have anything other than | |
15 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
16 | * on the Intel IOMMU support (CONFIG_DMAR). | |
17 | * Only newer chipsets need to bother with this, of course. | |
18 | */ | |
19 | #ifdef CONFIG_DMAR | |
20 | #define USE_PCI_DMA_API 1 | |
21 | #endif | |
22 | ||
e914a36a CM |
23 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 |
24 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
65c25aad EA |
25 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 |
26 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
9119f85a ZW |
27 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 |
28 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
65c25aad EA |
29 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 |
30 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
31 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
32 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
4598af33 WZ |
33 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 |
34 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
dde47876 | 35 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 |
c8eebfd6 | 36 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 |
dde47876 | 37 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC |
df80b148 | 38 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE |
2177832f SL |
39 | #define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010 |
40 | #define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011 | |
41 | #define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000 | |
42 | #define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001 | |
874808c6 WZ |
43 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 |
44 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
45 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
46 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
47 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
48 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
38d8a956 FH |
49 | #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 |
50 | #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 | |
99d32bd5 ZW |
51 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
52 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
25ce77ab ZW |
53 | #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 |
54 | #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 | |
55 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 | |
56 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
57 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
58 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
a50ccc6c ZW |
59 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
60 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 | |
32cb055b ZW |
61 | #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040 |
62 | #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042 | |
63 | #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044 | |
07fb6111 | 64 | #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB 0x0062 |
9cf1e35c | 65 | #define PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB 0x006a |
32cb055b | 66 | #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046 |
65c25aad | 67 | |
f011ae74 DA |
68 | /* cover 915 and 945 variants */ |
69 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | |
70 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ | |
71 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ | |
72 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ | |
73 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ | |
74 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) | |
75 | ||
65c25aad | 76 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ |
f011ae74 DA |
77 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ |
78 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
79 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ | |
80 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ | |
82e14a62 | 81 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) |
65c25aad | 82 | |
874808c6 WZ |
83 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ |
84 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
2177832f SL |
85 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ |
86 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ | |
87 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) | |
88 | ||
89 | #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ | |
90 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) | |
65c25aad | 91 | |
25ce77ab ZW |
92 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ |
93 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ | |
82e14a62 | 94 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ |
a50ccc6c | 95 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ |
32cb055b | 96 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ |
38d8a956 | 97 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ |
32cb055b | 98 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \ |
07fb6111 | 99 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \ |
9cf1e35c ZW |
100 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB || \ |
101 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB) | |
25ce77ab | 102 | |
a030ce44 TH |
103 | extern int agp_memory_reserved; |
104 | ||
105 | ||
1da177e4 LT |
106 | /* Intel 815 register */ |
107 | #define INTEL_815_APCONT 0x51 | |
108 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
109 | ||
110 | /* Intel i820 registers */ | |
111 | #define INTEL_I820_RDCR 0x51 | |
112 | #define INTEL_I820_ERRSTS 0xc8 | |
113 | ||
114 | /* Intel i840 registers */ | |
115 | #define INTEL_I840_MCHCFG 0x50 | |
116 | #define INTEL_I840_ERRSTS 0xc8 | |
117 | ||
118 | /* Intel i850 registers */ | |
119 | #define INTEL_I850_MCHCFG 0x50 | |
120 | #define INTEL_I850_ERRSTS 0xc8 | |
121 | ||
122 | /* intel 915G registers */ | |
123 | #define I915_GMADDR 0x18 | |
124 | #define I915_MMADDR 0x10 | |
125 | #define I915_PTEADDR 0x1C | |
126 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
127 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
25ce77ab ZW |
128 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
129 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
130 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
131 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
132 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
133 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
134 | ||
6c00a61e | 135 | #define I915_IFPADDR 0x60 |
1da177e4 | 136 | |
65c25aad EA |
137 | /* Intel 965G registers */ |
138 | #define I965_MSAC 0x62 | |
6c00a61e | 139 | #define I965_IFPADDR 0x70 |
1da177e4 LT |
140 | |
141 | /* Intel 7505 registers */ | |
142 | #define INTEL_I7505_APSIZE 0x74 | |
143 | #define INTEL_I7505_NCAPID 0x60 | |
144 | #define INTEL_I7505_NISTAT 0x6c | |
145 | #define INTEL_I7505_ATTBASE 0x78 | |
146 | #define INTEL_I7505_ERRSTS 0x42 | |
147 | #define INTEL_I7505_AGPCTRL 0x70 | |
148 | #define INTEL_I7505_MCHCFG 0x50 | |
149 | ||
e5524f35 | 150 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
1da177e4 LT |
151 | { |
152 | {64, 16384, 4}, | |
153 | /* The 32M mode still requires a 64k gatt */ | |
154 | {32, 8192, 4} | |
155 | }; | |
156 | ||
157 | #define AGP_DCACHE_MEMORY 1 | |
158 | #define AGP_PHYS_MEMORY 2 | |
a030ce44 | 159 | #define INTEL_AGP_CACHED_MEMORY 3 |
1da177e4 LT |
160 | |
161 | static struct gatt_mask intel_i810_masks[] = | |
162 | { | |
163 | {.mask = I810_PTE_VALID, .type = 0}, | |
164 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
a030ce44 TH |
165 | {.mask = I810_PTE_VALID, .type = 0}, |
166 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
167 | .type = INTEL_AGP_CACHED_MEMORY} | |
1da177e4 LT |
168 | }; |
169 | ||
c4ca8817 WZ |
170 | static struct _intel_private { |
171 | struct pci_dev *pcidev; /* device one */ | |
172 | u8 __iomem *registers; | |
173 | u32 __iomem *gtt; /* I915G */ | |
1da177e4 | 174 | int num_dcache_entries; |
c4ca8817 WZ |
175 | /* gtt_entries is the number of gtt entries that are already mapped |
176 | * to stolen memory. Stolen memory is larger than the memory mapped | |
177 | * through gtt_entries, as it includes some reserved space for the BIOS | |
178 | * popup and for the GTT. | |
179 | */ | |
180 | int gtt_entries; /* i830+ */ | |
2162e6a2 DA |
181 | union { |
182 | void __iomem *i9xx_flush_page; | |
183 | void *i8xx_flush_page; | |
184 | }; | |
185 | struct page *i8xx_page; | |
6c00a61e | 186 | struct resource ifp_resource; |
4d64dd9e | 187 | int resource_valid; |
c4ca8817 | 188 | } intel_private; |
1da177e4 | 189 | |
17661681 | 190 | #ifdef USE_PCI_DMA_API |
c2980d8c | 191 | static int intel_agp_map_page(struct page *page, dma_addr_t *ret) |
17661681 | 192 | { |
c2980d8c DW |
193 | *ret = pci_map_page(intel_private.pcidev, page, 0, |
194 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
17661681 ZW |
195 | if (pci_dma_mapping_error(intel_private.pcidev, *ret)) |
196 | return -EINVAL; | |
197 | return 0; | |
198 | } | |
199 | ||
c2980d8c | 200 | static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) |
17661681 | 201 | { |
c2980d8c DW |
202 | pci_unmap_page(intel_private.pcidev, dma, |
203 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
17661681 ZW |
204 | } |
205 | ||
91b8e305 DW |
206 | static void intel_agp_free_sglist(struct agp_memory *mem) |
207 | { | |
f692775d DW |
208 | struct sg_table st; |
209 | ||
210 | st.sgl = mem->sg_list; | |
211 | st.orig_nents = st.nents = mem->page_count; | |
212 | ||
213 | sg_free_table(&st); | |
91b8e305 | 214 | |
91b8e305 DW |
215 | mem->sg_list = NULL; |
216 | mem->num_sg = 0; | |
217 | } | |
218 | ||
17661681 ZW |
219 | static int intel_agp_map_memory(struct agp_memory *mem) |
220 | { | |
f692775d | 221 | struct sg_table st; |
17661681 ZW |
222 | struct scatterlist *sg; |
223 | int i; | |
224 | ||
225 | DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); | |
226 | ||
f692775d | 227 | if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) |
17661681 | 228 | return -ENOMEM; |
17661681 | 229 | |
f692775d DW |
230 | mem->sg_list = sg = st.sgl; |
231 | ||
17661681 ZW |
232 | for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) |
233 | sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); | |
234 | ||
235 | mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, | |
236 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
91b8e305 DW |
237 | if (unlikely(!mem->num_sg)) { |
238 | intel_agp_free_sglist(mem); | |
17661681 ZW |
239 | return -ENOMEM; |
240 | } | |
241 | return 0; | |
242 | } | |
243 | ||
244 | static void intel_agp_unmap_memory(struct agp_memory *mem) | |
245 | { | |
246 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); | |
247 | ||
248 | pci_unmap_sg(intel_private.pcidev, mem->sg_list, | |
249 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
91b8e305 | 250 | intel_agp_free_sglist(mem); |
17661681 ZW |
251 | } |
252 | ||
253 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
254 | off_t pg_start, int mask_type) | |
255 | { | |
256 | struct scatterlist *sg; | |
257 | int i, j; | |
258 | ||
259 | j = pg_start; | |
260 | ||
261 | WARN_ON(!mem->num_sg); | |
262 | ||
263 | if (mem->num_sg == mem->page_count) { | |
264 | for_each_sg(mem->sg_list, sg, mem->page_count, i) { | |
265 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
266 | sg_dma_address(sg), mask_type), | |
267 | intel_private.gtt+j); | |
268 | j++; | |
269 | } | |
270 | } else { | |
271 | /* sg may merge pages, but we have to seperate | |
272 | * per-page addr for GTT */ | |
273 | unsigned int len, m; | |
274 | ||
275 | for_each_sg(mem->sg_list, sg, mem->num_sg, i) { | |
276 | len = sg_dma_len(sg) / PAGE_SIZE; | |
277 | for (m = 0; m < len; m++) { | |
278 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
279 | sg_dma_address(sg) + m * PAGE_SIZE, | |
280 | mask_type), | |
281 | intel_private.gtt+j); | |
282 | j++; | |
283 | } | |
284 | } | |
285 | } | |
286 | readl(intel_private.gtt+j-1); | |
287 | } | |
288 | ||
289 | #else | |
290 | ||
291 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
292 | off_t pg_start, int mask_type) | |
293 | { | |
294 | int i, j; | |
295 | ||
296 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
297 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 298 | page_to_phys(mem->pages[i]), mask_type), |
17661681 ZW |
299 | intel_private.gtt+j); |
300 | } | |
301 | ||
302 | readl(intel_private.gtt+j-1); | |
303 | } | |
304 | ||
305 | #endif | |
306 | ||
1da177e4 LT |
307 | static int intel_i810_fetch_size(void) |
308 | { | |
309 | u32 smram_miscc; | |
310 | struct aper_size_info_fixed *values; | |
311 | ||
312 | pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); | |
313 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
314 | ||
315 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
e3cf6951 | 316 | dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); |
1da177e4 LT |
317 | return 0; |
318 | } | |
319 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
320 | agp_bridge->previous_size = | |
321 | agp_bridge->current_size = (void *) (values + 1); | |
322 | agp_bridge->aperture_size_idx = 1; | |
323 | return values[1].size; | |
324 | } else { | |
325 | agp_bridge->previous_size = | |
326 | agp_bridge->current_size = (void *) (values); | |
327 | agp_bridge->aperture_size_idx = 0; | |
328 | return values[0].size; | |
329 | } | |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | static int intel_i810_configure(void) | |
335 | { | |
336 | struct aper_size_info_fixed *current_size; | |
337 | u32 temp; | |
338 | int i; | |
339 | ||
340 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
341 | ||
c4ca8817 WZ |
342 | if (!intel_private.registers) { |
343 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
e4ac5e4f DJ |
344 | temp &= 0xfff80000; |
345 | ||
c4ca8817 WZ |
346 | intel_private.registers = ioremap(temp, 128 * 4096); |
347 | if (!intel_private.registers) { | |
e3cf6951 BH |
348 | dev_err(&intel_private.pcidev->dev, |
349 | "can't remap memory\n"); | |
e4ac5e4f DJ |
350 | return -ENOMEM; |
351 | } | |
1da177e4 LT |
352 | } |
353 | ||
c4ca8817 | 354 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
1da177e4 LT |
355 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
356 | /* This will need to be dynamically assigned */ | |
e3cf6951 BH |
357 | dev_info(&intel_private.pcidev->dev, |
358 | "detected 4MB dedicated video ram\n"); | |
c4ca8817 | 359 | intel_private.num_dcache_entries = 1024; |
1da177e4 | 360 | } |
c4ca8817 | 361 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 | 362 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
c4ca8817 WZ |
363 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
364 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
365 | |
366 | if (agp_bridge->driver->needs_scratch_page) { | |
367 | for (i = 0; i < current_size->num_entries; i++) { | |
c4ca8817 | 368 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 369 | } |
44d49441 | 370 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ |
1da177e4 LT |
371 | } |
372 | global_cache_flush(); | |
373 | return 0; | |
374 | } | |
375 | ||
376 | static void intel_i810_cleanup(void) | |
377 | { | |
c4ca8817 WZ |
378 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
379 | readl(intel_private.registers); /* PCI Posting. */ | |
380 | iounmap(intel_private.registers); | |
1da177e4 LT |
381 | } |
382 | ||
383 | static void intel_i810_tlbflush(struct agp_memory *mem) | |
384 | { | |
385 | return; | |
386 | } | |
387 | ||
388 | static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |
389 | { | |
390 | return; | |
391 | } | |
392 | ||
393 | /* Exists to support ARGB cursors */ | |
07613ba2 | 394 | static struct page *i8xx_alloc_pages(void) |
1da177e4 | 395 | { |
f011ae74 | 396 | struct page *page; |
1da177e4 | 397 | |
66c669ba | 398 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
1da177e4 LT |
399 | if (page == NULL) |
400 | return NULL; | |
401 | ||
6d238cc4 AV |
402 | if (set_pages_uc(page, 4) < 0) { |
403 | set_pages_wb(page, 4); | |
89cf7ccc | 404 | __free_pages(page, 2); |
1da177e4 LT |
405 | return NULL; |
406 | } | |
1da177e4 | 407 | get_page(page); |
1da177e4 | 408 | atomic_inc(&agp_bridge->current_memory_agp); |
07613ba2 | 409 | return page; |
1da177e4 LT |
410 | } |
411 | ||
07613ba2 | 412 | static void i8xx_destroy_pages(struct page *page) |
1da177e4 | 413 | { |
07613ba2 | 414 | if (page == NULL) |
1da177e4 LT |
415 | return; |
416 | ||
6d238cc4 | 417 | set_pages_wb(page, 4); |
1da177e4 | 418 | put_page(page); |
89cf7ccc | 419 | __free_pages(page, 2); |
1da177e4 LT |
420 | atomic_dec(&agp_bridge->current_memory_agp); |
421 | } | |
422 | ||
a030ce44 TH |
423 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, |
424 | int type) | |
425 | { | |
426 | if (type < AGP_USER_TYPES) | |
427 | return type; | |
428 | else if (type == AGP_USER_CACHED_MEMORY) | |
429 | return INTEL_AGP_CACHED_MEMORY; | |
430 | else | |
431 | return 0; | |
432 | } | |
433 | ||
1da177e4 LT |
434 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
435 | int type) | |
436 | { | |
437 | int i, j, num_entries; | |
438 | void *temp; | |
a030ce44 TH |
439 | int ret = -EINVAL; |
440 | int mask_type; | |
1da177e4 | 441 | |
5aa80c72 | 442 | if (mem->page_count == 0) |
a030ce44 | 443 | goto out; |
5aa80c72 | 444 | |
1da177e4 LT |
445 | temp = agp_bridge->current_size; |
446 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
447 | ||
6a92a4e0 | 448 | if ((pg_start + mem->page_count) > num_entries) |
a030ce44 | 449 | goto out_err; |
6a92a4e0 | 450 | |
1da177e4 | 451 | |
a030ce44 TH |
452 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { |
453 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
454 | ret = -EBUSY; | |
455 | goto out_err; | |
1da177e4 | 456 | } |
1da177e4 LT |
457 | } |
458 | ||
a030ce44 TH |
459 | if (type != mem->type) |
460 | goto out_err; | |
5aa80c72 | 461 | |
a030ce44 TH |
462 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); |
463 | ||
464 | switch (mask_type) { | |
465 | case AGP_DCACHE_MEMORY: | |
466 | if (!mem->is_flushed) | |
467 | global_cache_flush(); | |
468 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
469 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
c4ca8817 | 470 | intel_private.registers+I810_PTE_BASE+(i*4)); |
a030ce44 | 471 | } |
c4ca8817 | 472 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
a030ce44 TH |
473 | break; |
474 | case AGP_PHYS_MEMORY: | |
475 | case AGP_NORMAL_MEMORY: | |
476 | if (!mem->is_flushed) | |
477 | global_cache_flush(); | |
478 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
479 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 480 | page_to_phys(mem->pages[i]), mask_type), |
c4ca8817 | 481 | intel_private.registers+I810_PTE_BASE+(j*4)); |
a030ce44 | 482 | } |
c4ca8817 | 483 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
a030ce44 TH |
484 | break; |
485 | default: | |
486 | goto out_err; | |
1da177e4 | 487 | } |
1da177e4 LT |
488 | |
489 | agp_bridge->driver->tlb_flush(mem); | |
a030ce44 TH |
490 | out: |
491 | ret = 0; | |
492 | out_err: | |
9516b030 | 493 | mem->is_flushed = true; |
a030ce44 | 494 | return ret; |
1da177e4 LT |
495 | } |
496 | ||
497 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
498 | int type) | |
499 | { | |
500 | int i; | |
501 | ||
5aa80c72 TH |
502 | if (mem->page_count == 0) |
503 | return 0; | |
504 | ||
1da177e4 | 505 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
c4ca8817 | 506 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 507 | } |
c4ca8817 | 508 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 509 | |
1da177e4 LT |
510 | agp_bridge->driver->tlb_flush(mem); |
511 | return 0; | |
512 | } | |
513 | ||
514 | /* | |
515 | * The i810/i830 requires a physical address to program its mouse | |
516 | * pointer into hardware. | |
517 | * However the Xserver still writes to it through the agp aperture. | |
518 | */ | |
519 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
520 | { | |
521 | struct agp_memory *new; | |
07613ba2 | 522 | struct page *page; |
1da177e4 | 523 | |
1da177e4 | 524 | switch (pg_count) { |
07613ba2 | 525 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); |
1da177e4 LT |
526 | break; |
527 | case 4: | |
528 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 | 529 | page = i8xx_alloc_pages(); |
1da177e4 LT |
530 | break; |
531 | default: | |
532 | return NULL; | |
533 | } | |
534 | ||
07613ba2 | 535 | if (page == NULL) |
1da177e4 LT |
536 | return NULL; |
537 | ||
538 | new = agp_create_memory(pg_count); | |
539 | if (new == NULL) | |
540 | return NULL; | |
541 | ||
07613ba2 | 542 | new->pages[0] = page; |
1da177e4 LT |
543 | if (pg_count == 4) { |
544 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 DA |
545 | new->pages[1] = new->pages[0] + 1; |
546 | new->pages[2] = new->pages[1] + 1; | |
547 | new->pages[3] = new->pages[2] + 1; | |
1da177e4 LT |
548 | } |
549 | new->page_count = pg_count; | |
550 | new->num_scratch_pages = pg_count; | |
551 | new->type = AGP_PHYS_MEMORY; | |
07613ba2 | 552 | new->physical = page_to_phys(new->pages[0]); |
1da177e4 LT |
553 | return new; |
554 | } | |
555 | ||
556 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
557 | { | |
558 | struct agp_memory *new; | |
559 | ||
560 | if (type == AGP_DCACHE_MEMORY) { | |
c4ca8817 | 561 | if (pg_count != intel_private.num_dcache_entries) |
1da177e4 LT |
562 | return NULL; |
563 | ||
564 | new = agp_create_memory(1); | |
565 | if (new == NULL) | |
566 | return NULL; | |
567 | ||
568 | new->type = AGP_DCACHE_MEMORY; | |
569 | new->page_count = pg_count; | |
570 | new->num_scratch_pages = 0; | |
a030ce44 | 571 | agp_free_page_array(new); |
1da177e4 LT |
572 | return new; |
573 | } | |
574 | if (type == AGP_PHYS_MEMORY) | |
575 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
576 | return NULL; |
577 | } | |
578 | ||
579 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
580 | { | |
581 | agp_free_key(curr->key); | |
6a92a4e0 | 582 | if (curr->type == AGP_PHYS_MEMORY) { |
1da177e4 | 583 | if (curr->page_count == 4) |
07613ba2 | 584 | i8xx_destroy_pages(curr->pages[0]); |
88d51967 | 585 | else { |
07613ba2 | 586 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 587 | AGP_PAGE_DESTROY_UNMAP); |
07613ba2 | 588 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 589 | AGP_PAGE_DESTROY_FREE); |
88d51967 | 590 | } |
a030ce44 | 591 | agp_free_page_array(curr); |
1da177e4 LT |
592 | } |
593 | kfree(curr); | |
594 | } | |
595 | ||
596 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 597 | dma_addr_t addr, int type) |
1da177e4 LT |
598 | { |
599 | /* Type checking must be done elsewhere */ | |
600 | return addr | bridge->driver->masks[type].mask; | |
601 | } | |
602 | ||
603 | static struct aper_size_info_fixed intel_i830_sizes[] = | |
604 | { | |
605 | {128, 32768, 5}, | |
606 | /* The 64M mode still requires a 128k gatt */ | |
607 | {64, 16384, 5}, | |
608 | {256, 65536, 6}, | |
65c25aad | 609 | {512, 131072, 7}, |
1da177e4 LT |
610 | }; |
611 | ||
1da177e4 LT |
612 | static void intel_i830_init_gtt_entries(void) |
613 | { | |
614 | u16 gmch_ctrl; | |
615 | int gtt_entries; | |
616 | u8 rdct; | |
617 | int local = 0; | |
618 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
c41e0deb | 619 | int size; /* reserved space (in kb) at the top of stolen memory */ |
1da177e4 | 620 | |
f011ae74 | 621 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 622 | |
c41e0deb EA |
623 | if (IS_I965) { |
624 | u32 pgetbl_ctl; | |
c4ca8817 | 625 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
c41e0deb | 626 | |
c41e0deb EA |
627 | /* The 965 has a field telling us the size of the GTT, |
628 | * which may be larger than what is necessary to map the | |
629 | * aperture. | |
630 | */ | |
631 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
632 | case I965_PGETBL_SIZE_128KB: | |
633 | size = 128; | |
634 | break; | |
635 | case I965_PGETBL_SIZE_256KB: | |
636 | size = 256; | |
637 | break; | |
638 | case I965_PGETBL_SIZE_512KB: | |
639 | size = 512; | |
640 | break; | |
4e8b6e25 ZW |
641 | case I965_PGETBL_SIZE_1MB: |
642 | size = 1024; | |
643 | break; | |
644 | case I965_PGETBL_SIZE_2MB: | |
645 | size = 2048; | |
646 | break; | |
647 | case I965_PGETBL_SIZE_1_5MB: | |
648 | size = 1024 + 512; | |
649 | break; | |
c41e0deb | 650 | default: |
e3cf6951 BH |
651 | dev_info(&intel_private.pcidev->dev, |
652 | "unknown page table size, assuming 512KB\n"); | |
c41e0deb EA |
653 | size = 512; |
654 | } | |
655 | size += 4; /* add in BIOS popup space */ | |
2177832f | 656 | } else if (IS_G33 && !IS_IGD) { |
874808c6 WZ |
657 | /* G33's GTT size defined in gmch_ctrl */ |
658 | switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { | |
659 | case G33_PGETBL_SIZE_1M: | |
660 | size = 1024; | |
661 | break; | |
662 | case G33_PGETBL_SIZE_2M: | |
663 | size = 2048; | |
664 | break; | |
665 | default: | |
e3cf6951 BH |
666 | dev_info(&agp_bridge->dev->dev, |
667 | "unknown page table size 0x%x, assuming 512KB\n", | |
874808c6 WZ |
668 | (gmch_ctrl & G33_PGETBL_SIZE_MASK)); |
669 | size = 512; | |
670 | } | |
671 | size += 4; | |
2177832f | 672 | } else if (IS_G4X || IS_IGD) { |
25ce77ab | 673 | /* On 4 series hardware, GTT stolen is separate from graphics |
82e14a62 EA |
674 | * stolen, ignore it in stolen gtt entries counting. However, |
675 | * 4KB of the stolen memory doesn't get mapped to the GTT. | |
676 | */ | |
677 | size = 4; | |
c41e0deb EA |
678 | } else { |
679 | /* On previous hardware, the GTT size was just what was | |
680 | * required to map the aperture. | |
681 | */ | |
682 | size = agp_bridge->driver->fetch_size() + 4; | |
683 | } | |
1da177e4 LT |
684 | |
685 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || | |
686 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
687 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { | |
688 | case I830_GMCH_GMS_STOLEN_512: | |
689 | gtt_entries = KB(512) - KB(size); | |
690 | break; | |
691 | case I830_GMCH_GMS_STOLEN_1024: | |
692 | gtt_entries = MB(1) - KB(size); | |
693 | break; | |
694 | case I830_GMCH_GMS_STOLEN_8192: | |
695 | gtt_entries = MB(8) - KB(size); | |
696 | break; | |
697 | case I830_GMCH_GMS_LOCAL: | |
c4ca8817 | 698 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
1da177e4 LT |
699 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * |
700 | MB(ddt[I830_RDRAM_DDT(rdct)]); | |
701 | local = 1; | |
702 | break; | |
703 | default: | |
704 | gtt_entries = 0; | |
705 | break; | |
706 | } | |
707 | } else { | |
e67aa27a | 708 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
1da177e4 LT |
709 | case I855_GMCH_GMS_STOLEN_1M: |
710 | gtt_entries = MB(1) - KB(size); | |
711 | break; | |
712 | case I855_GMCH_GMS_STOLEN_4M: | |
713 | gtt_entries = MB(4) - KB(size); | |
714 | break; | |
715 | case I855_GMCH_GMS_STOLEN_8M: | |
716 | gtt_entries = MB(8) - KB(size); | |
717 | break; | |
718 | case I855_GMCH_GMS_STOLEN_16M: | |
719 | gtt_entries = MB(16) - KB(size); | |
720 | break; | |
721 | case I855_GMCH_GMS_STOLEN_32M: | |
722 | gtt_entries = MB(32) - KB(size); | |
723 | break; | |
724 | case I915_GMCH_GMS_STOLEN_48M: | |
725 | /* Check it's really I915G */ | |
25ce77ab | 726 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
727 | gtt_entries = MB(48) - KB(size); |
728 | else | |
729 | gtt_entries = 0; | |
730 | break; | |
731 | case I915_GMCH_GMS_STOLEN_64M: | |
732 | /* Check it's really I915G */ | |
25ce77ab | 733 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
734 | gtt_entries = MB(64) - KB(size); |
735 | else | |
736 | gtt_entries = 0; | |
874808c6 WZ |
737 | break; |
738 | case G33_GMCH_GMS_STOLEN_128M: | |
25ce77ab | 739 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
740 | gtt_entries = MB(128) - KB(size); |
741 | else | |
742 | gtt_entries = 0; | |
743 | break; | |
744 | case G33_GMCH_GMS_STOLEN_256M: | |
25ce77ab | 745 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
746 | gtt_entries = MB(256) - KB(size); |
747 | else | |
748 | gtt_entries = 0; | |
749 | break; | |
25ce77ab ZW |
750 | case INTEL_GMCH_GMS_STOLEN_96M: |
751 | if (IS_I965 || IS_G4X) | |
752 | gtt_entries = MB(96) - KB(size); | |
753 | else | |
754 | gtt_entries = 0; | |
755 | break; | |
756 | case INTEL_GMCH_GMS_STOLEN_160M: | |
757 | if (IS_I965 || IS_G4X) | |
758 | gtt_entries = MB(160) - KB(size); | |
759 | else | |
760 | gtt_entries = 0; | |
761 | break; | |
762 | case INTEL_GMCH_GMS_STOLEN_224M: | |
763 | if (IS_I965 || IS_G4X) | |
764 | gtt_entries = MB(224) - KB(size); | |
765 | else | |
766 | gtt_entries = 0; | |
767 | break; | |
768 | case INTEL_GMCH_GMS_STOLEN_352M: | |
769 | if (IS_I965 || IS_G4X) | |
770 | gtt_entries = MB(352) - KB(size); | |
771 | else | |
772 | gtt_entries = 0; | |
773 | break; | |
1da177e4 LT |
774 | default: |
775 | gtt_entries = 0; | |
776 | break; | |
777 | } | |
778 | } | |
9c1e8a4e | 779 | if (gtt_entries > 0) { |
e3cf6951 | 780 | dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", |
1da177e4 | 781 | gtt_entries / KB(1), local ? "local" : "stolen"); |
9c1e8a4e LR |
782 | gtt_entries /= KB(4); |
783 | } else { | |
e3cf6951 BH |
784 | dev_info(&agp_bridge->dev->dev, |
785 | "no pre-allocated video memory detected\n"); | |
9c1e8a4e LR |
786 | gtt_entries = 0; |
787 | } | |
1da177e4 | 788 | |
c4ca8817 | 789 | intel_private.gtt_entries = gtt_entries; |
1da177e4 LT |
790 | } |
791 | ||
2162e6a2 DA |
792 | static void intel_i830_fini_flush(void) |
793 | { | |
794 | kunmap(intel_private.i8xx_page); | |
795 | intel_private.i8xx_flush_page = NULL; | |
796 | unmap_page_from_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
797 | |
798 | __free_page(intel_private.i8xx_page); | |
4d64dd9e | 799 | intel_private.i8xx_page = NULL; |
2162e6a2 DA |
800 | } |
801 | ||
802 | static void intel_i830_setup_flush(void) | |
803 | { | |
4d64dd9e DA |
804 | /* return if we've already set the flush mechanism up */ |
805 | if (intel_private.i8xx_page) | |
806 | return; | |
2162e6a2 DA |
807 | |
808 | intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); | |
f011ae74 | 809 | if (!intel_private.i8xx_page) |
2162e6a2 | 810 | return; |
2162e6a2 | 811 | |
2162e6a2 DA |
812 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); |
813 | if (!intel_private.i8xx_flush_page) | |
814 | intel_i830_fini_flush(); | |
815 | } | |
816 | ||
e517a5e9 EA |
817 | static void |
818 | do_wbinvd(void *null) | |
819 | { | |
820 | wbinvd(); | |
821 | } | |
822 | ||
823 | /* The chipset_flush interface needs to get data that has already been | |
824 | * flushed out of the CPU all the way out to main memory, because the GPU | |
825 | * doesn't snoop those buffers. | |
826 | * | |
827 | * The 8xx series doesn't have the same lovely interface for flushing the | |
828 | * chipset write buffers that the later chips do. According to the 865 | |
829 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
830 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
831 | * that it'll push whatever was in there out. It appears to work. | |
832 | */ | |
2162e6a2 DA |
833 | static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) |
834 | { | |
835 | unsigned int *pg = intel_private.i8xx_flush_page; | |
2162e6a2 | 836 | |
e517a5e9 | 837 | memset(pg, 0, 1024); |
f011ae74 | 838 | |
e517a5e9 EA |
839 | if (cpu_has_clflush) { |
840 | clflush_cache_range(pg, 1024); | |
841 | } else { | |
842 | if (on_each_cpu(do_wbinvd, NULL, 1) != 0) | |
843 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
844 | } | |
2162e6a2 DA |
845 | } |
846 | ||
1da177e4 LT |
847 | /* The intel i830 automatically initializes the agp aperture during POST. |
848 | * Use the memory already set aside for in the GTT. | |
849 | */ | |
850 | static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |
851 | { | |
852 | int page_order; | |
853 | struct aper_size_info_fixed *size; | |
854 | int num_entries; | |
855 | u32 temp; | |
856 | ||
857 | size = agp_bridge->current_size; | |
858 | page_order = size->page_order; | |
859 | num_entries = size->num_entries; | |
860 | agp_bridge->gatt_table_real = NULL; | |
861 | ||
f011ae74 | 862 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); |
1da177e4 LT |
863 | temp &= 0xfff80000; |
864 | ||
f011ae74 | 865 | intel_private.registers = ioremap(temp, 128 * 4096); |
c4ca8817 | 866 | if (!intel_private.registers) |
1da177e4 LT |
867 | return -ENOMEM; |
868 | ||
c4ca8817 | 869 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
870 | global_cache_flush(); /* FIXME: ?? */ |
871 | ||
872 | /* we have to call this as early as possible after the MMIO base address is known */ | |
873 | intel_i830_init_gtt_entries(); | |
874 | ||
875 | agp_bridge->gatt_table = NULL; | |
876 | ||
877 | agp_bridge->gatt_bus_addr = temp; | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
882 | /* Return the gatt table to a sane state. Use the top of stolen | |
883 | * memory for the GTT. | |
884 | */ | |
885 | static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) | |
886 | { | |
887 | return 0; | |
888 | } | |
889 | ||
890 | static int intel_i830_fetch_size(void) | |
891 | { | |
892 | u16 gmch_ctrl; | |
893 | struct aper_size_info_fixed *values; | |
894 | ||
895 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
896 | ||
897 | if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && | |
898 | agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { | |
899 | /* 855GM/852GM/865G has 128MB aperture size */ | |
900 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
901 | agp_bridge->aperture_size_idx = 0; | |
902 | return values[0].size; | |
903 | } | |
904 | ||
f011ae74 | 905 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 LT |
906 | |
907 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { | |
908 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
909 | agp_bridge->aperture_size_idx = 0; | |
910 | return values[0].size; | |
911 | } else { | |
912 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); | |
913 | agp_bridge->aperture_size_idx = 1; | |
914 | return values[1].size; | |
915 | } | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
920 | static int intel_i830_configure(void) | |
921 | { | |
922 | struct aper_size_info_fixed *current_size; | |
923 | u32 temp; | |
924 | u16 gmch_ctrl; | |
925 | int i; | |
926 | ||
927 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
928 | ||
f011ae74 | 929 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 LT |
930 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
931 | ||
f011ae74 | 932 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 933 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 934 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 935 | |
c4ca8817 WZ |
936 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
937 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
938 | |
939 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
940 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
941 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
1da177e4 | 942 | } |
44d49441 | 943 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ |
1da177e4 LT |
944 | } |
945 | ||
946 | global_cache_flush(); | |
2162e6a2 DA |
947 | |
948 | intel_i830_setup_flush(); | |
1da177e4 LT |
949 | return 0; |
950 | } | |
951 | ||
952 | static void intel_i830_cleanup(void) | |
953 | { | |
c4ca8817 | 954 | iounmap(intel_private.registers); |
1da177e4 LT |
955 | } |
956 | ||
f011ae74 DA |
957 | static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, |
958 | int type) | |
1da177e4 | 959 | { |
f011ae74 | 960 | int i, j, num_entries; |
1da177e4 | 961 | void *temp; |
a030ce44 TH |
962 | int ret = -EINVAL; |
963 | int mask_type; | |
1da177e4 | 964 | |
5aa80c72 | 965 | if (mem->page_count == 0) |
a030ce44 | 966 | goto out; |
5aa80c72 | 967 | |
1da177e4 LT |
968 | temp = agp_bridge->current_size; |
969 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
970 | ||
c4ca8817 | 971 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
972 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
973 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
974 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 975 | |
e3cf6951 BH |
976 | dev_info(&intel_private.pcidev->dev, |
977 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 978 | goto out_err; |
1da177e4 LT |
979 | } |
980 | ||
981 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 982 | goto out_err; |
1da177e4 LT |
983 | |
984 | /* The i830 can't check the GTT for entries since its read only, | |
985 | * depend on the caller to make the correct offset decisions. | |
986 | */ | |
987 | ||
a030ce44 TH |
988 | if (type != mem->type) |
989 | goto out_err; | |
990 | ||
991 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 992 | |
a030ce44 TH |
993 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
994 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
995 | goto out_err; | |
996 | ||
997 | if (!mem->is_flushed) | |
5aa80c72 | 998 | global_cache_flush(); |
1da177e4 LT |
999 | |
1000 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
1001 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 1002 | page_to_phys(mem->pages[i]), mask_type), |
c4ca8817 | 1003 | intel_private.registers+I810_PTE_BASE+(j*4)); |
1da177e4 | 1004 | } |
c4ca8817 | 1005 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
1da177e4 | 1006 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1007 | |
1008 | out: | |
1009 | ret = 0; | |
1010 | out_err: | |
9516b030 | 1011 | mem->is_flushed = true; |
a030ce44 | 1012 | return ret; |
1da177e4 LT |
1013 | } |
1014 | ||
f011ae74 DA |
1015 | static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, |
1016 | int type) | |
1da177e4 LT |
1017 | { |
1018 | int i; | |
1019 | ||
5aa80c72 TH |
1020 | if (mem->page_count == 0) |
1021 | return 0; | |
1da177e4 | 1022 | |
c4ca8817 | 1023 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1024 | dev_info(&intel_private.pcidev->dev, |
1025 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1026 | return -EINVAL; |
1027 | } | |
1028 | ||
1029 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
c4ca8817 | 1030 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 1031 | } |
c4ca8817 | 1032 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 1033 | |
1da177e4 LT |
1034 | agp_bridge->driver->tlb_flush(mem); |
1035 | return 0; | |
1036 | } | |
1037 | ||
f011ae74 | 1038 | static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) |
1da177e4 LT |
1039 | { |
1040 | if (type == AGP_PHYS_MEMORY) | |
1041 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
1042 | /* always return NULL for other allocation types for now */ |
1043 | return NULL; | |
1044 | } | |
1045 | ||
6c00a61e DA |
1046 | static int intel_alloc_chipset_flush_resource(void) |
1047 | { | |
1048 | int ret; | |
1049 | ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, | |
1050 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, | |
1051 | pcibios_align_resource, agp_bridge->dev); | |
6c00a61e | 1052 | |
2162e6a2 | 1053 | return ret; |
6c00a61e DA |
1054 | } |
1055 | ||
1056 | static void intel_i915_setup_chipset_flush(void) | |
1057 | { | |
1058 | int ret; | |
1059 | u32 temp; | |
1060 | ||
1061 | pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); | |
1062 | if (!(temp & 0x1)) { | |
1063 | intel_alloc_chipset_flush_resource(); | |
4d64dd9e | 1064 | intel_private.resource_valid = 1; |
6c00a61e DA |
1065 | pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
1066 | } else { | |
1067 | temp &= ~1; | |
1068 | ||
4d64dd9e | 1069 | intel_private.resource_valid = 1; |
6c00a61e DA |
1070 | intel_private.ifp_resource.start = temp; |
1071 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1072 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
1073 | /* some BIOSes reserve this area in a pnp some don't */ |
1074 | if (ret) | |
1075 | intel_private.resource_valid = 0; | |
6c00a61e DA |
1076 | } |
1077 | } | |
1078 | ||
1079 | static void intel_i965_g33_setup_chipset_flush(void) | |
1080 | { | |
1081 | u32 temp_hi, temp_lo; | |
1082 | int ret; | |
1083 | ||
1084 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); | |
1085 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); | |
1086 | ||
1087 | if (!(temp_lo & 0x1)) { | |
1088 | ||
1089 | intel_alloc_chipset_flush_resource(); | |
1090 | ||
4d64dd9e | 1091 | intel_private.resource_valid = 1; |
1fa4db7d AM |
1092 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, |
1093 | upper_32_bits(intel_private.ifp_resource.start)); | |
6c00a61e | 1094 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
6c00a61e DA |
1095 | } else { |
1096 | u64 l64; | |
f011ae74 | 1097 | |
6c00a61e DA |
1098 | temp_lo &= ~0x1; |
1099 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1100 | ||
4d64dd9e | 1101 | intel_private.resource_valid = 1; |
6c00a61e DA |
1102 | intel_private.ifp_resource.start = l64; |
1103 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1104 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
1105 | /* some BIOSes reserve this area in a pnp some don't */ |
1106 | if (ret) | |
1107 | intel_private.resource_valid = 0; | |
6c00a61e DA |
1108 | } |
1109 | } | |
1110 | ||
2162e6a2 DA |
1111 | static void intel_i9xx_setup_flush(void) |
1112 | { | |
4d64dd9e DA |
1113 | /* return if already configured */ |
1114 | if (intel_private.ifp_resource.start) | |
1115 | return; | |
2162e6a2 | 1116 | |
4d64dd9e | 1117 | /* setup a resource for this object */ |
2162e6a2 DA |
1118 | intel_private.ifp_resource.name = "Intel Flush Page"; |
1119 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1120 | ||
1121 | /* Setup chipset flush for 915 */ | |
7d15ddf7 | 1122 | if (IS_I965 || IS_G33 || IS_G4X) { |
2162e6a2 DA |
1123 | intel_i965_g33_setup_chipset_flush(); |
1124 | } else { | |
1125 | intel_i915_setup_chipset_flush(); | |
1126 | } | |
1127 | ||
1128 | if (intel_private.ifp_resource.start) { | |
1129 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); | |
1130 | if (!intel_private.i9xx_flush_page) | |
e3cf6951 | 1131 | dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); |
2162e6a2 DA |
1132 | } |
1133 | } | |
1134 | ||
1da177e4 LT |
1135 | static int intel_i915_configure(void) |
1136 | { | |
1137 | struct aper_size_info_fixed *current_size; | |
1138 | u32 temp; | |
1139 | u16 gmch_ctrl; | |
1140 | int i; | |
1141 | ||
1142 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
1143 | ||
c4ca8817 | 1144 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); |
1da177e4 LT |
1145 | |
1146 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1147 | ||
f011ae74 | 1148 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 1149 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 1150 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 1151 | |
c4ca8817 WZ |
1152 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
1153 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
1154 | |
1155 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
1156 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
1157 | writel(agp_bridge->scratch_page, intel_private.gtt+i); | |
1da177e4 | 1158 | } |
44d49441 | 1159 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
1da177e4 LT |
1160 | } |
1161 | ||
1162 | global_cache_flush(); | |
6c00a61e | 1163 | |
2162e6a2 | 1164 | intel_i9xx_setup_flush(); |
f011ae74 | 1165 | |
1da177e4 LT |
1166 | return 0; |
1167 | } | |
1168 | ||
1169 | static void intel_i915_cleanup(void) | |
1170 | { | |
2162e6a2 DA |
1171 | if (intel_private.i9xx_flush_page) |
1172 | iounmap(intel_private.i9xx_flush_page); | |
4d64dd9e DA |
1173 | if (intel_private.resource_valid) |
1174 | release_resource(&intel_private.ifp_resource); | |
1175 | intel_private.ifp_resource.start = 0; | |
1176 | intel_private.resource_valid = 0; | |
c4ca8817 WZ |
1177 | iounmap(intel_private.gtt); |
1178 | iounmap(intel_private.registers); | |
1da177e4 LT |
1179 | } |
1180 | ||
6c00a61e DA |
1181 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) |
1182 | { | |
2162e6a2 DA |
1183 | if (intel_private.i9xx_flush_page) |
1184 | writel(1, intel_private.i9xx_flush_page); | |
6c00a61e DA |
1185 | } |
1186 | ||
f011ae74 DA |
1187 | static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, |
1188 | int type) | |
1da177e4 | 1189 | { |
17661681 | 1190 | int num_entries; |
1da177e4 | 1191 | void *temp; |
a030ce44 TH |
1192 | int ret = -EINVAL; |
1193 | int mask_type; | |
1da177e4 | 1194 | |
5aa80c72 | 1195 | if (mem->page_count == 0) |
a030ce44 | 1196 | goto out; |
5aa80c72 | 1197 | |
1da177e4 LT |
1198 | temp = agp_bridge->current_size; |
1199 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1200 | ||
c4ca8817 | 1201 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1202 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
1203 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
1204 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 1205 | |
e3cf6951 BH |
1206 | dev_info(&intel_private.pcidev->dev, |
1207 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 1208 | goto out_err; |
1da177e4 LT |
1209 | } |
1210 | ||
1211 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 1212 | goto out_err; |
1da177e4 | 1213 | |
17661681 | 1214 | /* The i915 can't check the GTT for entries since it's read only; |
1da177e4 LT |
1215 | * depend on the caller to make the correct offset decisions. |
1216 | */ | |
1217 | ||
a030ce44 TH |
1218 | if (type != mem->type) |
1219 | goto out_err; | |
1220 | ||
1221 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 1222 | |
a030ce44 TH |
1223 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
1224 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1225 | goto out_err; | |
1226 | ||
1227 | if (!mem->is_flushed) | |
5aa80c72 | 1228 | global_cache_flush(); |
1da177e4 | 1229 | |
17661681 | 1230 | intel_agp_insert_sg_entries(mem, pg_start, mask_type); |
1da177e4 | 1231 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1232 | |
1233 | out: | |
1234 | ret = 0; | |
1235 | out_err: | |
9516b030 | 1236 | mem->is_flushed = true; |
a030ce44 | 1237 | return ret; |
1da177e4 LT |
1238 | } |
1239 | ||
f011ae74 DA |
1240 | static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, |
1241 | int type) | |
1da177e4 LT |
1242 | { |
1243 | int i; | |
1244 | ||
5aa80c72 TH |
1245 | if (mem->page_count == 0) |
1246 | return 0; | |
1da177e4 | 1247 | |
c4ca8817 | 1248 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1249 | dev_info(&intel_private.pcidev->dev, |
1250 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1251 | return -EINVAL; |
1252 | } | |
1253 | ||
f011ae74 | 1254 | for (i = pg_start; i < (mem->page_count + pg_start); i++) |
c4ca8817 | 1255 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f011ae74 | 1256 | |
c4ca8817 | 1257 | readl(intel_private.gtt+i-1); |
1da177e4 | 1258 | |
1da177e4 LT |
1259 | agp_bridge->driver->tlb_flush(mem); |
1260 | return 0; | |
1261 | } | |
1262 | ||
c41e0deb EA |
1263 | /* Return the aperture size by just checking the resource length. The effect |
1264 | * described in the spec of the MSAC registers is just changing of the | |
1265 | * resource size. | |
1266 | */ | |
1267 | static int intel_i9xx_fetch_size(void) | |
1da177e4 | 1268 | { |
1eaf122c | 1269 | int num_sizes = ARRAY_SIZE(intel_i830_sizes); |
c41e0deb EA |
1270 | int aper_size; /* size in megabytes */ |
1271 | int i; | |
1da177e4 | 1272 | |
c4ca8817 | 1273 | aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); |
1da177e4 | 1274 | |
c41e0deb EA |
1275 | for (i = 0; i < num_sizes; i++) { |
1276 | if (aper_size == intel_i830_sizes[i].size) { | |
1277 | agp_bridge->current_size = intel_i830_sizes + i; | |
1278 | agp_bridge->previous_size = agp_bridge->current_size; | |
1279 | return aper_size; | |
1280 | } | |
1281 | } | |
1da177e4 | 1282 | |
c41e0deb | 1283 | return 0; |
1da177e4 LT |
1284 | } |
1285 | ||
1286 | /* The intel i915 automatically initializes the agp aperture during POST. | |
1287 | * Use the memory already set aside for in the GTT. | |
1288 | */ | |
1289 | static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |
1290 | { | |
1291 | int page_order; | |
1292 | struct aper_size_info_fixed *size; | |
1293 | int num_entries; | |
1294 | u32 temp, temp2; | |
4740622c | 1295 | int gtt_map_size = 256 * 1024; |
1da177e4 LT |
1296 | |
1297 | size = agp_bridge->current_size; | |
1298 | page_order = size->page_order; | |
1299 | num_entries = size->num_entries; | |
1300 | agp_bridge->gatt_table_real = NULL; | |
1301 | ||
c4ca8817 | 1302 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
f011ae74 | 1303 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); |
1da177e4 | 1304 | |
4740622c ZW |
1305 | if (IS_G33) |
1306 | gtt_map_size = 1024 * 1024; /* 1M on G33 */ | |
1307 | intel_private.gtt = ioremap(temp2, gtt_map_size); | |
c4ca8817 | 1308 | if (!intel_private.gtt) |
1da177e4 LT |
1309 | return -ENOMEM; |
1310 | ||
1311 | temp &= 0xfff80000; | |
1312 | ||
f011ae74 | 1313 | intel_private.registers = ioremap(temp, 128 * 4096); |
5bdbc7dc ST |
1314 | if (!intel_private.registers) { |
1315 | iounmap(intel_private.gtt); | |
1da177e4 | 1316 | return -ENOMEM; |
5bdbc7dc | 1317 | } |
1da177e4 | 1318 | |
c4ca8817 | 1319 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
1320 | global_cache_flush(); /* FIXME: ? */ |
1321 | ||
1322 | /* we have to call this as early as possible after the MMIO base address is known */ | |
1323 | intel_i830_init_gtt_entries(); | |
1324 | ||
1325 | agp_bridge->gatt_table = NULL; | |
1326 | ||
1327 | agp_bridge->gatt_bus_addr = temp; | |
1328 | ||
1329 | return 0; | |
1330 | } | |
7d915a38 LT |
1331 | |
1332 | /* | |
1333 | * The i965 supports 36-bit physical addresses, but to keep | |
1334 | * the format of the GTT the same, the bits that don't fit | |
1335 | * in a 32-bit word are shifted down to bits 4..7. | |
1336 | * | |
1337 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1338 | * is always zero on 32-bit architectures, so no need to make | |
1339 | * this conditional. | |
1340 | */ | |
1341 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 1342 | dma_addr_t addr, int type) |
7d915a38 LT |
1343 | { |
1344 | /* Shift high bits down */ | |
1345 | addr |= (addr >> 28) & 0xf0; | |
1346 | ||
1347 | /* Type checking must be done elsewhere */ | |
1348 | return addr | bridge->driver->masks[type].mask; | |
1349 | } | |
1350 | ||
25ce77ab ZW |
1351 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) |
1352 | { | |
1353 | switch (agp_bridge->dev->device) { | |
99d32bd5 | 1354 | case PCI_DEVICE_ID_INTEL_GM45_HB: |
25ce77ab ZW |
1355 | case PCI_DEVICE_ID_INTEL_IGD_E_HB: |
1356 | case PCI_DEVICE_ID_INTEL_Q45_HB: | |
1357 | case PCI_DEVICE_ID_INTEL_G45_HB: | |
a50ccc6c | 1358 | case PCI_DEVICE_ID_INTEL_G41_HB: |
38d8a956 | 1359 | case PCI_DEVICE_ID_INTEL_B43_HB: |
32cb055b ZW |
1360 | case PCI_DEVICE_ID_INTEL_IGDNG_D_HB: |
1361 | case PCI_DEVICE_ID_INTEL_IGDNG_M_HB: | |
07fb6111 | 1362 | case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB: |
9cf1e35c | 1363 | case PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB: |
25ce77ab ZW |
1364 | *gtt_offset = *gtt_size = MB(2); |
1365 | break; | |
1366 | default: | |
1367 | *gtt_offset = *gtt_size = KB(512); | |
1368 | } | |
1369 | } | |
1370 | ||
65c25aad | 1371 | /* The intel i965 automatically initializes the agp aperture during POST. |
c41e0deb EA |
1372 | * Use the memory already set aside for in the GTT. |
1373 | */ | |
65c25aad EA |
1374 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) |
1375 | { | |
62c96b9d DA |
1376 | int page_order; |
1377 | struct aper_size_info_fixed *size; | |
1378 | int num_entries; | |
1379 | u32 temp; | |
1380 | int gtt_offset, gtt_size; | |
65c25aad | 1381 | |
62c96b9d DA |
1382 | size = agp_bridge->current_size; |
1383 | page_order = size->page_order; | |
1384 | num_entries = size->num_entries; | |
1385 | agp_bridge->gatt_table_real = NULL; | |
65c25aad | 1386 | |
62c96b9d | 1387 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
65c25aad | 1388 | |
62c96b9d | 1389 | temp &= 0xfff00000; |
65c25aad | 1390 | |
25ce77ab | 1391 | intel_i965_get_gtt_range(>t_offset, >t_size); |
4e8b6e25 | 1392 | |
62c96b9d | 1393 | intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); |
65c25aad | 1394 | |
62c96b9d DA |
1395 | if (!intel_private.gtt) |
1396 | return -ENOMEM; | |
65c25aad | 1397 | |
62c96b9d DA |
1398 | intel_private.registers = ioremap(temp, 128 * 4096); |
1399 | if (!intel_private.registers) { | |
5bdbc7dc ST |
1400 | iounmap(intel_private.gtt); |
1401 | return -ENOMEM; | |
1402 | } | |
65c25aad | 1403 | |
62c96b9d DA |
1404 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1405 | global_cache_flush(); /* FIXME: ? */ | |
65c25aad | 1406 | |
62c96b9d DA |
1407 | /* we have to call this as early as possible after the MMIO base address is known */ |
1408 | intel_i830_init_gtt_entries(); | |
65c25aad | 1409 | |
62c96b9d | 1410 | agp_bridge->gatt_table = NULL; |
65c25aad | 1411 | |
62c96b9d | 1412 | agp_bridge->gatt_bus_addr = temp; |
65c25aad | 1413 | |
62c96b9d | 1414 | return 0; |
65c25aad EA |
1415 | } |
1416 | ||
1da177e4 LT |
1417 | |
1418 | static int intel_fetch_size(void) | |
1419 | { | |
1420 | int i; | |
1421 | u16 temp; | |
1422 | struct aper_size_info_16 *values; | |
1423 | ||
1424 | pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1425 | values = A_SIZE_16(agp_bridge->driver->aperture_sizes); | |
1426 | ||
1427 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1428 | if (temp == values[i].size_value) { | |
1429 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); | |
1430 | agp_bridge->aperture_size_idx = i; | |
1431 | return values[i].size; | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | return 0; | |
1436 | } | |
1437 | ||
1438 | static int __intel_8xx_fetch_size(u8 temp) | |
1439 | { | |
1440 | int i; | |
1441 | struct aper_size_info_8 *values; | |
1442 | ||
1443 | values = A_SIZE_8(agp_bridge->driver->aperture_sizes); | |
1444 | ||
1445 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1446 | if (temp == values[i].size_value) { | |
1447 | agp_bridge->previous_size = | |
1448 | agp_bridge->current_size = (void *) (values + i); | |
1449 | agp_bridge->aperture_size_idx = i; | |
1450 | return values[i].size; | |
1451 | } | |
1452 | } | |
1453 | return 0; | |
1454 | } | |
1455 | ||
1456 | static int intel_8xx_fetch_size(void) | |
1457 | { | |
1458 | u8 temp; | |
1459 | ||
1460 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1461 | return __intel_8xx_fetch_size(temp); | |
1462 | } | |
1463 | ||
1464 | static int intel_815_fetch_size(void) | |
1465 | { | |
1466 | u8 temp; | |
1467 | ||
1468 | /* Intel 815 chipsets have a _weird_ APSIZE register with only | |
1469 | * one non-reserved bit, so mask the others out ... */ | |
1470 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1471 | temp &= (1 << 3); | |
1472 | ||
1473 | return __intel_8xx_fetch_size(temp); | |
1474 | } | |
1475 | ||
1476 | static void intel_tlbflush(struct agp_memory *mem) | |
1477 | { | |
1478 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); | |
1479 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1480 | } | |
1481 | ||
1482 | ||
1483 | static void intel_8xx_tlbflush(struct agp_memory *mem) | |
1484 | { | |
1485 | u32 temp; | |
1486 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1487 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); | |
1488 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1489 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); | |
1490 | } | |
1491 | ||
1492 | ||
1493 | static void intel_cleanup(void) | |
1494 | { | |
1495 | u16 temp; | |
1496 | struct aper_size_info_16 *previous_size; | |
1497 | ||
1498 | previous_size = A_SIZE_16(agp_bridge->previous_size); | |
1499 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1500 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1501 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1502 | } | |
1503 | ||
1504 | ||
1505 | static void intel_8xx_cleanup(void) | |
1506 | { | |
1507 | u16 temp; | |
1508 | struct aper_size_info_8 *previous_size; | |
1509 | ||
1510 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1511 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1512 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1513 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1514 | } | |
1515 | ||
1516 | ||
1517 | static int intel_configure(void) | |
1518 | { | |
1519 | u32 temp; | |
1520 | u16 temp2; | |
1521 | struct aper_size_info_16 *current_size; | |
1522 | ||
1523 | current_size = A_SIZE_16(agp_bridge->current_size); | |
1524 | ||
1525 | /* aperture size */ | |
1526 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1527 | ||
1528 | /* address to map to */ | |
1529 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1530 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1531 | ||
1532 | /* attbase - aperture base */ | |
1533 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1534 | ||
1535 | /* agpctrl */ | |
1536 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1537 | ||
1538 | /* paccfg/nbxcfg */ | |
1539 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1540 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, | |
1541 | (temp2 & ~(1 << 10)) | (1 << 9)); | |
1542 | /* clear any possible error conditions */ | |
1543 | pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); | |
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | static int intel_815_configure(void) | |
1548 | { | |
1549 | u32 temp, addr; | |
1550 | u8 temp2; | |
1551 | struct aper_size_info_8 *current_size; | |
1552 | ||
1553 | /* attbase - aperture base */ | |
1554 | /* the Intel 815 chipset spec. says that bits 29-31 in the | |
1555 | * ATTBASE register are reserved -> try not to write them */ | |
1556 | if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { | |
e3cf6951 | 1557 | dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); |
1da177e4 LT |
1558 | return -EINVAL; |
1559 | } | |
1560 | ||
1561 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1562 | ||
1563 | /* aperture size */ | |
1564 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1565 | current_size->size_value); | |
1566 | ||
1567 | /* address to map to */ | |
1568 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1569 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1570 | ||
1571 | pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); | |
1572 | addr &= INTEL_815_ATTBASE_MASK; | |
1573 | addr |= agp_bridge->gatt_bus_addr; | |
1574 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); | |
1575 | ||
1576 | /* agpctrl */ | |
1577 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1578 | ||
1579 | /* apcont */ | |
1580 | pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); | |
1581 | pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); | |
1582 | ||
1583 | /* clear any possible error conditions */ | |
1584 | /* Oddness : this chipset seems to have no ERRSTS register ! */ | |
1585 | return 0; | |
1586 | } | |
1587 | ||
1588 | static void intel_820_tlbflush(struct agp_memory *mem) | |
1589 | { | |
1590 | return; | |
1591 | } | |
1592 | ||
1593 | static void intel_820_cleanup(void) | |
1594 | { | |
1595 | u8 temp; | |
1596 | struct aper_size_info_8 *previous_size; | |
1597 | ||
1598 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1599 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); | |
1600 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, | |
1601 | temp & ~(1 << 1)); | |
1602 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1603 | previous_size->size_value); | |
1604 | } | |
1605 | ||
1606 | ||
1607 | static int intel_820_configure(void) | |
1608 | { | |
1609 | u32 temp; | |
1610 | u8 temp2; | |
1611 | struct aper_size_info_8 *current_size; | |
1612 | ||
1613 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1614 | ||
1615 | /* aperture size */ | |
1616 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1617 | ||
1618 | /* address to map to */ | |
1619 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1620 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1621 | ||
1622 | /* attbase - aperture base */ | |
1623 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1624 | ||
1625 | /* agpctrl */ | |
1626 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1627 | ||
1628 | /* global enable aperture access */ | |
1629 | /* This flag is not accessed through MCHCFG register as in */ | |
1630 | /* i850 chipset. */ | |
1631 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); | |
1632 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); | |
1633 | /* clear any possible AGP-related error conditions */ | |
1634 | pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); | |
1635 | return 0; | |
1636 | } | |
1637 | ||
1638 | static int intel_840_configure(void) | |
1639 | { | |
1640 | u32 temp; | |
1641 | u16 temp2; | |
1642 | struct aper_size_info_8 *current_size; | |
1643 | ||
1644 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1645 | ||
1646 | /* aperture size */ | |
1647 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1648 | ||
1649 | /* address to map to */ | |
1650 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1651 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1652 | ||
1653 | /* attbase - aperture base */ | |
1654 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1655 | ||
1656 | /* agpctrl */ | |
1657 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1658 | ||
1659 | /* mcgcfg */ | |
1660 | pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); | |
1661 | pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); | |
1662 | /* clear any possible error conditions */ | |
1663 | pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); | |
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | static int intel_845_configure(void) | |
1668 | { | |
1669 | u32 temp; | |
1670 | u8 temp2; | |
1671 | struct aper_size_info_8 *current_size; | |
1672 | ||
1673 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1674 | ||
1675 | /* aperture size */ | |
1676 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1677 | ||
b0825488 MG |
1678 | if (agp_bridge->apbase_config != 0) { |
1679 | pci_write_config_dword(agp_bridge->dev, AGP_APBASE, | |
1680 | agp_bridge->apbase_config); | |
1681 | } else { | |
1682 | /* address to map to */ | |
1683 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1684 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1685 | agp_bridge->apbase_config = temp; | |
1686 | } | |
1da177e4 LT |
1687 | |
1688 | /* attbase - aperture base */ | |
1689 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1690 | ||
1691 | /* agpctrl */ | |
1692 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1693 | ||
1694 | /* agpm */ | |
1695 | pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); | |
1696 | pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); | |
1697 | /* clear any possible error conditions */ | |
1698 | pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); | |
2162e6a2 DA |
1699 | |
1700 | intel_i830_setup_flush(); | |
1da177e4 LT |
1701 | return 0; |
1702 | } | |
1703 | ||
1704 | static int intel_850_configure(void) | |
1705 | { | |
1706 | u32 temp; | |
1707 | u16 temp2; | |
1708 | struct aper_size_info_8 *current_size; | |
1709 | ||
1710 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1711 | ||
1712 | /* aperture size */ | |
1713 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1714 | ||
1715 | /* address to map to */ | |
1716 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1717 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1718 | ||
1719 | /* attbase - aperture base */ | |
1720 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1721 | ||
1722 | /* agpctrl */ | |
1723 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1724 | ||
1725 | /* mcgcfg */ | |
1726 | pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); | |
1727 | pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); | |
1728 | /* clear any possible AGP-related error conditions */ | |
1729 | pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); | |
1730 | return 0; | |
1731 | } | |
1732 | ||
1733 | static int intel_860_configure(void) | |
1734 | { | |
1735 | u32 temp; | |
1736 | u16 temp2; | |
1737 | struct aper_size_info_8 *current_size; | |
1738 | ||
1739 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1740 | ||
1741 | /* aperture size */ | |
1742 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1743 | ||
1744 | /* address to map to */ | |
1745 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1746 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1747 | ||
1748 | /* attbase - aperture base */ | |
1749 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1750 | ||
1751 | /* agpctrl */ | |
1752 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1753 | ||
1754 | /* mcgcfg */ | |
1755 | pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); | |
1756 | pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); | |
1757 | /* clear any possible AGP-related error conditions */ | |
1758 | pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); | |
1759 | return 0; | |
1760 | } | |
1761 | ||
1762 | static int intel_830mp_configure(void) | |
1763 | { | |
1764 | u32 temp; | |
1765 | u16 temp2; | |
1766 | struct aper_size_info_8 *current_size; | |
1767 | ||
1768 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1769 | ||
1770 | /* aperture size */ | |
1771 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1772 | ||
1773 | /* address to map to */ | |
1774 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1775 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1776 | ||
1777 | /* attbase - aperture base */ | |
1778 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1779 | ||
1780 | /* agpctrl */ | |
1781 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1782 | ||
1783 | /* gmch */ | |
1784 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1785 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); | |
1786 | /* clear any possible AGP-related error conditions */ | |
1787 | pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); | |
1788 | return 0; | |
1789 | } | |
1790 | ||
1791 | static int intel_7505_configure(void) | |
1792 | { | |
1793 | u32 temp; | |
1794 | u16 temp2; | |
1795 | struct aper_size_info_8 *current_size; | |
1796 | ||
1797 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1798 | ||
1799 | /* aperture size */ | |
1800 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1801 | ||
1802 | /* address to map to */ | |
1803 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1804 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1805 | ||
1806 | /* attbase - aperture base */ | |
1807 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1808 | ||
1809 | /* agpctrl */ | |
1810 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1811 | ||
1812 | /* mchcfg */ | |
1813 | pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); | |
1814 | pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); | |
1815 | ||
1816 | return 0; | |
1817 | } | |
1818 | ||
1819 | /* Setup function */ | |
e5524f35 | 1820 | static const struct gatt_mask intel_generic_masks[] = |
1da177e4 LT |
1821 | { |
1822 | {.mask = 0x00000017, .type = 0} | |
1823 | }; | |
1824 | ||
e5524f35 | 1825 | static const struct aper_size_info_8 intel_815_sizes[2] = |
1da177e4 LT |
1826 | { |
1827 | {64, 16384, 4, 0}, | |
1828 | {32, 8192, 3, 8}, | |
1829 | }; | |
1830 | ||
e5524f35 | 1831 | static const struct aper_size_info_8 intel_8xx_sizes[7] = |
1da177e4 LT |
1832 | { |
1833 | {256, 65536, 6, 0}, | |
1834 | {128, 32768, 5, 32}, | |
1835 | {64, 16384, 4, 48}, | |
1836 | {32, 8192, 3, 56}, | |
1837 | {16, 4096, 2, 60}, | |
1838 | {8, 2048, 1, 62}, | |
1839 | {4, 1024, 0, 63} | |
1840 | }; | |
1841 | ||
e5524f35 | 1842 | static const struct aper_size_info_16 intel_generic_sizes[7] = |
1da177e4 LT |
1843 | { |
1844 | {256, 65536, 6, 0}, | |
1845 | {128, 32768, 5, 32}, | |
1846 | {64, 16384, 4, 48}, | |
1847 | {32, 8192, 3, 56}, | |
1848 | {16, 4096, 2, 60}, | |
1849 | {8, 2048, 1, 62}, | |
1850 | {4, 1024, 0, 63} | |
1851 | }; | |
1852 | ||
e5524f35 | 1853 | static const struct aper_size_info_8 intel_830mp_sizes[4] = |
1da177e4 LT |
1854 | { |
1855 | {256, 65536, 6, 0}, | |
1856 | {128, 32768, 5, 32}, | |
1857 | {64, 16384, 4, 48}, | |
1858 | {32, 8192, 3, 56} | |
1859 | }; | |
1860 | ||
e5524f35 | 1861 | static const struct agp_bridge_driver intel_generic_driver = { |
1da177e4 LT |
1862 | .owner = THIS_MODULE, |
1863 | .aperture_sizes = intel_generic_sizes, | |
1864 | .size_type = U16_APER_SIZE, | |
1865 | .num_aperture_sizes = 7, | |
1866 | .configure = intel_configure, | |
1867 | .fetch_size = intel_fetch_size, | |
1868 | .cleanup = intel_cleanup, | |
1869 | .tlb_flush = intel_tlbflush, | |
1870 | .mask_memory = agp_generic_mask_memory, | |
1871 | .masks = intel_generic_masks, | |
1872 | .agp_enable = agp_generic_enable, | |
1873 | .cache_flush = global_cache_flush, | |
1874 | .create_gatt_table = agp_generic_create_gatt_table, | |
1875 | .free_gatt_table = agp_generic_free_gatt_table, | |
1876 | .insert_memory = agp_generic_insert_memory, | |
1877 | .remove_memory = agp_generic_remove_memory, | |
1878 | .alloc_by_type = agp_generic_alloc_by_type, | |
1879 | .free_by_type = agp_generic_free_by_type, | |
1880 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1881 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1882 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1883 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1884 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1885 | }; |
1886 | ||
e5524f35 | 1887 | static const struct agp_bridge_driver intel_810_driver = { |
1da177e4 LT |
1888 | .owner = THIS_MODULE, |
1889 | .aperture_sizes = intel_i810_sizes, | |
1890 | .size_type = FIXED_APER_SIZE, | |
1891 | .num_aperture_sizes = 2, | |
c7258012 | 1892 | .needs_scratch_page = true, |
1da177e4 LT |
1893 | .configure = intel_i810_configure, |
1894 | .fetch_size = intel_i810_fetch_size, | |
1895 | .cleanup = intel_i810_cleanup, | |
1896 | .tlb_flush = intel_i810_tlbflush, | |
1897 | .mask_memory = intel_i810_mask_memory, | |
1898 | .masks = intel_i810_masks, | |
1899 | .agp_enable = intel_i810_agp_enable, | |
1900 | .cache_flush = global_cache_flush, | |
1901 | .create_gatt_table = agp_generic_create_gatt_table, | |
1902 | .free_gatt_table = agp_generic_free_gatt_table, | |
1903 | .insert_memory = intel_i810_insert_entries, | |
1904 | .remove_memory = intel_i810_remove_entries, | |
1905 | .alloc_by_type = intel_i810_alloc_by_type, | |
1906 | .free_by_type = intel_i810_free_by_type, | |
1907 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1908 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1909 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1910 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1911 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1912 | }; |
1913 | ||
e5524f35 | 1914 | static const struct agp_bridge_driver intel_815_driver = { |
1da177e4 LT |
1915 | .owner = THIS_MODULE, |
1916 | .aperture_sizes = intel_815_sizes, | |
1917 | .size_type = U8_APER_SIZE, | |
1918 | .num_aperture_sizes = 2, | |
1919 | .configure = intel_815_configure, | |
1920 | .fetch_size = intel_815_fetch_size, | |
1921 | .cleanup = intel_8xx_cleanup, | |
1922 | .tlb_flush = intel_8xx_tlbflush, | |
1923 | .mask_memory = agp_generic_mask_memory, | |
1924 | .masks = intel_generic_masks, | |
1925 | .agp_enable = agp_generic_enable, | |
1926 | .cache_flush = global_cache_flush, | |
1927 | .create_gatt_table = agp_generic_create_gatt_table, | |
1928 | .free_gatt_table = agp_generic_free_gatt_table, | |
1929 | .insert_memory = agp_generic_insert_memory, | |
1930 | .remove_memory = agp_generic_remove_memory, | |
1931 | .alloc_by_type = agp_generic_alloc_by_type, | |
1932 | .free_by_type = agp_generic_free_by_type, | |
1933 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1934 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1935 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1936 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 1937 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1938 | }; |
1939 | ||
e5524f35 | 1940 | static const struct agp_bridge_driver intel_830_driver = { |
1da177e4 LT |
1941 | .owner = THIS_MODULE, |
1942 | .aperture_sizes = intel_i830_sizes, | |
1943 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 1944 | .num_aperture_sizes = 4, |
c7258012 | 1945 | .needs_scratch_page = true, |
1da177e4 LT |
1946 | .configure = intel_i830_configure, |
1947 | .fetch_size = intel_i830_fetch_size, | |
1948 | .cleanup = intel_i830_cleanup, | |
1949 | .tlb_flush = intel_i810_tlbflush, | |
1950 | .mask_memory = intel_i810_mask_memory, | |
1951 | .masks = intel_i810_masks, | |
1952 | .agp_enable = intel_i810_agp_enable, | |
1953 | .cache_flush = global_cache_flush, | |
1954 | .create_gatt_table = intel_i830_create_gatt_table, | |
1955 | .free_gatt_table = intel_i830_free_gatt_table, | |
1956 | .insert_memory = intel_i830_insert_entries, | |
1957 | .remove_memory = intel_i830_remove_entries, | |
1958 | .alloc_by_type = intel_i830_alloc_by_type, | |
1959 | .free_by_type = intel_i810_free_by_type, | |
1960 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1961 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1962 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1963 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1964 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
2162e6a2 | 1965 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
1966 | }; |
1967 | ||
e5524f35 | 1968 | static const struct agp_bridge_driver intel_820_driver = { |
1da177e4 LT |
1969 | .owner = THIS_MODULE, |
1970 | .aperture_sizes = intel_8xx_sizes, | |
1971 | .size_type = U8_APER_SIZE, | |
1972 | .num_aperture_sizes = 7, | |
1973 | .configure = intel_820_configure, | |
1974 | .fetch_size = intel_8xx_fetch_size, | |
1975 | .cleanup = intel_820_cleanup, | |
1976 | .tlb_flush = intel_820_tlbflush, | |
1977 | .mask_memory = agp_generic_mask_memory, | |
1978 | .masks = intel_generic_masks, | |
1979 | .agp_enable = agp_generic_enable, | |
1980 | .cache_flush = global_cache_flush, | |
1981 | .create_gatt_table = agp_generic_create_gatt_table, | |
1982 | .free_gatt_table = agp_generic_free_gatt_table, | |
1983 | .insert_memory = agp_generic_insert_memory, | |
1984 | .remove_memory = agp_generic_remove_memory, | |
1985 | .alloc_by_type = agp_generic_alloc_by_type, | |
1986 | .free_by_type = agp_generic_free_by_type, | |
1987 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1988 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1989 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1990 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1991 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1992 | }; |
1993 | ||
e5524f35 | 1994 | static const struct agp_bridge_driver intel_830mp_driver = { |
1da177e4 LT |
1995 | .owner = THIS_MODULE, |
1996 | .aperture_sizes = intel_830mp_sizes, | |
1997 | .size_type = U8_APER_SIZE, | |
1998 | .num_aperture_sizes = 4, | |
1999 | .configure = intel_830mp_configure, | |
2000 | .fetch_size = intel_8xx_fetch_size, | |
2001 | .cleanup = intel_8xx_cleanup, | |
2002 | .tlb_flush = intel_8xx_tlbflush, | |
2003 | .mask_memory = agp_generic_mask_memory, | |
2004 | .masks = intel_generic_masks, | |
2005 | .agp_enable = agp_generic_enable, | |
2006 | .cache_flush = global_cache_flush, | |
2007 | .create_gatt_table = agp_generic_create_gatt_table, | |
2008 | .free_gatt_table = agp_generic_free_gatt_table, | |
2009 | .insert_memory = agp_generic_insert_memory, | |
2010 | .remove_memory = agp_generic_remove_memory, | |
2011 | .alloc_by_type = agp_generic_alloc_by_type, | |
2012 | .free_by_type = agp_generic_free_by_type, | |
2013 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2014 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2015 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2016 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2017 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2018 | }; |
2019 | ||
e5524f35 | 2020 | static const struct agp_bridge_driver intel_840_driver = { |
1da177e4 LT |
2021 | .owner = THIS_MODULE, |
2022 | .aperture_sizes = intel_8xx_sizes, | |
2023 | .size_type = U8_APER_SIZE, | |
2024 | .num_aperture_sizes = 7, | |
2025 | .configure = intel_840_configure, | |
2026 | .fetch_size = intel_8xx_fetch_size, | |
2027 | .cleanup = intel_8xx_cleanup, | |
2028 | .tlb_flush = intel_8xx_tlbflush, | |
2029 | .mask_memory = agp_generic_mask_memory, | |
2030 | .masks = intel_generic_masks, | |
2031 | .agp_enable = agp_generic_enable, | |
2032 | .cache_flush = global_cache_flush, | |
2033 | .create_gatt_table = agp_generic_create_gatt_table, | |
2034 | .free_gatt_table = agp_generic_free_gatt_table, | |
2035 | .insert_memory = agp_generic_insert_memory, | |
2036 | .remove_memory = agp_generic_remove_memory, | |
2037 | .alloc_by_type = agp_generic_alloc_by_type, | |
2038 | .free_by_type = agp_generic_free_by_type, | |
2039 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2040 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2041 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2042 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2043 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2044 | }; |
2045 | ||
e5524f35 | 2046 | static const struct agp_bridge_driver intel_845_driver = { |
1da177e4 LT |
2047 | .owner = THIS_MODULE, |
2048 | .aperture_sizes = intel_8xx_sizes, | |
2049 | .size_type = U8_APER_SIZE, | |
2050 | .num_aperture_sizes = 7, | |
2051 | .configure = intel_845_configure, | |
2052 | .fetch_size = intel_8xx_fetch_size, | |
2053 | .cleanup = intel_8xx_cleanup, | |
2054 | .tlb_flush = intel_8xx_tlbflush, | |
2055 | .mask_memory = agp_generic_mask_memory, | |
2056 | .masks = intel_generic_masks, | |
2057 | .agp_enable = agp_generic_enable, | |
2058 | .cache_flush = global_cache_flush, | |
2059 | .create_gatt_table = agp_generic_create_gatt_table, | |
2060 | .free_gatt_table = agp_generic_free_gatt_table, | |
2061 | .insert_memory = agp_generic_insert_memory, | |
2062 | .remove_memory = agp_generic_remove_memory, | |
2063 | .alloc_by_type = agp_generic_alloc_by_type, | |
2064 | .free_by_type = agp_generic_free_by_type, | |
2065 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2066 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2067 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2068 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2069 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
2162e6a2 | 2070 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
2071 | }; |
2072 | ||
e5524f35 | 2073 | static const struct agp_bridge_driver intel_850_driver = { |
1da177e4 LT |
2074 | .owner = THIS_MODULE, |
2075 | .aperture_sizes = intel_8xx_sizes, | |
2076 | .size_type = U8_APER_SIZE, | |
2077 | .num_aperture_sizes = 7, | |
2078 | .configure = intel_850_configure, | |
2079 | .fetch_size = intel_8xx_fetch_size, | |
2080 | .cleanup = intel_8xx_cleanup, | |
2081 | .tlb_flush = intel_8xx_tlbflush, | |
2082 | .mask_memory = agp_generic_mask_memory, | |
2083 | .masks = intel_generic_masks, | |
2084 | .agp_enable = agp_generic_enable, | |
2085 | .cache_flush = global_cache_flush, | |
2086 | .create_gatt_table = agp_generic_create_gatt_table, | |
2087 | .free_gatt_table = agp_generic_free_gatt_table, | |
2088 | .insert_memory = agp_generic_insert_memory, | |
2089 | .remove_memory = agp_generic_remove_memory, | |
2090 | .alloc_by_type = agp_generic_alloc_by_type, | |
2091 | .free_by_type = agp_generic_free_by_type, | |
2092 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2093 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2094 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2095 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2096 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2097 | }; |
2098 | ||
e5524f35 | 2099 | static const struct agp_bridge_driver intel_860_driver = { |
1da177e4 LT |
2100 | .owner = THIS_MODULE, |
2101 | .aperture_sizes = intel_8xx_sizes, | |
2102 | .size_type = U8_APER_SIZE, | |
2103 | .num_aperture_sizes = 7, | |
2104 | .configure = intel_860_configure, | |
2105 | .fetch_size = intel_8xx_fetch_size, | |
2106 | .cleanup = intel_8xx_cleanup, | |
2107 | .tlb_flush = intel_8xx_tlbflush, | |
2108 | .mask_memory = agp_generic_mask_memory, | |
2109 | .masks = intel_generic_masks, | |
2110 | .agp_enable = agp_generic_enable, | |
2111 | .cache_flush = global_cache_flush, | |
2112 | .create_gatt_table = agp_generic_create_gatt_table, | |
2113 | .free_gatt_table = agp_generic_free_gatt_table, | |
2114 | .insert_memory = agp_generic_insert_memory, | |
2115 | .remove_memory = agp_generic_remove_memory, | |
2116 | .alloc_by_type = agp_generic_alloc_by_type, | |
2117 | .free_by_type = agp_generic_free_by_type, | |
2118 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2119 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2120 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2121 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2122 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2123 | }; |
2124 | ||
e5524f35 | 2125 | static const struct agp_bridge_driver intel_915_driver = { |
1da177e4 LT |
2126 | .owner = THIS_MODULE, |
2127 | .aperture_sizes = intel_i830_sizes, | |
2128 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 2129 | .num_aperture_sizes = 4, |
c7258012 | 2130 | .needs_scratch_page = true, |
1da177e4 | 2131 | .configure = intel_i915_configure, |
c41e0deb | 2132 | .fetch_size = intel_i9xx_fetch_size, |
1da177e4 LT |
2133 | .cleanup = intel_i915_cleanup, |
2134 | .tlb_flush = intel_i810_tlbflush, | |
2135 | .mask_memory = intel_i810_mask_memory, | |
2136 | .masks = intel_i810_masks, | |
2137 | .agp_enable = intel_i810_agp_enable, | |
2138 | .cache_flush = global_cache_flush, | |
2139 | .create_gatt_table = intel_i915_create_gatt_table, | |
2140 | .free_gatt_table = intel_i830_free_gatt_table, | |
2141 | .insert_memory = intel_i915_insert_entries, | |
2142 | .remove_memory = intel_i915_remove_entries, | |
2143 | .alloc_by_type = intel_i830_alloc_by_type, | |
2144 | .free_by_type = intel_i810_free_by_type, | |
2145 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2146 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2147 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2148 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2149 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2150 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2151 | #ifdef USE_PCI_DMA_API |
2152 | .agp_map_page = intel_agp_map_page, | |
2153 | .agp_unmap_page = intel_agp_unmap_page, | |
2154 | .agp_map_memory = intel_agp_map_memory, | |
2155 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2156 | #endif | |
1da177e4 LT |
2157 | }; |
2158 | ||
e5524f35 | 2159 | static const struct agp_bridge_driver intel_i965_driver = { |
62c96b9d DA |
2160 | .owner = THIS_MODULE, |
2161 | .aperture_sizes = intel_i830_sizes, | |
2162 | .size_type = FIXED_APER_SIZE, | |
2163 | .num_aperture_sizes = 4, | |
2164 | .needs_scratch_page = true, | |
0e480e5f DA |
2165 | .configure = intel_i915_configure, |
2166 | .fetch_size = intel_i9xx_fetch_size, | |
62c96b9d DA |
2167 | .cleanup = intel_i915_cleanup, |
2168 | .tlb_flush = intel_i810_tlbflush, | |
2169 | .mask_memory = intel_i965_mask_memory, | |
2170 | .masks = intel_i810_masks, | |
2171 | .agp_enable = intel_i810_agp_enable, | |
2172 | .cache_flush = global_cache_flush, | |
2173 | .create_gatt_table = intel_i965_create_gatt_table, | |
2174 | .free_gatt_table = intel_i830_free_gatt_table, | |
2175 | .insert_memory = intel_i915_insert_entries, | |
2176 | .remove_memory = intel_i915_remove_entries, | |
2177 | .alloc_by_type = intel_i830_alloc_by_type, | |
2178 | .free_by_type = intel_i810_free_by_type, | |
2179 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2180 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2181 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2182 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2183 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2184 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2185 | #ifdef USE_PCI_DMA_API |
2186 | .agp_map_page = intel_agp_map_page, | |
2187 | .agp_unmap_page = intel_agp_unmap_page, | |
2188 | .agp_map_memory = intel_agp_map_memory, | |
2189 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2190 | #endif | |
65c25aad | 2191 | }; |
1da177e4 | 2192 | |
e5524f35 | 2193 | static const struct agp_bridge_driver intel_7505_driver = { |
1da177e4 LT |
2194 | .owner = THIS_MODULE, |
2195 | .aperture_sizes = intel_8xx_sizes, | |
2196 | .size_type = U8_APER_SIZE, | |
2197 | .num_aperture_sizes = 7, | |
2198 | .configure = intel_7505_configure, | |
2199 | .fetch_size = intel_8xx_fetch_size, | |
2200 | .cleanup = intel_8xx_cleanup, | |
2201 | .tlb_flush = intel_8xx_tlbflush, | |
2202 | .mask_memory = agp_generic_mask_memory, | |
2203 | .masks = intel_generic_masks, | |
2204 | .agp_enable = agp_generic_enable, | |
2205 | .cache_flush = global_cache_flush, | |
2206 | .create_gatt_table = agp_generic_create_gatt_table, | |
2207 | .free_gatt_table = agp_generic_free_gatt_table, | |
2208 | .insert_memory = agp_generic_insert_memory, | |
2209 | .remove_memory = agp_generic_remove_memory, | |
2210 | .alloc_by_type = agp_generic_alloc_by_type, | |
2211 | .free_by_type = agp_generic_free_by_type, | |
2212 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2213 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2214 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2215 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2216 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2217 | }; |
2218 | ||
874808c6 | 2219 | static const struct agp_bridge_driver intel_g33_driver = { |
62c96b9d DA |
2220 | .owner = THIS_MODULE, |
2221 | .aperture_sizes = intel_i830_sizes, | |
2222 | .size_type = FIXED_APER_SIZE, | |
2223 | .num_aperture_sizes = 4, | |
2224 | .needs_scratch_page = true, | |
2225 | .configure = intel_i915_configure, | |
2226 | .fetch_size = intel_i9xx_fetch_size, | |
2227 | .cleanup = intel_i915_cleanup, | |
2228 | .tlb_flush = intel_i810_tlbflush, | |
2229 | .mask_memory = intel_i965_mask_memory, | |
2230 | .masks = intel_i810_masks, | |
2231 | .agp_enable = intel_i810_agp_enable, | |
2232 | .cache_flush = global_cache_flush, | |
2233 | .create_gatt_table = intel_i915_create_gatt_table, | |
2234 | .free_gatt_table = intel_i830_free_gatt_table, | |
2235 | .insert_memory = intel_i915_insert_entries, | |
2236 | .remove_memory = intel_i915_remove_entries, | |
2237 | .alloc_by_type = intel_i830_alloc_by_type, | |
2238 | .free_by_type = intel_i810_free_by_type, | |
2239 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2240 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2241 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2242 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2243 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2244 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2245 | #ifdef USE_PCI_DMA_API |
2246 | .agp_map_page = intel_agp_map_page, | |
2247 | .agp_unmap_page = intel_agp_unmap_page, | |
2248 | .agp_map_memory = intel_agp_map_memory, | |
2249 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2250 | #endif | |
874808c6 | 2251 | }; |
1da177e4 | 2252 | |
9614ece1 | 2253 | static int find_gmch(u16 device) |
1da177e4 | 2254 | { |
9614ece1 | 2255 | struct pci_dev *gmch_device; |
1da177e4 | 2256 | |
9614ece1 WZ |
2257 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
2258 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
2259 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
f011ae74 | 2260 | device, gmch_device); |
1da177e4 LT |
2261 | } |
2262 | ||
9614ece1 | 2263 | if (!gmch_device) |
1da177e4 LT |
2264 | return 0; |
2265 | ||
9614ece1 | 2266 | intel_private.pcidev = gmch_device; |
1da177e4 LT |
2267 | return 1; |
2268 | } | |
2269 | ||
9614ece1 WZ |
2270 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
2271 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
2272 | * which one should be used if a gmch_chip_id is present. | |
2273 | */ | |
2274 | static const struct intel_driver_description { | |
2275 | unsigned int chip_id; | |
2276 | unsigned int gmch_chip_id; | |
88889851 | 2277 | unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ |
9614ece1 WZ |
2278 | char *name; |
2279 | const struct agp_bridge_driver *driver; | |
2280 | const struct agp_bridge_driver *gmch_driver; | |
2281 | } intel_agp_chipsets[] = { | |
88889851 WZ |
2282 | { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, |
2283 | { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, | |
2284 | { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, | |
2285 | { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", | |
9614ece1 | 2286 | NULL, &intel_810_driver }, |
88889851 | 2287 | { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", |
9614ece1 | 2288 | NULL, &intel_810_driver }, |
88889851 | 2289 | { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", |
9614ece1 | 2290 | NULL, &intel_810_driver }, |
88889851 WZ |
2291 | { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", |
2292 | &intel_815_driver, &intel_810_driver }, | |
2293 | { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2294 | { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2295 | { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", | |
9614ece1 | 2296 | &intel_830mp_driver, &intel_830_driver }, |
88889851 WZ |
2297 | { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, |
2298 | { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, | |
2299 | { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", | |
9614ece1 | 2300 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2301 | { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, |
347486bb SH |
2302 | { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", |
2303 | &intel_845_driver, &intel_830_driver }, | |
88889851 WZ |
2304 | { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, |
2305 | { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", | |
9614ece1 | 2306 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
2307 | { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, |
2308 | { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", | |
9614ece1 | 2309 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2310 | { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, |
e914a36a CM |
2311 | { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", |
2312 | NULL, &intel_915_driver }, | |
88889851 | 2313 | { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", |
47d46379 | 2314 | NULL, &intel_915_driver }, |
88889851 | 2315 | { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", |
47d46379 | 2316 | NULL, &intel_915_driver }, |
88889851 | 2317 | { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", |
47d46379 | 2318 | NULL, &intel_915_driver }, |
dde47876 | 2319 | { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", |
47d46379 | 2320 | NULL, &intel_915_driver }, |
dde47876 | 2321 | { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", |
47d46379 | 2322 | NULL, &intel_915_driver }, |
88889851 | 2323 | { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", |
47d46379 | 2324 | NULL, &intel_i965_driver }, |
9119f85a | 2325 | { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", |
47d46379 | 2326 | NULL, &intel_i965_driver }, |
88889851 | 2327 | { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", |
47d46379 | 2328 | NULL, &intel_i965_driver }, |
88889851 | 2329 | { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", |
47d46379 | 2330 | NULL, &intel_i965_driver }, |
dde47876 | 2331 | { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", |
47d46379 | 2332 | NULL, &intel_i965_driver }, |
dde47876 | 2333 | { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", |
47d46379 | 2334 | NULL, &intel_i965_driver }, |
88889851 WZ |
2335 | { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, |
2336 | { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, | |
2337 | { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", | |
47d46379 | 2338 | NULL, &intel_g33_driver }, |
88889851 | 2339 | { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", |
47d46379 | 2340 | NULL, &intel_g33_driver }, |
88889851 | 2341 | { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", |
47d46379 | 2342 | NULL, &intel_g33_driver }, |
2177832f SL |
2343 | { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD", |
2344 | NULL, &intel_g33_driver }, | |
2345 | { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD", | |
2346 | NULL, &intel_g33_driver }, | |
99d32bd5 | 2347 | { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, |
b854b2ab | 2348 | "Mobile Intel® GM45 Express", NULL, &intel_i965_driver }, |
25ce77ab ZW |
2349 | { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, |
2350 | "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, | |
2351 | { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, | |
2352 | "Q45/Q43", NULL, &intel_i965_driver }, | |
2353 | { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, | |
2354 | "G45/G43", NULL, &intel_i965_driver }, | |
38d8a956 FH |
2355 | { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0, |
2356 | "B43", NULL, &intel_i965_driver }, | |
a50ccc6c ZW |
2357 | { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, |
2358 | "G41", NULL, &intel_i965_driver }, | |
32cb055b ZW |
2359 | { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, |
2360 | "IGDNG/D", NULL, &intel_i965_driver }, | |
2361 | { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, | |
2362 | "IGDNG/M", NULL, &intel_i965_driver }, | |
07fb6111 ZW |
2363 | { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, |
2364 | "IGDNG/MA", NULL, &intel_i965_driver }, | |
9cf1e35c ZW |
2365 | { PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, |
2366 | "IGDNG/MC2", NULL, &intel_i965_driver }, | |
88889851 | 2367 | { 0, 0, 0, NULL, NULL, NULL } |
9614ece1 WZ |
2368 | }; |
2369 | ||
1da177e4 LT |
2370 | static int __devinit agp_intel_probe(struct pci_dev *pdev, |
2371 | const struct pci_device_id *ent) | |
2372 | { | |
2373 | struct agp_bridge_data *bridge; | |
1da177e4 LT |
2374 | u8 cap_ptr = 0; |
2375 | struct resource *r; | |
9614ece1 | 2376 | int i; |
1da177e4 LT |
2377 | |
2378 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
2379 | ||
2380 | bridge = agp_alloc_bridge(); | |
2381 | if (!bridge) | |
2382 | return -ENOMEM; | |
2383 | ||
9614ece1 WZ |
2384 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { |
2385 | /* In case that multiple models of gfx chip may | |
2386 | stand on same host bridge type, this can be | |
2387 | sure we detect the right IGD. */ | |
88889851 WZ |
2388 | if (pdev->device == intel_agp_chipsets[i].chip_id) { |
2389 | if ((intel_agp_chipsets[i].gmch_chip_id != 0) && | |
2390 | find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { | |
2391 | bridge->driver = | |
2392 | intel_agp_chipsets[i].gmch_driver; | |
2393 | break; | |
2394 | } else if (intel_agp_chipsets[i].multi_gmch_chip) { | |
2395 | continue; | |
2396 | } else { | |
2397 | bridge->driver = intel_agp_chipsets[i].driver; | |
2398 | break; | |
2399 | } | |
2400 | } | |
9614ece1 WZ |
2401 | } |
2402 | ||
2403 | if (intel_agp_chipsets[i].name == NULL) { | |
1da177e4 | 2404 | if (cap_ptr) |
e3cf6951 BH |
2405 | dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", |
2406 | pdev->vendor, pdev->device); | |
9614ece1 WZ |
2407 | agp_put_bridge(bridge); |
2408 | return -ENODEV; | |
2409 | } | |
2410 | ||
9614ece1 | 2411 | if (bridge->driver == NULL) { |
47d46379 WZ |
2412 | /* bridge has no AGP and no IGD detected */ |
2413 | if (cap_ptr) | |
e3cf6951 BH |
2414 | dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", |
2415 | intel_agp_chipsets[i].gmch_chip_id); | |
1da177e4 LT |
2416 | agp_put_bridge(bridge); |
2417 | return -ENODEV; | |
f011ae74 | 2418 | } |
1da177e4 LT |
2419 | |
2420 | bridge->dev = pdev; | |
2421 | bridge->capndx = cap_ptr; | |
c4ca8817 | 2422 | bridge->dev_private_data = &intel_private; |
1da177e4 | 2423 | |
e3cf6951 | 2424 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); |
1da177e4 LT |
2425 | |
2426 | /* | |
2427 | * The following fixes the case where the BIOS has "forgotten" to | |
2428 | * provide an address range for the GART. | |
2429 | * 20030610 - hamish@zot.org | |
2430 | */ | |
2431 | r = &pdev->resource[0]; | |
2432 | if (!r->start && r->end) { | |
6a92a4e0 | 2433 | if (pci_assign_resource(pdev, 0)) { |
e3cf6951 | 2434 | dev_err(&pdev->dev, "can't assign resource 0\n"); |
1da177e4 LT |
2435 | agp_put_bridge(bridge); |
2436 | return -ENODEV; | |
2437 | } | |
2438 | } | |
2439 | ||
2440 | /* | |
2441 | * If the device has not been properly setup, the following will catch | |
2442 | * the problem and should stop the system from crashing. | |
2443 | * 20030610 - hamish@zot.org | |
2444 | */ | |
2445 | if (pci_enable_device(pdev)) { | |
e3cf6951 | 2446 | dev_err(&pdev->dev, "can't enable PCI device\n"); |
1da177e4 LT |
2447 | agp_put_bridge(bridge); |
2448 | return -ENODEV; | |
2449 | } | |
2450 | ||
2451 | /* Fill in the mode register */ | |
2452 | if (cap_ptr) { | |
2453 | pci_read_config_dword(pdev, | |
2454 | bridge->capndx+PCI_AGP_STATUS, | |
2455 | &bridge->mode); | |
2456 | } | |
2457 | ||
ec402ba9 DW |
2458 | if (bridge->driver->mask_memory == intel_i965_mask_memory) |
2459 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) | |
2460 | dev_err(&intel_private.pcidev->dev, | |
2461 | "set gfx device dma mask 36bit failed!\n"); | |
2462 | ||
1da177e4 LT |
2463 | pci_set_drvdata(pdev, bridge); |
2464 | return agp_add_bridge(bridge); | |
1da177e4 LT |
2465 | } |
2466 | ||
2467 | static void __devexit agp_intel_remove(struct pci_dev *pdev) | |
2468 | { | |
2469 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2470 | ||
2471 | agp_remove_bridge(bridge); | |
2472 | ||
c4ca8817 WZ |
2473 | if (intel_private.pcidev) |
2474 | pci_dev_put(intel_private.pcidev); | |
1da177e4 LT |
2475 | |
2476 | agp_put_bridge(bridge); | |
2477 | } | |
2478 | ||
85be7d60 | 2479 | #ifdef CONFIG_PM |
1da177e4 LT |
2480 | static int agp_intel_resume(struct pci_dev *pdev) |
2481 | { | |
2482 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
a8c84df9 | 2483 | int ret_val; |
1da177e4 | 2484 | |
1da177e4 LT |
2485 | if (bridge->driver == &intel_generic_driver) |
2486 | intel_configure(); | |
2487 | else if (bridge->driver == &intel_850_driver) | |
2488 | intel_850_configure(); | |
2489 | else if (bridge->driver == &intel_845_driver) | |
2490 | intel_845_configure(); | |
2491 | else if (bridge->driver == &intel_830mp_driver) | |
2492 | intel_830mp_configure(); | |
2493 | else if (bridge->driver == &intel_915_driver) | |
2494 | intel_i915_configure(); | |
2495 | else if (bridge->driver == &intel_830_driver) | |
2496 | intel_i830_configure(); | |
2497 | else if (bridge->driver == &intel_810_driver) | |
2498 | intel_i810_configure(); | |
08da3f41 DJ |
2499 | else if (bridge->driver == &intel_i965_driver) |
2500 | intel_i915_configure(); | |
1da177e4 | 2501 | |
a8c84df9 KP |
2502 | ret_val = agp_rebind_memory(); |
2503 | if (ret_val != 0) | |
2504 | return ret_val; | |
2505 | ||
1da177e4 LT |
2506 | return 0; |
2507 | } | |
85be7d60 | 2508 | #endif |
1da177e4 LT |
2509 | |
2510 | static struct pci_device_id agp_intel_pci_table[] = { | |
2511 | #define ID(x) \ | |
2512 | { \ | |
2513 | .class = (PCI_CLASS_BRIDGE_HOST << 8), \ | |
2514 | .class_mask = ~0, \ | |
2515 | .vendor = PCI_VENDOR_ID_INTEL, \ | |
2516 | .device = x, \ | |
2517 | .subvendor = PCI_ANY_ID, \ | |
2518 | .subdevice = PCI_ANY_ID, \ | |
2519 | } | |
2520 | ID(PCI_DEVICE_ID_INTEL_82443LX_0), | |
2521 | ID(PCI_DEVICE_ID_INTEL_82443BX_0), | |
2522 | ID(PCI_DEVICE_ID_INTEL_82443GX_0), | |
2523 | ID(PCI_DEVICE_ID_INTEL_82810_MC1), | |
2524 | ID(PCI_DEVICE_ID_INTEL_82810_MC3), | |
2525 | ID(PCI_DEVICE_ID_INTEL_82810E_MC), | |
2526 | ID(PCI_DEVICE_ID_INTEL_82815_MC), | |
2527 | ID(PCI_DEVICE_ID_INTEL_82820_HB), | |
2528 | ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), | |
2529 | ID(PCI_DEVICE_ID_INTEL_82830_HB), | |
2530 | ID(PCI_DEVICE_ID_INTEL_82840_HB), | |
2531 | ID(PCI_DEVICE_ID_INTEL_82845_HB), | |
2532 | ID(PCI_DEVICE_ID_INTEL_82845G_HB), | |
2533 | ID(PCI_DEVICE_ID_INTEL_82850_HB), | |
347486bb | 2534 | ID(PCI_DEVICE_ID_INTEL_82854_HB), |
1da177e4 LT |
2535 | ID(PCI_DEVICE_ID_INTEL_82855PM_HB), |
2536 | ID(PCI_DEVICE_ID_INTEL_82855GM_HB), | |
2537 | ID(PCI_DEVICE_ID_INTEL_82860_HB), | |
2538 | ID(PCI_DEVICE_ID_INTEL_82865_HB), | |
2539 | ID(PCI_DEVICE_ID_INTEL_82875_HB), | |
2540 | ID(PCI_DEVICE_ID_INTEL_7505_0), | |
2541 | ID(PCI_DEVICE_ID_INTEL_7205_0), | |
e914a36a | 2542 | ID(PCI_DEVICE_ID_INTEL_E7221_HB), |
1da177e4 LT |
2543 | ID(PCI_DEVICE_ID_INTEL_82915G_HB), |
2544 | ID(PCI_DEVICE_ID_INTEL_82915GM_HB), | |
d0de98fa | 2545 | ID(PCI_DEVICE_ID_INTEL_82945G_HB), |
3b0e8ead | 2546 | ID(PCI_DEVICE_ID_INTEL_82945GM_HB), |
dde47876 | 2547 | ID(PCI_DEVICE_ID_INTEL_82945GME_HB), |
2177832f SL |
2548 | ID(PCI_DEVICE_ID_INTEL_IGDGM_HB), |
2549 | ID(PCI_DEVICE_ID_INTEL_IGDG_HB), | |
65c25aad | 2550 | ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), |
9119f85a | 2551 | ID(PCI_DEVICE_ID_INTEL_82G35_HB), |
65c25aad EA |
2552 | ID(PCI_DEVICE_ID_INTEL_82965Q_HB), |
2553 | ID(PCI_DEVICE_ID_INTEL_82965G_HB), | |
4598af33 | 2554 | ID(PCI_DEVICE_ID_INTEL_82965GM_HB), |
dde47876 | 2555 | ID(PCI_DEVICE_ID_INTEL_82965GME_HB), |
874808c6 WZ |
2556 | ID(PCI_DEVICE_ID_INTEL_G33_HB), |
2557 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), | |
2558 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), | |
99d32bd5 | 2559 | ID(PCI_DEVICE_ID_INTEL_GM45_HB), |
25ce77ab ZW |
2560 | ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), |
2561 | ID(PCI_DEVICE_ID_INTEL_Q45_HB), | |
2562 | ID(PCI_DEVICE_ID_INTEL_G45_HB), | |
a50ccc6c | 2563 | ID(PCI_DEVICE_ID_INTEL_G41_HB), |
38d8a956 | 2564 | ID(PCI_DEVICE_ID_INTEL_B43_HB), |
32cb055b ZW |
2565 | ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB), |
2566 | ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB), | |
07fb6111 | 2567 | ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB), |
9cf1e35c | 2568 | ID(PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB), |
1da177e4 LT |
2569 | { } |
2570 | }; | |
2571 | ||
2572 | MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); | |
2573 | ||
2574 | static struct pci_driver agp_intel_pci_driver = { | |
2575 | .name = "agpgart-intel", | |
2576 | .id_table = agp_intel_pci_table, | |
2577 | .probe = agp_intel_probe, | |
2578 | .remove = __devexit_p(agp_intel_remove), | |
85be7d60 | 2579 | #ifdef CONFIG_PM |
1da177e4 | 2580 | .resume = agp_intel_resume, |
85be7d60 | 2581 | #endif |
1da177e4 LT |
2582 | }; |
2583 | ||
2584 | static int __init agp_intel_init(void) | |
2585 | { | |
2586 | if (agp_off) | |
2587 | return -EINVAL; | |
2588 | return pci_register_driver(&agp_intel_pci_driver); | |
2589 | } | |
2590 | ||
2591 | static void __exit agp_intel_cleanup(void) | |
2592 | { | |
2593 | pci_unregister_driver(&agp_intel_pci_driver); | |
2594 | } | |
2595 | ||
2596 | module_init(agp_intel_init); | |
2597 | module_exit(agp_intel_cleanup); | |
2598 | ||
f4432c5c | 2599 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); |
1da177e4 | 2600 | MODULE_LICENSE("GPL and additional rights"); |