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[PATCH] x86-64: Account for module percpu space separately from kernel percpu
[net-next-2.6.git] / drivers / char / agp / amd64-agp.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/init.h>
14#include <linux/agp_backend.h>
8c65b4a6 15#include <linux/mmzone.h>
4e57b681 16#include <asm/page.h> /* PAGE_SIZE */
a32073bf 17#include <asm/k8.h>
1da177e4
LT		 18#include "agp.h"
19
1da177e4
LT		 20/* PTE bits. */
21#define GPTE_VALID 1
22#define GPTE_COHERENT 2
23
24/* Aperture control register bits. */
25#define GARTEN (1<<0)
26#define DISGARTCPU (1<<4)
27#define DISGARTIO (1<<5)
28
29/* GART cache control register bits. */
30#define INVGART (1<<0)
31#define GARTPTEERR (1<<1)
32
33/* K8 On-cpu GART registers */
34#define AMD64_GARTAPERTURECTL 0x90
35#define AMD64_GARTAPERTUREBASE 0x94
36#define AMD64_GARTTABLEBASE 0x98
37#define AMD64_GARTCACHECTL 0x9c
38#define AMD64_GARTEN (1<<0)
39
40/* NVIDIA K8 registers */
41#define NVIDIA_X86_64_0_APBASE 0x10
42#define NVIDIA_X86_64_1_APBASE1 0x50
43#define NVIDIA_X86_64_1_APLIMIT1 0x54
44#define NVIDIA_X86_64_1_APSIZE 0xa8
45#define NVIDIA_X86_64_1_APBASE2 0xd8
46#define NVIDIA_X86_64_1_APLIMIT2 0xdc
47
48/* ULi K8 registers */
49#define ULI_X86_64_BASE_ADDR 0x10
50#define ULI_X86_64_HTT_FEA_REG 0x50
51#define ULI_X86_64_ENU_SCR_REG 0x54
52
1da177e4 53static struct resource *aperture_resource;
172efbb4 54static int __initdata agp_try_unsupported = 1;
1da177e4 55
1da177e4
LT		 56static void amd64_tlbflush(struct agp_memory *temp)
57{
a32073bf 58 k8_flush_garts();
1da177e4
LT		 59}
60
61static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
62{
63 int i, j, num_entries;
64 long long tmp;
a030ce44
TH		 65 int mask_type;
66 struct agp_bridge_data *bridge = mem->bridge;
1da177e4
LT		 67 u32 pte;
68
69 num_entries = agp_num_entries();
70
a030ce44 71 if (type != mem->type)
1da177e4 72 return -EINVAL;
a030ce44
TH		 73 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
74 if (mask_type != 0)
75 return -EINVAL;
76
1da177e4
LT		 77
78 /* Make sure we can fit the range in the gatt table. */
79 /* FIXME: could wrap */
80 if (((unsigned long)pg_start + mem->page_count) > num_entries)
81 return -EINVAL;
82
83 j = pg_start;
84
85 /* gatt table should be empty. */
86 while (j < (pg_start + mem->page_count)) {
87 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
88 return -EBUSY;
89 j++;
90 }
91
92 if (mem->is_flushed == FALSE) {
93 global_cache_flush();
94 mem->is_flushed = TRUE;
95 }
96
97 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
98 tmp = agp_bridge->driver->mask_memory(agp_bridge,
a030ce44 99 mem->memory[i], mask_type);
1da177e4
LT		 100
101 BUG_ON(tmp & 0xffffff0000000ffcULL);
102 pte = (tmp & 0x000000ff00000000ULL) >> 28;
103 pte |=(tmp & 0x00000000fffff000ULL);
104 pte |= GPTE_VALID | GPTE_COHERENT;
105
106 writel(pte, agp_bridge->gatt_table+j);
107 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
108 }
109 amd64_tlbflush(mem);
110 return 0;
111}
112
113/*
114 * This hack alters the order element according
115 * to the size of a long. It sucks. I totally disown this, even
116 * though it does appear to work for the most part.
117 */
118static struct aper_size_info_32 amd64_aperture_sizes[7] =
119{
120 {32, 8192, 3+(sizeof(long)/8), 0 },
121 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
122 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
123 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
124 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
125 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
126 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
127};
128
129
130/*
131 * Get the current Aperture size from the x86-64.
132 * Note, that there may be multiple x86-64's, but we just return
133 * the value from the first one we find. The set_size functions
134 * keep the rest coherent anyway. Or at least should do.
135 */
136static int amd64_fetch_size(void)
137{
138 struct pci_dev *dev;
139 int i;
140 u32 temp;
141 struct aper_size_info_32 *values;
142
a32073bf 143 dev = k8_northbridges[0];
1da177e4
LT		 144 if (dev==NULL)
145 return 0;
146
147 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
148 temp = (temp & 0xe);
149 values = A_SIZE_32(amd64_aperture_sizes);
150
151 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
152 if (temp == values[i].size_value) {
153 agp_bridge->previous_size =
154 agp_bridge->current_size = (void *) (values + i);
155
156 agp_bridge->aperture_size_idx = i;
157 return values[i].size;
158 }
159 }
160 return 0;
161}
162
163/*
164 * In a multiprocessor x86-64 system, this function gets
165 * called once for each CPU.
166 */
167static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
168{
169 u64 aperturebase;
170 u32 tmp;
171 u64 addr, aper_base;
172
173 /* Address to map to */
174 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
175 aperturebase = tmp << 25;
176 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
177
178 /* address of the mappings table */
179 addr = (u64) gatt_table;
180 addr >>= 12;
181 tmp = (u32) addr<<4;
182 tmp &= ~0xf;
183 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
184
185 /* Enable GART translation for this hammer. */
186 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
187 tmp |= GARTEN;
188 tmp &= ~(DISGARTCPU | DISGARTIO);
189 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
190
1da177e4
LT		 191 return aper_base;
192}
193
194
e5524f35 195static const struct aper_size_info_32 amd_8151_sizes[7] =
1da177e4
LT		 196{
197 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
198 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
199 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
200 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
201 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
202 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
6a92a4e0 203 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
1da177e4
LT		 204};
205
206static int amd_8151_configure(void)
207{
07eee78e 208 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
a32073bf 209 int i;
1da177e4
LT		 210
211 /* Configure AGP regs in each x86-64 host bridge. */
a32073bf 212 for (i = 0; i < num_k8_northbridges; i++) {
1da177e4 213 agp_bridge->gart_bus_addr =
a32073bf 214 amd64_configure(k8_northbridges[i], gatt_bus);
1da177e4 215 }
a32073bf 216 k8_flush_garts();
1da177e4
LT		 217 return 0;
218}
219
220
221static void amd64_cleanup(void)
222{
223 u32 tmp;
a32073bf
AK		 224 int i;
225 for (i = 0; i < num_k8_northbridges; i++) {
226 struct pci_dev *dev = k8_northbridges[i];
1da177e4 227 /* disable gart translation */
a32073bf 228 pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp);
1da177e4 229 tmp &= ~AMD64_GARTEN;
a32073bf 230 pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp);
1da177e4
LT		 231 }
232}
233
234
e5524f35 235static const struct agp_bridge_driver amd_8151_driver = {
1da177e4
LT		 236 .owner = THIS_MODULE,
237 .aperture_sizes = amd_8151_sizes,
238 .size_type = U32_APER_SIZE,
239 .num_aperture_sizes = 7,
240 .configure = amd_8151_configure,
241 .fetch_size = amd64_fetch_size,
242 .cleanup = amd64_cleanup,
243 .tlb_flush = amd64_tlbflush,
244 .mask_memory = agp_generic_mask_memory,
245 .masks = NULL,
246 .agp_enable = agp_generic_enable,
247 .cache_flush = global_cache_flush,
248 .create_gatt_table = agp_generic_create_gatt_table,
249 .free_gatt_table = agp_generic_free_gatt_table,
250 .insert_memory = amd64_insert_memory,
251 .remove_memory = agp_generic_remove_memory,
252 .alloc_by_type = agp_generic_alloc_by_type,
253 .free_by_type = agp_generic_free_by_type,
254 .agp_alloc_page = agp_generic_alloc_page,
255 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 256 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 257};
258
259/* Some basic sanity checks for the aperture. */
260static int __devinit aperture_valid(u64 aper, u32 size)
261{
262 u32 pfn, c;
263 if (aper == 0) {
264 printk(KERN_ERR PFX "No aperture\n");
265 return 0;
266 }
267 if (size < 32*1024*1024) {
268 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
269 return 0;
270 }
271 if (aper + size > 0xffffffff) {
272 printk(KERN_ERR PFX "Aperture out of bounds\n");
273 return 0;
274 }
275 pfn = aper >> PAGE_SHIFT;
276 for (c = 0; c < size/PAGE_SIZE; c++) {
277 if (!pfn_valid(pfn + c))
278 break;
279 if (!PageReserved(pfn_to_page(pfn + c))) {
280 printk(KERN_ERR PFX "Aperture pointing to RAM\n");
281 return 0;
282 }
283 }
284
285 /* Request the Aperture. This catches cases when someone else
286 already put a mapping in there - happens with some very broken BIOS
287
288 Maybe better to use pci_assign_resource/pci_enable_device instead
289 trusting the bridges? */
290 if (!aperture_resource &&
291 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
292 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
293 return 0;
294 }
295 return 1;
296}
297
298/*
299 * W*s centric BIOS sometimes only set up the aperture in the AGP
300 * bridge, not the northbridge. On AMD64 this is handled early
a813ce43 301 * in aperture.c, but when IOMMU is not enabled or we run
1da177e4
LT		 302 * on a 32bit kernel this needs to be redone.
303 * Unfortunately it is impossible to fix the aperture here because it's too late
304 * to allocate that much memory. But at least error out cleanly instead of
305 * crashing.
306 */
307static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
308 u16 cap)
309{
310 u32 aper_low, aper_hi;
311 u64 aper, nb_aper;
312 int order = 0;
313 u32 nb_order, nb_base;
314 u16 apsize;
315
316 pci_read_config_dword(nb, 0x90, &nb_order);
317 nb_order = (nb_order >> 1) & 7;
318 pci_read_config_dword(nb, 0x94, &nb_base);
319 nb_aper = nb_base << 25;
320 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
321 return 0;
322 }
323
324 /* Northbridge seems to contain crap. Try the AGP bridge. */
325
326 pci_read_config_word(agp, cap+0x14, &apsize);
327 if (apsize == 0xffff)
328 return -1;
329
330 apsize &= 0xfff;
331 /* Some BIOS use weird encodings not in the AGPv3 table. */
332 if (apsize & 0xff)
333 apsize |= 0xf00;
334 order = 7 - hweight16(apsize);
335
336 pci_read_config_dword(agp, 0x10, &aper_low);
337 pci_read_config_dword(agp, 0x14, &aper_hi);
338 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
339 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
340 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
341 return -1;
342
343 pci_write_config_dword(nb, 0x90, order << 1);
344 pci_write_config_dword(nb, 0x94, aper >> 25);
345
346 return 0;
347}
348
349static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
350{
a32073bf
AK		 351 int i;
352
353 if (cache_k8_northbridges() < 0)
354 return -ENODEV;
355
356 i = 0;
357 for (i = 0; i < num_k8_northbridges; i++) {
358 struct pci_dev *dev = k8_northbridges[i];
359 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
1da177e4
LT		 360 printk(KERN_ERR PFX "No usable aperture found.\n");
361#ifdef __x86_64__
362 /* should port this to i386 */
363 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
364#endif
365 return -1;
366 }
1da177e4 367 }
a32073bf 368 return 0;
1da177e4
LT		 369}
370
371/* Handle AMD 8151 quirks */
372static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
373{
374 char *revstring;
375 u8 rev_id;
376
377 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
378 switch (rev_id) {
379 case 0x01: revstring="A0"; break;
380 case 0x02: revstring="A1"; break;
381 case 0x11: revstring="B0"; break;
382 case 0x12: revstring="B1"; break;
383 case 0x13: revstring="B2"; break;
384 case 0x14: revstring="B3"; break;
385 default: revstring="??"; break;
386 }
387
388 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);
389
390 /*
391 * Work around errata.
392 * Chips before B2 stepping incorrectly reporting v3.5
393 */
394 if (rev_id < 0x13) {
395 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
396 bridge->major_version = 3;
397 bridge->minor_version = 0;
398 }
399}
400
401
a42ab7f2 402static const struct aper_size_info_32 uli_sizes[7] =
1da177e4
LT		 403{
404 {256, 65536, 6, 10},
405 {128, 32768, 5, 9},
406 {64, 16384, 4, 8},
407 {32, 8192, 3, 7},
408 {16, 4096, 2, 6},
409 {8, 2048, 1, 4},
410 {4, 1024, 0, 3}
411};
412static int __devinit uli_agp_init(struct pci_dev *pdev)
413{
414 u32 httfea,baseaddr,enuscr;
415 struct pci_dev *dev1;
416 int i;
417 unsigned size = amd64_fetch_size();
29db35ed 418 printk(KERN_INFO "Setting up ULi AGP.\n");
7357db12 419 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
1da177e4
LT		 420 if (dev1 == NULL) {
421 printk(KERN_INFO PFX "Detected a ULi chipset, "
422 "but could not fine the secondary device.\n");
423 return -ENODEV;
424 }
425
426 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
427 if (uli_sizes[i].size == size)
428 break;
429
430 if (i == ARRAY_SIZE(uli_sizes)) {
431 printk(KERN_INFO PFX "No ULi size found for %d\n", size);
432 return -ENODEV;
433 }
434
435 /* shadow x86-64 registers into ULi registers */
a32073bf 436 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
1da177e4
LT		 437
438 /* if x86-64 aperture base is beyond 4G, exit here */
439 if ((httfea & 0x7fff) >> (32 - 25))
440 return -ENODEV;
441
442 httfea = (httfea& 0x7fff) << 25;
443
444 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
445 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
446 baseaddr|= httfea;
447 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
448
449 enuscr= httfea+ (size * 1024 * 1024) - 1;
450 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
451 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
7357db12
AC		 452
453 pci_dev_put(dev1);
1da177e4
LT		 454 return 0;
455}
456
457
a42ab7f2 458static const struct aper_size_info_32 nforce3_sizes[5] =
1da177e4
LT		 459{
460 {512, 131072, 7, 0x00000000 },
461 {256, 65536, 6, 0x00000008 },
462 {128, 32768, 5, 0x0000000C },
463 {64, 16384, 4, 0x0000000E },
464 {32, 8192, 3, 0x0000000F }
465};
466
467/* Handle shadow device of the Nvidia NForce3 */
468/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
da015a67 469static int nforce3_agp_init(struct pci_dev *pdev)
1da177e4
LT		 470{
471 u32 tmp, apbase, apbar, aplimit;
472 struct pci_dev *dev1;
473 int i;
474 unsigned size = amd64_fetch_size();
475
476 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");
477
7357db12 478 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
1da177e4
LT		 479 if (dev1 == NULL) {
480 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
481 "nForce3 chipset, but could not find "
482 "the secondary device.\n");
483 return -ENODEV;
484 }
485
486 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
487 if (nforce3_sizes[i].size == size)
488 break;
489
490 if (i == ARRAY_SIZE(nforce3_sizes)) {
491 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
492 return -ENODEV;
493 }
494
495 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
496 tmp &= ~(0xf);
497 tmp |= nforce3_sizes[i].size_value;
498 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
499
500 /* shadow x86-64 registers into NVIDIA registers */
a32073bf 501 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
1da177e4
LT		 502
503 /* if x86-64 aperture base is beyond 4G, exit here */
b41c82eb
DJ		 504 if ( (apbase & 0x7fff) >> (32 - 25) ) {
505 printk(KERN_INFO PFX "aperture base > 4G\n");
506 return -ENODEV;
507 }
1da177e4
LT		 508
509 apbase = (apbase & 0x7fff) << 25;
510
511 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
512 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
513 apbar |= apbase;
514 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
515
516 aplimit = apbase + (size * 1024 * 1024) - 1;
517 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
518 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
519 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
520 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
521
7357db12
AC		 522 pci_dev_put(dev1);
523
1da177e4
LT		 524 return 0;
525}
526
527static int __devinit agp_amd64_probe(struct pci_dev *pdev,
528 const struct pci_device_id *ent)
529{
530 struct agp_bridge_data *bridge;
531 u8 cap_ptr;
532
533 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
534 if (!cap_ptr)
535 return -ENODEV;
536
537 /* Could check for AGPv3 here */
538
539 bridge = agp_alloc_bridge();
540 if (!bridge)
541 return -ENOMEM;
542
543 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
544 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
545 amd8151_init(pdev, bridge);
546 } else {
547 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
548 }
549
550 bridge->driver = &amd_8151_driver;
551 bridge->dev = pdev;
552 bridge->capndx = cap_ptr;
553
554 /* Fill in the mode register */
555 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
556
557 if (cache_nbs(pdev, cap_ptr) == -1) {
558 agp_put_bridge(bridge);
559 return -ENODEV;
560 }
561
562 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
563 int ret = nforce3_agp_init(pdev);
564 if (ret) {
565 agp_put_bridge(bridge);
566 return ret;
567 }
568 }
569
570 if (pdev->vendor == PCI_VENDOR_ID_AL) {
571 int ret = uli_agp_init(pdev);
572 if (ret) {
573 agp_put_bridge(bridge);
574 return ret;
575 }
576 }
577
578 pci_set_drvdata(pdev, bridge);
579 return agp_add_bridge(bridge);
580}
581
582static void __devexit agp_amd64_remove(struct pci_dev *pdev)
583{
584 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
585
07eee78e 586 release_mem_region(virt_to_gart(bridge->gatt_table_real),
1da177e4
LT		 587 amd64_aperture_sizes[bridge->aperture_size_idx].size);
588 agp_remove_bridge(bridge);
589 agp_put_bridge(bridge);
590}
591
90be4b49
AM		 592#ifdef CONFIG_PM
593
594static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
595{
596 pci_save_state(pdev);
597 pci_set_power_state(pdev, pci_choose_state(pdev, state));
598
599 return 0;
600}
601
602static int agp_amd64_resume(struct pci_dev *pdev)
603{
604 pci_set_power_state(pdev, PCI_D0);
605 pci_restore_state(pdev);
606
ca2797ff
DJ		 607 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
608 nforce3_agp_init(pdev);
609
90be4b49
AM		 610 return amd_8151_configure();
611}
612
613#endif /* CONFIG_PM */
614
1da177e4
LT		 615static struct pci_device_id agp_amd64_pci_table[] = {
616 {
617 .class = (PCI_CLASS_BRIDGE_HOST << 8),
618 .class_mask = ~0,
619 .vendor = PCI_VENDOR_ID_AMD,
620 .device = PCI_DEVICE_ID_AMD_8151_0,
621 .subvendor = PCI_ANY_ID,
622 .subdevice = PCI_ANY_ID,
623 },
624 /* ULi M1689 */
625 {
626 .class = (PCI_CLASS_BRIDGE_HOST << 8),
627 .class_mask = ~0,
628 .vendor = PCI_VENDOR_ID_AL,
629 .device = PCI_DEVICE_ID_AL_M1689,
630 .subvendor = PCI_ANY_ID,
631 .subdevice = PCI_ANY_ID,
632 },
633 /* VIA K8T800Pro */
634 {
635 .class = (PCI_CLASS_BRIDGE_HOST << 8),
636 .class_mask = ~0,
637 .vendor = PCI_VENDOR_ID_VIA,
638 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
639 .subvendor = PCI_ANY_ID,
640 .subdevice = PCI_ANY_ID,
641 },
642 /* VIA K8T800 */
643 {
644 .class = (PCI_CLASS_BRIDGE_HOST << 8),
645 .class_mask = ~0,
646 .vendor = PCI_VENDOR_ID_VIA,
647 .device = PCI_DEVICE_ID_VIA_8385_0,
648 .subvendor = PCI_ANY_ID,
649 .subdevice = PCI_ANY_ID,
650 },
651 /* VIA K8M800 / K8N800 */
652 {
653 .class = (PCI_CLASS_BRIDGE_HOST << 8),
654 .class_mask = ~0,
655 .vendor = PCI_VENDOR_ID_VIA,
656 .device = PCI_DEVICE_ID_VIA_8380_0,
657 .subvendor = PCI_ANY_ID,
658 .subdevice = PCI_ANY_ID,
659 },
d5cb8d38
GM		 660 /* VIA K8M890 / K8N890 */
661 {
662 .class = (PCI_CLASS_BRIDGE_HOST << 8),
663 .class_mask = ~0,
664 .vendor = PCI_VENDOR_ID_VIA,
43ed41f6 665 .device = PCI_DEVICE_ID_VIA_VT3336,
d5cb8d38
GM		 666 .subvendor = PCI_ANY_ID,
667 .subdevice = PCI_ANY_ID,
668 },
1da177e4
LT		 669 /* VIA K8T890 */
670 {
671 .class = (PCI_CLASS_BRIDGE_HOST << 8),
672 .class_mask = ~0,
673 .vendor = PCI_VENDOR_ID_VIA,
674 .device = PCI_DEVICE_ID_VIA_3238_0,
675 .subvendor = PCI_ANY_ID,
676 .subdevice = PCI_ANY_ID,
677 },
678 /* VIA K8T800/K8M800/K8N800 */
679 {
680 .class = (PCI_CLASS_BRIDGE_HOST << 8),
681 .class_mask = ~0,
682 .vendor = PCI_VENDOR_ID_VIA,
683 .device = PCI_DEVICE_ID_VIA_838X_1,
684 .subvendor = PCI_ANY_ID,
685 .subdevice = PCI_ANY_ID,
686 },
687 /* NForce3 */
688 {
689 .class = (PCI_CLASS_BRIDGE_HOST << 8),
690 .class_mask = ~0,
691 .vendor = PCI_VENDOR_ID_NVIDIA,
692 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
693 .subvendor = PCI_ANY_ID,
694 .subdevice = PCI_ANY_ID,
695 },
696 {
697 .class = (PCI_CLASS_BRIDGE_HOST << 8),
698 .class_mask = ~0,
699 .vendor = PCI_VENDOR_ID_NVIDIA,
700 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
701 .subvendor = PCI_ANY_ID,
702 .subdevice = PCI_ANY_ID,
703 },
704 /* SIS 755 */
705 {
706 .class = (PCI_CLASS_BRIDGE_HOST << 8),
707 .class_mask = ~0,
708 .vendor = PCI_VENDOR_ID_SI,
709 .device = PCI_DEVICE_ID_SI_755,
710 .subvendor = PCI_ANY_ID,
711 .subdevice = PCI_ANY_ID,
712 },
2fa938b8
DJ		 713 /* SIS 760 */
714 {
715 .class = (PCI_CLASS_BRIDGE_HOST << 8),
716 .class_mask = ~0,
717 .vendor = PCI_VENDOR_ID_SI,
718 .device = PCI_DEVICE_ID_SI_760,
719 .subvendor = PCI_ANY_ID,
720 .subdevice = PCI_ANY_ID,
721 },
870b7681
AK		 722 /* ALI/ULI M1695 */
723 {
724 .class = (PCI_CLASS_BRIDGE_HOST << 8),
725 .class_mask = ~0,
726 .vendor = PCI_VENDOR_ID_AL,
5c48b0e3 727 .device = 0x1695,
870b7681
AK		 728 .subvendor = PCI_ANY_ID,
729 .subdevice = PCI_ANY_ID,
730 },
731
1da177e4
LT		 732 { }
733};
734
735MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
736
737static struct pci_driver agp_amd64_pci_driver = {
738 .name = "agpgart-amd64",
739 .id_table = agp_amd64_pci_table,
740 .probe = agp_amd64_probe,
741 .remove = agp_amd64_remove,
90be4b49
AM		 742#ifdef CONFIG_PM
743 .suspend = agp_amd64_suspend,
744 .resume = agp_amd64_resume,
745#endif
1da177e4
LT		 746};
747
748
749/* Not static due to IOMMU code calling it early. */
750int __init agp_amd64_init(void)
751{
752 int err = 0;
1da177e4
LT		 753
754 if (agp_off)
755 return -EINVAL;
4092e256 756 if (pci_register_driver(&agp_amd64_pci_driver) < 0) {
1da177e4
LT		 757 struct pci_dev *dev;
758 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
759 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
760#ifdef MODULE
761 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
762#else
763 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
764#endif
765 return -ENODEV;
766 }
767
768 /* First check that we have at least one AMD64 NB */
a32073bf 769 if (!pci_dev_present(k8_nb_ids))
1da177e4
LT		 770 return -ENODEV;
771
772 /* Look for any AGP bridge */
773 dev = NULL;
774 err = -ENODEV;
775 for_each_pci_dev(dev) {
776 if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
777 continue;
778 /* Only one bridge supported right now */
779 if (agp_amd64_probe(dev, NULL) == 0) {
780 err = 0;
781 break;
782 }
783 }
784 }
785 return err;
786}
787
788static void __exit agp_amd64_cleanup(void)
789{
790 if (aperture_resource)
791 release_resource(aperture_resource);
792 pci_unregister_driver(&agp_amd64_pci_driver);
793}
794
795/* On AMD64 the PCI driver needs to initialize this driver early
796 for the IOMMU, so it has to be called via a backdoor. */
a813ce43 797#ifndef CONFIG_IOMMU
1da177e4
LT		 798module_init(agp_amd64_init);
799module_exit(agp_amd64_cleanup);
800#endif
801
802MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
803module_param(agp_try_unsupported, bool, 0);
804MODULE_LICENSE("GPL");
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