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[PATCH] x86_64: Make sure is_compat_task works early
[net-next-2.6.git] / drivers / char / agp / amd64-agp.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
11#include <linux/config.h>
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/init.h>
15#include <linux/agp_backend.h>
8c65b4a6 16#include <linux/mmzone.h>
4e57b681 17#include <asm/page.h> /* PAGE_SIZE */
a32073bf 18#include <asm/k8.h>
1da177e4
LT		 19#include "agp.h"
20
1da177e4
LT		 21/* PTE bits. */
22#define GPTE_VALID 1
23#define GPTE_COHERENT 2
24
25/* Aperture control register bits. */
26#define GARTEN (1<<0)
27#define DISGARTCPU (1<<4)
28#define DISGARTIO (1<<5)
29
30/* GART cache control register bits. */
31#define INVGART (1<<0)
32#define GARTPTEERR (1<<1)
33
34/* K8 On-cpu GART registers */
35#define AMD64_GARTAPERTURECTL 0x90
36#define AMD64_GARTAPERTUREBASE 0x94
37#define AMD64_GARTTABLEBASE 0x98
38#define AMD64_GARTCACHECTL 0x9c
39#define AMD64_GARTEN (1<<0)
40
41/* NVIDIA K8 registers */
42#define NVIDIA_X86_64_0_APBASE 0x10
43#define NVIDIA_X86_64_1_APBASE1 0x50
44#define NVIDIA_X86_64_1_APLIMIT1 0x54
45#define NVIDIA_X86_64_1_APSIZE 0xa8
46#define NVIDIA_X86_64_1_APBASE2 0xd8
47#define NVIDIA_X86_64_1_APLIMIT2 0xdc
48
49/* ULi K8 registers */
50#define ULI_X86_64_BASE_ADDR 0x10
51#define ULI_X86_64_HTT_FEA_REG 0x50
52#define ULI_X86_64_ENU_SCR_REG 0x54
53
1da177e4 54static struct resource *aperture_resource;
172efbb4 55static int __initdata agp_try_unsupported = 1;
1da177e4 56
1da177e4
LT		 57static void amd64_tlbflush(struct agp_memory *temp)
58{
a32073bf 59 k8_flush_garts();
1da177e4
LT		 60}
61
62static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
63{
64 int i, j, num_entries;
65 long long tmp;
66 u32 pte;
67
68 num_entries = agp_num_entries();
69
70 if (type != 0 || mem->type != 0)
71 return -EINVAL;
72
73 /* Make sure we can fit the range in the gatt table. */
74 /* FIXME: could wrap */
75 if (((unsigned long)pg_start + mem->page_count) > num_entries)
76 return -EINVAL;
77
78 j = pg_start;
79
80 /* gatt table should be empty. */
81 while (j < (pg_start + mem->page_count)) {
82 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
83 return -EBUSY;
84 j++;
85 }
86
87 if (mem->is_flushed == FALSE) {
88 global_cache_flush();
89 mem->is_flushed = TRUE;
90 }
91
92 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
93 tmp = agp_bridge->driver->mask_memory(agp_bridge,
94 mem->memory[i], mem->type);
95
96 BUG_ON(tmp & 0xffffff0000000ffcULL);
97 pte = (tmp & 0x000000ff00000000ULL) >> 28;
98 pte |=(tmp & 0x00000000fffff000ULL);
99 pte |= GPTE_VALID | GPTE_COHERENT;
100
101 writel(pte, agp_bridge->gatt_table+j);
102 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
103 }
104 amd64_tlbflush(mem);
105 return 0;
106}
107
108/*
109 * This hack alters the order element according
110 * to the size of a long. It sucks. I totally disown this, even
111 * though it does appear to work for the most part.
112 */
113static struct aper_size_info_32 amd64_aperture_sizes[7] =
114{
115 {32, 8192, 3+(sizeof(long)/8), 0 },
116 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
117 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
118 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
119 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
120 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
121 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
122};
123
124
125/*
126 * Get the current Aperture size from the x86-64.
127 * Note, that there may be multiple x86-64's, but we just return
128 * the value from the first one we find. The set_size functions
129 * keep the rest coherent anyway. Or at least should do.
130 */
131static int amd64_fetch_size(void)
132{
133 struct pci_dev *dev;
134 int i;
135 u32 temp;
136 struct aper_size_info_32 *values;
137
a32073bf 138 dev = k8_northbridges[0];
1da177e4
LT		 139 if (dev==NULL)
140 return 0;
141
142 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
143 temp = (temp & 0xe);
144 values = A_SIZE_32(amd64_aperture_sizes);
145
146 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
147 if (temp == values[i].size_value) {
148 agp_bridge->previous_size =
149 agp_bridge->current_size = (void *) (values + i);
150
151 agp_bridge->aperture_size_idx = i;
152 return values[i].size;
153 }
154 }
155 return 0;
156}
157
158/*
159 * In a multiprocessor x86-64 system, this function gets
160 * called once for each CPU.
161 */
162static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
163{
164 u64 aperturebase;
165 u32 tmp;
166 u64 addr, aper_base;
167
168 /* Address to map to */
169 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
170 aperturebase = tmp << 25;
171 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
172
173 /* address of the mappings table */
174 addr = (u64) gatt_table;
175 addr >>= 12;
176 tmp = (u32) addr<<4;
177 tmp &= ~0xf;
178 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
179
180 /* Enable GART translation for this hammer. */
181 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
182 tmp |= GARTEN;
183 tmp &= ~(DISGARTCPU | DISGARTIO);
184 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
185
1da177e4
LT		 186 return aper_base;
187}
188
189
190static struct aper_size_info_32 amd_8151_sizes[7] =
191{
192 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
193 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
194 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
195 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
196 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
197 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
6a92a4e0 198 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
1da177e4
LT		 199};
200
201static int amd_8151_configure(void)
202{
07eee78e 203 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
a32073bf 204 int i;
1da177e4
LT		 205
206 /* Configure AGP regs in each x86-64 host bridge. */
a32073bf 207 for (i = 0; i < num_k8_northbridges; i++) {
1da177e4 208 agp_bridge->gart_bus_addr =
a32073bf 209 amd64_configure(k8_northbridges[i], gatt_bus);
1da177e4 210 }
a32073bf 211 k8_flush_garts();
1da177e4
LT		 212 return 0;
213}
214
215
216static void amd64_cleanup(void)
217{
218 u32 tmp;
a32073bf
AK		 219 int i;
220 for (i = 0; i < num_k8_northbridges; i++) {
221 struct pci_dev *dev = k8_northbridges[i];
1da177e4 222 /* disable gart translation */
a32073bf 223 pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp);
1da177e4 224 tmp &= ~AMD64_GARTEN;
a32073bf 225 pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp);
1da177e4
LT		 226 }
227}
228
229
408b664a 230static struct agp_bridge_driver amd_8151_driver = {
1da177e4
LT		 231 .owner = THIS_MODULE,
232 .aperture_sizes = amd_8151_sizes,
233 .size_type = U32_APER_SIZE,
234 .num_aperture_sizes = 7,
235 .configure = amd_8151_configure,
236 .fetch_size = amd64_fetch_size,
237 .cleanup = amd64_cleanup,
238 .tlb_flush = amd64_tlbflush,
239 .mask_memory = agp_generic_mask_memory,
240 .masks = NULL,
241 .agp_enable = agp_generic_enable,
242 .cache_flush = global_cache_flush,
243 .create_gatt_table = agp_generic_create_gatt_table,
244 .free_gatt_table = agp_generic_free_gatt_table,
245 .insert_memory = amd64_insert_memory,
246 .remove_memory = agp_generic_remove_memory,
247 .alloc_by_type = agp_generic_alloc_by_type,
248 .free_by_type = agp_generic_free_by_type,
249 .agp_alloc_page = agp_generic_alloc_page,
250 .agp_destroy_page = agp_generic_destroy_page,
251};
252
253/* Some basic sanity checks for the aperture. */
254static int __devinit aperture_valid(u64 aper, u32 size)
255{
256 u32 pfn, c;
257 if (aper == 0) {
258 printk(KERN_ERR PFX "No aperture\n");
259 return 0;
260 }
261 if (size < 32*1024*1024) {
262 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
263 return 0;
264 }
265 if (aper + size > 0xffffffff) {
266 printk(KERN_ERR PFX "Aperture out of bounds\n");
267 return 0;
268 }
269 pfn = aper >> PAGE_SHIFT;
270 for (c = 0; c < size/PAGE_SIZE; c++) {
271 if (!pfn_valid(pfn + c))
272 break;
273 if (!PageReserved(pfn_to_page(pfn + c))) {
274 printk(KERN_ERR PFX "Aperture pointing to RAM\n");
275 return 0;
276 }
277 }
278
279 /* Request the Aperture. This catches cases when someone else
280 already put a mapping in there - happens with some very broken BIOS
281
282 Maybe better to use pci_assign_resource/pci_enable_device instead
283 trusting the bridges? */
284 if (!aperture_resource &&
285 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
286 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
287 return 0;
288 }
289 return 1;
290}
291
292/*
293 * W*s centric BIOS sometimes only set up the aperture in the AGP
294 * bridge, not the northbridge. On AMD64 this is handled early
295 * in aperture.c, but when GART_IOMMU is not enabled or we run
296 * on a 32bit kernel this needs to be redone.
297 * Unfortunately it is impossible to fix the aperture here because it's too late
298 * to allocate that much memory. But at least error out cleanly instead of
299 * crashing.
300 */
301static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
302 u16 cap)
303{
304 u32 aper_low, aper_hi;
305 u64 aper, nb_aper;
306 int order = 0;
307 u32 nb_order, nb_base;
308 u16 apsize;
309
310 pci_read_config_dword(nb, 0x90, &nb_order);
311 nb_order = (nb_order >> 1) & 7;
312 pci_read_config_dword(nb, 0x94, &nb_base);
313 nb_aper = nb_base << 25;
314 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
315 return 0;
316 }
317
318 /* Northbridge seems to contain crap. Try the AGP bridge. */
319
320 pci_read_config_word(agp, cap+0x14, &apsize);
321 if (apsize == 0xffff)
322 return -1;
323
324 apsize &= 0xfff;
325 /* Some BIOS use weird encodings not in the AGPv3 table. */
326 if (apsize & 0xff)
327 apsize |= 0xf00;
328 order = 7 - hweight16(apsize);
329
330 pci_read_config_dword(agp, 0x10, &aper_low);
331 pci_read_config_dword(agp, 0x14, &aper_hi);
332 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
333 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
334 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
335 return -1;
336
337 pci_write_config_dword(nb, 0x90, order << 1);
338 pci_write_config_dword(nb, 0x94, aper >> 25);
339
340 return 0;
341}
342
343static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
344{
a32073bf
AK		 345 int i;
346
347 if (cache_k8_northbridges() < 0)
348 return -ENODEV;
349
350 i = 0;
351 for (i = 0; i < num_k8_northbridges; i++) {
352 struct pci_dev *dev = k8_northbridges[i];
353 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
1da177e4
LT		 354 printk(KERN_ERR PFX "No usable aperture found.\n");
355#ifdef __x86_64__
356 /* should port this to i386 */
357 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
358#endif
359 return -1;
360 }
1da177e4 361 }
a32073bf 362 return 0;
1da177e4
LT		 363}
364
365/* Handle AMD 8151 quirks */
366static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
367{
368 char *revstring;
369 u8 rev_id;
370
371 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
372 switch (rev_id) {
373 case 0x01: revstring="A0"; break;
374 case 0x02: revstring="A1"; break;
375 case 0x11: revstring="B0"; break;
376 case 0x12: revstring="B1"; break;
377 case 0x13: revstring="B2"; break;
378 case 0x14: revstring="B3"; break;
379 default: revstring="??"; break;
380 }
381
382 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);
383
384 /*
385 * Work around errata.
386 * Chips before B2 stepping incorrectly reporting v3.5
387 */
388 if (rev_id < 0x13) {
389 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
390 bridge->major_version = 3;
391 bridge->minor_version = 0;
392 }
393}
394
395
a42ab7f2 396static const struct aper_size_info_32 uli_sizes[7] =
1da177e4
LT		 397{
398 {256, 65536, 6, 10},
399 {128, 32768, 5, 9},
400 {64, 16384, 4, 8},
401 {32, 8192, 3, 7},
402 {16, 4096, 2, 6},
403 {8, 2048, 1, 4},
404 {4, 1024, 0, 3}
405};
406static int __devinit uli_agp_init(struct pci_dev *pdev)
407{
408 u32 httfea,baseaddr,enuscr;
409 struct pci_dev *dev1;
410 int i;
411 unsigned size = amd64_fetch_size();
29db35ed 412 printk(KERN_INFO "Setting up ULi AGP.\n");
1da177e4
LT		 413 dev1 = pci_find_slot ((unsigned int)pdev->bus->number,PCI_DEVFN(0,0));
414 if (dev1 == NULL) {
415 printk(KERN_INFO PFX "Detected a ULi chipset, "
416 "but could not fine the secondary device.\n");
417 return -ENODEV;
418 }
419
420 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
421 if (uli_sizes[i].size == size)
422 break;
423
424 if (i == ARRAY_SIZE(uli_sizes)) {
425 printk(KERN_INFO PFX "No ULi size found for %d\n", size);
426 return -ENODEV;
427 }
428
429 /* shadow x86-64 registers into ULi registers */
a32073bf 430 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
1da177e4
LT		 431
432 /* if x86-64 aperture base is beyond 4G, exit here */
433 if ((httfea & 0x7fff) >> (32 - 25))
434 return -ENODEV;
435
436 httfea = (httfea& 0x7fff) << 25;
437
438 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
439 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
440 baseaddr|= httfea;
441 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
442
443 enuscr= httfea+ (size * 1024 * 1024) - 1;
444 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
445 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
446 return 0;
447}
448
449
a42ab7f2 450static const struct aper_size_info_32 nforce3_sizes[5] =
1da177e4
LT		 451{
452 {512, 131072, 7, 0x00000000 },
453 {256, 65536, 6, 0x00000008 },
454 {128, 32768, 5, 0x0000000C },
455 {64, 16384, 4, 0x0000000E },
456 {32, 8192, 3, 0x0000000F }
457};
458
459/* Handle shadow device of the Nvidia NForce3 */
460/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
461static int __devinit nforce3_agp_init(struct pci_dev *pdev)
462{
463 u32 tmp, apbase, apbar, aplimit;
464 struct pci_dev *dev1;
465 int i;
466 unsigned size = amd64_fetch_size();
467
468 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");
469
470 dev1 = pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(11, 0));
471 if (dev1 == NULL) {
472 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
473 "nForce3 chipset, but could not find "
474 "the secondary device.\n");
475 return -ENODEV;
476 }
477
478 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
479 if (nforce3_sizes[i].size == size)
480 break;
481
482 if (i == ARRAY_SIZE(nforce3_sizes)) {
483 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
484 return -ENODEV;
485 }
486
487 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
488 tmp &= ~(0xf);
489 tmp |= nforce3_sizes[i].size_value;
490 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
491
492 /* shadow x86-64 registers into NVIDIA registers */
a32073bf 493 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
1da177e4
LT		 494
495 /* if x86-64 aperture base is beyond 4G, exit here */
b41c82eb
DJ		 496 if ( (apbase & 0x7fff) >> (32 - 25) ) {
497 printk(KERN_INFO PFX "aperture base > 4G\n");
498 return -ENODEV;
499 }
1da177e4
LT		 500
501 apbase = (apbase & 0x7fff) << 25;
502
503 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
504 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
505 apbar |= apbase;
506 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
507
508 aplimit = apbase + (size * 1024 * 1024) - 1;
509 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
510 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
511 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
512 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
513
514 return 0;
515}
516
517static int __devinit agp_amd64_probe(struct pci_dev *pdev,
518 const struct pci_device_id *ent)
519{
520 struct agp_bridge_data *bridge;
521 u8 cap_ptr;
522
523 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
524 if (!cap_ptr)
525 return -ENODEV;
526
527 /* Could check for AGPv3 here */
528
529 bridge = agp_alloc_bridge();
530 if (!bridge)
531 return -ENOMEM;
532
533 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
534 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
535 amd8151_init(pdev, bridge);
536 } else {
537 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
538 }
539
540 bridge->driver = &amd_8151_driver;
541 bridge->dev = pdev;
542 bridge->capndx = cap_ptr;
543
544 /* Fill in the mode register */
545 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
546
547 if (cache_nbs(pdev, cap_ptr) == -1) {
548 agp_put_bridge(bridge);
549 return -ENODEV;
550 }
551
552 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
553 int ret = nforce3_agp_init(pdev);
554 if (ret) {
555 agp_put_bridge(bridge);
556 return ret;
557 }
558 }
559
560 if (pdev->vendor == PCI_VENDOR_ID_AL) {
561 int ret = uli_agp_init(pdev);
562 if (ret) {
563 agp_put_bridge(bridge);
564 return ret;
565 }
566 }
567
568 pci_set_drvdata(pdev, bridge);
569 return agp_add_bridge(bridge);
570}
571
572static void __devexit agp_amd64_remove(struct pci_dev *pdev)
573{
574 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
575
07eee78e 576 release_mem_region(virt_to_gart(bridge->gatt_table_real),
1da177e4
LT		 577 amd64_aperture_sizes[bridge->aperture_size_idx].size);
578 agp_remove_bridge(bridge);
579 agp_put_bridge(bridge);
580}
581
90be4b49
AM		 582#ifdef CONFIG_PM
583
584static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
585{
586 pci_save_state(pdev);
587 pci_set_power_state(pdev, pci_choose_state(pdev, state));
588
589 return 0;
590}
591
592static int agp_amd64_resume(struct pci_dev *pdev)
593{
594 pci_set_power_state(pdev, PCI_D0);
595 pci_restore_state(pdev);
596
ca2797ff
DJ		 597 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
598 nforce3_agp_init(pdev);
599
90be4b49
AM		 600 return amd_8151_configure();
601}
602
603#endif /* CONFIG_PM */
604
1da177e4
LT		 605static struct pci_device_id agp_amd64_pci_table[] = {
606 {
607 .class = (PCI_CLASS_BRIDGE_HOST << 8),
608 .class_mask = ~0,
609 .vendor = PCI_VENDOR_ID_AMD,
610 .device = PCI_DEVICE_ID_AMD_8151_0,
611 .subvendor = PCI_ANY_ID,
612 .subdevice = PCI_ANY_ID,
613 },
614 /* ULi M1689 */
615 {
616 .class = (PCI_CLASS_BRIDGE_HOST << 8),
617 .class_mask = ~0,
618 .vendor = PCI_VENDOR_ID_AL,
619 .device = PCI_DEVICE_ID_AL_M1689,
620 .subvendor = PCI_ANY_ID,
621 .subdevice = PCI_ANY_ID,
622 },
623 /* VIA K8T800Pro */
624 {
625 .class = (PCI_CLASS_BRIDGE_HOST << 8),
626 .class_mask = ~0,
627 .vendor = PCI_VENDOR_ID_VIA,
628 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
629 .subvendor = PCI_ANY_ID,
630 .subdevice = PCI_ANY_ID,
631 },
632 /* VIA K8T800 */
633 {
634 .class = (PCI_CLASS_BRIDGE_HOST << 8),
635 .class_mask = ~0,
636 .vendor = PCI_VENDOR_ID_VIA,
637 .device = PCI_DEVICE_ID_VIA_8385_0,
638 .subvendor = PCI_ANY_ID,
639 .subdevice = PCI_ANY_ID,
640 },
641 /* VIA K8M800 / K8N800 */
642 {
643 .class = (PCI_CLASS_BRIDGE_HOST << 8),
644 .class_mask = ~0,
645 .vendor = PCI_VENDOR_ID_VIA,
646 .device = PCI_DEVICE_ID_VIA_8380_0,
647 .subvendor = PCI_ANY_ID,
648 .subdevice = PCI_ANY_ID,
649 },
650 /* VIA K8T890 */
651 {
652 .class = (PCI_CLASS_BRIDGE_HOST << 8),
653 .class_mask = ~0,
654 .vendor = PCI_VENDOR_ID_VIA,
655 .device = PCI_DEVICE_ID_VIA_3238_0,
656 .subvendor = PCI_ANY_ID,
657 .subdevice = PCI_ANY_ID,
658 },
659 /* VIA K8T800/K8M800/K8N800 */
660 {
661 .class = (PCI_CLASS_BRIDGE_HOST << 8),
662 .class_mask = ~0,
663 .vendor = PCI_VENDOR_ID_VIA,
664 .device = PCI_DEVICE_ID_VIA_838X_1,
665 .subvendor = PCI_ANY_ID,
666 .subdevice = PCI_ANY_ID,
667 },
668 /* NForce3 */
669 {
670 .class = (PCI_CLASS_BRIDGE_HOST << 8),
671 .class_mask = ~0,
672 .vendor = PCI_VENDOR_ID_NVIDIA,
673 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
674 .subvendor = PCI_ANY_ID,
675 .subdevice = PCI_ANY_ID,
676 },
677 {
678 .class = (PCI_CLASS_BRIDGE_HOST << 8),
679 .class_mask = ~0,
680 .vendor = PCI_VENDOR_ID_NVIDIA,
681 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
682 .subvendor = PCI_ANY_ID,
683 .subdevice = PCI_ANY_ID,
684 },
685 /* SIS 755 */
686 {
687 .class = (PCI_CLASS_BRIDGE_HOST << 8),
688 .class_mask = ~0,
689 .vendor = PCI_VENDOR_ID_SI,
690 .device = PCI_DEVICE_ID_SI_755,
691 .subvendor = PCI_ANY_ID,
692 .subdevice = PCI_ANY_ID,
693 },
2fa938b8
DJ		 694 /* SIS 760 */
695 {
696 .class = (PCI_CLASS_BRIDGE_HOST << 8),
697 .class_mask = ~0,
698 .vendor = PCI_VENDOR_ID_SI,
699 .device = PCI_DEVICE_ID_SI_760,
700 .subvendor = PCI_ANY_ID,
701 .subdevice = PCI_ANY_ID,
702 },
870b7681
AK		 703 /* ALI/ULI M1695 */
704 {
705 .class = (PCI_CLASS_BRIDGE_HOST << 8),
706 .class_mask = ~0,
707 .vendor = PCI_VENDOR_ID_AL,
5c48b0e3 708 .device = 0x1695,
870b7681
AK		 709 .subvendor = PCI_ANY_ID,
710 .subdevice = PCI_ANY_ID,
711 },
712
1da177e4
LT		 713 { }
714};
715
716MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
717
718static struct pci_driver agp_amd64_pci_driver = {
719 .name = "agpgart-amd64",
720 .id_table = agp_amd64_pci_table,
721 .probe = agp_amd64_probe,
722 .remove = agp_amd64_remove,
90be4b49
AM		 723#ifdef CONFIG_PM
724 .suspend = agp_amd64_suspend,
725 .resume = agp_amd64_resume,
726#endif
1da177e4
LT		 727};
728
729
730/* Not static due to IOMMU code calling it early. */
731int __init agp_amd64_init(void)
732{
733 int err = 0;
1da177e4
LT		 734
735 if (agp_off)
736 return -EINVAL;
737 if (pci_register_driver(&agp_amd64_pci_driver) > 0) {
738 struct pci_dev *dev;
739 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
740 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
741#ifdef MODULE
742 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
743#else
744 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
745#endif
746 return -ENODEV;
747 }
748
749 /* First check that we have at least one AMD64 NB */
a32073bf 750 if (!pci_dev_present(k8_nb_ids))
1da177e4
LT		 751 return -ENODEV;
752
753 /* Look for any AGP bridge */
754 dev = NULL;
755 err = -ENODEV;
756 for_each_pci_dev(dev) {
757 if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
758 continue;
759 /* Only one bridge supported right now */
760 if (agp_amd64_probe(dev, NULL) == 0) {
761 err = 0;
762 break;
763 }
764 }
765 }
766 return err;
767}
768
769static void __exit agp_amd64_cleanup(void)
770{
771 if (aperture_resource)
772 release_resource(aperture_resource);
773 pci_unregister_driver(&agp_amd64_pci_driver);
774}
775
776/* On AMD64 the PCI driver needs to initialize this driver early
777 for the IOMMU, so it has to be called via a backdoor. */
778#ifndef CONFIG_GART_IOMMU
779module_init(agp_amd64_init);
780module_exit(agp_amd64_cleanup);
781#endif
782
783MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
784module_param(agp_try_unsupported, bool, 0);
785MODULE_LICENSE("GPL");
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