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block: remove wrappers for request type/flags
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1/*
2 * Xilinx SystemACE device driver
3 *
4 * Copyright 2007 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11/*
12 * The SystemACE chip is designed to configure FPGAs by loading an FPGA
13 * bitstream from a file on a CF card and squirting it into FPGAs connected
14 * to the SystemACE JTAG chain. It also has the advantage of providing an
15 * MPU interface which can be used to control the FPGA configuration process
16 * and to use the attached CF card for general purpose storage.
17 *
18 * This driver is a block device driver for the SystemACE.
19 *
20 * Initialization:
21 * The driver registers itself as a platform_device driver at module
22 * load time. The platform bus will take care of calling the
23 * ace_probe() method for all SystemACE instances in the system. Any
24 * number of SystemACE instances are supported. ace_probe() calls
25 * ace_setup() which initialized all data structures, reads the CF
26 * id structure and registers the device.
27 *
28 * Processing:
29 * Just about all of the heavy lifting in this driver is performed by
30 * a Finite State Machine (FSM). The driver needs to wait on a number
31 * of events; some raised by interrupts, some which need to be polled
32 * for. Describing all of the behaviour in a FSM seems to be the
33 * easiest way to keep the complexity low and make it easy to
34 * understand what the driver is doing. If the block ops or the
35 * request function need to interact with the hardware, then they
36 * simply need to flag the request and kick of FSM processing.
37 *
38 * The FSM itself is atomic-safe code which can be run from any
39 * context. The general process flow is:
40 * 1. obtain the ace->lock spinlock.
41 * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is
42 * cleared.
43 * 3. release the lock.
44 *
45 * Individual states do not sleep in any way. If a condition needs to
46 * be waited for then the state much clear the fsm_continue flag and
47 * either schedule the FSM to be run again at a later time, or expect
48 * an interrupt to call the FSM when the desired condition is met.
49 *
50 * In normal operation, the FSM is processed at interrupt context
51 * either when the driver's tasklet is scheduled, or when an irq is
52 * raised by the hardware. The tasklet can be scheduled at any time.
53 * The request method in particular schedules the tasklet when a new
54 * request has been indicated by the block layer. Once started, the
55 * FSM proceeds as far as it can processing the request until it
56 * needs on a hardware event. At this point, it must yield execution.
57 *
58 * A state has two options when yielding execution:
59 * 1. ace_fsm_yield()
60 * - Call if need to poll for event.
61 * - clears the fsm_continue flag to exit the processing loop
62 * - reschedules the tasklet to run again as soon as possible
63 * 2. ace_fsm_yieldirq()
64 * - Call if an irq is expected from the HW
65 * - clears the fsm_continue flag to exit the processing loop
66 * - does not reschedule the tasklet so the FSM will not be processed
67 * again until an irq is received.
68 * After calling a yield function, the state must return control back
69 * to the FSM main loop.
70 *
71 * Additionally, the driver maintains a kernel timer which can process
72 * the FSM. If the FSM gets stalled, typically due to a missed
73 * interrupt, then the kernel timer will expire and the driver can
74 * continue where it left off.
75 *
76 * To Do:
77 * - Add FPGA configuration control interface.
78 * - Request major number from lanana
79 */
80
81#undef DEBUG
82
83#include <linux/module.h>
84#include <linux/ctype.h>
85#include <linux/init.h>
86#include <linux/interrupt.h>
87#include <linux/errno.h>
88#include <linux/kernel.h>
89#include <linux/delay.h>
90#include <linux/slab.h>
91#include <linux/blkdev.h>
4aaf2fec 92#include <linux/ata.h>
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93#include <linux/hdreg.h>
94#include <linux/platform_device.h>
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95#if defined(CONFIG_OF)
96#include <linux/of_device.h>
97#include <linux/of_platform.h>
98#endif
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99
100MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
101MODULE_DESCRIPTION("Xilinx SystemACE device driver");
102MODULE_LICENSE("GPL");
103
104/* SystemACE register definitions */
105#define ACE_BUSMODE (0x00)
106
107#define ACE_STATUS (0x04)
108#define ACE_STATUS_CFGLOCK (0x00000001)
109#define ACE_STATUS_MPULOCK (0x00000002)
110#define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */
111#define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */
112#define ACE_STATUS_CFDETECT (0x00000010)
113#define ACE_STATUS_DATABUFRDY (0x00000020)
114#define ACE_STATUS_DATABUFMODE (0x00000040)
115#define ACE_STATUS_CFGDONE (0x00000080)
116#define ACE_STATUS_RDYFORCFCMD (0x00000100)
117#define ACE_STATUS_CFGMODEPIN (0x00000200)
118#define ACE_STATUS_CFGADDR_MASK (0x0000e000)
119#define ACE_STATUS_CFBSY (0x00020000)
120#define ACE_STATUS_CFRDY (0x00040000)
121#define ACE_STATUS_CFDWF (0x00080000)
122#define ACE_STATUS_CFDSC (0x00100000)
123#define ACE_STATUS_CFDRQ (0x00200000)
124#define ACE_STATUS_CFCORR (0x00400000)
125#define ACE_STATUS_CFERR (0x00800000)
126
127#define ACE_ERROR (0x08)
128#define ACE_CFGLBA (0x0c)
129#define ACE_MPULBA (0x10)
130
131#define ACE_SECCNTCMD (0x14)
132#define ACE_SECCNTCMD_RESET (0x0100)
133#define ACE_SECCNTCMD_IDENTIFY (0x0200)
134#define ACE_SECCNTCMD_READ_DATA (0x0300)
135#define ACE_SECCNTCMD_WRITE_DATA (0x0400)
136#define ACE_SECCNTCMD_ABORT (0x0600)
137
138#define ACE_VERSION (0x16)
139#define ACE_VERSION_REVISION_MASK (0x00FF)
140#define ACE_VERSION_MINOR_MASK (0x0F00)
141#define ACE_VERSION_MAJOR_MASK (0xF000)
142
143#define ACE_CTRL (0x18)
144#define ACE_CTRL_FORCELOCKREQ (0x0001)
145#define ACE_CTRL_LOCKREQ (0x0002)
146#define ACE_CTRL_FORCECFGADDR (0x0004)
147#define ACE_CTRL_FORCECFGMODE (0x0008)
148#define ACE_CTRL_CFGMODE (0x0010)
149#define ACE_CTRL_CFGSTART (0x0020)
150#define ACE_CTRL_CFGSEL (0x0040)
151#define ACE_CTRL_CFGRESET (0x0080)
152#define ACE_CTRL_DATABUFRDYIRQ (0x0100)
153#define ACE_CTRL_ERRORIRQ (0x0200)
154#define ACE_CTRL_CFGDONEIRQ (0x0400)
155#define ACE_CTRL_RESETIRQ (0x0800)
156#define ACE_CTRL_CFGPROG (0x1000)
157#define ACE_CTRL_CFGADDR_MASK (0xe000)
158
159#define ACE_FATSTAT (0x1c)
160
161#define ACE_NUM_MINORS 16
162#define ACE_SECTOR_SIZE (512)
163#define ACE_FIFO_SIZE (32)
164#define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE)
165
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166#define ACE_BUS_WIDTH_8 0
167#define ACE_BUS_WIDTH_16 1
168
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169struct ace_reg_ops;
170
171struct ace_device {
172 /* driver state data */
173 int id;
174 int media_change;
175 int users;
176 struct list_head list;
177
178 /* finite state machine data */
179 struct tasklet_struct fsm_tasklet;
180 uint fsm_task; /* Current activity (ACE_TASK_*) */
181 uint fsm_state; /* Current state (ACE_FSM_STATE_*) */
182 uint fsm_continue_flag; /* cleared to exit FSM mainloop */
183 uint fsm_iter_num;
184 struct timer_list stall_timer;
185
186 /* Transfer state/result, use for both id and block request */
187 struct request *req; /* request being processed */
188 void *data_ptr; /* pointer to I/O buffer */
189 int data_count; /* number of buffers remaining */
190 int data_result; /* Result of transfer; 0 := success */
191
192 int id_req_count; /* count of id requests */
193 int id_result;
194 struct completion id_completion; /* used when id req finishes */
195 int in_irq;
196
197 /* Details of hardware device */
c14464bf 198 resource_size_t physaddr;
b5515d86 199 void __iomem *baseaddr;
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200 int irq;
201 int bus_width; /* 0 := 8 bit; 1 := 16 bit */
202 struct ace_reg_ops *reg_ops;
203 int lock_count;
204
205 /* Block device data structures */
206 spinlock_t lock;
207 struct device *dev;
208 struct request_queue *queue;
209 struct gendisk *gd;
210
211 /* Inserted CF card parameters */
4aaf2fec 212 u16 cf_id[ATA_ID_WORDS];
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213};
214
215static int ace_major;
216
217/* ---------------------------------------------------------------------
218 * Low level register access
219 */
220
221struct ace_reg_ops {
222 u16(*in) (struct ace_device * ace, int reg);
223 void (*out) (struct ace_device * ace, int reg, u16 val);
224 void (*datain) (struct ace_device * ace);
225 void (*dataout) (struct ace_device * ace);
226};
227
228/* 8 Bit bus width */
229static u16 ace_in_8(struct ace_device *ace, int reg)
230{
b5515d86 231 void __iomem *r = ace->baseaddr + reg;
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232 return in_8(r) | (in_8(r + 1) << 8);
233}
234
235static void ace_out_8(struct ace_device *ace, int reg, u16 val)
236{
b5515d86 237 void __iomem *r = ace->baseaddr + reg;
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238 out_8(r, val);
239 out_8(r + 1, val >> 8);
240}
241
242static void ace_datain_8(struct ace_device *ace)
243{
b5515d86 244 void __iomem *r = ace->baseaddr + 0x40;
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245 u8 *dst = ace->data_ptr;
246 int i = ACE_FIFO_SIZE;
247 while (i--)
248 *dst++ = in_8(r++);
249 ace->data_ptr = dst;
250}
251
252static void ace_dataout_8(struct ace_device *ace)
253{
b5515d86 254 void __iomem *r = ace->baseaddr + 0x40;
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255 u8 *src = ace->data_ptr;
256 int i = ACE_FIFO_SIZE;
257 while (i--)
258 out_8(r++, *src++);
259 ace->data_ptr = src;
260}
261
262static struct ace_reg_ops ace_reg_8_ops = {
263 .in = ace_in_8,
264 .out = ace_out_8,
265 .datain = ace_datain_8,
266 .dataout = ace_dataout_8,
267};
268
269/* 16 bit big endian bus attachment */
270static u16 ace_in_be16(struct ace_device *ace, int reg)
271{
272 return in_be16(ace->baseaddr + reg);
273}
274
275static void ace_out_be16(struct ace_device *ace, int reg, u16 val)
276{
277 out_be16(ace->baseaddr + reg, val);
278}
279
280static void ace_datain_be16(struct ace_device *ace)
281{
282 int i = ACE_FIFO_SIZE / 2;
283 u16 *dst = ace->data_ptr;
284 while (i--)
285 *dst++ = in_le16(ace->baseaddr + 0x40);
286 ace->data_ptr = dst;
287}
288
289static void ace_dataout_be16(struct ace_device *ace)
290{
291 int i = ACE_FIFO_SIZE / 2;
292 u16 *src = ace->data_ptr;
293 while (i--)
294 out_le16(ace->baseaddr + 0x40, *src++);
295 ace->data_ptr = src;
296}
297
298/* 16 bit little endian bus attachment */
299static u16 ace_in_le16(struct ace_device *ace, int reg)
300{
301 return in_le16(ace->baseaddr + reg);
302}
303
304static void ace_out_le16(struct ace_device *ace, int reg, u16 val)
305{
306 out_le16(ace->baseaddr + reg, val);
307}
308
309static void ace_datain_le16(struct ace_device *ace)
310{
311 int i = ACE_FIFO_SIZE / 2;
312 u16 *dst = ace->data_ptr;
313 while (i--)
314 *dst++ = in_be16(ace->baseaddr + 0x40);
315 ace->data_ptr = dst;
316}
317
318static void ace_dataout_le16(struct ace_device *ace)
319{
320 int i = ACE_FIFO_SIZE / 2;
321 u16 *src = ace->data_ptr;
322 while (i--)
323 out_be16(ace->baseaddr + 0x40, *src++);
324 ace->data_ptr = src;
325}
326
327static struct ace_reg_ops ace_reg_be16_ops = {
328 .in = ace_in_be16,
329 .out = ace_out_be16,
330 .datain = ace_datain_be16,
331 .dataout = ace_dataout_be16,
332};
333
334static struct ace_reg_ops ace_reg_le16_ops = {
335 .in = ace_in_le16,
336 .out = ace_out_le16,
337 .datain = ace_datain_le16,
338 .dataout = ace_dataout_le16,
339};
340
341static inline u16 ace_in(struct ace_device *ace, int reg)
342{
343 return ace->reg_ops->in(ace, reg);
344}
345
346static inline u32 ace_in32(struct ace_device *ace, int reg)
347{
348 return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16);
349}
350
351static inline void ace_out(struct ace_device *ace, int reg, u16 val)
352{
353 ace->reg_ops->out(ace, reg, val);
354}
355
356static inline void ace_out32(struct ace_device *ace, int reg, u32 val)
357{
358 ace_out(ace, reg, val);
359 ace_out(ace, reg + 2, val >> 16);
360}
361
362/* ---------------------------------------------------------------------
363 * Debug support functions
364 */
365
366#if defined(DEBUG)
367static void ace_dump_mem(void *base, int len)
368{
369 const char *ptr = base;
370 int i, j;
371
372 for (i = 0; i < len; i += 16) {
373 printk(KERN_INFO "%.8x:", i);
374 for (j = 0; j < 16; j++) {
375 if (!(j % 4))
376 printk(" ");
377 printk("%.2x", ptr[i + j]);
378 }
379 printk(" ");
380 for (j = 0; j < 16; j++)
381 printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.');
382 printk("\n");
383 }
384}
385#else
386static inline void ace_dump_mem(void *base, int len)
387{
388}
389#endif
390
391static void ace_dump_regs(struct ace_device *ace)
392{
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393 dev_info(ace->dev,
394 " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n"
395 " status:%.8x mpu_lba:%.8x busmode:%4x\n"
396 " error: %.8x cfg_lba:%.8x fatstat:%.4x\n",
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397 ace_in32(ace, ACE_CTRL),
398 ace_in(ace, ACE_SECCNTCMD),
399 ace_in(ace, ACE_VERSION),
400 ace_in32(ace, ACE_STATUS),
401 ace_in32(ace, ACE_MPULBA),
402 ace_in(ace, ACE_BUSMODE),
403 ace_in32(ace, ACE_ERROR),
404 ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT));
405}
406
4aaf2fec 407void ace_fix_driveid(u16 *id)
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408{
409#if defined(__BIG_ENDIAN)
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410 int i;
411
412 /* All half words have wrong byte order; swap the bytes */
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413 for (i = 0; i < ATA_ID_WORDS; i++, id++)
414 *id = le16_to_cpu(*id);
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415#endif
416}
417
418/* ---------------------------------------------------------------------
419 * Finite State Machine (FSM) implementation
420 */
421
422/* FSM tasks; used to direct state transitions */
423#define ACE_TASK_IDLE 0
424#define ACE_TASK_IDENTIFY 1
425#define ACE_TASK_READ 2
426#define ACE_TASK_WRITE 3
427#define ACE_FSM_NUM_TASKS 4
428
429/* FSM state definitions */
430#define ACE_FSM_STATE_IDLE 0
431#define ACE_FSM_STATE_REQ_LOCK 1
432#define ACE_FSM_STATE_WAIT_LOCK 2
433#define ACE_FSM_STATE_WAIT_CFREADY 3
434#define ACE_FSM_STATE_IDENTIFY_PREPARE 4
435#define ACE_FSM_STATE_IDENTIFY_TRANSFER 5
436#define ACE_FSM_STATE_IDENTIFY_COMPLETE 6
437#define ACE_FSM_STATE_REQ_PREPARE 7
438#define ACE_FSM_STATE_REQ_TRANSFER 8
439#define ACE_FSM_STATE_REQ_COMPLETE 9
440#define ACE_FSM_STATE_ERROR 10
441#define ACE_FSM_NUM_STATES 11
442
443/* Set flag to exit FSM loop and reschedule tasklet */
444static inline void ace_fsm_yield(struct ace_device *ace)
445{
446 dev_dbg(ace->dev, "ace_fsm_yield()\n");
447 tasklet_schedule(&ace->fsm_tasklet);
448 ace->fsm_continue_flag = 0;
449}
450
451/* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */
452static inline void ace_fsm_yieldirq(struct ace_device *ace)
453{
454 dev_dbg(ace->dev, "ace_fsm_yieldirq()\n");
455
456 if (ace->irq == NO_IRQ)
457 /* No IRQ assigned, so need to poll */
458 tasklet_schedule(&ace->fsm_tasklet);
459 ace->fsm_continue_flag = 0;
460}
461
462/* Get the next read/write request; ending requests that we don't handle */
165125e1 463struct request *ace_get_next_request(struct request_queue * q)
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464{
465 struct request *req;
466
9934c8c0 467 while ((req = blk_peek_request(q)) != NULL) {
33659ebb 468 if (req->cmd_type == REQ_TYPE_FS)
74489a91 469 break;
9934c8c0 470 blk_start_request(req);
2d75ce08 471 __blk_end_request_all(req, -EIO);
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472 }
473 return req;
474}
475
476static void ace_fsm_dostate(struct ace_device *ace)
477{
478 struct request *req;
479 u32 status;
480 u16 val;
481 int count;
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482
483#if defined(DEBUG)
484 dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n",
485 ace->fsm_state, ace->id_req_count);
486#endif
487
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488 /* Verify that there is actually a CF in the slot. If not, then
489 * bail out back to the idle state and wake up all the waiters */
490 status = ace_in32(ace, ACE_STATUS);
491 if ((status & ACE_STATUS_CFDETECT) == 0) {
492 ace->fsm_state = ACE_FSM_STATE_IDLE;
493 ace->media_change = 1;
494 set_capacity(ace->gd, 0);
495 dev_info(ace->dev, "No CF in slot\n");
496
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497 /* Drop all in-flight and pending requests */
498 if (ace->req) {
499 __blk_end_request_all(ace->req, -EIO);
500 ace->req = NULL;
501 }
9934c8c0 502 while ((req = blk_fetch_request(ace->queue)) != NULL)
2d75ce08 503 __blk_end_request_all(req, -EIO);
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504
505 /* Drop back to IDLE state and notify waiters */
506 ace->fsm_state = ACE_FSM_STATE_IDLE;
507 ace->id_result = -EIO;
508 while (ace->id_req_count) {
509 complete(&ace->id_completion);
510 ace->id_req_count--;
511 }
512 }
513
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514 switch (ace->fsm_state) {
515 case ACE_FSM_STATE_IDLE:
516 /* See if there is anything to do */
517 if (ace->id_req_count || ace_get_next_request(ace->queue)) {
518 ace->fsm_iter_num++;
519 ace->fsm_state = ACE_FSM_STATE_REQ_LOCK;
520 mod_timer(&ace->stall_timer, jiffies + HZ);
521 if (!timer_pending(&ace->stall_timer))
522 add_timer(&ace->stall_timer);
523 break;
524 }
525 del_timer(&ace->stall_timer);
526 ace->fsm_continue_flag = 0;
527 break;
528
529 case ACE_FSM_STATE_REQ_LOCK:
530 if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
531 /* Already have the lock, jump to next state */
532 ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
533 break;
534 }
535
536 /* Request the lock */
537 val = ace_in(ace, ACE_CTRL);
538 ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ);
539 ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK;
540 break;
541
542 case ACE_FSM_STATE_WAIT_LOCK:
543 if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
544 /* got the lock; move to next state */
545 ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
546 break;
547 }
548
549 /* wait a bit for the lock */
550 ace_fsm_yield(ace);
551 break;
552
553 case ACE_FSM_STATE_WAIT_CFREADY:
554 status = ace_in32(ace, ACE_STATUS);
555 if (!(status & ACE_STATUS_RDYFORCFCMD) ||
556 (status & ACE_STATUS_CFBSY)) {
557 /* CF card isn't ready; it needs to be polled */
558 ace_fsm_yield(ace);
559 break;
560 }
561
562 /* Device is ready for command; determine what to do next */
563 if (ace->id_req_count)
564 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE;
565 else
566 ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE;
567 break;
568
569 case ACE_FSM_STATE_IDENTIFY_PREPARE:
570 /* Send identify command */
571 ace->fsm_task = ACE_TASK_IDENTIFY;
f0edef8c 572 ace->data_ptr = ace->cf_id;
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573 ace->data_count = ACE_BUF_PER_SECTOR;
574 ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY);
575
576 /* As per datasheet, put config controller in reset */
577 val = ace_in(ace, ACE_CTRL);
578 ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
579
580 /* irq handler takes over from this point; wait for the
581 * transfer to complete */
582 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER;
583 ace_fsm_yieldirq(ace);
584 break;
585
586 case ACE_FSM_STATE_IDENTIFY_TRANSFER:
587 /* Check that the sysace is ready to receive data */
588 status = ace_in32(ace, ACE_STATUS);
589 if (status & ACE_STATUS_CFBSY) {
590 dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n",
591 ace->fsm_task, ace->fsm_iter_num,
592 ace->data_count);
593 ace_fsm_yield(ace);
594 break;
595 }
596 if (!(status & ACE_STATUS_DATABUFRDY)) {
597 ace_fsm_yield(ace);
598 break;
599 }
600
601 /* Transfer the next buffer */
602 ace->reg_ops->datain(ace);
603 ace->data_count--;
604
605 /* If there are still buffers to be transfers; jump out here */
606 if (ace->data_count != 0) {
607 ace_fsm_yieldirq(ace);
608 break;
609 }
610
611 /* transfer finished; kick state machine */
612 dev_dbg(ace->dev, "identify finished\n");
613 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE;
614 break;
615
616 case ACE_FSM_STATE_IDENTIFY_COMPLETE:
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617 ace_fix_driveid(ace->cf_id);
618 ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */
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619
620 if (ace->data_result) {
621 /* Error occured, disable the disk */
622 ace->media_change = 1;
623 set_capacity(ace->gd, 0);
624 dev_err(ace->dev, "error fetching CF id (%i)\n",
625 ace->data_result);
626 } else {
627 ace->media_change = 0;
628
629 /* Record disk parameters */
4aaf2fec 630 set_capacity(ace->gd,
f0edef8c 631 ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY));
74489a91 632 dev_info(ace->dev, "capacity: %i sectors\n",
f0edef8c 633 ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY));
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634 }
635
636 /* We're done, drop to IDLE state and notify waiters */
637 ace->fsm_state = ACE_FSM_STATE_IDLE;
638 ace->id_result = ace->data_result;
639 while (ace->id_req_count) {
640 complete(&ace->id_completion);
641 ace->id_req_count--;
642 }
643 break;
644
645 case ACE_FSM_STATE_REQ_PREPARE:
646 req = ace_get_next_request(ace->queue);
647 if (!req) {
648 ace->fsm_state = ACE_FSM_STATE_IDLE;
649 break;
650 }
9934c8c0 651 blk_start_request(req);
74489a91
GL
652
653 /* Okay, it's a data request, set it up for transfer */
654 dev_dbg(ace->dev,
5b93629b 655 "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n",
83096ebf
TH
656 (unsigned long long)blk_rq_pos(req),
657 blk_rq_sectors(req), blk_rq_cur_sectors(req),
658 rq_data_dir(req));
74489a91
GL
659
660 ace->req = req;
661 ace->data_ptr = req->buffer;
83096ebf
TH
662 ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR;
663 ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF);
74489a91 664
5b93629b 665 count = blk_rq_sectors(req);
74489a91
GL
666 if (rq_data_dir(req)) {
667 /* Kick off write request */
668 dev_dbg(ace->dev, "write data\n");
669 ace->fsm_task = ACE_TASK_WRITE;
670 ace_out(ace, ACE_SECCNTCMD,
671 count | ACE_SECCNTCMD_WRITE_DATA);
672 } else {
673 /* Kick off read request */
674 dev_dbg(ace->dev, "read data\n");
675 ace->fsm_task = ACE_TASK_READ;
676 ace_out(ace, ACE_SECCNTCMD,
677 count | ACE_SECCNTCMD_READ_DATA);
678 }
679
680 /* As per datasheet, put config controller in reset */
681 val = ace_in(ace, ACE_CTRL);
682 ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
683
684 /* Move to the transfer state. The systemace will raise
685 * an interrupt once there is something to do
686 */
687 ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER;
688 if (ace->fsm_task == ACE_TASK_READ)
689 ace_fsm_yieldirq(ace); /* wait for data ready */
690 break;
691
692 case ACE_FSM_STATE_REQ_TRANSFER:
693 /* Check that the sysace is ready to receive data */
694 status = ace_in32(ace, ACE_STATUS);
695 if (status & ACE_STATUS_CFBSY) {
696 dev_dbg(ace->dev,
697 "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n",
698 ace->fsm_task, ace->fsm_iter_num,
83096ebf 699 blk_rq_cur_sectors(ace->req) * 16,
74489a91
GL
700 ace->data_count, ace->in_irq);
701 ace_fsm_yield(ace); /* need to poll CFBSY bit */
702 break;
703 }
704 if (!(status & ACE_STATUS_DATABUFRDY)) {
705 dev_dbg(ace->dev,
706 "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n",
707 ace->fsm_task, ace->fsm_iter_num,
83096ebf 708 blk_rq_cur_sectors(ace->req) * 16,
74489a91
GL
709 ace->data_count, ace->in_irq);
710 ace_fsm_yieldirq(ace);
711 break;
712 }
713
714 /* Transfer the next buffer */
74489a91
GL
715 if (ace->fsm_task == ACE_TASK_WRITE)
716 ace->reg_ops->dataout(ace);
717 else
718 ace->reg_ops->datain(ace);
719 ace->data_count--;
720
721 /* If there are still buffers to be transfers; jump out here */
722 if (ace->data_count != 0) {
723 ace_fsm_yieldirq(ace);
724 break;
725 }
726
727 /* bio finished; is there another one? */
2d75ce08 728 if (__blk_end_request_cur(ace->req, 0)) {
5b93629b
TH
729 /* dev_dbg(ace->dev, "next block; h=%u c=%u\n",
730 * blk_rq_sectors(ace->req),
83096ebf 731 * blk_rq_cur_sectors(ace->req));
74489a91
GL
732 */
733 ace->data_ptr = ace->req->buffer;
83096ebf 734 ace->data_count = blk_rq_cur_sectors(ace->req) * 16;
74489a91
GL
735 ace_fsm_yieldirq(ace);
736 break;
737 }
738
739 ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE;
740 break;
741
742 case ACE_FSM_STATE_REQ_COMPLETE:
74489a91
GL
743 ace->req = NULL;
744
745 /* Finished request; go to idle state */
746 ace->fsm_state = ACE_FSM_STATE_IDLE;
747 break;
748
749 default:
750 ace->fsm_state = ACE_FSM_STATE_IDLE;
751 break;
752 }
753}
754
755static void ace_fsm_tasklet(unsigned long data)
756{
757 struct ace_device *ace = (void *)data;
758 unsigned long flags;
759
760 spin_lock_irqsave(&ace->lock, flags);
761
762 /* Loop over state machine until told to stop */
763 ace->fsm_continue_flag = 1;
764 while (ace->fsm_continue_flag)
765 ace_fsm_dostate(ace);
766
767 spin_unlock_irqrestore(&ace->lock, flags);
768}
769
770static void ace_stall_timer(unsigned long data)
771{
772 struct ace_device *ace = (void *)data;
773 unsigned long flags;
774
775 dev_warn(ace->dev,
776 "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n",
777 ace->fsm_state, ace->fsm_task, ace->fsm_iter_num,
778 ace->data_count);
779 spin_lock_irqsave(&ace->lock, flags);
780
781 /* Rearm the stall timer *before* entering FSM (which may then
782 * delete the timer) */
783 mod_timer(&ace->stall_timer, jiffies + HZ);
784
785 /* Loop over state machine until told to stop */
786 ace->fsm_continue_flag = 1;
787 while (ace->fsm_continue_flag)
788 ace_fsm_dostate(ace);
789
790 spin_unlock_irqrestore(&ace->lock, flags);
791}
792
793/* ---------------------------------------------------------------------
794 * Interrupt handling routines
795 */
796static int ace_interrupt_checkstate(struct ace_device *ace)
797{
798 u32 sreg = ace_in32(ace, ACE_STATUS);
799 u16 creg = ace_in(ace, ACE_CTRL);
800
801 /* Check for error occurance */
802 if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) &&
803 (creg & ACE_CTRL_ERRORIRQ)) {
804 dev_err(ace->dev, "transfer failure\n");
805 ace_dump_regs(ace);
806 return -EIO;
807 }
808
809 return 0;
810}
811
812static irqreturn_t ace_interrupt(int irq, void *dev_id)
813{
814 u16 creg;
815 struct ace_device *ace = dev_id;
816
817 /* be safe and get the lock */
818 spin_lock(&ace->lock);
819 ace->in_irq = 1;
820
821 /* clear the interrupt */
822 creg = ace_in(ace, ACE_CTRL);
823 ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ);
824 ace_out(ace, ACE_CTRL, creg);
825
826 /* check for IO failures */
827 if (ace_interrupt_checkstate(ace))
828 ace->data_result = -EIO;
829
830 if (ace->fsm_task == 0) {
831 dev_err(ace->dev,
832 "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n",
833 ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL),
834 ace_in(ace, ACE_SECCNTCMD));
835 dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n",
836 ace->fsm_task, ace->fsm_state, ace->data_count);
837 }
838
839 /* Loop over state machine until told to stop */
840 ace->fsm_continue_flag = 1;
841 while (ace->fsm_continue_flag)
842 ace_fsm_dostate(ace);
843
844 /* done with interrupt; drop the lock */
845 ace->in_irq = 0;
846 spin_unlock(&ace->lock);
847
848 return IRQ_HANDLED;
849}
850
851/* ---------------------------------------------------------------------
852 * Block ops
853 */
165125e1 854static void ace_request(struct request_queue * q)
74489a91
GL
855{
856 struct request *req;
857 struct ace_device *ace;
858
859 req = ace_get_next_request(q);
860
861 if (req) {
862 ace = req->rq_disk->private_data;
863 tasklet_schedule(&ace->fsm_tasklet);
864 }
865}
866
867static int ace_media_changed(struct gendisk *gd)
868{
869 struct ace_device *ace = gd->private_data;
870 dev_dbg(ace->dev, "ace_media_changed(): %i\n", ace->media_change);
871
872 return ace->media_change;
873}
874
875static int ace_revalidate_disk(struct gendisk *gd)
876{
877 struct ace_device *ace = gd->private_data;
878 unsigned long flags;
879
880 dev_dbg(ace->dev, "ace_revalidate_disk()\n");
881
882 if (ace->media_change) {
883 dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n");
884
885 spin_lock_irqsave(&ace->lock, flags);
886 ace->id_req_count++;
887 spin_unlock_irqrestore(&ace->lock, flags);
888
889 tasklet_schedule(&ace->fsm_tasklet);
890 wait_for_completion(&ace->id_completion);
891 }
892
893 dev_dbg(ace->dev, "revalidate complete\n");
894 return ace->id_result;
895}
896
f3f68b36 897static int ace_open(struct block_device *bdev, fmode_t mode)
74489a91 898{
f3f68b36 899 struct ace_device *ace = bdev->bd_disk->private_data;
74489a91
GL
900 unsigned long flags;
901
902 dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1);
903
74489a91
GL
904 spin_lock_irqsave(&ace->lock, flags);
905 ace->users++;
906 spin_unlock_irqrestore(&ace->lock, flags);
907
f3f68b36 908 check_disk_change(bdev);
74489a91
GL
909 return 0;
910}
911
f3f68b36 912static int ace_release(struct gendisk *disk, fmode_t mode)
74489a91 913{
f3f68b36 914 struct ace_device *ace = disk->private_data;
74489a91
GL
915 unsigned long flags;
916 u16 val;
917
918 dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1);
919
920 spin_lock_irqsave(&ace->lock, flags);
921 ace->users--;
922 if (ace->users == 0) {
923 val = ace_in(ace, ACE_CTRL);
924 ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ);
925 }
926 spin_unlock_irqrestore(&ace->lock, flags);
927 return 0;
928}
929
a6b3a93e 930static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo)
74489a91 931{
a6b3a93e 932 struct ace_device *ace = bdev->bd_disk->private_data;
f0edef8c 933 u16 *cf_id = ace->cf_id;
74489a91 934
a6b3a93e
CH
935 dev_dbg(ace->dev, "ace_getgeo()\n");
936
4aaf2fec
BZ
937 geo->heads = cf_id[ATA_ID_HEADS];
938 geo->sectors = cf_id[ATA_ID_SECTORS];
939 geo->cylinders = cf_id[ATA_ID_CYLS];
a6b3a93e
CH
940
941 return 0;
74489a91
GL
942}
943
83d5cde4 944static const struct block_device_operations ace_fops = {
74489a91 945 .owner = THIS_MODULE,
f3f68b36
AV
946 .open = ace_open,
947 .release = ace_release,
74489a91
GL
948 .media_changed = ace_media_changed,
949 .revalidate_disk = ace_revalidate_disk,
a6b3a93e 950 .getgeo = ace_getgeo,
74489a91
GL
951};
952
953/* --------------------------------------------------------------------
954 * SystemACE device setup/teardown code
955 */
956static int __devinit ace_setup(struct ace_device *ace)
957{
958 u16 version;
959 u16 val;
74489a91
GL
960 int rc;
961
4a24d861 962 dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace);
c14464bf
YT
963 dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n",
964 (unsigned long long)ace->physaddr, ace->irq);
4a24d861 965
74489a91
GL
966 spin_lock_init(&ace->lock);
967 init_completion(&ace->id_completion);
968
969 /*
970 * Map the device
971 */
972 ace->baseaddr = ioremap(ace->physaddr, 0x80);
973 if (!ace->baseaddr)
974 goto err_ioremap;
975
74489a91
GL
976 /*
977 * Initialize the state machine tasklet and stall timer
978 */
979 tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace);
980 setup_timer(&ace->stall_timer, ace_stall_timer, (unsigned long)ace);
981
982 /*
983 * Initialize the request queue
984 */
985 ace->queue = blk_init_queue(ace_request, &ace->lock);
986 if (ace->queue == NULL)
987 goto err_blk_initq;
e1defc4f 988 blk_queue_logical_block_size(ace->queue, 512);
74489a91
GL
989
990 /*
991 * Allocate and initialize GD structure
992 */
993 ace->gd = alloc_disk(ACE_NUM_MINORS);
994 if (!ace->gd)
995 goto err_alloc_disk;
996
997 ace->gd->major = ace_major;
998 ace->gd->first_minor = ace->id * ACE_NUM_MINORS;
999 ace->gd->fops = &ace_fops;
1000 ace->gd->queue = ace->queue;
1001 ace->gd->private_data = ace;
1002 snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a');
1003
1004 /* set bus width */
4a24d861 1005 if (ace->bus_width == ACE_BUS_WIDTH_16) {
74489a91
GL
1006 /* 0x0101 should work regardless of endianess */
1007 ace_out_le16(ace, ACE_BUSMODE, 0x0101);
1008
1009 /* read it back to determine endianess */
1010 if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001)
1011 ace->reg_ops = &ace_reg_le16_ops;
1012 else
1013 ace->reg_ops = &ace_reg_be16_ops;
1014 } else {
1015 ace_out_8(ace, ACE_BUSMODE, 0x00);
1016 ace->reg_ops = &ace_reg_8_ops;
1017 }
1018
1019 /* Make sure version register is sane */
1020 version = ace_in(ace, ACE_VERSION);
1021 if ((version == 0) || (version == 0xFFFF))
1022 goto err_read;
1023
1024 /* Put sysace in a sane state by clearing most control reg bits */
1025 ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE |
1026 ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ);
1027
32f6fff4
GL
1028 /* Now we can hook up the irq handler */
1029 if (ace->irq != NO_IRQ) {
1030 rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace);
1031 if (rc) {
1032 /* Failure - fall back to polled mode */
1033 dev_err(ace->dev, "request_irq failed\n");
1034 ace->irq = NO_IRQ;
1035 }
1036 }
1037
d2bbf3da
GL
1038 /* Enable interrupts */
1039 val = ace_in(ace, ACE_CTRL);
1040 val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ;
1041 ace_out(ace, ACE_CTRL, val);
1042
74489a91
GL
1043 /* Print the identification */
1044 dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n",
1045 (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff);
c14464bf
YT
1046 dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n",
1047 (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq);
74489a91
GL
1048
1049 ace->media_change = 1;
1050 ace_revalidate_disk(ace->gd);
1051
1052 /* Make the sysace device 'live' */
1053 add_disk(ace->gd);
1054
1055 return 0;
1056
ed155a95 1057err_read:
74489a91 1058 put_disk(ace->gd);
ed155a95 1059err_alloc_disk:
74489a91 1060 blk_cleanup_queue(ace->queue);
ed155a95 1061err_blk_initq:
74489a91 1062 iounmap(ace->baseaddr);
ed155a95 1063err_ioremap:
c14464bf
YT
1064 dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n",
1065 (unsigned long long) ace->physaddr);
74489a91
GL
1066 return -ENOMEM;
1067}
1068
1069static void __devexit ace_teardown(struct ace_device *ace)
1070{
1071 if (ace->gd) {
1072 del_gendisk(ace->gd);
1073 put_disk(ace->gd);
1074 }
1075
1076 if (ace->queue)
1077 blk_cleanup_queue(ace->queue);
1078
1079 tasklet_kill(&ace->fsm_tasklet);
1080
1081 if (ace->irq != NO_IRQ)
1082 free_irq(ace->irq, ace);
1083
1084 iounmap(ace->baseaddr);
1085}
1086
1b455466 1087static int __devinit
c14464bf 1088ace_alloc(struct device *dev, int id, resource_size_t physaddr,
1b455466 1089 int irq, int bus_width)
74489a91 1090{
74489a91 1091 struct ace_device *ace;
1b455466
GL
1092 int rc;
1093 dev_dbg(dev, "ace_alloc(%p)\n", dev);
74489a91 1094
1b455466
GL
1095 if (!physaddr) {
1096 rc = -ENODEV;
1097 goto err_noreg;
1098 }
74489a91 1099
1b455466 1100 /* Allocate and initialize the ace device structure */
74489a91 1101 ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL);
1b455466
GL
1102 if (!ace) {
1103 rc = -ENOMEM;
74489a91 1104 goto err_alloc;
74489a91
GL
1105 }
1106
1b455466
GL
1107 ace->dev = dev;
1108 ace->id = id;
1109 ace->physaddr = physaddr;
1110 ace->irq = irq;
1111 ace->bus_width = bus_width;
74489a91 1112
1b455466 1113 /* Call the setup code */
34e1b834
GL
1114 rc = ace_setup(ace);
1115 if (rc)
74489a91
GL
1116 goto err_setup;
1117
1b455466 1118 dev_set_drvdata(dev, ace);
74489a91
GL
1119 return 0;
1120
ed155a95 1121err_setup:
1b455466 1122 dev_set_drvdata(dev, NULL);
74489a91 1123 kfree(ace);
ed155a95
GL
1124err_alloc:
1125err_noreg:
1b455466
GL
1126 dev_err(dev, "could not initialize device, err=%i\n", rc);
1127 return rc;
74489a91
GL
1128}
1129
1b455466 1130static void __devexit ace_free(struct device *dev)
74489a91 1131{
1b455466
GL
1132 struct ace_device *ace = dev_get_drvdata(dev);
1133 dev_dbg(dev, "ace_free(%p)\n", dev);
74489a91
GL
1134
1135 if (ace) {
1136 ace_teardown(ace);
1b455466 1137 dev_set_drvdata(dev, NULL);
74489a91
GL
1138 kfree(ace);
1139 }
1b455466
GL
1140}
1141
1142/* ---------------------------------------------------------------------
1143 * Platform Bus Support
1144 */
1145
1146static int __devinit ace_probe(struct platform_device *dev)
1147{
c14464bf 1148 resource_size_t physaddr = 0;
4a24d861 1149 int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */
1b455466
GL
1150 int id = dev->id;
1151 int irq = NO_IRQ;
1152 int i;
1153
1154 dev_dbg(&dev->dev, "ace_probe(%p)\n", dev);
1155
1156 for (i = 0; i < dev->num_resources; i++) {
1157 if (dev->resource[i].flags & IORESOURCE_MEM)
1158 physaddr = dev->resource[i].start;
1159 if (dev->resource[i].flags & IORESOURCE_IRQ)
1160 irq = dev->resource[i].start;
1161 }
1162
1163 /* Call the bus-independant setup code */
1164 return ace_alloc(&dev->dev, id, physaddr, irq, bus_width);
1165}
74489a91 1166
1b455466
GL
1167/*
1168 * Platform bus remove() method
1169 */
1170static int __devexit ace_remove(struct platform_device *dev)
1171{
1172 ace_free(&dev->dev);
74489a91
GL
1173 return 0;
1174}
1175
edec4961 1176static struct platform_driver ace_platform_driver = {
74489a91
GL
1177 .probe = ace_probe,
1178 .remove = __devexit_p(ace_remove),
edec4961
GL
1179 .driver = {
1180 .owner = THIS_MODULE,
1181 .name = "xsysace",
1182 },
74489a91
GL
1183};
1184
95e896c3
GL
1185/* ---------------------------------------------------------------------
1186 * OF_Platform Bus Support
1187 */
1188
1189#if defined(CONFIG_OF)
1190static int __devinit
1191ace_of_probe(struct of_device *op, const struct of_device_id *match)
1192{
1193 struct resource res;
c14464bf 1194 resource_size_t physaddr;
95e896c3
GL
1195 const u32 *id;
1196 int irq, bus_width, rc;
1197
1198 dev_dbg(&op->dev, "ace_of_probe(%p, %p)\n", op, match);
1199
1200 /* device id */
61c7a080 1201 id = of_get_property(op->dev.of_node, "port-number", NULL);
95e896c3
GL
1202
1203 /* physaddr */
61c7a080 1204 rc = of_address_to_resource(op->dev.of_node, 0, &res);
95e896c3
GL
1205 if (rc) {
1206 dev_err(&op->dev, "invalid address\n");
1207 return rc;
1208 }
1209 physaddr = res.start;
1210
1211 /* irq */
61c7a080 1212 irq = irq_of_parse_and_map(op->dev.of_node, 0);
95e896c3
GL
1213
1214 /* bus width */
1215 bus_width = ACE_BUS_WIDTH_16;
61c7a080 1216 if (of_find_property(op->dev.of_node, "8-bit", NULL))
95e896c3
GL
1217 bus_width = ACE_BUS_WIDTH_8;
1218
1219 /* Call the bus-independant setup code */
1220 return ace_alloc(&op->dev, id ? *id : 0, physaddr, irq, bus_width);
1221}
1222
1223static int __devexit ace_of_remove(struct of_device *op)
1224{
1225 ace_free(&op->dev);
1226 return 0;
1227}
1228
1229/* Match table for of_platform binding */
5cccfd9b 1230static const struct of_device_id ace_of_match[] __devinitconst = {
0e349b0e
SN
1231 { .compatible = "xlnx,opb-sysace-1.00.b", },
1232 { .compatible = "xlnx,opb-sysace-1.00.c", },
1233 { .compatible = "xlnx,xps-sysace-1.00.a", },
f5020384 1234 { .compatible = "xlnx,sysace", },
95e896c3
GL
1235 {},
1236};
1237MODULE_DEVICE_TABLE(of, ace_of_match);
1238
1239static struct of_platform_driver ace_of_driver = {
95e896c3
GL
1240 .probe = ace_of_probe,
1241 .remove = __devexit_p(ace_of_remove),
1242 .driver = {
1243 .name = "xsysace",
4018294b
GL
1244 .owner = THIS_MODULE,
1245 .of_match_table = ace_of_match,
95e896c3
GL
1246 },
1247};
1248
1249/* Registration helpers to keep the number of #ifdefs to a minimum */
1250static inline int __init ace_of_register(void)
1251{
1252 pr_debug("xsysace: registering OF binding\n");
1253 return of_register_platform_driver(&ace_of_driver);
1254}
1255
1256static inline void __exit ace_of_unregister(void)
1257{
1258 of_unregister_platform_driver(&ace_of_driver);
1259}
1260#else /* CONFIG_OF */
1261/* CONFIG_OF not enabled; do nothing helpers */
1262static inline int __init ace_of_register(void) { return 0; }
1263static inline void __exit ace_of_unregister(void) { }
1264#endif /* CONFIG_OF */
1265
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1266/* ---------------------------------------------------------------------
1267 * Module init/exit routines
1268 */
1269static int __init ace_init(void)
1270{
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1271 int rc;
1272
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1273 ace_major = register_blkdev(ace_major, "xsysace");
1274 if (ace_major <= 0) {
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1275 rc = -ENOMEM;
1276 goto err_blk;
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1277 }
1278
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1279 rc = ace_of_register();
1280 if (rc)
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1281 goto err_of;
1282
4a24d861 1283 pr_debug("xsysace: registering platform binding\n");
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1284 rc = platform_driver_register(&ace_platform_driver);
1285 if (rc)
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1286 goto err_plat;
1287
1288 pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major);
1289 return 0;
1290
ed155a95 1291err_plat:
95e896c3 1292 ace_of_unregister();
ed155a95 1293err_of:
edec4961 1294 unregister_blkdev(ace_major, "xsysace");
ed155a95 1295err_blk:
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1296 printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc);
1297 return rc;
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1298}
1299
1300static void __exit ace_exit(void)
1301{
1302 pr_debug("Unregistering Xilinx SystemACE driver\n");
edec4961 1303 platform_driver_unregister(&ace_platform_driver);
95e896c3 1304 ace_of_unregister();
c6d4d634 1305 unregister_blkdev(ace_major, "xsysace");
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1306}
1307
1308module_init(ace_init);
1309module_exit(ace_exit);