[net-next-2.6.git] / drivers / ata / sata_sis.c

/*
 *  sata_sis.c - Silicon Integrated Systems SATA
 *
 *  Maintained by:  Uwe Koziolek
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 Uwe Koziolek
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_sis"
#define DRV_VERSION	"0.6"

enum {
	sis_180			= 0,
	SIS_SCR_PCI_BAR		= 5,

	/* PCI configuration registers */
	SIS_GENCTL		= 0x54, /* IDE General Control register */
	SIS_SCR_BASE		= 0xc0, /* sata0 phy SCR registers */
	SIS180_SATA1_OFS	= 0x10, /* offset from sata0->sata1 phy regs */
	SIS182_SATA1_OFS	= 0x20, /* offset from sata0->sata1 phy regs */
	SIS_PMR			= 0x90, /* port mapping register */
	SIS_PMR_COMBINED	= 0x30,

	/* random bits */
	SIS_FLAG_CFGSCR		= (1 << 30), /* host flag: SCRs via PCI cfg */

	GENCTL_IOMAPPED_SCR	= (1 << 26), /* if set, SCRs are in IO space */
};

static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);

static const struct pci_device_id sis_pci_tbl[] = {
	{ PCI_VDEVICE(SI, 0x180), sis_180 },
	{ PCI_VDEVICE(SI, 0x181), sis_180 },
	{ PCI_VDEVICE(SI, 0x182), sis_180 },

	{ }	/* terminate list */
};

static struct pci_driver sis_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sis_pci_tbl,
	.probe			= sis_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template sis_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= ATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations sis_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_pio_data_xfer,
	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= sis_scr_read,
	.scr_write		= sis_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_host_stop,
};

static struct ata_port_info sis_port_info = {
	.sht		= &sis_sht,
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x7,
	.udma_mask	= 0x7f,
	.port_ops	= &sis_ops,
};


MODULE_AUTHOR("Uwe Koziolek");
MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
{
	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);

	if (port_no)  {
		if (device == 0x182)
			addr += SIS182_SATA1_OFS;
		else
			addr += SIS180_SATA1_OFS;
	}

	return addr;
}

static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
	u32 val, val2 = 0;
	u8 pmr;

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return 0xffffffff;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	pci_read_config_dword(pdev, cfg_addr, &val);

	if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
		pci_read_config_dword(pdev, cfg_addr+0x10, &val2);

	return (val|val2) &  0xfffffffb; /* avoid problems with powerdowned ports */
}

static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
	u8 pmr;

	if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	pci_write_config_dword(pdev, cfg_addr, val);

	if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
		pci_write_config_dword(pdev, cfg_addr+0x10, val);
}

static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 val, val2 = 0;
	u8 pmr;

	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_read(ap, sc_reg);

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));

	if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
		val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);

	return (val | val2) &  0xfffffffb;
}

static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 pmr;

	if (sc_reg > SCR_CONTROL)
		return;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	if (ap->flags & SIS_FLAG_CFGSCR)
		sis_scr_cfg_write(ap, sc_reg, val);
	else {
		outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
		if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
			outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
	}
}

static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	int rc;
	u32 genctl, val;
	struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
	int pci_dev_busy = 0;
	u8 pmr;
	u8 port2_start;

	if (!printed_version++)
		dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pci_enable_device(pdev);
	if (rc)
		return rc;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	/* check and see if the SCRs are in IO space or PCI cfg space */
	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
		pi.flags |= SIS_FLAG_CFGSCR;

	/* if hardware thinks SCRs are in IO space, but there are
	 * no IO resources assigned, change to PCI cfg space.
	 */
	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
	    ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
	     (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
		genctl &= ~GENCTL_IOMAPPED_SCR;
		pci_write_config_dword(pdev, SIS_GENCTL, genctl);
		pi.flags |= SIS_FLAG_CFGSCR;
	}

	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	if (ent->device != 0x182) {
		if ((pmr & SIS_PMR_COMBINED) == 0) {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 180/181/964 chipset in SATA mode\n");
			port2_start = 64;
		}
		else {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 180/181 chipset in combined mode\n");
			port2_start=0;
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		}
	}
	else {
		pci_read_config_dword ( pdev, 0x6C, &val);
		if (val & (1L << 31)) {
			dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		}
		else
			dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
		port2_start = 0x20;
	}

	probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
	if (!probe_ent) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) {
		probe_ent->port[0].scr_addr =
			pci_resource_start(pdev, SIS_SCR_PCI_BAR);
		probe_ent->port[1].scr_addr =
			pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
	}

	pci_set_master(pdev);
	pci_intx(pdev, 1);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_regions:
	pci_release_regions(pdev);

err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;

}

static int __init sis_init(void)
{
	return pci_register_driver(&sis_pci_driver);
}

static void __exit sis_exit(void)
{
	pci_unregister_driver(&sis_pci_driver);
}

module_init(sis_init);
module_exit(sis_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sis.c - Silicon Integrated Systems SATA
	3	*
	4	* Maintained by: Uwe Koziolek
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 Uwe Koziolek
	9	*
af36d7f0 JG	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; see the file COPYING. If not, write to
	23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*
	25	*
	26	* libata documentation is available via 'make {ps\|pdf}docs',
	27	* as Documentation/DocBook/libata.*
	28	*
	29	* Hardware documentation available under NDA.
1da177e4 LT	30	*
	31	*/
	32
1da177e4 LT	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/pci.h>
	36	#include <linux/init.h>
	37	#include <linux/blkdev.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
a9524a76	40	#include <linux/device.h>
1da177e4 LT	41	#include <scsi/scsi_host.h>
	42	#include <linux/libata.h>
	43
	44	#define DRV_NAME "sata_sis"
af64371a	45	#define DRV_VERSION "0.6"
1da177e4 LT	46
	47	enum {
	48	sis_180 = 0,
	49	SIS_SCR_PCI_BAR = 5,
	50
	51	/* PCI configuration registers */
	52	SIS_GENCTL = 0x54, /* IDE General Control register */
	53	SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
f2c853bc AP	54	SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
	55	SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
	56	SIS_PMR = 0x90, /* port mapping register */
8add7885	57	SIS_PMR_COMBINED = 0x30,
1da177e4 LT	58
	59	/* random bits */
	60	SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
	61
	62	GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
	63	};
	64
	65	static int sis_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	66	static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
	67	static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	68
3b7d697d	69	static const struct pci_device_id sis_pci_tbl[] = {
54bb3a94 JG	70	{ PCI_VDEVICE(SI, 0x180), sis_180 },
	71	{ PCI_VDEVICE(SI, 0x181), sis_180 },
	72	{ PCI_VDEVICE(SI, 0x182), sis_180 },
2d2744fc	73
1da177e4 LT	74	{ } /* terminate list */
	75	};
	76
1da177e4 LT	77	static struct pci_driver sis_pci_driver = {
	78	.name = DRV_NAME,
	79	.id_table = sis_pci_tbl,
	80	.probe = sis_init_one,
	81	.remove = ata_pci_remove_one,
	82	};
	83
193515d5	84	static struct scsi_host_template sis_sht = {
1da177e4 LT	85	.module = THIS_MODULE,
	86	.name = DRV_NAME,
	87	.ioctl = ata_scsi_ioctl,
	88	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	89	.can_queue = ATA_DEF_QUEUE,
	90	.this_id = ATA_SHT_THIS_ID,
	91	.sg_tablesize = ATA_MAX_PRD,
1da177e4 LT	92	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	93	.emulated = ATA_SHT_EMULATED,
	94	.use_clustering = ATA_SHT_USE_CLUSTERING,
	95	.proc_name = DRV_NAME,
	96	.dma_boundary = ATA_DMA_BOUNDARY,
	97	.slave_configure = ata_scsi_slave_config,
ccf68c34	98	.slave_destroy = ata_scsi_slave_destroy,
1da177e4	99	.bios_param = ata_std_bios_param,
1da177e4 LT	100	};
1da177e4 LT	101
057ace5e	102	static const struct ata_port_operations sis_ops = {
1da177e4 LT	103	.port_disable = ata_port_disable,
	104	.tf_load = ata_tf_load,
	105	.tf_read = ata_tf_read,
	106	.check_status = ata_check_status,
	107	.exec_command = ata_exec_command,
	108	.dev_select = ata_std_dev_select,
1da177e4 LT	109	.bmdma_setup = ata_bmdma_setup,
	110	.bmdma_start = ata_bmdma_start,
	111	.bmdma_stop = ata_bmdma_stop,
	112	.bmdma_status = ata_bmdma_status,
	113	.qc_prep = ata_qc_prep,
	114	.qc_issue = ata_qc_issue_prot,
a6b2c5d4	115	.data_xfer = ata_pio_data_xfer,
d7a80dad TH	116	.freeze = ata_bmdma_freeze,
	117	.thaw = ata_bmdma_thaw,
	118	.error_handler = ata_bmdma_error_handler,
	119	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4 LT	120	.irq_handler = ata_interrupt,
	121	.irq_clear = ata_bmdma_irq_clear,
	122	.scr_read = sis_scr_read,
	123	.scr_write = sis_scr_write,
	124	.port_start = ata_port_start,
	125	.port_stop = ata_port_stop,
aa8f0dc6	126	.host_stop = ata_host_stop,
1da177e4 LT	127	};
	128
	129	static struct ata_port_info sis_port_info = {
	130	.sht = &sis_sht,
cca3974e	131	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
1da177e4 LT	132	.pio_mask = 0x1f,
	133	.mwdma_mask = 0x7,
	134	.udma_mask = 0x7f,
	135	.port_ops = &sis_ops,
	136	};
	137
	138
	139	MODULE_AUTHOR("Uwe Koziolek");
	140	MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
	141	MODULE_LICENSE("GPL");
	142	MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
	143	MODULE_VERSION(DRV_VERSION);
	144
f2c853bc	145	static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
1da177e4 LT	146	{
	147	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
	148
8add7885	149	if (port_no) {
f2c853bc AP	150	if (device == 0x182)
	151	addr += SIS182_SATA1_OFS;
	152	else
	153	addr += SIS180_SATA1_OFS;
8add7885 JG	154	}
8add7885 JG	155
1da177e4 LT	156	return addr;
	157	}
	158
	159	static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
	160	{
cca3974e	161	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
f2c853bc	162	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
668e4bc7	163	u32 val, val2 = 0;
f2c853bc	164	u8 pmr;
1da177e4 LT	165
	166	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
	167	return 0xffffffff;
f2c853bc AP	168
f2c853bc AP	169	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	170
1da177e4	171	pci_read_config_dword(pdev, cfg_addr, &val);
f2c853bc	172
8add7885	173	if ((pdev->device == 0x182) \|\| (pmr & SIS_PMR_COMBINED))
f2c853bc AP	174	pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
f2c853bc AP	175
4adccf6f	176	return (val\|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */
1da177e4 LT	177	}
	178
	179	static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
	180	{
cca3974e	181	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
f2c853bc AP	182	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
f2c853bc AP	183	u8 pmr;
1da177e4 LT	184
	185	if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
	186	return;
f2c853bc AP	187
f2c853bc AP	188	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	189
1da177e4	190	pci_write_config_dword(pdev, cfg_addr, val);
f2c853bc AP	191
	192	if ((pdev->device == 0x182) \|\| (pmr & SIS_PMR_COMBINED))
	193	pci_write_config_dword(pdev, cfg_addr+0x10, val);
1da177e4 LT	194	}
	195
	196	static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
	197	{
cca3974e	198	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
8add7885	199	u32 val, val2 = 0;
f2c853bc AP	200	u8 pmr;
f2c853bc AP	201
1da177e4 LT	202	if (sc_reg > SCR_CONTROL)
	203	return 0xffffffffU;
	204
	205	if (ap->flags & SIS_FLAG_CFGSCR)
	206	return sis_scr_cfg_read(ap, sc_reg);
f2c853bc AP	207
	208	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	209
	210	val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
	211
	212	if ((pdev->device == 0x182) \|\| (pmr & SIS_PMR_COMBINED))
8add7885	213	val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
f2c853bc	214
4adccf6f	215	return (val \| val2) & 0xfffffffb;
1da177e4 LT	216	}
	217
	218	static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	219	{
cca3974e	220	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
f2c853bc AP	221	u8 pmr;
f2c853bc AP	222
1da177e4 LT	223	if (sc_reg > SCR_CONTROL)
	224	return;
	225
f2c853bc	226	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	227
1da177e4 LT	228	if (ap->flags & SIS_FLAG_CFGSCR)
1da177e4 LT	229	sis_scr_cfg_write(ap, sc_reg, val);
f2c853bc	230	else {
1da177e4	231	outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
f2c853bc AP	232	if ((pdev->device == 0x182) \|\| (pmr & SIS_PMR_COMBINED))
	233	outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
	234	}
1da177e4 LT	235	}
1da177e4 LT	236
1da177e4 LT	237	static int sis_init_one (struct pci_dev pdev, const struct pci_device_id ent)
1da177e4 LT	238	{
a9524a76	239	static int printed_version;
1da177e4 LT	240	struct ata_probe_ent *probe_ent = NULL;
1da177e4 LT	241	int rc;
4adccf6f	242	u32 genctl, val;
cf0e812f	243	struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
1da177e4	244	int pci_dev_busy = 0;
f2c853bc AP	245	u8 pmr;
f2c853bc AP	246	u8 port2_start;
1da177e4	247
a9524a76 JG	248	if (!printed_version++)
	249	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
	250
1da177e4 LT	251	rc = pci_enable_device(pdev);
	252	if (rc)
	253	return rc;
	254
	255	rc = pci_request_regions(pdev, DRV_NAME);
	256	if (rc) {
	257	pci_dev_busy = 1;
	258	goto err_out;
	259	}
	260
	261	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	262	if (rc)
	263	goto err_out_regions;
	264	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	265	if (rc)
	266	goto err_out_regions;
	267
1da177e4 LT	268	/* check and see if the SCRs are in IO space or PCI cfg space */
	269	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	270	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
cf0e812f	271	pi.flags \|= SIS_FLAG_CFGSCR;
8a60a071	272
1da177e4 LT	273	/* if hardware thinks SCRs are in IO space, but there are
	274	* no IO resources assigned, change to PCI cfg space.
	275	*/
cf0e812f	276	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
1da177e4 LT	277	((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) \|\|
	278	(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
	279	genctl &= ~GENCTL_IOMAPPED_SCR;
	280	pci_write_config_dword(pdev, SIS_GENCTL, genctl);
cf0e812f	281	pi.flags \|= SIS_FLAG_CFGSCR;
1da177e4 LT	282	}
1da177e4 LT	283
f2c853bc AP	284	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	285	if (ent->device != 0x182) {
	286	if ((pmr & SIS_PMR_COMBINED) == 0) {
a9524a76	287	dev_printk(KERN_INFO, &pdev->dev,
4adccf6f	288	"Detected SiS 180/181/964 chipset in SATA mode\n");
39eb936c	289	port2_start = 64;
f2c853bc AP	290	}
f2c853bc AP	291	else {
a9524a76 JG	292	dev_printk(KERN_INFO, &pdev->dev,
a9524a76 JG	293	"Detected SiS 180/181 chipset in combined mode\n");
f2c853bc	294	port2_start=0;
4adccf6f	295	pi.flags \|= ATA_FLAG_SLAVE_POSS;
f2c853bc AP	296	}
	297	}
	298	else {
4adccf6f UK	299	pci_read_config_dword ( pdev, 0x6C, &val);
	300	if (val & (1L << 31)) {
	301	dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
	302	pi.flags \|= ATA_FLAG_SLAVE_POSS;
	303	}
	304	else
	305	dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
f2c853bc AP	306	port2_start = 0x20;
	307	}
	308
cf0e812f TH	309	probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY \| ATA_PORT_SECONDARY);
	310	if (!probe_ent) {
	311	rc = -ENOMEM;
	312	goto err_out_regions;
	313	}
	314
cca3974e	315	if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) {
1da177e4 LT	316	probe_ent->port[0].scr_addr =
	317	pci_resource_start(pdev, SIS_SCR_PCI_BAR);
	318	probe_ent->port[1].scr_addr =
f2c853bc	319	pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
1da177e4 LT	320	}
	321
	322	pci_set_master(pdev);
a04ce0ff	323	pci_intx(pdev, 1);
1da177e4 LT	324
	325	/* FIXME: check ata_device_add return value */
	326	ata_device_add(probe_ent);
	327	kfree(probe_ent);
	328
	329	return 0;
	330
	331	err_out_regions:
	332	pci_release_regions(pdev);
	333
	334	err_out:
	335	if (!pci_dev_busy)
	336	pci_disable_device(pdev);
	337	return rc;
	338
	339	}
	340
	341	static int __init sis_init(void)
	342	{
b7887196	343	return pci_register_driver(&sis_pci_driver);
1da177e4 LT	344	}
	345
	346	static void __exit sis_exit(void)
	347	{
	348	pci_unregister_driver(&sis_pci_driver);
	349	}
	350
	351	module_init(sis_init);
	352	module_exit(sis_exit);
	353