[net-next-2.6.git] / drivers / ata / sata_sis.c

/*
 *  sata_sis.c - Silicon Integrated Systems SATA
 *
 *  Maintained by:  Uwe Koziolek
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 Uwe Koziolek
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include "sis.h"

#define DRV_NAME	"sata_sis"
#define DRV_VERSION	"1.0"

enum {
	sis_180			= 0,
	SIS_SCR_PCI_BAR		= 5,

	/* PCI configuration registers */
	SIS_GENCTL		= 0x54, /* IDE General Control register */
	SIS_SCR_BASE		= 0xc0, /* sata0 phy SCR registers */
	SIS180_SATA1_OFS	= 0x10, /* offset from sata0->sata1 phy regs */
	SIS182_SATA1_OFS	= 0x20, /* offset from sata0->sata1 phy regs */
	SIS_PMR			= 0x90, /* port mapping register */
	SIS_PMR_COMBINED	= 0x30,

	/* random bits */
	SIS_FLAG_CFGSCR		= (1 << 30), /* host flag: SCRs via PCI cfg */

	GENCTL_IOMAPPED_SCR	= (1 << 26), /* if set, SCRs are in IO space */
};

static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);

static const struct pci_device_id sis_pci_tbl[] = {
	{ PCI_VDEVICE(SI, 0x0180), sis_180 },	/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0181), sis_180 },	/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0182), sis_180 },	/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x0183), sis_180 },	/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x1182), sis_180 },	/* SiS 966/680 */
	{ PCI_VDEVICE(SI, 0x1183), sis_180 },	/* SiS 966/966L/968/680 */

	{ }	/* terminate list */
};

static struct pci_driver sis_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sis_pci_tbl,
	.probe			= sis_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template sis_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations sis_ops = {
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,
	.mode_filter		= ata_pci_default_filter,
	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.scr_read		= sis_scr_read,
	.scr_write		= sis_scr_write,
	.port_start		= ata_sff_port_start,
};

static const struct ata_port_info sis_port_info = {
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x7,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &sis_ops,
};

MODULE_AUTHOR("Uwe Koziolek");
MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
	u8 pmr;

	if (ap->port_no)  {
		switch (pdev->device) {
		case 0x0180:
		case 0x0181:
			pci_read_config_byte(pdev, SIS_PMR, &pmr);
			if ((pmr & SIS_PMR_COMBINED) == 0)
				addr += SIS180_SATA1_OFS;
			break;

		case 0x0182:
		case 0x0183:
		case 0x1182:
			addr += SIS182_SATA1_OFS;
			break;
		}
	}
	return addr;
}

static u32 sis_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
	u32 val2 = 0;
	u8 pmr;

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return 0xffffffff;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	pci_read_config_dword(pdev, cfg_addr, val);

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
	    (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
		pci_read_config_dword(pdev, cfg_addr+0x10, &val2);

	*val |= val2;
	*val &= 0xfffffffb;	/* avoid problems with powerdowned ports */

	return 0;
}

static void sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
	u8 pmr;

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	pci_write_config_dword(pdev, cfg_addr, val);

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
	    (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
		pci_write_config_dword(pdev, cfg_addr+0x10, val);
}

static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 pmr;

	if (sc_reg > SCR_CONTROL)
		return -EINVAL;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_read(ap, sc_reg, val);

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	*val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
	    (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
		*val |= ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);

	*val &= 0xfffffffb;

	return 0;
}

static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 pmr;

	if (sc_reg > SCR_CONTROL)
		return -EINVAL;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	if (ap->flags & SIS_FLAG_CFGSCR)
		sis_scr_cfg_write(ap, sc_reg, val);
	else {
		iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
		if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
		    (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
			iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
	}
	return 0;
}

static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_port_info pi = sis_port_info;
	const struct ata_port_info *ppi[] = { &pi, &pi };
	struct ata_host *host;
	u32 genctl, val;
	u8 pmr;
	u8 port2_start = 0x20;
	int rc;

	if (!printed_version++)
		dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check and see if the SCRs are in IO space or PCI cfg space */
	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
		pi.flags |= SIS_FLAG_CFGSCR;

	/* if hardware thinks SCRs are in IO space, but there are
	 * no IO resources assigned, change to PCI cfg space.
	 */
	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
	    ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
	     (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
		genctl &= ~GENCTL_IOMAPPED_SCR;
		pci_write_config_dword(pdev, SIS_GENCTL, genctl);
		pi.flags |= SIS_FLAG_CFGSCR;
	}

	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	switch (ent->device) {
	case 0x0180:
	case 0x0181:

		/* The PATA-handling is provided by pata_sis */
		switch (pmr & 0x30) {
		case 0x10:
			ppi[1] = &sis_info133_for_sata;
			break;

		case 0x30:
			ppi[0] = &sis_info133_for_sata;
			break;
		}
		if ((pmr & SIS_PMR_COMBINED) == 0) {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 180/181/964 chipset in SATA mode\n");
			port2_start = 64;
		} else {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 180/181 chipset in combined mode\n");
			port2_start = 0;
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		}
		break;

	case 0x0182:
	case 0x0183:
		pci_read_config_dword(pdev, 0x6C, &val);
		if (val & (1L << 31)) {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 182/965 chipset\n");
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		} else {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 182/965L chipset\n");
		}
		break;

	case 0x1182:
		dev_printk(KERN_INFO, &pdev->dev,
			   "Detected SiS 1182/966/680 SATA controller\n");
		pi.flags |= ATA_FLAG_SLAVE_POSS;
		break;

	case 0x1183:
		dev_printk(KERN_INFO, &pdev->dev,
			   "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
		ppi[0] = &sis_info133_for_sata;
		ppi[1] = &sis_info133_for_sata;
		break;
	}

	rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
	if (rc)
		return rc;

	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
		void __iomem *mmio;

		rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
		if (rc)
			return rc;
		mmio = host->iomap[SIS_SCR_PCI_BAR];

		host->ports[0]->ioaddr.scr_addr = mmio;
		host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
	}

	pci_set_master(pdev);
	pci_intx(pdev, 1);
	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
				 &sis_sht);
}

static int __init sis_init(void)
{
	return pci_register_driver(&sis_pci_driver);
}

static void __exit sis_exit(void)
{
	pci_unregister_driver(&sis_pci_driver);
}

module_init(sis_init);
module_exit(sis_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sis.c - Silicon Integrated Systems SATA
	3	*
	4	* Maintained by: Uwe Koziolek
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 Uwe Koziolek
	9	*
af36d7f0 JG	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; see the file COPYING. If not, write to
	23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*
	25	*
	26	* libata documentation is available via 'make {ps\|pdf}docs',
	27	* as Documentation/DocBook/libata.*
	28	*
	29	* Hardware documentation available under NDA.
1da177e4 LT	30	*
	31	*/
	32
1da177e4 LT	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/pci.h>
	36	#include <linux/init.h>
	37	#include <linux/blkdev.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
a9524a76	40	#include <linux/device.h>
1da177e4 LT	41	#include <scsi/scsi_host.h>
1da177e4 LT	42	#include <linux/libata.h>
4bb64fb9	43	#include "sis.h"
1da177e4 LT	44
1da177e4 LT	45	#define DRV_NAME "sata_sis"
2a3103ce	46	#define DRV_VERSION "1.0"
1da177e4 LT	47
	48	enum {
	49	sis_180 = 0,
	50	SIS_SCR_PCI_BAR = 5,
	51
	52	/* PCI configuration registers */
	53	SIS_GENCTL = 0x54, /* IDE General Control register */
	54	SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
f2c853bc AP	55	SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
	56	SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
	57	SIS_PMR = 0x90, /* port mapping register */
8add7885	58	SIS_PMR_COMBINED = 0x30,
1da177e4 LT	59
	60	/* random bits */
	61	SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
	62
	63	GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
	64	};
	65
5796d1c4 JG	66	static int sis_init_one(struct pci_dev pdev, const struct pci_device_id ent);
	67	static int sis_scr_read(struct ata_port ap, unsigned int sc_reg, u32 val);
	68	static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
1da177e4	69
3b7d697d	70	static const struct pci_device_id sis_pci_tbl[] = {
5796d1c4 JG	71	{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
	72	{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
	73	{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
	74	{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
	75	{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
	76	{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
2d2744fc	77
1da177e4 LT	78	{ } /* terminate list */
	79	};
	80
1da177e4 LT	81	static struct pci_driver sis_pci_driver = {
	82	.name = DRV_NAME,
	83	.id_table = sis_pci_tbl,
	84	.probe = sis_init_one,
	85	.remove = ata_pci_remove_one,
	86	};
	87
193515d5	88	static struct scsi_host_template sis_sht = {
68d1d07b	89	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	90	};
1da177e4 LT	91
057ace5e	92	static const struct ata_port_operations sis_ops = {
1da177e4 LT	93	.tf_load = ata_tf_load,
	94	.tf_read = ata_tf_read,
	95	.check_status = ata_check_status,
	96	.exec_command = ata_exec_command,
	97	.dev_select = ata_std_dev_select,
1da177e4 LT	98	.bmdma_setup = ata_bmdma_setup,
	99	.bmdma_start = ata_bmdma_start,
	100	.bmdma_stop = ata_bmdma_stop,
	101	.bmdma_status = ata_bmdma_status,
	102	.qc_prep = ata_qc_prep,
	103	.qc_issue = ata_qc_issue_prot,
0d5ff566	104	.data_xfer = ata_data_xfer,
6bd99b4e	105	.mode_filter = ata_pci_default_filter,
d7a80dad TH	106	.freeze = ata_bmdma_freeze,
	107	.thaw = ata_bmdma_thaw,
	108	.error_handler = ata_bmdma_error_handler,
	109	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4	110	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	111	.irq_on = ata_irq_on,
1da177e4 LT	112	.scr_read = sis_scr_read,
1da177e4 LT	113	.scr_write = sis_scr_write,
6bd99b4e	114	.port_start = ata_sff_port_start,
1da177e4 LT	115	};
1da177e4 LT	116
1626aeb8	117	static const struct ata_port_info sis_port_info = {
cca3974e	118	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
1da177e4 LT	119	.pio_mask = 0x1f,
1da177e4 LT	120	.mwdma_mask = 0x7,
bf6263a8	121	.udma_mask = ATA_UDMA6,
1da177e4 LT	122	.port_ops = &sis_ops,
	123	};
	124
1da177e4 LT	125	MODULE_AUTHOR("Uwe Koziolek");
	126	MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
	127	MODULE_LICENSE("GPL");
	128	MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
	129	MODULE_VERSION(DRV_VERSION);
	130
9b14dec5	131	static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
1da177e4	132	{
9b14dec5	133	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4	134	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
9b14dec5	135	u8 pmr;
1da177e4	136
9b14dec5	137	if (ap->port_no) {
3f3e7313	138	switch (pdev->device) {
5796d1c4 JG	139	case 0x0180:
	140	case 0x0181:
	141	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	142	if ((pmr & SIS_PMR_COMBINED) == 0)
	143	addr += SIS180_SATA1_OFS;
	144	break;
	145
	146	case 0x0182:
	147	case 0x0183:
	148	case 0x1182:
	149	addr += SIS182_SATA1_OFS;
	150	break;
3f3e7313	151	}
8add7885	152	}
1da177e4 LT	153	return addr;
	154	}
	155
5796d1c4	156	static u32 sis_scr_cfg_read(struct ata_port ap, unsigned int sc_reg, u32 val)
1da177e4	157	{
cca3974e	158	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
9b14dec5	159	unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
aaa092a1	160	u32 val2 = 0;
f2c853bc	161	u8 pmr;
1da177e4 LT	162
	163	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
	164	return 0xffffffff;
f2c853bc AP	165
f2c853bc AP	166	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	167
aaa092a1	168	pci_read_config_dword(pdev, cfg_addr, val);
f2c853bc	169
a3cabb27 UK	170	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\|
a3cabb27 UK	171	(pdev->device == 0x1182) \|\| (pmr & SIS_PMR_COMBINED))
f2c853bc AP	172	pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
f2c853bc AP	173
aaa092a1 TH	174	*val \|= val2;
	175	val &= 0xfffffffb; / avoid problems with powerdowned ports */
	176
	177	return 0;
1da177e4 LT	178	}
1da177e4 LT	179
5796d1c4	180	static void sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4	181	{
cca3974e	182	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
9b14dec5	183	unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
f2c853bc	184	u8 pmr;
1da177e4	185
9b14dec5	186	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
1da177e4	187	return;
f2c853bc AP	188
f2c853bc AP	189	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	190
1da177e4	191	pci_write_config_dword(pdev, cfg_addr, val);
f2c853bc	192
a3cabb27 UK	193	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\|
a3cabb27 UK	194	(pdev->device == 0x1182) \|\| (pmr & SIS_PMR_COMBINED))
f2c853bc	195	pci_write_config_dword(pdev, cfg_addr+0x10, val);
1da177e4 LT	196	}
1da177e4 LT	197
da3dbb17	198	static int sis_scr_read(struct ata_port ap, unsigned int sc_reg, u32 val)
1da177e4	199	{
cca3974e	200	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
f2c853bc AP	201	u8 pmr;
f2c853bc AP	202
1da177e4	203	if (sc_reg > SCR_CONTROL)
da3dbb17	204	return -EINVAL;
1da177e4 LT	205
1da177e4 LT	206	if (ap->flags & SIS_FLAG_CFGSCR)
aaa092a1	207	return sis_scr_cfg_read(ap, sc_reg, val);
f2c853bc AP	208
	209	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	210
da3dbb17	211	val = ioread32(ap->ioaddr.scr_addr + (sc_reg 4));
f2c853bc	212
a3cabb27 UK	213	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\|
a3cabb27 UK	214	(pdev->device == 0x1182) \|\| (pmr & SIS_PMR_COMBINED))
da3dbb17 TH	215	val \|= ioread32(ap->ioaddr.scr_addr + (sc_reg 4) + 0x10);
	216
	217	*val &= 0xfffffffb;
f2c853bc	218
da3dbb17	219	return 0;
1da177e4 LT	220	}
1da177e4 LT	221
da3dbb17	222	static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4	223	{
cca3974e	224	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
f2c853bc AP	225	u8 pmr;
f2c853bc AP	226
1da177e4	227	if (sc_reg > SCR_CONTROL)
da3dbb17	228	return -EINVAL;
1da177e4	229
f2c853bc	230	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	231
1da177e4 LT	232	if (ap->flags & SIS_FLAG_CFGSCR)
1da177e4 LT	233	sis_scr_cfg_write(ap, sc_reg, val);
f2c853bc	234	else {
0d5ff566	235	iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
a3cabb27 UK	236	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\|
a3cabb27 UK	237	(pdev->device == 0x1182) \|\| (pmr & SIS_PMR_COMBINED))
0d5ff566	238	iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
f2c853bc	239	}
da3dbb17	240	return 0;
1da177e4 LT	241	}
1da177e4 LT	242
5796d1c4	243	static int sis_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	244	{
a9524a76	245	static int printed_version;
9a829ccf	246	struct ata_port_info pi = sis_port_info;
ddfc87a0	247	const struct ata_port_info *ppi[] = { &pi, &pi };
9a829ccf	248	struct ata_host *host;
4adccf6f	249	u32 genctl, val;
f2c853bc	250	u8 pmr;
3f3e7313	251	u8 port2_start = 0x20;
9a829ccf	252	int rc;
1da177e4	253
a9524a76 JG	254	if (!printed_version++)
	255	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
	256
24dc5f33	257	rc = pcim_enable_device(pdev);
1da177e4 LT	258	if (rc)
	259	return rc;
	260
1da177e4 LT	261	/* check and see if the SCRs are in IO space or PCI cfg space */
	262	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	263	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
cf0e812f	264	pi.flags \|= SIS_FLAG_CFGSCR;
8a60a071	265
1da177e4 LT	266	/* if hardware thinks SCRs are in IO space, but there are
	267	* no IO resources assigned, change to PCI cfg space.
	268	*/
cf0e812f	269	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
1da177e4 LT	270	((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) \|\|
	271	(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
	272	genctl &= ~GENCTL_IOMAPPED_SCR;
	273	pci_write_config_dword(pdev, SIS_GENCTL, genctl);
cf0e812f	274	pi.flags \|= SIS_FLAG_CFGSCR;
1da177e4 LT	275	}
1da177e4 LT	276
f2c853bc	277	pci_read_config_byte(pdev, SIS_PMR, &pmr);
3f3e7313 UK	278	switch (ent->device) {
	279	case 0x0180:
	280	case 0x0181:
9b14dec5 AC	281
	282	/* The PATA-handling is provided by pata_sis */
	283	switch (pmr & 0x30) {
	284	case 0x10:
a3cabb27	285	ppi[1] = &sis_info133_for_sata;
9b14dec5	286	break;
a84471fe	287
9b14dec5	288	case 0x30:
a3cabb27	289	ppi[0] = &sis_info133_for_sata;
9b14dec5 AC	290	break;
9b14dec5 AC	291	}
f2c853bc	292	if ((pmr & SIS_PMR_COMBINED) == 0) {
a9524a76	293	dev_printk(KERN_INFO, &pdev->dev,
4adccf6f	294	"Detected SiS 180/181/964 chipset in SATA mode\n");
39eb936c	295	port2_start = 64;
3f3e7313	296	} else {
a9524a76 JG	297	dev_printk(KERN_INFO, &pdev->dev,
a9524a76 JG	298	"Detected SiS 180/181 chipset in combined mode\n");
5796d1c4	299	port2_start = 0;
4adccf6f	300	pi.flags \|= ATA_FLAG_SLAVE_POSS;
f2c853bc	301	}
3f3e7313	302	break;
f20b16ff	303
3f3e7313 UK	304	case 0x0182:
3f3e7313 UK	305	case 0x0183:
5796d1c4	306	pci_read_config_dword(pdev, 0x6C, &val);
4adccf6f	307	if (val & (1L << 31)) {
5796d1c4 JG	308	dev_printk(KERN_INFO, &pdev->dev,
5796d1c4 JG	309	"Detected SiS 182/965 chipset\n");
4adccf6f	310	pi.flags \|= ATA_FLAG_SLAVE_POSS;
3f3e7313	311	} else {
5796d1c4 JG	312	dev_printk(KERN_INFO, &pdev->dev,
5796d1c4 JG	313	"Detected SiS 182/965L chipset\n");
3f3e7313 UK	314	}
	315	break;
	316
	317	case 0x1182:
5796d1c4 JG	318	dev_printk(KERN_INFO, &pdev->dev,
5796d1c4 JG	319	"Detected SiS 1182/966/680 SATA controller\n");
a3cabb27 UK	320	pi.flags \|= ATA_FLAG_SLAVE_POSS;
	321	break;
	322
3f3e7313	323	case 0x1183:
5796d1c4 JG	324	dev_printk(KERN_INFO, &pdev->dev,
5796d1c4 JG	325	"Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
a3cabb27 UK	326	ppi[0] = &sis_info133_for_sata;
a3cabb27 UK	327	ppi[1] = &sis_info133_for_sata;
3f3e7313	328	break;
f2c853bc AP	329	}
f2c853bc AP	330
d583bc18	331	rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
9a829ccf TH	332	if (rc)
9a829ccf TH	333	return rc;
cf0e812f	334
9a829ccf	335	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
edceec3d	336	void __iomem *mmio;
0d5ff566	337
9a829ccf TH	338	rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
	339	if (rc)
	340	return rc;
	341	mmio = host->iomap[SIS_SCR_PCI_BAR];
0d5ff566	342
9a829ccf TH	343	host->ports[0]->ioaddr.scr_addr = mmio;
9a829ccf TH	344	host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
1da177e4 LT	345	}
	346
	347	pci_set_master(pdev);
a04ce0ff	348	pci_intx(pdev, 1);
9a829ccf TH	349	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
9a829ccf TH	350	&sis_sht);
1da177e4 LT	351	}
	352
	353	static int __init sis_init(void)
	354	{
b7887196	355	return pci_register_driver(&sis_pci_driver);
1da177e4 LT	356	}
	357
	358	static void __exit sis_exit(void)
	359	{
	360	pci_unregister_driver(&sis_pci_driver);
	361	}
	362
	363	module_init(sis_init);
	364	module_exit(sis_exit);