[net-next-2.6.git] / drivers / ata / sata_sis.c

/*
 *  sata_sis.c - Silicon Integrated Systems SATA
 *
 *  Maintained by:  Uwe Koziolek
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 Uwe Koziolek
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include "sis.h"

#define DRV_NAME	"sata_sis"
#define DRV_VERSION	"1.0"

enum {
	sis_180			= 0,
	SIS_SCR_PCI_BAR		= 5,

	/* PCI configuration registers */
	SIS_GENCTL		= 0x54, /* IDE General Control register */
	SIS_SCR_BASE		= 0xc0, /* sata0 phy SCR registers */
	SIS180_SATA1_OFS	= 0x10, /* offset from sata0->sata1 phy regs */
	SIS182_SATA1_OFS	= 0x20, /* offset from sata0->sata1 phy regs */
	SIS_PMR			= 0x90, /* port mapping register */
	SIS_PMR_COMBINED	= 0x30,

	/* random bits */
	SIS_FLAG_CFGSCR		= (1 << 30), /* host flag: SCRs via PCI cfg */

	GENCTL_IOMAPPED_SCR	= (1 << 26), /* if set, SCRs are in IO space */
};

static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);

static const struct pci_device_id sis_pci_tbl[] = {
	{ PCI_VDEVICE(SI, 0x0180), sis_180 },	/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0181), sis_180 },	/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0182), sis_180 },	/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x0183), sis_180 },	/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x1182), sis_180 },	/* SiS 966/680 */
	{ PCI_VDEVICE(SI, 0x1183), sis_180 },	/* SiS 966/966L/968/680 */

	{ }	/* terminate list */
};

static struct pci_driver sis_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sis_pci_tbl,
	.probe			= sis_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template sis_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations sis_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.scr_read		= sis_scr_read,
	.scr_write		= sis_scr_write,
};

static const struct ata_port_info sis_port_info = {
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x7,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &sis_ops,
};

MODULE_AUTHOR("Uwe Koziolek");
MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
	u8 pmr;

	if (ap->port_no)  {
		switch (pdev->device) {
		case 0x0180:
		case 0x0181:
			pci_read_config_byte(pdev, SIS_PMR, &pmr);
			if ((pmr & SIS_PMR_COMBINED) == 0)
				addr += SIS180_SATA1_OFS;
			break;

		case 0x0182:
		case 0x0183:
		case 0x1182:
			addr += SIS182_SATA1_OFS;
			break;
		}
	}
	return addr;
}

static u32 sis_scr_cfg_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
	u32 val2 = 0;
	u8 pmr;

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return -EINVAL;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	pci_read_config_dword(pdev, cfg_addr, val);

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
	    (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
		pci_read_config_dword(pdev, cfg_addr+0x10, &val2);

	*val |= val2;
	*val &= 0xfffffffb;	/* avoid problems with powerdowned ports */

	return 0;
}

static int sis_scr_cfg_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
	u8 pmr;

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return -EINVAL;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	pci_write_config_dword(pdev, cfg_addr, val);

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
	    (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
		pci_write_config_dword(pdev, cfg_addr+0x10, val);

	return 0;
}

static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 pmr;

	if (sc_reg > SCR_CONTROL)
		return -EINVAL;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_read(link, sc_reg, val);

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	*val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
	    (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
		*val |= ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);

	*val &= 0xfffffffb;

	return 0;
}

static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 pmr;

	if (sc_reg > SCR_CONTROL)
		return -EINVAL;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_write(link, sc_reg, val);
	else {
		iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
		if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
		    (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
			iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
		return 0;
	}
}

static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_port_info pi = sis_port_info;
	const struct ata_port_info *ppi[] = { &pi, &pi };
	struct ata_host *host;
	u32 genctl, val;
	u8 pmr;
	u8 port2_start = 0x20;
	int rc;

	if (!printed_version++)
		dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check and see if the SCRs are in IO space or PCI cfg space */
	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
		pi.flags |= SIS_FLAG_CFGSCR;

	/* if hardware thinks SCRs are in IO space, but there are
	 * no IO resources assigned, change to PCI cfg space.
	 */
	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
	    ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
	     (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
		genctl &= ~GENCTL_IOMAPPED_SCR;
		pci_write_config_dword(pdev, SIS_GENCTL, genctl);
		pi.flags |= SIS_FLAG_CFGSCR;
	}

	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	switch (ent->device) {
	case 0x0180:
	case 0x0181:

		/* The PATA-handling is provided by pata_sis */
		switch (pmr & 0x30) {
		case 0x10:
			ppi[1] = &sis_info133_for_sata;
			break;

		case 0x30:
			ppi[0] = &sis_info133_for_sata;
			break;
		}
		if ((pmr & SIS_PMR_COMBINED) == 0) {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 180/181/964 chipset in SATA mode\n");
			port2_start = 64;
		} else {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 180/181 chipset in combined mode\n");
			port2_start = 0;
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		}
		break;

	case 0x0182:
	case 0x0183:
		pci_read_config_dword(pdev, 0x6C, &val);
		if (val & (1L << 31)) {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 182/965 chipset\n");
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		} else {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 182/965L chipset\n");
		}
		break;

	case 0x1182:
		dev_printk(KERN_INFO, &pdev->dev,
			   "Detected SiS 1182/966/680 SATA controller\n");
		pi.flags |= ATA_FLAG_SLAVE_POSS;
		break;

	case 0x1183:
		dev_printk(KERN_INFO, &pdev->dev,
			   "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
		ppi[0] = &sis_info133_for_sata;
		ppi[1] = &sis_info133_for_sata;
		break;
	}

	rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
	if (rc)
		return rc;

	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
		void __iomem *mmio;

		rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
		if (rc)
			return rc;
		mmio = host->iomap[SIS_SCR_PCI_BAR];

		host->ports[0]->ioaddr.scr_addr = mmio;
		host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
	}

	pci_set_master(pdev);
	pci_intx(pdev, 1);
	return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
				 IRQF_SHARED, &sis_sht);
}

static int __init sis_init(void)
{
	return pci_register_driver(&sis_pci_driver);
}

static void __exit sis_exit(void)
{
	pci_unregister_driver(&sis_pci_driver);
}

module_init(sis_init);
module_exit(sis_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sis.c - Silicon Integrated Systems SATA
	3	*
	4	* Maintained by: Uwe Koziolek
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 Uwe Koziolek
	9	*
af36d7f0 JG	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; see the file COPYING. If not, write to
	23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*
	25	*
	26	* libata documentation is available via 'make {ps\|pdf}docs',
	27	* as Documentation/DocBook/libata.*
	28	*
	29	* Hardware documentation available under NDA.
1da177e4 LT	30	*
	31	*/
	32
1da177e4 LT	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/pci.h>
	36	#include <linux/init.h>
	37	#include <linux/blkdev.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
a9524a76	40	#include <linux/device.h>
1da177e4 LT	41	#include <scsi/scsi_host.h>
1da177e4 LT	42	#include <linux/libata.h>
4bb64fb9	43	#include "sis.h"
1da177e4 LT	44
1da177e4 LT	45	#define DRV_NAME "sata_sis"
2a3103ce	46	#define DRV_VERSION "1.0"
1da177e4 LT	47
	48	enum {
	49	sis_180 = 0,
	50	SIS_SCR_PCI_BAR = 5,
	51
	52	/* PCI configuration registers */
	53	SIS_GENCTL = 0x54, /* IDE General Control register */
	54	SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
f2c853bc AP	55	SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
	56	SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
	57	SIS_PMR = 0x90, /* port mapping register */
8add7885	58	SIS_PMR_COMBINED = 0x30,
1da177e4 LT	59
	60	/* random bits */
	61	SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
	62
	63	GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
	64	};
	65
5796d1c4	66	static int sis_init_one(struct pci_dev pdev, const struct pci_device_id ent);
82ef04fb TH	67	static int sis_scr_read(struct ata_link link, unsigned int sc_reg, u32 val);
82ef04fb TH	68	static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
1da177e4	69
3b7d697d	70	static const struct pci_device_id sis_pci_tbl[] = {
5796d1c4 JG	71	{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
	72	{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
	73	{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
	74	{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
	75	{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
	76	{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
2d2744fc	77
1da177e4 LT	78	{ } /* terminate list */
	79	};
	80
1da177e4 LT	81	static struct pci_driver sis_pci_driver = {
	82	.name = DRV_NAME,
	83	.id_table = sis_pci_tbl,
	84	.probe = sis_init_one,
	85	.remove = ata_pci_remove_one,
	86	};
	87
193515d5	88	static struct scsi_host_template sis_sht = {
68d1d07b	89	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	90	};
1da177e4 LT	91
029cfd6b TH	92	static struct ata_port_operations sis_ops = {
029cfd6b TH	93	.inherits = &ata_bmdma_port_ops,
1da177e4 LT	94	.scr_read = sis_scr_read,
1da177e4 LT	95	.scr_write = sis_scr_write,
1da177e4 LT	96	};
1da177e4 LT	97
1626aeb8	98	static const struct ata_port_info sis_port_info = {
cca3974e	99	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
1da177e4 LT	100	.pio_mask = 0x1f,
1da177e4 LT	101	.mwdma_mask = 0x7,
bf6263a8	102	.udma_mask = ATA_UDMA6,
1da177e4 LT	103	.port_ops = &sis_ops,
	104	};
	105
1da177e4 LT	106	MODULE_AUTHOR("Uwe Koziolek");
	107	MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
	108	MODULE_LICENSE("GPL");
	109	MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
	110	MODULE_VERSION(DRV_VERSION);
	111
9b14dec5	112	static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
1da177e4	113	{
9b14dec5	114	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4	115	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
9b14dec5	116	u8 pmr;
1da177e4	117
9b14dec5	118	if (ap->port_no) {
3f3e7313	119	switch (pdev->device) {
5796d1c4 JG	120	case 0x0180:
	121	case 0x0181:
	122	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	123	if ((pmr & SIS_PMR_COMBINED) == 0)
	124	addr += SIS180_SATA1_OFS;
	125	break;
	126
	127	case 0x0182:
	128	case 0x0183:
	129	case 0x1182:
	130	addr += SIS182_SATA1_OFS;
	131	break;
3f3e7313	132	}
8add7885	133	}
1da177e4 LT	134	return addr;
	135	}
	136
82ef04fb TH	137	static u32 sis_scr_cfg_read(struct ata_link *link,
82ef04fb TH	138	unsigned int sc_reg, u32 *val)
1da177e4	139	{
82ef04fb TH	140	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
82ef04fb TH	141	unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
aaa092a1	142	u32 val2 = 0;
f2c853bc	143	u8 pmr;
1da177e4 LT	144
1da177e4 LT	145	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
8e5443a0	146	return -EINVAL;
f2c853bc AP	147
f2c853bc AP	148	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	149
aaa092a1	150	pci_read_config_dword(pdev, cfg_addr, val);
f2c853bc	151
a3cabb27 UK	152	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\|
a3cabb27 UK	153	(pdev->device == 0x1182) \|\| (pmr & SIS_PMR_COMBINED))
f2c853bc AP	154	pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
f2c853bc AP	155
aaa092a1 TH	156	*val \|= val2;
	157	val &= 0xfffffffb; / avoid problems with powerdowned ports */
	158
	159	return 0;
1da177e4 LT	160	}
1da177e4 LT	161
82ef04fb TH	162	static int sis_scr_cfg_write(struct ata_link *link,
82ef04fb TH	163	unsigned int sc_reg, u32 val)
1da177e4	164	{
82ef04fb TH	165	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
82ef04fb TH	166	unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
f2c853bc	167	u8 pmr;
1da177e4	168
9b14dec5	169	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
8e5443a0	170	return -EINVAL;
f2c853bc AP	171
f2c853bc AP	172	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	173
1da177e4	174	pci_write_config_dword(pdev, cfg_addr, val);
f2c853bc	175
a3cabb27 UK	176	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\|
a3cabb27 UK	177	(pdev->device == 0x1182) \|\| (pmr & SIS_PMR_COMBINED))
f2c853bc	178	pci_write_config_dword(pdev, cfg_addr+0x10, val);
8e5443a0 TH	179
8e5443a0 TH	180	return 0;
1da177e4 LT	181	}
1da177e4 LT	182
82ef04fb	183	static int sis_scr_read(struct ata_link link, unsigned int sc_reg, u32 val)
1da177e4	184	{
82ef04fb	185	struct ata_port *ap = link->ap;
cca3974e	186	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
f2c853bc AP	187	u8 pmr;
f2c853bc AP	188
1da177e4	189	if (sc_reg > SCR_CONTROL)
da3dbb17	190	return -EINVAL;
1da177e4 LT	191
1da177e4 LT	192	if (ap->flags & SIS_FLAG_CFGSCR)
82ef04fb	193	return sis_scr_cfg_read(link, sc_reg, val);
f2c853bc AP	194
	195	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	196
da3dbb17	197	val = ioread32(ap->ioaddr.scr_addr + (sc_reg 4));
f2c853bc	198
a3cabb27 UK	199	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\|
a3cabb27 UK	200	(pdev->device == 0x1182) \|\| (pmr & SIS_PMR_COMBINED))
da3dbb17 TH	201	val \|= ioread32(ap->ioaddr.scr_addr + (sc_reg 4) + 0x10);
	202
	203	*val &= 0xfffffffb;
f2c853bc	204
da3dbb17	205	return 0;
1da177e4 LT	206	}
1da177e4 LT	207
82ef04fb	208	static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
1da177e4	209	{
82ef04fb	210	struct ata_port *ap = link->ap;
cca3974e	211	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
f2c853bc AP	212	u8 pmr;
f2c853bc AP	213
1da177e4	214	if (sc_reg > SCR_CONTROL)
da3dbb17	215	return -EINVAL;
1da177e4	216
f2c853bc	217	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	218
1da177e4	219	if (ap->flags & SIS_FLAG_CFGSCR)
82ef04fb	220	return sis_scr_cfg_write(link, sc_reg, val);
f2c853bc	221	else {
0d5ff566	222	iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
a3cabb27 UK	223	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\|
a3cabb27 UK	224	(pdev->device == 0x1182) \|\| (pmr & SIS_PMR_COMBINED))
0d5ff566	225	iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
8e5443a0	226	return 0;
f2c853bc	227	}
1da177e4 LT	228	}
1da177e4 LT	229
5796d1c4	230	static int sis_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	231	{
a9524a76	232	static int printed_version;
9a829ccf	233	struct ata_port_info pi = sis_port_info;
ddfc87a0	234	const struct ata_port_info *ppi[] = { &pi, &pi };
9a829ccf	235	struct ata_host *host;
4adccf6f	236	u32 genctl, val;
f2c853bc	237	u8 pmr;
3f3e7313	238	u8 port2_start = 0x20;
9a829ccf	239	int rc;
1da177e4	240
a9524a76 JG	241	if (!printed_version++)
	242	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
	243
24dc5f33	244	rc = pcim_enable_device(pdev);
1da177e4 LT	245	if (rc)
	246	return rc;
	247
1da177e4 LT	248	/* check and see if the SCRs are in IO space or PCI cfg space */
	249	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	250	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
cf0e812f	251	pi.flags \|= SIS_FLAG_CFGSCR;
8a60a071	252
1da177e4 LT	253	/* if hardware thinks SCRs are in IO space, but there are
	254	* no IO resources assigned, change to PCI cfg space.
	255	*/
cf0e812f	256	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
1da177e4 LT	257	((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) \|\|
	258	(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
	259	genctl &= ~GENCTL_IOMAPPED_SCR;
	260	pci_write_config_dword(pdev, SIS_GENCTL, genctl);
cf0e812f	261	pi.flags \|= SIS_FLAG_CFGSCR;
1da177e4 LT	262	}
1da177e4 LT	263
f2c853bc	264	pci_read_config_byte(pdev, SIS_PMR, &pmr);
3f3e7313 UK	265	switch (ent->device) {
	266	case 0x0180:
	267	case 0x0181:
9b14dec5 AC	268
	269	/* The PATA-handling is provided by pata_sis */
	270	switch (pmr & 0x30) {
	271	case 0x10:
a3cabb27	272	ppi[1] = &sis_info133_for_sata;
9b14dec5	273	break;
a84471fe	274
9b14dec5	275	case 0x30:
a3cabb27	276	ppi[0] = &sis_info133_for_sata;
9b14dec5 AC	277	break;
9b14dec5 AC	278	}
f2c853bc	279	if ((pmr & SIS_PMR_COMBINED) == 0) {
a9524a76	280	dev_printk(KERN_INFO, &pdev->dev,
4adccf6f	281	"Detected SiS 180/181/964 chipset in SATA mode\n");
39eb936c	282	port2_start = 64;
3f3e7313	283	} else {
a9524a76 JG	284	dev_printk(KERN_INFO, &pdev->dev,
a9524a76 JG	285	"Detected SiS 180/181 chipset in combined mode\n");
5796d1c4	286	port2_start = 0;
4adccf6f	287	pi.flags \|= ATA_FLAG_SLAVE_POSS;
f2c853bc	288	}
3f3e7313	289	break;
f20b16ff	290
3f3e7313 UK	291	case 0x0182:
3f3e7313 UK	292	case 0x0183:
5796d1c4	293	pci_read_config_dword(pdev, 0x6C, &val);
4adccf6f	294	if (val & (1L << 31)) {
5796d1c4 JG	295	dev_printk(KERN_INFO, &pdev->dev,
5796d1c4 JG	296	"Detected SiS 182/965 chipset\n");
4adccf6f	297	pi.flags \|= ATA_FLAG_SLAVE_POSS;
3f3e7313	298	} else {
5796d1c4 JG	299	dev_printk(KERN_INFO, &pdev->dev,
5796d1c4 JG	300	"Detected SiS 182/965L chipset\n");
3f3e7313 UK	301	}
	302	break;
	303
	304	case 0x1182:
5796d1c4 JG	305	dev_printk(KERN_INFO, &pdev->dev,
5796d1c4 JG	306	"Detected SiS 1182/966/680 SATA controller\n");
a3cabb27 UK	307	pi.flags \|= ATA_FLAG_SLAVE_POSS;
	308	break;
	309
3f3e7313	310	case 0x1183:
5796d1c4 JG	311	dev_printk(KERN_INFO, &pdev->dev,
5796d1c4 JG	312	"Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
a3cabb27 UK	313	ppi[0] = &sis_info133_for_sata;
a3cabb27 UK	314	ppi[1] = &sis_info133_for_sata;
3f3e7313	315	break;
f2c853bc AP	316	}
f2c853bc AP	317
9363c382	318	rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
9a829ccf TH	319	if (rc)
9a829ccf TH	320	return rc;
cf0e812f	321
9a829ccf	322	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
edceec3d	323	void __iomem *mmio;
0d5ff566	324
9a829ccf TH	325	rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
	326	if (rc)
	327	return rc;
	328	mmio = host->iomap[SIS_SCR_PCI_BAR];
0d5ff566	329
9a829ccf TH	330	host->ports[0]->ioaddr.scr_addr = mmio;
9a829ccf TH	331	host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
1da177e4 LT	332	}
	333
	334	pci_set_master(pdev);
a04ce0ff	335	pci_intx(pdev, 1);
9363c382 TH	336	return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
9363c382 TH	337	IRQF_SHARED, &sis_sht);
1da177e4 LT	338	}
	339
	340	static int __init sis_init(void)
	341	{
b7887196	342	return pci_register_driver(&sis_pci_driver);
1da177e4 LT	343	}
	344
	345	static void __exit sis_exit(void)
	346	{
	347	pci_unregister_driver(&sis_pci_driver);
	348	}
	349
	350	module_init(sis_init);
	351	module_exit(sis_exit);