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libata-pmp-prep: implement sata_async_notification()
[net-next-2.6.git] / drivers / ata / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
edb33667
TH		 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
a9524a76 27#include <linux/device.h>
edb33667 28#include <scsi/scsi_host.h>
193515d5 29#include <scsi/scsi_cmnd.h>
edb33667 30#include <linux/libata.h>
edb33667
TH		 31
32#define DRV_NAME "sata_sil24"
2a3103ce 33#define DRV_VERSION "1.0"
edb33667 34
edb33667
TH		 35/*
36 * Port request block (PRB) 32 bytes
37 */
38struct sil24_prb {
b4772574
AD		 39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
edb33667
TH		 42 u8 fis[6 * 4];
43};
44
45/*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48struct sil24_sge {
b4772574
AD		 49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
edb33667
TH		 52};
53
54/*
55 * Port multiplier
56 */
57struct sil24_port_multiplier {
b4772574
AD		 58 __le32 diag;
59 __le32 sactive;
edb33667
TH		 60};
61
62enum {
0d5ff566
TH		 63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
edb33667
TH		 66 /*
67 * Global controller registers (128 bytes @ BAR0)
68 */
69 /* 32 bit regs */
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
71 HOST_CTRL = 0x40,
72 HOST_IRQ_STAT = 0x44,
73 HOST_PHY_CFG = 0x48,
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
79 /* 8 bit regs */
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
84 HOST_I2C_DATA = 0x7c,
85 HOST_I2C_XFER_CNT = 0x7e,
86 HOST_I2C_CTRL = 0x7f,
87
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
90
7dafc3fd
TH		 91 /* HOST_CTRL bits */
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
d2298dca 97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
7dafc3fd 98
edb33667
TH		 99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
135da345 104
28c8f3b4 105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
135da345 106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
edb33667 107
28c8f3b4 108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
c0c55908
TH		 109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112
edb33667 113 /* 32 bit regs */
83bbecc9
TH		 114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
124 /* 16 bit regs */
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
131 /* 32 bit regs */
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
c0c55908 135 PORT_CONTEXT = 0x1e04,
edb33667
TH		 136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
142
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
28c8f3b4 149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
e382eb1d 150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
28c8f3b4 151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
e382eb1d 152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 153
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
7dafc3fd
TH		 162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
3b9f1d0f 167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
edb33667 168
88ce7550 169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
0542925b 170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
854c73a2 171 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
88ce7550 172
edb33667
TH		 173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
177
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
181
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
64008802 202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
edb33667 203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 205
d10cb35a
TH		 206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
212
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
220
edb33667
TH		 221 /*
222 * Other constants
223 */
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
edb33667 229
aee10a03
TH		 230 SIL24_MAX_CMDS = 31,
231
edb33667
TH		 232 /* board id */
233 BID_SIL3124 = 0,
234 BID_SIL3132 = 1,
042c21fd 235 BID_SIL3131 = 2,
edb33667 236
9466d85b
TH		 237 /* host flags */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
aee10a03 239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
854c73a2
TH		 240 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
241 ATA_FLAG_AN,
0c88758b 242 SIL24_COMMON_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY,
37024e8e 243 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
9466d85b 244
edb33667
TH		 245 IRQ_STAT_4PORTS = 0xf,
246};
247
69ad185f 248struct sil24_ata_block {
edb33667
TH		 249 struct sil24_prb prb;
250 struct sil24_sge sge[LIBATA_MAX_PRD];
251};
252
69ad185f
TH		 253struct sil24_atapi_block {
254 struct sil24_prb prb;
255 u8 cdb[16];
256 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
257};
258
259union sil24_cmd_block {
260 struct sil24_ata_block ata;
261 struct sil24_atapi_block atapi;
262};
263
88ce7550
TH		 264static struct sil24_cerr_info {
265 unsigned int err_mask, action;
266 const char *desc;
267} sil24_cerr_db[] = {
268 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
269 "device error" },
270 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
271 "device error via D2H FIS" },
272 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
273 "device error via SDB FIS" },
274 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
275 "error in data FIS" },
276 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
277 "failed to transmit command FIS" },
278 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "protocol mismatch" },
280 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "data directon mismatch" },
282 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "ran out of SGEs while writing" },
284 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
285 "ran out of SGEs while reading" },
286 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
287 "invalid data directon for ATAPI CDB" },
288 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
289 "SGT no on qword boundary" },
290 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI target abort while fetching SGT" },
292 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI master abort while fetching SGT" },
294 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
295 "PCI parity error while fetching SGT" },
296 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
297 "PRB not on qword boundary" },
298 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI target abort while fetching PRB" },
300 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI master abort while fetching PRB" },
302 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "PCI parity error while fetching PRB" },
304 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "undefined error while transferring data" },
306 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI target abort while transferring data" },
308 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
309 "PCI master abort while transferring data" },
310 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
311 "PCI parity error while transferring data" },
312 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
313 "FIS received while sending service FIS" },
314};
315
edb33667
TH		 316/*
317 * ap->private_data
318 *
319 * The preview driver always returned 0 for status. We emulate it
320 * here from the previous interrupt.
321 */
322struct sil24_port_priv {
69ad185f 323 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
edb33667 324 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 325 struct ata_taskfile tf; /* Cached taskfile registers */
edb33667
TH		 326};
327
cd0d3bbc 328static void sil24_dev_config(struct ata_device *dev);
edb33667 329static u8 sil24_check_status(struct ata_port *ap);
da3dbb17
TH		 330static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
331static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 332static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
edb33667 333static void sil24_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0 334static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
edb33667 335static void sil24_irq_clear(struct ata_port *ap);
88ce7550
TH		 336static void sil24_freeze(struct ata_port *ap);
337static void sil24_thaw(struct ata_port *ap);
338static void sil24_error_handler(struct ata_port *ap);
339static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
edb33667 340static int sil24_port_start(struct ata_port *ap);
edb33667 341static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
281d426c 342#ifdef CONFIG_PM
d2298dca 343static int sil24_pci_device_resume(struct pci_dev *pdev);
281d426c 344#endif
edb33667 345
3b7d697d 346static const struct pci_device_id sil24_pci_tbl[] = {
54bb3a94
JG		 347 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
348 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
349 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
722d67b6 350 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
54bb3a94
JG		 351 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
352 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
353
1fcce839 354 { } /* terminate list */
edb33667
TH		 355};
356
357static struct pci_driver sil24_pci_driver = {
358 .name = DRV_NAME,
359 .id_table = sil24_pci_tbl,
360 .probe = sil24_init_one,
24dc5f33 361 .remove = ata_pci_remove_one,
281d426c 362#ifdef CONFIG_PM
d2298dca
TH		 363 .suspend = ata_pci_device_suspend,
364 .resume = sil24_pci_device_resume,
281d426c 365#endif
edb33667
TH		 366};
367
193515d5 368static struct scsi_host_template sil24_sht = {
edb33667
TH		 369 .module = THIS_MODULE,
370 .name = DRV_NAME,
371 .ioctl = ata_scsi_ioctl,
372 .queuecommand = ata_scsi_queuecmd,
aee10a03
TH		 373 .change_queue_depth = ata_scsi_change_queue_depth,
374 .can_queue = SIL24_MAX_CMDS,
edb33667
TH		 375 .this_id = ATA_SHT_THIS_ID,
376 .sg_tablesize = LIBATA_MAX_PRD,
edb33667
TH		 377 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
378 .emulated = ATA_SHT_EMULATED,
379 .use_clustering = ATA_SHT_USE_CLUSTERING,
380 .proc_name = DRV_NAME,
381 .dma_boundary = ATA_DMA_BOUNDARY,
382 .slave_configure = ata_scsi_slave_config,
ccf68c34 383 .slave_destroy = ata_scsi_slave_destroy,
edb33667 384 .bios_param = ata_std_bios_param,
edb33667
TH		 385};
386
057ace5e 387static const struct ata_port_operations sil24_ops = {
69ad185f
TH		 388 .dev_config = sil24_dev_config,
389
edb33667
TH		 390 .check_status = sil24_check_status,
391 .check_altstatus = sil24_check_status,
edb33667
TH		 392 .dev_select = ata_noop_dev_select,
393
7f726d12
TH		 394 .tf_read = sil24_tf_read,
395
31cc23b3 396 .qc_defer = ata_std_qc_defer,
edb33667
TH		 397 .qc_prep = sil24_qc_prep,
398 .qc_issue = sil24_qc_issue,
399
edb33667
TH		 400 .irq_clear = sil24_irq_clear,
401
402 .scr_read = sil24_scr_read,
403 .scr_write = sil24_scr_write,
404
88ce7550
TH		 405 .freeze = sil24_freeze,
406 .thaw = sil24_thaw,
407 .error_handler = sil24_error_handler,
408 .post_internal_cmd = sil24_post_internal_cmd,
409
edb33667 410 .port_start = sil24_port_start,
edb33667
TH		 411};
412
042c21fd 413/*
cca3974e 414 * Use bits 30-31 of port_flags to encode available port numbers.
042c21fd
TH		 415 * Current maxium is 4.
416 */
417#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
418#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
419
4447d351 420static const struct ata_port_info sil24_port_info[] = {
edb33667
TH		 421 /* sil_3124 */
422 {
cca3974e 423 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
37024e8e 424 SIL24_FLAG_PCIX_IRQ_WOC,
0c88758b 425 .link_flags = SIL24_COMMON_LFLAGS,
edb33667
TH		 426 .pio_mask = 0x1f, /* pio0-4 */
427 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 428 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 429 .port_ops = &sil24_ops,
430 },
2e9edbf8 431 /* sil_3132 */
edb33667 432 {
cca3974e 433 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
0c88758b 434 .link_flags = SIL24_COMMON_LFLAGS,
042c21fd
TH		 435 .pio_mask = 0x1f, /* pio0-4 */
436 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 437 .udma_mask = ATA_UDMA5, /* udma0-5 */
042c21fd
TH		 438 .port_ops = &sil24_ops,
439 },
440 /* sil_3131/sil_3531 */
441 {
cca3974e 442 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
0c88758b 443 .link_flags = SIL24_COMMON_LFLAGS,
edb33667
TH		 444 .pio_mask = 0x1f, /* pio0-4 */
445 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 446 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 447 .port_ops = &sil24_ops,
448 },
449};
450
aee10a03
TH		 451static int sil24_tag(int tag)
452{
453 if (unlikely(ata_tag_internal(tag)))
454 return 0;
455 return tag;
456}
457
cd0d3bbc 458static void sil24_dev_config(struct ata_device *dev)
69ad185f 459{
9af5c9c9 460 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
69ad185f 461
6e7846e9 462 if (dev->cdb_len == 16)
69ad185f
TH		 463 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
464 else
465 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
466}
467
e59f0dad 468static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
6a575fa9 469{
0d5ff566 470 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 471 struct sil24_prb __iomem *prb;
4b4a5eae 472 u8 fis[6 * 4];
6a575fa9 473
e59f0dad
TH		 474 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
475 memcpy_fromio(fis, prb->fis, sizeof(fis));
476 ata_tf_from_fis(fis, tf);
6a575fa9
TH		 477}
478
edb33667
TH		 479static u8 sil24_check_status(struct ata_port *ap)
480{
6a575fa9
TH		 481 struct sil24_port_priv *pp = ap->private_data;
482 return pp->tf.command;
edb33667
TH		 483}
484
edb33667
TH		 485static int sil24_scr_map[] = {
486 [SCR_CONTROL] = 0,
487 [SCR_STATUS] = 1,
488 [SCR_ERROR] = 2,
489 [SCR_ACTIVE] = 3,
490};
491
da3dbb17 492static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
edb33667 493{
0d5ff566 494 void __iomem *scr_addr = ap->ioaddr.scr_addr;
da3dbb17 495
edb33667 496 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 497 void __iomem *addr;
edb33667 498 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
da3dbb17
TH		 499 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
500 return 0;
edb33667 501 }
da3dbb17 502 return -EINVAL;
edb33667
TH		 503}
504
da3dbb17 505static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
edb33667 506{
0d5ff566 507 void __iomem *scr_addr = ap->ioaddr.scr_addr;
da3dbb17 508
edb33667 509 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 510 void __iomem *addr;
edb33667
TH		 511 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
512 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
da3dbb17 513 return 0;
edb33667 514 }
da3dbb17 515 return -EINVAL;
edb33667
TH		 516}
517
7f726d12
TH		 518static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
519{
520 struct sil24_port_priv *pp = ap->private_data;
521 *tf = pp->tf;
522}
523
b5bc421c
TH		 524static int sil24_init_port(struct ata_port *ap)
525{
0d5ff566 526 void __iomem *port = ap->ioaddr.cmd_addr;
b5bc421c
TH		 527 u32 tmp;
528
529 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
530 ata_wait_register(port + PORT_CTRL_STAT,
531 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
532 tmp = ata_wait_register(port + PORT_CTRL_STAT,
533 PORT_CS_RDY, 0, 10, 100);
534
535 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
536 return -EIO;
537 return 0;
538}
539
37b99cba
TH		 540static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
541 const struct ata_taskfile *tf,
542 int is_cmd, u32 ctrl,
543 unsigned long timeout_msec)
edb33667 544{
0d5ff566 545 void __iomem *port = ap->ioaddr.cmd_addr;
ca45160d 546 struct sil24_port_priv *pp = ap->private_data;
69ad185f 547 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
ca45160d 548 dma_addr_t paddr = pp->cmd_block_dma;
37b99cba
TH		 549 u32 irq_enabled, irq_mask, irq_stat;
550 int rc;
551
552 prb->ctrl = cpu_to_le16(ctrl);
553 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
554
555 /* temporarily plug completion and error interrupts */
556 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
557 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
558
559 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
560 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
561
562 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
563 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
564 10, timeout_msec);
565
566 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
567 irq_stat >>= PORT_IRQ_RAW_SHIFT;
568
569 if (irq_stat & PORT_IRQ_COMPLETE)
570 rc = 0;
571 else {
572 /* force port into known state */
573 sil24_init_port(ap);
574
575 if (irq_stat & PORT_IRQ_ERROR)
576 rc = -EIO;
577 else
578 rc = -EBUSY;
579 }
580
581 /* restore IRQ enabled */
582 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
583
584 return rc;
585}
586
cc0680a5 587static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
975530e8 588 int pmp, unsigned long deadline)
37b99cba 589{
cc0680a5 590 struct ata_port *ap = link->ap;
37b99cba 591 unsigned long timeout_msec = 0;
e59f0dad 592 struct ata_taskfile tf;
643be977 593 const char *reason;
37b99cba 594 int rc;
ca45160d 595
07b73470
TH		 596 DPRINTK("ENTER\n");
597
cc0680a5 598 if (ata_link_offline(link)) {
10d996ad
TH		 599 DPRINTK("PHY reports no device\n");
600 *class = ATA_DEV_NONE;
601 goto out;
602 }
603
2555d6c2
TH		 604 /* put the port into known state */
605 if (sil24_init_port(ap)) {
606 reason ="port not ready";
607 goto err;
608 }
609
0eaa6058 610 /* do SRST */
37b99cba
TH		 611 if (time_after(deadline, jiffies))
612 timeout_msec = jiffies_to_msecs(deadline - jiffies);
ca45160d 613
cc0680a5 614 ata_tf_init(link->device, &tf); /* doesn't really matter */
975530e8
TH		 615 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
616 timeout_msec);
37b99cba
TH		 617 if (rc == -EBUSY) {
618 reason = "timeout";
619 goto err;
620 } else if (rc) {
621 reason = "SRST command error";
643be977 622 goto err;
07b73470 623 }
10d996ad 624
e59f0dad
TH		 625 sil24_read_tf(ap, 0, &tf);
626 *class = ata_dev_classify(&tf);
10d996ad 627
07b73470
TH		 628 if (*class == ATA_DEV_UNKNOWN)
629 *class = ATA_DEV_NONE;
ca45160d 630
10d996ad 631 out:
07b73470 632 DPRINTK("EXIT, class=%u\n", *class);
ca45160d 633 return 0;
643be977
TH		 634
635 err:
cc0680a5 636 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
643be977 637 return -EIO;
ca45160d
TH		 638}
639
cc0680a5 640static int sil24_softreset(struct ata_link *link, unsigned int *class,
975530e8
TH		 641 unsigned long deadline)
642{
cc0680a5 643 return sil24_do_softreset(link, class, 0, deadline);
975530e8
TH		 644}
645
cc0680a5 646static int sil24_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 647 unsigned long deadline)
489ff4c7 648{
cc0680a5 649 struct ata_port *ap = link->ap;
0d5ff566 650 void __iomem *port = ap->ioaddr.cmd_addr;
ecc2e2b9 651 const char *reason;
e8e008e7 652 int tout_msec, rc;
ecc2e2b9
TH		 653 u32 tmp;
654
655 /* sil24 does the right thing(tm) without any protection */
cc0680a5 656 sata_set_spd(link);
ecc2e2b9
TH		 657
658 tout_msec = 100;
cc0680a5 659 if (ata_link_online(link))
ecc2e2b9
TH		 660 tout_msec = 5000;
661
662 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
663 tmp = ata_wait_register(port + PORT_CTRL_STAT,
664 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
665
e8e008e7
TH		 666 /* SStatus oscillates between zero and valid status after
667 * DEV_RST, debounce it.
ecc2e2b9 668 */
cc0680a5 669 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
e8e008e7
TH		 670 if (rc) {
671 reason = "PHY debouncing failed";
672 goto err;
673 }
ecc2e2b9
TH		 674
675 if (tmp & PORT_CS_DEV_RST) {
cc0680a5 676 if (ata_link_offline(link))
ecc2e2b9
TH		 677 return 0;
678 reason = "link not ready";
679 goto err;
680 }
681
e8e008e7
TH		 682 /* Sil24 doesn't store signature FIS after hardreset, so we
683 * can't wait for BSY to clear. Some devices take a long time
684 * to get ready and those devices will choke if we don't wait
685 * for BSY clearance here. Tell libata to perform follow-up
686 * softreset.
ecc2e2b9 687 */
e8e008e7 688 return -EAGAIN;
ecc2e2b9
TH		 689
690 err:
cc0680a5 691 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
ecc2e2b9 692 return -EIO;
489ff4c7
TH		 693}
694
edb33667 695static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
69ad185f 696 struct sil24_sge *sge)
edb33667 697{
972c26bd 698 struct scatterlist *sg;
edb33667 699
972c26bd 700 ata_for_each_sg(sg, qc) {
edb33667
TH		 701 sge->addr = cpu_to_le64(sg_dma_address(sg));
702 sge->cnt = cpu_to_le32(sg_dma_len(sg));
972c26bd
JG		 703 if (ata_sg_is_last(sg, qc))
704 sge->flags = cpu_to_le32(SGE_TRM);
705 else
706 sge->flags = 0;
972c26bd 707 sge++;
edb33667
TH		 708 }
709}
710
711static void sil24_qc_prep(struct ata_queued_cmd *qc)
712{
713 struct ata_port *ap = qc->ap;
714 struct sil24_port_priv *pp = ap->private_data;
aee10a03 715 union sil24_cmd_block *cb;
69ad185f
TH		 716 struct sil24_prb *prb;
717 struct sil24_sge *sge;
bad28a37 718 u16 ctrl = 0;
edb33667 719
aee10a03
TH		 720 cb = &pp->cmd_block[sil24_tag(qc->tag)];
721
edb33667
TH		 722 switch (qc->tf.protocol) {
723 case ATA_PROT_PIO:
724 case ATA_PROT_DMA:
aee10a03 725 case ATA_PROT_NCQ:
edb33667 726 case ATA_PROT_NODATA:
69ad185f
TH		 727 prb = &cb->ata.prb;
728 sge = cb->ata.sge;
edb33667 729 break;
69ad185f
TH		 730
731 case ATA_PROT_ATAPI:
732 case ATA_PROT_ATAPI_DMA:
733 case ATA_PROT_ATAPI_NODATA:
734 prb = &cb->atapi.prb;
735 sge = cb->atapi.sge;
736 memset(cb->atapi.cdb, 0, 32);
6e7846e9 737 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
69ad185f
TH		 738
739 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
740 if (qc->tf.flags & ATA_TFLAG_WRITE)
bad28a37 741 ctrl = PRB_CTRL_PACKET_WRITE;
69ad185f 742 else
bad28a37
TH		 743 ctrl = PRB_CTRL_PACKET_READ;
744 }
69ad185f
TH		 745 break;
746
edb33667 747 default:
69ad185f
TH		 748 prb = NULL; /* shut up, gcc */
749 sge = NULL;
edb33667
TH		 750 BUG();
751 }
752
bad28a37 753 prb->ctrl = cpu_to_le16(ctrl);
9977126c 754 ata_tf_to_fis(&qc->tf, 0, 1, prb->fis);
edb33667
TH		 755
756 if (qc->flags & ATA_QCFLAG_DMAMAP)
69ad185f 757 sil24_fill_sg(qc, sge);
edb33667
TH		 758}
759
9a3d9eb0 760static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
edb33667
TH		 761{
762 struct ata_port *ap = qc->ap;
763 struct sil24_port_priv *pp = ap->private_data;
0d5ff566 764 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 765 unsigned int tag = sil24_tag(qc->tag);
766 dma_addr_t paddr;
767 void __iomem *activate;
edb33667 768
aee10a03
TH		 769 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
770 activate = port + PORT_CMD_ACTIVATE + tag * 8;
771
772 writel((u32)paddr, activate);
773 writel((u64)paddr >> 32, activate + 4);
26ec634c 774
edb33667
TH		 775 return 0;
776}
777
778static void sil24_irq_clear(struct ata_port *ap)
779{
780 /* unused */
781}
782
88ce7550 783static void sil24_freeze(struct ata_port *ap)
7d1ce682 784{
0d5ff566 785 void __iomem *port = ap->ioaddr.cmd_addr;
7d1ce682 786
88ce7550
TH		 787 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
788 * PORT_IRQ_ENABLE instead.
789 */
790 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
7d1ce682
TH		 791}
792
88ce7550 793static void sil24_thaw(struct ata_port *ap)
edb33667 794{
0d5ff566 795 void __iomem *port = ap->ioaddr.cmd_addr;
edb33667
TH		 796 u32 tmp;
797
88ce7550
TH		 798 /* clear IRQ */
799 tmp = readl(port + PORT_IRQ_STAT);
800 writel(tmp, port + PORT_IRQ_STAT);
edb33667 801
88ce7550
TH		 802 /* turn IRQ back on */
803 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
edb33667
TH		 804}
805
88ce7550 806static void sil24_error_intr(struct ata_port *ap)
8746618d 807{
0d5ff566 808 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 809 struct sil24_port_priv *pp = ap->private_data;
9af5c9c9 810 struct ata_eh_info *ehi = &ap->link.eh_info;
88ce7550
TH		 811 int freeze = 0;
812 u32 irq_stat;
8746618d 813
88ce7550 814 /* on error, we need to clear IRQ explicitly */
8746618d 815 irq_stat = readl(port + PORT_IRQ_STAT);
88ce7550 816 writel(irq_stat, port + PORT_IRQ_STAT);
ad6e90f6 817
88ce7550
TH		 818 /* first, analyze and record host port events */
819 ata_ehi_clear_desc(ehi);
ad6e90f6 820
88ce7550 821 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
8746618d 822
854c73a2 823 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
854c73a2 824 ata_ehi_push_desc(ehi, "SDB notify");
7d77b247 825 sata_async_notification(ap);
854c73a2
TH		 826 }
827
0542925b
TH		 828 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
829 ata_ehi_hotplugged(ehi);
b64bbc39
TH		 830 ata_ehi_push_desc(ehi, "%s",
831 irq_stat & PORT_IRQ_PHYRDY_CHG ?
832 "PHY RDY changed" : "device exchanged");
88ce7550 833 freeze = 1;
6a575fa9
TH		 834 }
835
88ce7550
TH		 836 if (irq_stat & PORT_IRQ_UNK_FIS) {
837 ehi->err_mask |= AC_ERR_HSM;
838 ehi->action |= ATA_EH_SOFTRESET;
b64bbc39 839 ata_ehi_push_desc(ehi, "unknown FIS");
88ce7550
TH		 840 freeze = 1;
841 }
842
843 /* deal with command error */
844 if (irq_stat & PORT_IRQ_ERROR) {
845 struct sil24_cerr_info *ci = NULL;
846 unsigned int err_mask = 0, action = 0;
847 struct ata_queued_cmd *qc;
848 u32 cerr;
849
850 /* analyze CMD_ERR */
851 cerr = readl(port + PORT_CMD_ERR);
852 if (cerr < ARRAY_SIZE(sil24_cerr_db))
853 ci = &sil24_cerr_db[cerr];
854
855 if (ci && ci->desc) {
856 err_mask |= ci->err_mask;
857 action |= ci->action;
b64bbc39 858 ata_ehi_push_desc(ehi, "%s", ci->desc);
88ce7550
TH		 859 } else {
860 err_mask |= AC_ERR_OTHER;
861 action |= ATA_EH_SOFTRESET;
b64bbc39 862 ata_ehi_push_desc(ehi, "unknown command error %d",
88ce7550
TH		 863 cerr);
864 }
865
866 /* record error info */
9af5c9c9 867 qc = ata_qc_from_tag(ap, ap->link.active_tag);
88ce7550 868 if (qc) {
e59f0dad 869 sil24_read_tf(ap, qc->tag, &pp->tf);
88ce7550
TH		 870 qc->err_mask |= err_mask;
871 } else
872 ehi->err_mask |= err_mask;
873
874 ehi->action |= action;
a22e2eb0 875 }
88ce7550
TH		 876
877 /* freeze or abort */
878 if (freeze)
879 ata_port_freeze(ap);
880 else
881 ata_port_abort(ap);
8746618d
TH		 882}
883
aee10a03
TH		 884static void sil24_finish_qc(struct ata_queued_cmd *qc)
885{
e59f0dad
TH		 886 struct ata_port *ap = qc->ap;
887 struct sil24_port_priv *pp = ap->private_data;
888
aee10a03 889 if (qc->flags & ATA_QCFLAG_RESULT_TF)
e59f0dad 890 sil24_read_tf(ap, qc->tag, &pp->tf);
aee10a03
TH		 891}
892
edb33667
TH		 893static inline void sil24_host_intr(struct ata_port *ap)
894{
0d5ff566 895 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 896 u32 slot_stat, qc_active;
897 int rc;
edb33667 898
228f47b9
TH		 899 /* If PCIX_IRQ_WOC, there's an inherent race window between
900 * clearing IRQ pending status and reading PORT_SLOT_STAT
901 * which may cause spurious interrupts afterwards. This is
902 * unavoidable and much better than losing interrupts which
903 * happens if IRQ pending is cleared after reading
904 * PORT_SLOT_STAT.
905 */
906 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
907 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
908
edb33667 909 slot_stat = readl(port + PORT_SLOT_STAT);
37024e8e 910
88ce7550
TH		 911 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
912 sil24_error_intr(ap);
913 return;
914 }
915
aee10a03
TH		 916 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
917 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
918 if (rc > 0)
919 return;
920 if (rc < 0) {
9af5c9c9 921 struct ata_eh_info *ehi = &ap->link.eh_info;
aee10a03
TH		 922 ehi->err_mask |= AC_ERR_HSM;
923 ehi->action |= ATA_EH_SOFTRESET;
924 ata_port_freeze(ap);
88ce7550
TH		 925 return;
926 }
927
228f47b9
TH		 928 /* spurious interrupts are expected if PCIX_IRQ_WOC */
929 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
88ce7550 930 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
aee10a03 931 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
9af5c9c9 932 slot_stat, ap->link.active_tag, ap->link.sactive);
edb33667
TH		 933}
934
7d12e780 935static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
edb33667 936{
cca3974e 937 struct ata_host *host = dev_instance;
0d5ff566 938 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
edb33667
TH		 939 unsigned handled = 0;
940 u32 status;
941 int i;
942
0d5ff566 943 status = readl(host_base + HOST_IRQ_STAT);
edb33667 944
06460aea
TH		 945 if (status == 0xffffffff) {
946 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
947 "PCI fault or device removal?\n");
948 goto out;
949 }
950
edb33667
TH		 951 if (!(status & IRQ_STAT_4PORTS))
952 goto out;
953
cca3974e 954 spin_lock(&host->lock);
edb33667 955
cca3974e 956 for (i = 0; i < host->n_ports; i++)
edb33667 957 if (status & (1 << i)) {
cca3974e 958 struct ata_port *ap = host->ports[i];
198e0fed 959 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
825cd6dd 960 sil24_host_intr(ap);
3cc4571c
TH		 961 handled++;
962 } else
963 printk(KERN_ERR DRV_NAME
964 ": interrupt from disabled port %d\n", i);
edb33667
TH		 965 }
966
cca3974e 967 spin_unlock(&host->lock);
edb33667
TH		 968 out:
969 return IRQ_RETVAL(handled);
970}
971
88ce7550
TH		 972static void sil24_error_handler(struct ata_port *ap)
973{
9af5c9c9 974 struct ata_eh_context *ehc = &ap->link.eh_context;
88ce7550
TH		 975
976 if (sil24_init_port(ap)) {
977 ata_eh_freeze_port(ap);
978 ehc->i.action |= ATA_EH_HARDRESET;
979 }
980
981 /* perform recovery */
f5914a46
TH		 982 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
983 ata_std_postreset);
88ce7550
TH		 984}
985
986static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
987{
988 struct ata_port *ap = qc->ap;
989
88ce7550 990 /* make DMA engine forget about the failed command */
a51d644a 991 if (qc->flags & ATA_QCFLAG_FAILED)
88ce7550
TH		 992 sil24_init_port(ap);
993}
994
edb33667
TH		 995static int sil24_port_start(struct ata_port *ap)
996{
cca3974e 997 struct device *dev = ap->host->dev;
edb33667 998 struct sil24_port_priv *pp;
69ad185f 999 union sil24_cmd_block *cb;
aee10a03 1000 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
edb33667 1001 dma_addr_t cb_dma;
24dc5f33 1002 int rc;
edb33667 1003
24dc5f33 1004 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
edb33667 1005 if (!pp)
24dc5f33 1006 return -ENOMEM;
edb33667 1007
6a575fa9
TH		 1008 pp->tf.command = ATA_DRDY;
1009
24dc5f33 1010 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb 1011 if (!cb)
24dc5f33 1012 return -ENOMEM;
edb33667
TH		 1013 memset(cb, 0, cb_size);
1014
6037d6bb
JG		 1015 rc = ata_pad_alloc(ap, dev);
1016 if (rc)
24dc5f33 1017 return rc;
6037d6bb 1018
edb33667
TH		 1019 pp->cmd_block = cb;
1020 pp->cmd_block_dma = cb_dma;
1021
1022 ap->private_data = pp;
1023
1024 return 0;
edb33667
TH		 1025}
1026
4447d351 1027static void sil24_init_controller(struct ata_host *host)
2a41a610 1028{
4447d351
TH		 1029 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1030 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
2a41a610
TH		 1031 u32 tmp;
1032 int i;
1033
1034 /* GPIO off */
1035 writel(0, host_base + HOST_FLASH_CMD);
1036
1037 /* clear global reset & mask interrupts during initialization */
1038 writel(0, host_base + HOST_CTRL);
1039
1040 /* init ports */
4447d351 1041 for (i = 0; i < host->n_ports; i++) {
2a41a610
TH		 1042 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1043
1044 /* Initial PHY setting */
1045 writel(0x20c, port + PORT_PHY_CFG);
1046
1047 /* Clear port RST */
1048 tmp = readl(port + PORT_CTRL_STAT);
1049 if (tmp & PORT_CS_PORT_RST) {
1050 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1051 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1052 PORT_CS_PORT_RST,
1053 PORT_CS_PORT_RST, 10, 100);
1054 if (tmp & PORT_CS_PORT_RST)
4447d351 1055 dev_printk(KERN_ERR, host->dev,
2a41a610
TH		 1056 "failed to clear port RST\n");
1057 }
1058
1059 /* Configure IRQ WoC */
4447d351 1060 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
2a41a610
TH		 1061 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1062 else
1063 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1064
1065 /* Zero error counters. */
1066 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1067 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1068 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1069 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1070 writel(0x0000, port + PORT_CRC_ERR_CNT);
1071 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1072
1073 /* Always use 64bit activation */
1074 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1075
1076 /* Clear port multiplier enable and resume bits */
28c8f3b4
TH		 1077 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1078 port + PORT_CTRL_CLR);
2a41a610
TH		 1079 }
1080
1081 /* Turn on interrupts */
1082 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1083}
1084
edb33667
TH		 1085static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1086{
1087 static int printed_version = 0;
4447d351
TH		 1088 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1089 const struct ata_port_info *ppi[] = { &pi, NULL };
1090 void __iomem * const *iomap;
1091 struct ata_host *host;
edb33667 1092 int i, rc;
37024e8e 1093 u32 tmp;
edb33667
TH		 1094
1095 if (!printed_version++)
a9524a76 1096 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667 1097
4447d351 1098 /* acquire resources */
24dc5f33 1099 rc = pcim_enable_device(pdev);
edb33667
TH		 1100 if (rc)
1101 return rc;
1102
0d5ff566
TH		 1103 rc = pcim_iomap_regions(pdev,
1104 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1105 DRV_NAME);
edb33667 1106 if (rc)
24dc5f33 1107 return rc;
4447d351 1108 iomap = pcim_iomap_table(pdev);
edb33667 1109
4447d351
TH		 1110 /* apply workaround for completion IRQ loss on PCI-X errata */
1111 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1112 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1113 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1114 dev_printk(KERN_INFO, &pdev->dev,
1115 "Applying completion IRQ loss on PCI-X "
1116 "errata fix\n");
1117 else
1118 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1119 }
edb33667 1120
4447d351
TH		 1121 /* allocate and fill host */
1122 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1123 SIL24_FLAG2NPORTS(ppi[0]->flags));
1124 if (!host)
1125 return -ENOMEM;
1126 host->iomap = iomap;
edb33667 1127
4447d351 1128 for (i = 0; i < host->n_ports; i++) {
cbcdd875
TH		 1129 struct ata_port *ap = host->ports[i];
1130 size_t offset = ap->port_no * PORT_REGS_SIZE;
1131 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
edb33667 1132
4447d351
TH		 1133 host->ports[i]->ioaddr.cmd_addr = port;
1134 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
edb33667 1135
cbcdd875
TH		 1136 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1137 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
4447d351 1138 }
edb33667 1139
4447d351 1140 /* configure and activate the device */
26ec634c
TH		 1141 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1142 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1143 if (rc) {
1144 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1145 if (rc) {
1146 dev_printk(KERN_ERR, &pdev->dev,
1147 "64-bit DMA enable failed\n");
24dc5f33 1148 return rc;
26ec634c
TH		 1149 }
1150 }
1151 } else {
1152 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1153 if (rc) {
1154 dev_printk(KERN_ERR, &pdev->dev,
1155 "32-bit DMA enable failed\n");
24dc5f33 1156 return rc;
26ec634c
TH		 1157 }
1158 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1159 if (rc) {
1160 dev_printk(KERN_ERR, &pdev->dev,
1161 "32-bit consistent DMA enable failed\n");
24dc5f33 1162 return rc;
26ec634c 1163 }
edb33667
TH		 1164 }
1165
4447d351 1166 sil24_init_controller(host);
edb33667
TH		 1167
1168 pci_set_master(pdev);
4447d351
TH		 1169 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1170 &sil24_sht);
edb33667
TH		 1171}
1172
281d426c 1173#ifdef CONFIG_PM
d2298dca
TH		 1174static int sil24_pci_device_resume(struct pci_dev *pdev)
1175{
cca3974e 1176 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1177 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
553c4aa6 1178 int rc;
d2298dca 1179
553c4aa6
TH		 1180 rc = ata_pci_device_do_resume(pdev);
1181 if (rc)
1182 return rc;
d2298dca
TH		 1183
1184 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
0d5ff566 1185 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
d2298dca 1186
4447d351 1187 sil24_init_controller(host);
d2298dca 1188
cca3974e 1189 ata_host_resume(host);
d2298dca
TH		 1190
1191 return 0;
1192}
281d426c 1193#endif
d2298dca 1194
edb33667
TH		 1195static int __init sil24_init(void)
1196{
b7887196 1197 return pci_register_driver(&sil24_pci_driver);
edb33667
TH		 1198}
1199
1200static void __exit sil24_exit(void)
1201{
1202 pci_unregister_driver(&sil24_pci_driver);
1203}
1204
1205MODULE_AUTHOR("Tejun Heo");
1206MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1207MODULE_LICENSE("GPL");
1208MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1209
1210module_init(sil24_init);
1211module_exit(sil24_exit);
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