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libata: add qc_fill_rtf port operation
[net-next-2.6.git] / drivers / ata / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
edb33667
TH		 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
a9524a76 27#include <linux/device.h>
edb33667 28#include <scsi/scsi_host.h>
193515d5 29#include <scsi/scsi_cmnd.h>
edb33667 30#include <linux/libata.h>
edb33667
TH		 31
32#define DRV_NAME "sata_sil24"
3454dc69 33#define DRV_VERSION "1.1"
edb33667 34
edb33667
TH		 35/*
36 * Port request block (PRB) 32 bytes
37 */
38struct sil24_prb {
b4772574
AD		 39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
edb33667
TH		 42 u8 fis[6 * 4];
43};
44
45/*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48struct sil24_sge {
b4772574
AD		 49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
edb33667
TH		 52};
53
54/*
55 * Port multiplier
56 */
57struct sil24_port_multiplier {
b4772574
AD		 58 __le32 diag;
59 __le32 sactive;
edb33667
TH		 60};
61
62enum {
0d5ff566
TH		 63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
93e2618e
TH		 66 /* sil24 fetches in chunks of 64bytes. The first block
67 * contains the PRB and two SGEs. From the second block, it's
68 * consisted of four SGEs and called SGT. Calculate the
69 * number of SGTs that fit into one page.
70 */
71 SIL24_PRB_SZ = sizeof(struct sil24_prb)
72 + 2 * sizeof(struct sil24_sge),
73 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
74 / (4 * sizeof(struct sil24_sge)),
75
76 /* This will give us one unused SGEs for ATA. This extra SGE
77 * will be used to store CDB for ATAPI devices.
78 */
79 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
80
edb33667
TH		 81 /*
82 * Global controller registers (128 bytes @ BAR0)
83 */
84 /* 32 bit regs */
85 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
86 HOST_CTRL = 0x40,
87 HOST_IRQ_STAT = 0x44,
88 HOST_PHY_CFG = 0x48,
89 HOST_BIST_CTRL = 0x50,
90 HOST_BIST_PTRN = 0x54,
91 HOST_BIST_STAT = 0x58,
92 HOST_MEM_BIST_STAT = 0x5c,
93 HOST_FLASH_CMD = 0x70,
94 /* 8 bit regs */
95 HOST_FLASH_DATA = 0x74,
96 HOST_TRANSITION_DETECT = 0x75,
97 HOST_GPIO_CTRL = 0x76,
98 HOST_I2C_ADDR = 0x78, /* 32 bit */
99 HOST_I2C_DATA = 0x7c,
100 HOST_I2C_XFER_CNT = 0x7e,
101 HOST_I2C_CTRL = 0x7f,
102
103 /* HOST_SLOT_STAT bits */
104 HOST_SSTAT_ATTN = (1 << 31),
105
7dafc3fd
TH		 106 /* HOST_CTRL bits */
107 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
108 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
109 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
110 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
111 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
d2298dca 112 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
7dafc3fd 113
edb33667
TH		 114 /*
115 * Port registers
116 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
117 */
118 PORT_REGS_SIZE = 0x2000,
135da345 119
28c8f3b4 120 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
135da345 121 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
edb33667 122
28c8f3b4 123 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
c0c55908
TH		 124 PORT_PMP_STATUS = 0x0000, /* port device status offset */
125 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
126 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
127
edb33667 128 /* 32 bit regs */
83bbecc9
TH		 129 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
130 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
131 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
132 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
133 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 134 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 135 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
136 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 137 PORT_FIS_CFG = 0x1028,
138 PORT_FIFO_THRES = 0x102c,
139 /* 16 bit regs */
140 PORT_DECODE_ERR_CNT = 0x1040,
141 PORT_DECODE_ERR_THRESH = 0x1042,
142 PORT_CRC_ERR_CNT = 0x1044,
143 PORT_CRC_ERR_THRESH = 0x1046,
144 PORT_HSHK_ERR_CNT = 0x1048,
145 PORT_HSHK_ERR_THRESH = 0x104a,
146 /* 32 bit regs */
147 PORT_PHY_CFG = 0x1050,
148 PORT_SLOT_STAT = 0x1800,
149 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
c0c55908 150 PORT_CONTEXT = 0x1e04,
edb33667
TH		 151 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
152 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
153 PORT_SCONTROL = 0x1f00,
154 PORT_SSTATUS = 0x1f04,
155 PORT_SERROR = 0x1f08,
156 PORT_SACTIVE = 0x1f0c,
157
158 /* PORT_CTRL_STAT bits */
159 PORT_CS_PORT_RST = (1 << 0), /* port reset */
160 PORT_CS_DEV_RST = (1 << 1), /* device reset */
161 PORT_CS_INIT = (1 << 2), /* port initialize */
162 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 163 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
28c8f3b4 164 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
e382eb1d 165 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
28c8f3b4 166 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
e382eb1d 167 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 168
169 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
170 /* bits[11:0] are masked */
171 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
172 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
173 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
174 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
175 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
176 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
7dafc3fd
TH		 177 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
178 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
179 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
180 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
181 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
3b9f1d0f 182 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
edb33667 183
88ce7550 184 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
0542925b 185 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
854c73a2 186 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
88ce7550 187
edb33667
TH		 188 /* bits[27:16] are unmasked (raw) */
189 PORT_IRQ_RAW_SHIFT = 16,
190 PORT_IRQ_MASKED_MASK = 0x7ff,
191 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
192
193 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
194 PORT_IRQ_STEER_SHIFT = 30,
195 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
196
197 /* PORT_CMD_ERR constants */
198 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
199 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
200 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
201 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
202 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
203 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
204 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
205 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
206 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
207 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
208 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
209 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
210 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
211 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
212 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
213 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
214 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
215 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
216 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
64008802 217 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
edb33667 218 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 219 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 220
d10cb35a
TH		 221 /* bits of PRB control field */
222 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
223 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
224 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
225 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
226 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
227
228 /* PRB protocol field */
229 PRB_PROT_PACKET = (1 << 0),
230 PRB_PROT_TCQ = (1 << 1),
231 PRB_PROT_NCQ = (1 << 2),
232 PRB_PROT_READ = (1 << 3),
233 PRB_PROT_WRITE = (1 << 4),
234 PRB_PROT_TRANSPARENT = (1 << 5),
235
edb33667
TH		 236 /*
237 * Other constants
238 */
239 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 240 SGE_LNK = (1 << 30), /* linked list
241 Points to SGT, not SGE */
242 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
243 data address ignored */
edb33667 244
aee10a03
TH		 245 SIL24_MAX_CMDS = 31,
246
edb33667
TH		 247 /* board id */
248 BID_SIL3124 = 0,
249 BID_SIL3132 = 1,
042c21fd 250 BID_SIL3131 = 2,
edb33667 251
9466d85b
TH		 252 /* host flags */
253 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
aee10a03 254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
854c73a2 255 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
3454dc69 256 ATA_FLAG_AN | ATA_FLAG_PMP,
37024e8e 257 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
9466d85b 258
edb33667
TH		 259 IRQ_STAT_4PORTS = 0xf,
260};
261
69ad185f 262struct sil24_ata_block {
edb33667 263 struct sil24_prb prb;
93e2618e 264 struct sil24_sge sge[SIL24_MAX_SGE];
edb33667
TH		 265};
266
69ad185f
TH		 267struct sil24_atapi_block {
268 struct sil24_prb prb;
269 u8 cdb[16];
93e2618e 270 struct sil24_sge sge[SIL24_MAX_SGE];
69ad185f
TH		 271};
272
273union sil24_cmd_block {
274 struct sil24_ata_block ata;
275 struct sil24_atapi_block atapi;
276};
277
88ce7550
TH		 278static struct sil24_cerr_info {
279 unsigned int err_mask, action;
280 const char *desc;
281} sil24_cerr_db[] = {
f90f0828 282 [0] = { AC_ERR_DEV, 0,
88ce7550 283 "device error" },
f90f0828 284 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
88ce7550 285 "device error via D2H FIS" },
f90f0828 286 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
88ce7550 287 "device error via SDB FIS" },
cf480626 288 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
88ce7550 289 "error in data FIS" },
cf480626 290 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
88ce7550 291 "failed to transmit command FIS" },
cf480626 292 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 293 "protocol mismatch" },
cf480626 294 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 295 "data directon mismatch" },
cf480626 296 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 297 "ran out of SGEs while writing" },
cf480626 298 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 299 "ran out of SGEs while reading" },
cf480626 300 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 301 "invalid data directon for ATAPI CDB" },
cf480626 302 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
7293fa8f 303 "SGT not on qword boundary" },
cf480626 304 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 305 "PCI target abort while fetching SGT" },
cf480626 306 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 307 "PCI master abort while fetching SGT" },
cf480626 308 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 309 "PCI parity error while fetching SGT" },
cf480626 310 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
88ce7550 311 "PRB not on qword boundary" },
cf480626 312 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 313 "PCI target abort while fetching PRB" },
cf480626 314 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 315 "PCI master abort while fetching PRB" },
cf480626 316 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 317 "PCI parity error while fetching PRB" },
cf480626 318 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 319 "undefined error while transferring data" },
cf480626 320 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 321 "PCI target abort while transferring data" },
cf480626 322 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 323 "PCI master abort while transferring data" },
cf480626 324 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 325 "PCI parity error while transferring data" },
cf480626 326 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550
TH		 327 "FIS received while sending service FIS" },
328};
329
edb33667
TH		 330/*
331 * ap->private_data
332 *
333 * The preview driver always returned 0 for status. We emulate it
334 * here from the previous interrupt.
335 */
336struct sil24_port_priv {
69ad185f 337 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
edb33667 338 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 339 struct ata_taskfile tf; /* Cached taskfile registers */
23818034 340 int do_port_rst;
edb33667
TH		 341};
342
cd0d3bbc 343static void sil24_dev_config(struct ata_device *dev);
edb33667 344static u8 sil24_check_status(struct ata_port *ap);
da3dbb17
TH		 345static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
346static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 347static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
3454dc69 348static int sil24_qc_defer(struct ata_queued_cmd *qc);
edb33667 349static void sil24_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0 350static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
3454dc69
TH		 351static void sil24_pmp_attach(struct ata_port *ap);
352static void sil24_pmp_detach(struct ata_port *ap);
88ce7550
TH		 353static void sil24_freeze(struct ata_port *ap);
354static void sil24_thaw(struct ata_port *ap);
a1efdaba
TH		 355static int sil24_softreset(struct ata_link *link, unsigned int *class,
356 unsigned long deadline);
357static int sil24_hardreset(struct ata_link *link, unsigned int *class,
358 unsigned long deadline);
359static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
360 unsigned long deadline);
361static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
362 unsigned long deadline);
88ce7550
TH		 363static void sil24_error_handler(struct ata_port *ap);
364static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
edb33667 365static int sil24_port_start(struct ata_port *ap);
edb33667 366static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
281d426c 367#ifdef CONFIG_PM
d2298dca 368static int sil24_pci_device_resume(struct pci_dev *pdev);
3454dc69 369static int sil24_port_resume(struct ata_port *ap);
281d426c 370#endif
edb33667 371
3b7d697d 372static const struct pci_device_id sil24_pci_tbl[] = {
54bb3a94
JG		 373 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
374 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
375 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
722d67b6 376 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
54bb3a94
JG		 377 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
378 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
379
1fcce839 380 { } /* terminate list */
edb33667
TH		 381};
382
383static struct pci_driver sil24_pci_driver = {
384 .name = DRV_NAME,
385 .id_table = sil24_pci_tbl,
386 .probe = sil24_init_one,
24dc5f33 387 .remove = ata_pci_remove_one,
281d426c 388#ifdef CONFIG_PM
d2298dca
TH		 389 .suspend = ata_pci_device_suspend,
390 .resume = sil24_pci_device_resume,
281d426c 391#endif
edb33667
TH		 392};
393
193515d5 394static struct scsi_host_template sil24_sht = {
68d1d07b 395 ATA_NCQ_SHT(DRV_NAME),
aee10a03 396 .can_queue = SIL24_MAX_CMDS,
93e2618e 397 .sg_tablesize = SIL24_MAX_SGE,
edb33667 398 .dma_boundary = ATA_DMA_BOUNDARY,
edb33667
TH		 399};
400
029cfd6b
TH		 401static struct ata_port_operations sil24_ops = {
402 .inherits = &sata_pmp_port_ops,
69ad185f 403
5682ed33
TH		 404 .sff_check_status = sil24_check_status,
405 .sff_check_altstatus = sil24_check_status,
406 .sff_tf_read = sil24_tf_read,
3454dc69 407 .qc_defer = sil24_qc_defer,
edb33667
TH		 408 .qc_prep = sil24_qc_prep,
409 .qc_issue = sil24_qc_issue,
410
029cfd6b
TH		 411 .freeze = sil24_freeze,
412 .thaw = sil24_thaw,
a1efdaba
TH		 413 .softreset = sil24_softreset,
414 .hardreset = sil24_hardreset,
415 .pmp_softreset = sil24_pmp_softreset,
416 .pmp_hardreset = sil24_pmp_hardreset,
029cfd6b
TH		 417 .error_handler = sil24_error_handler,
418 .post_internal_cmd = sil24_post_internal_cmd,
419 .dev_config = sil24_dev_config,
edb33667
TH		 420
421 .scr_read = sil24_scr_read,
422 .scr_write = sil24_scr_write,
3454dc69
TH		 423 .pmp_attach = sil24_pmp_attach,
424 .pmp_detach = sil24_pmp_detach,
3454dc69 425
edb33667 426 .port_start = sil24_port_start,
3454dc69
TH		 427#ifdef CONFIG_PM
428 .port_resume = sil24_port_resume,
429#endif
edb33667
TH		 430};
431
042c21fd 432/*
cca3974e 433 * Use bits 30-31 of port_flags to encode available port numbers.
042c21fd
TH		 434 * Current maxium is 4.
435 */
436#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
437#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
438
4447d351 439static const struct ata_port_info sil24_port_info[] = {
edb33667
TH		 440 /* sil_3124 */
441 {
cca3974e 442 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
37024e8e 443 SIL24_FLAG_PCIX_IRQ_WOC,
edb33667
TH		 444 .pio_mask = 0x1f, /* pio0-4 */
445 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 446 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 447 .port_ops = &sil24_ops,
448 },
2e9edbf8 449 /* sil_3132 */
edb33667 450 {
cca3974e 451 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
042c21fd
TH		 452 .pio_mask = 0x1f, /* pio0-4 */
453 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 454 .udma_mask = ATA_UDMA5, /* udma0-5 */
042c21fd
TH		 455 .port_ops = &sil24_ops,
456 },
457 /* sil_3131/sil_3531 */
458 {
cca3974e 459 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
edb33667
TH		 460 .pio_mask = 0x1f, /* pio0-4 */
461 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 462 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 463 .port_ops = &sil24_ops,
464 },
465};
466
aee10a03
TH		 467static int sil24_tag(int tag)
468{
469 if (unlikely(ata_tag_internal(tag)))
470 return 0;
471 return tag;
472}
473
cd0d3bbc 474static void sil24_dev_config(struct ata_device *dev)
69ad185f 475{
9af5c9c9 476 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
69ad185f 477
6e7846e9 478 if (dev->cdb_len == 16)
69ad185f
TH		 479 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
480 else
481 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
482}
483
e59f0dad 484static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
6a575fa9 485{
0d5ff566 486 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 487 struct sil24_prb __iomem *prb;
4b4a5eae 488 u8 fis[6 * 4];
6a575fa9 489
e59f0dad
TH		 490 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
491 memcpy_fromio(fis, prb->fis, sizeof(fis));
492 ata_tf_from_fis(fis, tf);
6a575fa9
TH		 493}
494
edb33667
TH		 495static u8 sil24_check_status(struct ata_port *ap)
496{
6a575fa9
TH		 497 struct sil24_port_priv *pp = ap->private_data;
498 return pp->tf.command;
edb33667
TH		 499}
500
edb33667
TH		 501static int sil24_scr_map[] = {
502 [SCR_CONTROL] = 0,
503 [SCR_STATUS] = 1,
504 [SCR_ERROR] = 2,
505 [SCR_ACTIVE] = 3,
506};
507
da3dbb17 508static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
edb33667 509{
0d5ff566 510 void __iomem *scr_addr = ap->ioaddr.scr_addr;
da3dbb17 511
edb33667 512 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 513 void __iomem *addr;
edb33667 514 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
da3dbb17
TH		 515 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
516 return 0;
edb33667 517 }
da3dbb17 518 return -EINVAL;
edb33667
TH		 519}
520
da3dbb17 521static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
edb33667 522{
0d5ff566 523 void __iomem *scr_addr = ap->ioaddr.scr_addr;
da3dbb17 524
edb33667 525 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 526 void __iomem *addr;
edb33667
TH		 527 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
528 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
da3dbb17 529 return 0;
edb33667 530 }
da3dbb17 531 return -EINVAL;
edb33667
TH		 532}
533
7f726d12
TH		 534static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
535{
536 struct sil24_port_priv *pp = ap->private_data;
537 *tf = pp->tf;
538}
539
23818034
TH		 540static void sil24_config_port(struct ata_port *ap)
541{
542 void __iomem *port = ap->ioaddr.cmd_addr;
543
544 /* configure IRQ WoC */
545 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
546 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
547 else
548 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
549
550 /* zero error counters. */
551 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
552 writel(0x8000, port + PORT_CRC_ERR_THRESH);
553 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
554 writel(0x0000, port + PORT_DECODE_ERR_CNT);
555 writel(0x0000, port + PORT_CRC_ERR_CNT);
556 writel(0x0000, port + PORT_HSHK_ERR_CNT);
557
558 /* always use 64bit activation */
559 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
560
561 /* clear port multiplier enable and resume bits */
562 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
563}
564
3454dc69
TH		 565static void sil24_config_pmp(struct ata_port *ap, int attached)
566{
567 void __iomem *port = ap->ioaddr.cmd_addr;
568
569 if (attached)
570 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
571 else
572 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
573}
574
575static void sil24_clear_pmp(struct ata_port *ap)
576{
577 void __iomem *port = ap->ioaddr.cmd_addr;
578 int i;
579
580 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
581
582 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
583 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
584
585 writel(0, pmp_base + PORT_PMP_STATUS);
586 writel(0, pmp_base + PORT_PMP_QACTIVE);
587 }
588}
589
b5bc421c
TH		 590static int sil24_init_port(struct ata_port *ap)
591{
0d5ff566 592 void __iomem *port = ap->ioaddr.cmd_addr;
23818034 593 struct sil24_port_priv *pp = ap->private_data;
b5bc421c
TH		 594 u32 tmp;
595
3454dc69
TH		 596 /* clear PMP error status */
597 if (ap->nr_pmp_links)
598 sil24_clear_pmp(ap);
599
b5bc421c
TH		 600 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
601 ata_wait_register(port + PORT_CTRL_STAT,
602 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
603 tmp = ata_wait_register(port + PORT_CTRL_STAT,
604 PORT_CS_RDY, 0, 10, 100);
605
23818034
TH		 606 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
607 pp->do_port_rst = 1;
cf480626 608 ap->link.eh_context.i.action |= ATA_EH_RESET;
b5bc421c 609 return -EIO;
23818034
TH		 610 }
611
b5bc421c
TH		 612 return 0;
613}
614
37b99cba
TH		 615static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
616 const struct ata_taskfile *tf,
617 int is_cmd, u32 ctrl,
618 unsigned long timeout_msec)
edb33667 619{
0d5ff566 620 void __iomem *port = ap->ioaddr.cmd_addr;
ca45160d 621 struct sil24_port_priv *pp = ap->private_data;
69ad185f 622 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
ca45160d 623 dma_addr_t paddr = pp->cmd_block_dma;
37b99cba
TH		 624 u32 irq_enabled, irq_mask, irq_stat;
625 int rc;
626
627 prb->ctrl = cpu_to_le16(ctrl);
628 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
629
630 /* temporarily plug completion and error interrupts */
631 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
632 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
633
634 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
635 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
636
637 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
638 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
639 10, timeout_msec);
640
641 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
642 irq_stat >>= PORT_IRQ_RAW_SHIFT;
643
644 if (irq_stat & PORT_IRQ_COMPLETE)
645 rc = 0;
646 else {
647 /* force port into known state */
648 sil24_init_port(ap);
649
650 if (irq_stat & PORT_IRQ_ERROR)
651 rc = -EIO;
652 else
653 rc = -EBUSY;
654 }
655
656 /* restore IRQ enabled */
657 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
658
659 return rc;
660}
661
cc0680a5 662static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
975530e8 663 int pmp, unsigned long deadline)
37b99cba 664{
cc0680a5 665 struct ata_port *ap = link->ap;
37b99cba 666 unsigned long timeout_msec = 0;
e59f0dad 667 struct ata_taskfile tf;
643be977 668 const char *reason;
37b99cba 669 int rc;
ca45160d 670
07b73470
TH		 671 DPRINTK("ENTER\n");
672
cc0680a5 673 if (ata_link_offline(link)) {
10d996ad
TH		 674 DPRINTK("PHY reports no device\n");
675 *class = ATA_DEV_NONE;
676 goto out;
677 }
678
2555d6c2
TH		 679 /* put the port into known state */
680 if (sil24_init_port(ap)) {
5796d1c4 681 reason = "port not ready";
2555d6c2
TH		 682 goto err;
683 }
684
0eaa6058 685 /* do SRST */
37b99cba
TH		 686 if (time_after(deadline, jiffies))
687 timeout_msec = jiffies_to_msecs(deadline - jiffies);
ca45160d 688
cc0680a5 689 ata_tf_init(link->device, &tf); /* doesn't really matter */
975530e8
TH		 690 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
691 timeout_msec);
37b99cba
TH		 692 if (rc == -EBUSY) {
693 reason = "timeout";
694 goto err;
695 } else if (rc) {
696 reason = "SRST command error";
643be977 697 goto err;
07b73470 698 }
10d996ad 699
e59f0dad
TH		 700 sil24_read_tf(ap, 0, &tf);
701 *class = ata_dev_classify(&tf);
10d996ad 702
07b73470
TH		 703 if (*class == ATA_DEV_UNKNOWN)
704 *class = ATA_DEV_NONE;
ca45160d 705
10d996ad 706 out:
07b73470 707 DPRINTK("EXIT, class=%u\n", *class);
ca45160d 708 return 0;
643be977
TH		 709
710 err:
cc0680a5 711 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
643be977 712 return -EIO;
ca45160d
TH		 713}
714
cc0680a5 715static int sil24_softreset(struct ata_link *link, unsigned int *class,
975530e8
TH		 716 unsigned long deadline)
717{
3454dc69 718 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
975530e8
TH		 719}
720
cc0680a5 721static int sil24_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 722 unsigned long deadline)
489ff4c7 723{
cc0680a5 724 struct ata_port *ap = link->ap;
0d5ff566 725 void __iomem *port = ap->ioaddr.cmd_addr;
23818034
TH		 726 struct sil24_port_priv *pp = ap->private_data;
727 int did_port_rst = 0;
ecc2e2b9 728 const char *reason;
e8e008e7 729 int tout_msec, rc;
ecc2e2b9
TH		 730 u32 tmp;
731
23818034
TH		 732 retry:
733 /* Sometimes, DEV_RST is not enough to recover the controller.
734 * This happens often after PM DMA CS errata.
735 */
736 if (pp->do_port_rst) {
737 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
738 "state, performing PORT_RST\n");
739
740 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
741 msleep(10);
742 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
743 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
744 10, 5000);
745
746 /* restore port configuration */
747 sil24_config_port(ap);
748 sil24_config_pmp(ap, ap->nr_pmp_links);
749
750 pp->do_port_rst = 0;
751 did_port_rst = 1;
752 }
753
ecc2e2b9 754 /* sil24 does the right thing(tm) without any protection */
cc0680a5 755 sata_set_spd(link);
ecc2e2b9
TH		 756
757 tout_msec = 100;
cc0680a5 758 if (ata_link_online(link))
ecc2e2b9
TH		 759 tout_msec = 5000;
760
761 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
762 tmp = ata_wait_register(port + PORT_CTRL_STAT,
5796d1c4
JG		 763 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
764 tout_msec);
ecc2e2b9 765
e8e008e7
TH		 766 /* SStatus oscillates between zero and valid status after
767 * DEV_RST, debounce it.
ecc2e2b9 768 */
cc0680a5 769 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
e8e008e7
TH		 770 if (rc) {
771 reason = "PHY debouncing failed";
772 goto err;
773 }
ecc2e2b9
TH		 774
775 if (tmp & PORT_CS_DEV_RST) {
cc0680a5 776 if (ata_link_offline(link))
ecc2e2b9
TH		 777 return 0;
778 reason = "link not ready";
779 goto err;
780 }
781
e8e008e7
TH		 782 /* Sil24 doesn't store signature FIS after hardreset, so we
783 * can't wait for BSY to clear. Some devices take a long time
784 * to get ready and those devices will choke if we don't wait
785 * for BSY clearance here. Tell libata to perform follow-up
786 * softreset.
ecc2e2b9 787 */
e8e008e7 788 return -EAGAIN;
ecc2e2b9
TH		 789
790 err:
23818034
TH		 791 if (!did_port_rst) {
792 pp->do_port_rst = 1;
793 goto retry;
794 }
795
cc0680a5 796 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
ecc2e2b9 797 return -EIO;
489ff4c7
TH		 798}
799
edb33667 800static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
69ad185f 801 struct sil24_sge *sge)
edb33667 802{
972c26bd 803 struct scatterlist *sg;
3be6cbd7 804 struct sil24_sge *last_sge = NULL;
ff2aeb1e 805 unsigned int si;
edb33667 806
ff2aeb1e 807 for_each_sg(qc->sg, sg, qc->n_elem, si) {
edb33667
TH		 808 sge->addr = cpu_to_le64(sg_dma_address(sg));
809 sge->cnt = cpu_to_le32(sg_dma_len(sg));
3be6cbd7
JG		 810 sge->flags = 0;
811
812 last_sge = sge;
972c26bd 813 sge++;
edb33667 814 }
3be6cbd7 815
ff2aeb1e 816 last_sge->flags = cpu_to_le32(SGE_TRM);
edb33667
TH		 817}
818
3454dc69
TH		 819static int sil24_qc_defer(struct ata_queued_cmd *qc)
820{
821 struct ata_link *link = qc->dev->link;
822 struct ata_port *ap = link->ap;
823 u8 prot = qc->tf.protocol;
13cc546b
GG		 824
825 /*
826 * There is a bug in the chip:
827 * Port LRAM Causes the PRB/SGT Data to be Corrupted
828 * If the host issues a read request for LRAM and SActive registers
829 * while active commands are available in the port, PRB/SGT data in
830 * the LRAM can become corrupted. This issue applies only when
831 * reading from, but not writing to, the LRAM.
832 *
833 * Therefore, reading LRAM when there is no particular error [and
834 * other commands may be outstanding] is prohibited.
835 *
836 * To avoid this bug there are two situations where a command must run
837 * exclusive of any other commands on the port:
838 *
839 * - ATAPI commands which check the sense data
840 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
841 * set.
842 *
843 */
405e66b3 844 int is_excl = (ata_is_atapi(prot) ||
13cc546b
GG		 845 (qc->flags & ATA_QCFLAG_RESULT_TF));
846
3454dc69
TH		 847 if (unlikely(ap->excl_link)) {
848 if (link == ap->excl_link) {
849 if (ap->nr_active_links)
850 return ATA_DEFER_PORT;
851 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
852 } else
853 return ATA_DEFER_PORT;
13cc546b 854 } else if (unlikely(is_excl)) {
3454dc69
TH		 855 ap->excl_link = link;
856 if (ap->nr_active_links)
857 return ATA_DEFER_PORT;
858 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
859 }
860
861 return ata_std_qc_defer(qc);
862}
863
edb33667
TH		 864static void sil24_qc_prep(struct ata_queued_cmd *qc)
865{
866 struct ata_port *ap = qc->ap;
867 struct sil24_port_priv *pp = ap->private_data;
aee10a03 868 union sil24_cmd_block *cb;
69ad185f
TH		 869 struct sil24_prb *prb;
870 struct sil24_sge *sge;
bad28a37 871 u16 ctrl = 0;
edb33667 872
aee10a03
TH		 873 cb = &pp->cmd_block[sil24_tag(qc->tag)];
874
405e66b3 875 if (!ata_is_atapi(qc->tf.protocol)) {
69ad185f
TH		 876 prb = &cb->ata.prb;
877 sge = cb->ata.sge;
405e66b3 878 } else {
69ad185f
TH		 879 prb = &cb->atapi.prb;
880 sge = cb->atapi.sge;
881 memset(cb->atapi.cdb, 0, 32);
6e7846e9 882 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
69ad185f 883
405e66b3 884 if (ata_is_data(qc->tf.protocol)) {
69ad185f 885 if (qc->tf.flags & ATA_TFLAG_WRITE)
bad28a37 886 ctrl = PRB_CTRL_PACKET_WRITE;
69ad185f 887 else
bad28a37
TH		 888 ctrl = PRB_CTRL_PACKET_READ;
889 }
edb33667
TH		 890 }
891
bad28a37 892 prb->ctrl = cpu_to_le16(ctrl);
3454dc69 893 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
edb33667
TH		 894
895 if (qc->flags & ATA_QCFLAG_DMAMAP)
69ad185f 896 sil24_fill_sg(qc, sge);
edb33667
TH		 897}
898
9a3d9eb0 899static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
edb33667
TH		 900{
901 struct ata_port *ap = qc->ap;
902 struct sil24_port_priv *pp = ap->private_data;
0d5ff566 903 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 904 unsigned int tag = sil24_tag(qc->tag);
905 dma_addr_t paddr;
906 void __iomem *activate;
edb33667 907
aee10a03
TH		 908 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
909 activate = port + PORT_CMD_ACTIVATE + tag * 8;
910
911 writel((u32)paddr, activate);
912 writel((u64)paddr >> 32, activate + 4);
26ec634c 913
edb33667
TH		 914 return 0;
915}
916
3454dc69
TH		 917static void sil24_pmp_attach(struct ata_port *ap)
918{
919 sil24_config_pmp(ap, 1);
920 sil24_init_port(ap);
921}
922
923static void sil24_pmp_detach(struct ata_port *ap)
924{
925 sil24_init_port(ap);
926 sil24_config_pmp(ap, 0);
927}
928
3454dc69
TH		 929static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
930 unsigned long deadline)
931{
932 return sil24_do_softreset(link, class, link->pmp, deadline);
933}
934
935static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
936 unsigned long deadline)
937{
938 int rc;
939
940 rc = sil24_init_port(link->ap);
941 if (rc) {
942 ata_link_printk(link, KERN_ERR,
943 "hardreset failed (port not ready)\n");
944 return rc;
945 }
946
5958e302 947 return sata_std_hardreset(link, class, deadline);
3454dc69
TH		 948}
949
88ce7550 950static void sil24_freeze(struct ata_port *ap)
7d1ce682 951{
0d5ff566 952 void __iomem *port = ap->ioaddr.cmd_addr;
7d1ce682 953
88ce7550
TH		 954 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
955 * PORT_IRQ_ENABLE instead.
956 */
957 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
7d1ce682
TH		 958}
959
88ce7550 960static void sil24_thaw(struct ata_port *ap)
edb33667 961{
0d5ff566 962 void __iomem *port = ap->ioaddr.cmd_addr;
edb33667
TH		 963 u32 tmp;
964
88ce7550
TH		 965 /* clear IRQ */
966 tmp = readl(port + PORT_IRQ_STAT);
967 writel(tmp, port + PORT_IRQ_STAT);
edb33667 968
88ce7550
TH		 969 /* turn IRQ back on */
970 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
edb33667
TH		 971}
972
88ce7550 973static void sil24_error_intr(struct ata_port *ap)
8746618d 974{
0d5ff566 975 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 976 struct sil24_port_priv *pp = ap->private_data;
3454dc69
TH		 977 struct ata_queued_cmd *qc = NULL;
978 struct ata_link *link;
979 struct ata_eh_info *ehi;
980 int abort = 0, freeze = 0;
88ce7550 981 u32 irq_stat;
8746618d 982
88ce7550 983 /* on error, we need to clear IRQ explicitly */
8746618d 984 irq_stat = readl(port + PORT_IRQ_STAT);
88ce7550 985 writel(irq_stat, port + PORT_IRQ_STAT);
ad6e90f6 986
88ce7550 987 /* first, analyze and record host port events */
3454dc69
TH		 988 link = &ap->link;
989 ehi = &link->eh_info;
88ce7550 990 ata_ehi_clear_desc(ehi);
ad6e90f6 991
88ce7550 992 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
8746618d 993
854c73a2 994 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
854c73a2 995 ata_ehi_push_desc(ehi, "SDB notify");
7d77b247 996 sata_async_notification(ap);
854c73a2
TH		 997 }
998
0542925b
TH		 999 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1000 ata_ehi_hotplugged(ehi);
b64bbc39
TH		 1001 ata_ehi_push_desc(ehi, "%s",
1002 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1003 "PHY RDY changed" : "device exchanged");
88ce7550 1004 freeze = 1;
6a575fa9
TH		 1005 }
1006
88ce7550
TH		 1007 if (irq_stat & PORT_IRQ_UNK_FIS) {
1008 ehi->err_mask |= AC_ERR_HSM;
cf480626 1009 ehi->action |= ATA_EH_RESET;
b64bbc39 1010 ata_ehi_push_desc(ehi, "unknown FIS");
88ce7550
TH		 1011 freeze = 1;
1012 }
1013
1014 /* deal with command error */
1015 if (irq_stat & PORT_IRQ_ERROR) {
1016 struct sil24_cerr_info *ci = NULL;
1017 unsigned int err_mask = 0, action = 0;
3454dc69
TH		 1018 u32 context, cerr;
1019 int pmp;
1020
1021 abort = 1;
1022
1023 /* DMA Context Switch Failure in Port Multiplier Mode
1024 * errata. If we have active commands to 3 or more
1025 * devices, any error condition on active devices can
1026 * corrupt DMA context switching.
1027 */
1028 if (ap->nr_active_links >= 3) {
1029 ehi->err_mask |= AC_ERR_OTHER;
cf480626 1030 ehi->action |= ATA_EH_RESET;
3454dc69 1031 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
23818034 1032 pp->do_port_rst = 1;
3454dc69
TH		 1033 freeze = 1;
1034 }
1035
1036 /* find out the offending link and qc */
1037 if (ap->nr_pmp_links) {
1038 context = readl(port + PORT_CONTEXT);
1039 pmp = (context >> 5) & 0xf;
1040
1041 if (pmp < ap->nr_pmp_links) {
1042 link = &ap->pmp_link[pmp];
1043 ehi = &link->eh_info;
1044 qc = ata_qc_from_tag(ap, link->active_tag);
1045
1046 ata_ehi_clear_desc(ehi);
1047 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1048 irq_stat);
1049 } else {
1050 err_mask |= AC_ERR_HSM;
cf480626 1051 action |= ATA_EH_RESET;
3454dc69
TH		 1052 freeze = 1;
1053 }
1054 } else
1055 qc = ata_qc_from_tag(ap, link->active_tag);
88ce7550
TH		 1056
1057 /* analyze CMD_ERR */
1058 cerr = readl(port + PORT_CMD_ERR);
1059 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1060 ci = &sil24_cerr_db[cerr];
1061
1062 if (ci && ci->desc) {
1063 err_mask |= ci->err_mask;
1064 action |= ci->action;
cf480626 1065 if (action & ATA_EH_RESET)
c2e14f11 1066 freeze = 1;
b64bbc39 1067 ata_ehi_push_desc(ehi, "%s", ci->desc);
88ce7550
TH		 1068 } else {
1069 err_mask |= AC_ERR_OTHER;
cf480626 1070 action |= ATA_EH_RESET;
c2e14f11 1071 freeze = 1;
b64bbc39 1072 ata_ehi_push_desc(ehi, "unknown command error %d",
88ce7550
TH		 1073 cerr);
1074 }
1075
1076 /* record error info */
88ce7550 1077 if (qc) {
e59f0dad 1078 sil24_read_tf(ap, qc->tag, &pp->tf);
88ce7550
TH		 1079 qc->err_mask |= err_mask;
1080 } else
1081 ehi->err_mask |= err_mask;
1082
1083 ehi->action |= action;
3454dc69
TH		 1084
1085 /* if PMP, resume */
1086 if (ap->nr_pmp_links)
1087 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
a22e2eb0 1088 }
88ce7550
TH		 1089
1090 /* freeze or abort */
1091 if (freeze)
1092 ata_port_freeze(ap);
3454dc69
TH		 1093 else if (abort) {
1094 if (qc)
1095 ata_link_abort(qc->dev->link);
1096 else
1097 ata_port_abort(ap);
1098 }
8746618d
TH		 1099}
1100
aee10a03
TH		 1101static void sil24_finish_qc(struct ata_queued_cmd *qc)
1102{
e59f0dad
TH		 1103 struct ata_port *ap = qc->ap;
1104 struct sil24_port_priv *pp = ap->private_data;
1105
aee10a03 1106 if (qc->flags & ATA_QCFLAG_RESULT_TF)
e59f0dad 1107 sil24_read_tf(ap, qc->tag, &pp->tf);
aee10a03
TH		 1108}
1109
edb33667
TH		 1110static inline void sil24_host_intr(struct ata_port *ap)
1111{
0d5ff566 1112 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 1113 u32 slot_stat, qc_active;
1114 int rc;
edb33667 1115
228f47b9
TH		 1116 /* If PCIX_IRQ_WOC, there's an inherent race window between
1117 * clearing IRQ pending status and reading PORT_SLOT_STAT
1118 * which may cause spurious interrupts afterwards. This is
1119 * unavoidable and much better than losing interrupts which
1120 * happens if IRQ pending is cleared after reading
1121 * PORT_SLOT_STAT.
1122 */
1123 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1124 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1125
edb33667 1126 slot_stat = readl(port + PORT_SLOT_STAT);
37024e8e 1127
88ce7550
TH		 1128 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1129 sil24_error_intr(ap);
1130 return;
1131 }
1132
aee10a03
TH		 1133 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1134 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
1135 if (rc > 0)
1136 return;
1137 if (rc < 0) {
9af5c9c9 1138 struct ata_eh_info *ehi = &ap->link.eh_info;
aee10a03 1139 ehi->err_mask |= AC_ERR_HSM;
cf480626 1140 ehi->action |= ATA_EH_RESET;
aee10a03 1141 ata_port_freeze(ap);
88ce7550
TH		 1142 return;
1143 }
1144
228f47b9
TH		 1145 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1146 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
88ce7550 1147 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
aee10a03 1148 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
9af5c9c9 1149 slot_stat, ap->link.active_tag, ap->link.sactive);
edb33667
TH		 1150}
1151
7d12e780 1152static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
edb33667 1153{
cca3974e 1154 struct ata_host *host = dev_instance;
0d5ff566 1155 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
edb33667
TH		 1156 unsigned handled = 0;
1157 u32 status;
1158 int i;
1159
0d5ff566 1160 status = readl(host_base + HOST_IRQ_STAT);
edb33667 1161
06460aea
TH		 1162 if (status == 0xffffffff) {
1163 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1164 "PCI fault or device removal?\n");
1165 goto out;
1166 }
1167
edb33667
TH		 1168 if (!(status & IRQ_STAT_4PORTS))
1169 goto out;
1170
cca3974e 1171 spin_lock(&host->lock);
edb33667 1172
cca3974e 1173 for (i = 0; i < host->n_ports; i++)
edb33667 1174 if (status & (1 << i)) {
cca3974e 1175 struct ata_port *ap = host->ports[i];
198e0fed 1176 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
825cd6dd 1177 sil24_host_intr(ap);
3cc4571c
TH		 1178 handled++;
1179 } else
1180 printk(KERN_ERR DRV_NAME
1181 ": interrupt from disabled port %d\n", i);
edb33667
TH		 1182 }
1183
cca3974e 1184 spin_unlock(&host->lock);
edb33667
TH		 1185 out:
1186 return IRQ_RETVAL(handled);
1187}
1188
88ce7550
TH		 1189static void sil24_error_handler(struct ata_port *ap)
1190{
23818034
TH		 1191 struct sil24_port_priv *pp = ap->private_data;
1192
3454dc69 1193 if (sil24_init_port(ap))
88ce7550 1194 ata_eh_freeze_port(ap);
88ce7550 1195
a1efdaba 1196 sata_pmp_error_handler(ap);
23818034
TH		 1197
1198 pp->do_port_rst = 0;
88ce7550
TH		 1199}
1200
1201static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1202{
1203 struct ata_port *ap = qc->ap;
1204
88ce7550 1205 /* make DMA engine forget about the failed command */
3454dc69
TH		 1206 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1207 ata_eh_freeze_port(ap);
88ce7550
TH		 1208}
1209
edb33667
TH		 1210static int sil24_port_start(struct ata_port *ap)
1211{
cca3974e 1212 struct device *dev = ap->host->dev;
edb33667 1213 struct sil24_port_priv *pp;
69ad185f 1214 union sil24_cmd_block *cb;
aee10a03 1215 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
edb33667
TH		 1216 dma_addr_t cb_dma;
1217
24dc5f33 1218 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
edb33667 1219 if (!pp)
24dc5f33 1220 return -ENOMEM;
edb33667 1221
6a575fa9
TH		 1222 pp->tf.command = ATA_DRDY;
1223
24dc5f33 1224 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb 1225 if (!cb)
24dc5f33 1226 return -ENOMEM;
edb33667
TH		 1227 memset(cb, 0, cb_size);
1228
edb33667
TH		 1229 pp->cmd_block = cb;
1230 pp->cmd_block_dma = cb_dma;
1231
1232 ap->private_data = pp;
1233
1234 return 0;
edb33667
TH		 1235}
1236
4447d351 1237static void sil24_init_controller(struct ata_host *host)
2a41a610 1238{
4447d351 1239 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
2a41a610
TH		 1240 u32 tmp;
1241 int i;
1242
1243 /* GPIO off */
1244 writel(0, host_base + HOST_FLASH_CMD);
1245
1246 /* clear global reset & mask interrupts during initialization */
1247 writel(0, host_base + HOST_CTRL);
1248
1249 /* init ports */
4447d351 1250 for (i = 0; i < host->n_ports; i++) {
23818034
TH		 1251 struct ata_port *ap = host->ports[i];
1252 void __iomem *port = ap->ioaddr.cmd_addr;
2a41a610
TH		 1253
1254 /* Initial PHY setting */
1255 writel(0x20c, port + PORT_PHY_CFG);
1256
1257 /* Clear port RST */
1258 tmp = readl(port + PORT_CTRL_STAT);
1259 if (tmp & PORT_CS_PORT_RST) {
1260 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1261 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1262 PORT_CS_PORT_RST,
1263 PORT_CS_PORT_RST, 10, 100);
1264 if (tmp & PORT_CS_PORT_RST)
4447d351 1265 dev_printk(KERN_ERR, host->dev,
5796d1c4 1266 "failed to clear port RST\n");
2a41a610
TH		 1267 }
1268
23818034
TH		 1269 /* configure port */
1270 sil24_config_port(ap);
2a41a610
TH		 1271 }
1272
1273 /* Turn on interrupts */
1274 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1275}
1276
edb33667
TH		 1277static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1278{
93e2618e 1279 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
5796d1c4 1280 static int printed_version;
4447d351
TH		 1281 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1282 const struct ata_port_info *ppi[] = { &pi, NULL };
1283 void __iomem * const *iomap;
1284 struct ata_host *host;
edb33667 1285 int i, rc;
37024e8e 1286 u32 tmp;
edb33667 1287
93e2618e
TH		 1288 /* cause link error if sil24_cmd_block is sized wrongly */
1289 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1290 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1291
edb33667 1292 if (!printed_version++)
a9524a76 1293 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667 1294
4447d351 1295 /* acquire resources */
24dc5f33 1296 rc = pcim_enable_device(pdev);
edb33667
TH		 1297 if (rc)
1298 return rc;
1299
0d5ff566
TH		 1300 rc = pcim_iomap_regions(pdev,
1301 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1302 DRV_NAME);
edb33667 1303 if (rc)
24dc5f33 1304 return rc;
4447d351 1305 iomap = pcim_iomap_table(pdev);
edb33667 1306
4447d351
TH		 1307 /* apply workaround for completion IRQ loss on PCI-X errata */
1308 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1309 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1310 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1311 dev_printk(KERN_INFO, &pdev->dev,
1312 "Applying completion IRQ loss on PCI-X "
1313 "errata fix\n");
1314 else
1315 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1316 }
edb33667 1317
4447d351
TH		 1318 /* allocate and fill host */
1319 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1320 SIL24_FLAG2NPORTS(ppi[0]->flags));
1321 if (!host)
1322 return -ENOMEM;
1323 host->iomap = iomap;
edb33667 1324
4447d351 1325 for (i = 0; i < host->n_ports; i++) {
cbcdd875
TH		 1326 struct ata_port *ap = host->ports[i];
1327 size_t offset = ap->port_no * PORT_REGS_SIZE;
1328 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
edb33667 1329
4447d351
TH		 1330 host->ports[i]->ioaddr.cmd_addr = port;
1331 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
edb33667 1332
cbcdd875
TH		 1333 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1334 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
4447d351 1335 }
edb33667 1336
4447d351 1337 /* configure and activate the device */
26ec634c
TH		 1338 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1339 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1340 if (rc) {
1341 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1342 if (rc) {
1343 dev_printk(KERN_ERR, &pdev->dev,
1344 "64-bit DMA enable failed\n");
24dc5f33 1345 return rc;
26ec634c
TH		 1346 }
1347 }
1348 } else {
1349 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1350 if (rc) {
1351 dev_printk(KERN_ERR, &pdev->dev,
1352 "32-bit DMA enable failed\n");
24dc5f33 1353 return rc;
26ec634c
TH		 1354 }
1355 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1356 if (rc) {
1357 dev_printk(KERN_ERR, &pdev->dev,
1358 "32-bit consistent DMA enable failed\n");
24dc5f33 1359 return rc;
26ec634c 1360 }
edb33667
TH		 1361 }
1362
4447d351 1363 sil24_init_controller(host);
edb33667
TH		 1364
1365 pci_set_master(pdev);
4447d351
TH		 1366 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1367 &sil24_sht);
edb33667
TH		 1368}
1369
281d426c 1370#ifdef CONFIG_PM
d2298dca
TH		 1371static int sil24_pci_device_resume(struct pci_dev *pdev)
1372{
cca3974e 1373 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1374 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
553c4aa6 1375 int rc;
d2298dca 1376
553c4aa6
TH		 1377 rc = ata_pci_device_do_resume(pdev);
1378 if (rc)
1379 return rc;
d2298dca
TH		 1380
1381 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
0d5ff566 1382 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
d2298dca 1383
4447d351 1384 sil24_init_controller(host);
d2298dca 1385
cca3974e 1386 ata_host_resume(host);
d2298dca
TH		 1387
1388 return 0;
1389}
3454dc69
TH		 1390
1391static int sil24_port_resume(struct ata_port *ap)
1392{
1393 sil24_config_pmp(ap, ap->nr_pmp_links);
1394 return 0;
1395}
281d426c 1396#endif
d2298dca 1397
edb33667
TH		 1398static int __init sil24_init(void)
1399{
b7887196 1400 return pci_register_driver(&sil24_pci_driver);
edb33667
TH		 1401}
1402
1403static void __exit sil24_exit(void)
1404{
1405 pci_unregister_driver(&sil24_pci_driver);
1406}
1407
1408MODULE_AUTHOR("Tejun Heo");
1409MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1410MODULE_LICENSE("GPL");
1411MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1412
1413module_init(sil24_init);
1414module_exit(sil24_exit);
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