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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
a9524a76 | 40 | #include <linux/device.h> |
95006188 | 41 | #include <scsi/scsi.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 44 | #include <linux/libata.h> |
1da177e4 LT |
45 | #include "sata_promise.h" |
46 | ||
47 | #define DRV_NAME "sata_promise" | |
799331fd | 48 | #define DRV_VERSION "2.02" |
1da177e4 LT |
49 | |
50 | ||
51 | enum { | |
0d5ff566 TH |
52 | PDC_MMIO_BAR = 3, |
53 | ||
95006188 MP |
54 | /* register offsets */ |
55 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | |
56 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
57 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
58 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
59 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
60 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
61 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 62 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 LT |
63 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
64 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 65 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
66 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
67 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
68 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 69 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
70 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
71 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 LT |
72 | |
73 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
74 | (1<<8) | (1<<9) | (1<<10), | |
75 | ||
76 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
77 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 78 | board_20619 = 2, /* FastTrak TX4000 */ |
d324d462 MP |
79 | board_2057x = 3, /* SATAII150 Tx2plus */ |
80 | board_40518 = 4, /* SATAII150 Tx4 */ | |
1da177e4 | 81 | |
6340f019 | 82 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 83 | |
95006188 MP |
84 | /* Sequence counter control registers bit definitions */ |
85 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
86 | ||
87 | /* Feature register values */ | |
88 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
89 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
90 | ||
91 | /* Device/Head register values */ | |
92 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
93 | ||
25b93d81 MP |
94 | /* PDC_CTLSTAT bit definitions */ |
95 | PDC_DMA_ENABLE = (1 << 7), | |
96 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 97 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 98 | |
25b93d81 | 99 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 100 | ATA_FLAG_MMIO | |
3d0a59c0 | 101 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 MP |
102 | |
103 | /* hp->flags bits */ | |
104 | PDC_FLAG_GEN_II = (1 << 0), | |
1da177e4 LT |
105 | }; |
106 | ||
107 | ||
108 | struct pdc_port_priv { | |
109 | u8 *pkt; | |
110 | dma_addr_t pkt_dma; | |
111 | }; | |
112 | ||
6340f019 | 113 | struct pdc_host_priv { |
b2d1eee1 | 114 | unsigned long flags; |
870ae337 | 115 | unsigned long port_flags[ATA_MAX_PORTS]; |
6340f019 LK |
116 | }; |
117 | ||
1da177e4 LT |
118 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
119 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
120 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
7d12e780 | 121 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance); |
1da177e4 | 122 | static int pdc_port_start(struct ata_port *ap); |
1da177e4 | 123 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
124 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
125 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 MP |
126 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
127 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc); | |
1da177e4 | 128 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 129 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
25b93d81 MP |
130 | static void pdc_freeze(struct ata_port *ap); |
131 | static void pdc_thaw(struct ata_port *ap); | |
132 | static void pdc_error_handler(struct ata_port *ap); | |
133 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); | |
e2a9752a | 134 | static int pdc_cable_detect(struct ata_port *ap); |
374b1873 | 135 | |
193515d5 | 136 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
137 | .module = THIS_MODULE, |
138 | .name = DRV_NAME, | |
139 | .ioctl = ata_scsi_ioctl, | |
140 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
141 | .can_queue = ATA_DEF_QUEUE, |
142 | .this_id = ATA_SHT_THIS_ID, | |
143 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
144 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
145 | .emulated = ATA_SHT_EMULATED, | |
146 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
147 | .proc_name = DRV_NAME, | |
148 | .dma_boundary = ATA_DMA_BOUNDARY, | |
149 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 150 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 151 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
152 | }; |
153 | ||
057ace5e | 154 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
155 | .port_disable = ata_port_disable, |
156 | .tf_load = pdc_tf_load_mmio, | |
157 | .tf_read = ata_tf_read, | |
158 | .check_status = ata_check_status, | |
159 | .exec_command = pdc_exec_command_mmio, | |
160 | .dev_select = ata_std_dev_select, | |
95006188 MP |
161 | .check_atapi_dma = pdc_check_atapi_dma, |
162 | ||
163 | .qc_prep = pdc_qc_prep, | |
164 | .qc_issue = pdc_qc_issue_prot, | |
165 | .freeze = pdc_freeze, | |
166 | .thaw = pdc_thaw, | |
167 | .error_handler = pdc_error_handler, | |
168 | .post_internal_cmd = pdc_post_internal_cmd, | |
e2a9752a | 169 | .cable_detect = pdc_cable_detect, |
0d5ff566 | 170 | .data_xfer = ata_data_xfer, |
95006188 MP |
171 | .irq_handler = pdc_interrupt, |
172 | .irq_clear = pdc_irq_clear, | |
246ce3b6 AI |
173 | .irq_on = ata_irq_on, |
174 | .irq_ack = ata_irq_ack, | |
95006188 MP |
175 | |
176 | .scr_read = pdc_sata_scr_read, | |
177 | .scr_write = pdc_sata_scr_write, | |
178 | .port_start = pdc_port_start, | |
95006188 MP |
179 | }; |
180 | ||
181 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ | |
182 | static const struct ata_port_operations pdc_old_sata_ops = { | |
183 | .port_disable = ata_port_disable, | |
184 | .tf_load = pdc_tf_load_mmio, | |
185 | .tf_read = ata_tf_read, | |
186 | .check_status = ata_check_status, | |
187 | .exec_command = pdc_exec_command_mmio, | |
188 | .dev_select = ata_std_dev_select, | |
189 | .check_atapi_dma = pdc_old_check_atapi_dma, | |
2cba582a | 190 | |
1da177e4 LT |
191 | .qc_prep = pdc_qc_prep, |
192 | .qc_issue = pdc_qc_issue_prot, | |
25b93d81 MP |
193 | .freeze = pdc_freeze, |
194 | .thaw = pdc_thaw, | |
195 | .error_handler = pdc_error_handler, | |
196 | .post_internal_cmd = pdc_post_internal_cmd, | |
799331fd | 197 | .cable_detect = pdc_cable_detect, |
0d5ff566 | 198 | .data_xfer = ata_data_xfer, |
1da177e4 LT |
199 | .irq_handler = pdc_interrupt, |
200 | .irq_clear = pdc_irq_clear, | |
246ce3b6 AI |
201 | .irq_on = ata_irq_on, |
202 | .irq_ack = ata_irq_ack, | |
2cba582a | 203 | |
1da177e4 LT |
204 | .scr_read = pdc_sata_scr_read, |
205 | .scr_write = pdc_sata_scr_write, | |
206 | .port_start = pdc_port_start, | |
1da177e4 LT |
207 | }; |
208 | ||
057ace5e | 209 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
210 | .port_disable = ata_port_disable, |
211 | .tf_load = pdc_tf_load_mmio, | |
212 | .tf_read = ata_tf_read, | |
213 | .check_status = ata_check_status, | |
214 | .exec_command = pdc_exec_command_mmio, | |
215 | .dev_select = ata_std_dev_select, | |
95006188 | 216 | .check_atapi_dma = pdc_check_atapi_dma, |
2cba582a | 217 | |
2cba582a JG |
218 | .qc_prep = pdc_qc_prep, |
219 | .qc_issue = pdc_qc_issue_prot, | |
5387373b MP |
220 | .freeze = pdc_freeze, |
221 | .thaw = pdc_thaw, | |
222 | .error_handler = pdc_error_handler, | |
540477b4 | 223 | .post_internal_cmd = pdc_post_internal_cmd, |
799331fd | 224 | .cable_detect = pdc_cable_detect, |
0d5ff566 | 225 | .data_xfer = ata_data_xfer, |
2cba582a JG |
226 | .irq_handler = pdc_interrupt, |
227 | .irq_clear = pdc_irq_clear, | |
246ce3b6 AI |
228 | .irq_on = ata_irq_on, |
229 | .irq_ack = ata_irq_ack, | |
2cba582a JG |
230 | |
231 | .port_start = pdc_port_start, | |
2cba582a JG |
232 | }; |
233 | ||
98ac62de | 234 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
235 | /* board_2037x */ |
236 | { | |
237 | .sht = &pdc_ata_sht, | |
870ae337 | 238 | .flags = PDC_COMMON_FLAGS, |
1da177e4 LT |
239 | .pio_mask = 0x1f, /* pio0-4 */ |
240 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
241 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 242 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
243 | }, |
244 | ||
245 | /* board_20319 */ | |
246 | { | |
247 | .sht = &pdc_ata_sht, | |
cca3974e | 248 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
249 | .pio_mask = 0x1f, /* pio0-4 */ |
250 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
251 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 252 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 253 | }, |
f497ba73 TL |
254 | |
255 | /* board_20619 */ | |
256 | { | |
257 | .sht = &pdc_ata_sht, | |
5387373b | 258 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
259 | .pio_mask = 0x1f, /* pio0-4 */ |
260 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
261 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 262 | .port_ops = &pdc_pata_ops, |
f497ba73 | 263 | }, |
5a46fe89 | 264 | |
6340f019 LK |
265 | /* board_2057x */ |
266 | { | |
267 | .sht = &pdc_ata_sht, | |
870ae337 | 268 | .flags = PDC_COMMON_FLAGS, |
6340f019 LK |
269 | .pio_mask = 0x1f, /* pio0-4 */ |
270 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
271 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
272 | .port_ops = &pdc_sata_ops, | |
273 | }, | |
274 | ||
275 | /* board_40518 */ | |
276 | { | |
277 | .sht = &pdc_ata_sht, | |
cca3974e | 278 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
279 | .pio_mask = 0x1f, /* pio0-4 */ |
280 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
281 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
282 | .port_ops = &pdc_sata_ops, | |
283 | }, | |
1da177e4 LT |
284 | }; |
285 | ||
3b7d697d | 286 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 287 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
288 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
289 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
290 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
291 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
292 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 293 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 294 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 295 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 296 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
297 | |
298 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
299 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
300 | { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, | |
301 | { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, | |
b2d1eee1 | 302 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
303 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
304 | ||
305 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 306 | |
1da177e4 LT |
307 | { } /* terminate list */ |
308 | }; | |
309 | ||
310 | ||
311 | static struct pci_driver pdc_ata_pci_driver = { | |
312 | .name = DRV_NAME, | |
313 | .id_table = pdc_ata_pci_tbl, | |
314 | .probe = pdc_ata_init_one, | |
315 | .remove = ata_pci_remove_one, | |
316 | }; | |
317 | ||
318 | ||
319 | static int pdc_port_start(struct ata_port *ap) | |
320 | { | |
cca3974e | 321 | struct device *dev = ap->host->dev; |
599b7202 | 322 | struct pdc_host_priv *hp = ap->host->private_data; |
1da177e4 LT |
323 | struct pdc_port_priv *pp; |
324 | int rc; | |
325 | ||
870ae337 MP |
326 | /* fix up port flags and cable type for SATA+PATA chips */ |
327 | ap->flags |= hp->port_flags[ap->port_no]; | |
328 | if (ap->flags & ATA_FLAG_SATA) | |
329 | ap->cbl = ATA_CBL_SATA; | |
330 | ||
1da177e4 LT |
331 | rc = ata_port_start(ap); |
332 | if (rc) | |
333 | return rc; | |
334 | ||
24dc5f33 TH |
335 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
336 | if (!pp) | |
337 | return -ENOMEM; | |
1da177e4 | 338 | |
24dc5f33 TH |
339 | pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); |
340 | if (!pp->pkt) | |
341 | return -ENOMEM; | |
1da177e4 LT |
342 | |
343 | ap->private_data = pp; | |
344 | ||
599b7202 MP |
345 | /* fix up PHYMODE4 align timing */ |
346 | if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) { | |
347 | void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr; | |
348 | unsigned int tmp; | |
349 | ||
350 | tmp = readl(mmio + 0x014); | |
351 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | |
352 | writel(tmp, mmio + 0x014); | |
353 | } | |
354 | ||
1da177e4 | 355 | return 0; |
1da177e4 LT |
356 | } |
357 | ||
1da177e4 LT |
358 | static void pdc_reset_port(struct ata_port *ap) |
359 | { | |
0d5ff566 | 360 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
361 | unsigned int i; |
362 | u32 tmp; | |
363 | ||
364 | for (i = 11; i > 0; i--) { | |
365 | tmp = readl(mmio); | |
366 | if (tmp & PDC_RESET) | |
367 | break; | |
368 | ||
369 | udelay(100); | |
370 | ||
371 | tmp |= PDC_RESET; | |
372 | writel(tmp, mmio); | |
373 | } | |
374 | ||
375 | tmp &= ~PDC_RESET; | |
376 | writel(tmp, mmio); | |
377 | readl(mmio); /* flush */ | |
378 | } | |
379 | ||
e2a9752a | 380 | static int pdc_cable_detect(struct ata_port *ap) |
2cba582a | 381 | { |
d3fb4e8d | 382 | u8 tmp; |
03dc5506 | 383 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d | 384 | |
e2a9752a AC |
385 | if (!sata_scr_valid(ap)) { |
386 | tmp = readb(mmio); | |
387 | if (tmp & 0x01) | |
388 | return ATA_CBL_PATA40; | |
389 | return ATA_CBL_PATA80; | |
390 | } | |
391 | return ATA_CBL_SATA; | |
d3fb4e8d | 392 | } |
2cba582a | 393 | |
1da177e4 LT |
394 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
395 | { | |
870ae337 | 396 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 397 | return 0xffffffffU; |
0d5ff566 | 398 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
399 | } |
400 | ||
401 | ||
402 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
403 | u32 val) | |
404 | { | |
870ae337 | 405 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 406 | return; |
0d5ff566 | 407 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
408 | } |
409 | ||
fba6edbd | 410 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
95006188 | 411 | { |
4113bb6b MP |
412 | struct ata_port *ap = qc->ap; |
413 | dma_addr_t sg_table = ap->prd_dma; | |
414 | unsigned int cdb_len = qc->dev->cdb_len; | |
415 | u8 *cdb = qc->cdb; | |
416 | struct pdc_port_priv *pp = ap->private_data; | |
417 | u8 *buf = pp->pkt; | |
95006188 | 418 | u32 *buf32 = (u32 *) buf; |
4113bb6b | 419 | unsigned int dev_sel, feature, nbytes; |
95006188 MP |
420 | |
421 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
422 | * and seq id (byte 2) | |
423 | */ | |
fba6edbd MP |
424 | switch (qc->tf.protocol) { |
425 | case ATA_PROT_ATAPI_DMA: | |
426 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | |
427 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
428 | else | |
429 | buf32[0] = 0; | |
430 | break; | |
431 | case ATA_PROT_ATAPI_NODATA: | |
432 | buf32[0] = cpu_to_le32(PDC_PKT_NODATA); | |
433 | break; | |
434 | default: | |
435 | BUG(); | |
436 | break; | |
437 | } | |
95006188 MP |
438 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ |
439 | buf32[2] = 0; /* no next-packet */ | |
440 | ||
4113bb6b MP |
441 | /* select drive */ |
442 | if (sata_scr_valid(ap)) { | |
443 | dev_sel = PDC_DEVICE_SATA; | |
444 | } else { | |
445 | dev_sel = ATA_DEVICE_OBS; | |
446 | if (qc->dev->devno != 0) | |
447 | dev_sel |= ATA_DEV1; | |
448 | } | |
449 | buf[12] = (1 << 5) | ATA_REG_DEVICE; | |
450 | buf[13] = dev_sel; | |
451 | buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; | |
452 | buf[15] = dev_sel; /* once more, waiting for BSY to clear */ | |
453 | ||
454 | buf[16] = (1 << 5) | ATA_REG_NSECT; | |
455 | buf[17] = 0x00; | |
456 | buf[18] = (1 << 5) | ATA_REG_LBAL; | |
457 | buf[19] = 0x00; | |
458 | ||
459 | /* set feature and byte counter registers */ | |
460 | if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { | |
461 | feature = PDC_FEATURE_ATAPI_PIO; | |
462 | /* set byte counter register to real transfer byte count */ | |
463 | nbytes = qc->nbytes; | |
4113bb6b MP |
464 | if (nbytes > 0xffff) |
465 | nbytes = 0xffff; | |
466 | } else { | |
467 | feature = PDC_FEATURE_ATAPI_DMA; | |
468 | /* set byte counter register to 0 */ | |
469 | nbytes = 0; | |
470 | } | |
471 | buf[20] = (1 << 5) | ATA_REG_FEATURE; | |
472 | buf[21] = feature; | |
473 | buf[22] = (1 << 5) | ATA_REG_BYTEL; | |
474 | buf[23] = nbytes & 0xFF; | |
475 | buf[24] = (1 << 5) | ATA_REG_BYTEH; | |
476 | buf[25] = (nbytes >> 8) & 0xFF; | |
477 | ||
478 | /* send ATAPI packet command 0xA0 */ | |
479 | buf[26] = (1 << 5) | ATA_REG_CMD; | |
480 | buf[27] = ATA_CMD_PACKET; | |
481 | ||
482 | /* select drive and check DRQ */ | |
483 | buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; | |
484 | buf[29] = dev_sel; | |
485 | ||
95006188 MP |
486 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ |
487 | BUG_ON(cdb_len & ~0x1E); | |
488 | ||
4113bb6b MP |
489 | /* append the CDB as the final part */ |
490 | buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
491 | memcpy(buf+31, cdb, cdb_len); | |
95006188 MP |
492 | } |
493 | ||
1da177e4 LT |
494 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
495 | { | |
496 | struct pdc_port_priv *pp = qc->ap->private_data; | |
497 | unsigned int i; | |
498 | ||
499 | VPRINTK("ENTER\n"); | |
500 | ||
501 | switch (qc->tf.protocol) { | |
502 | case ATA_PROT_DMA: | |
503 | ata_qc_prep(qc); | |
504 | /* fall through */ | |
505 | ||
506 | case ATA_PROT_NODATA: | |
507 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
508 | qc->dev->devno, pp->pkt); | |
509 | ||
510 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
511 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
512 | else | |
513 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
514 | ||
515 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
516 | break; | |
517 | ||
95006188 | 518 | case ATA_PROT_ATAPI: |
95006188 MP |
519 | ata_qc_prep(qc); |
520 | break; | |
521 | ||
522 | case ATA_PROT_ATAPI_DMA: | |
523 | ata_qc_prep(qc); | |
fba6edbd MP |
524 | /*FALLTHROUGH*/ |
525 | case ATA_PROT_ATAPI_NODATA: | |
526 | pdc_atapi_pkt(qc); | |
95006188 MP |
527 | break; |
528 | ||
1da177e4 LT |
529 | default: |
530 | break; | |
531 | } | |
532 | } | |
533 | ||
25b93d81 MP |
534 | static void pdc_freeze(struct ata_port *ap) |
535 | { | |
536 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
537 | u32 tmp; | |
538 | ||
539 | tmp = readl(mmio + PDC_CTLSTAT); | |
540 | tmp |= PDC_IRQ_DISABLE; | |
541 | tmp &= ~PDC_DMA_ENABLE; | |
542 | writel(tmp, mmio + PDC_CTLSTAT); | |
543 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
544 | } | |
545 | ||
546 | static void pdc_thaw(struct ata_port *ap) | |
547 | { | |
548 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
549 | u32 tmp; | |
550 | ||
551 | /* clear IRQ */ | |
552 | readl(mmio + PDC_INT_SEQMASK); | |
553 | ||
554 | /* turn IRQ back on */ | |
555 | tmp = readl(mmio + PDC_CTLSTAT); | |
556 | tmp &= ~PDC_IRQ_DISABLE; | |
557 | writel(tmp, mmio + PDC_CTLSTAT); | |
558 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
559 | } | |
560 | ||
561 | static void pdc_error_handler(struct ata_port *ap) | |
562 | { | |
563 | ata_reset_fn_t hardreset; | |
564 | ||
565 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) | |
566 | pdc_reset_port(ap); | |
567 | ||
568 | hardreset = NULL; | |
569 | if (sata_scr_valid(ap)) | |
570 | hardreset = sata_std_hardreset; | |
571 | ||
572 | /* perform recovery */ | |
e2a9752a | 573 | ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, |
25b93d81 MP |
574 | ata_std_postreset); |
575 | } | |
576 | ||
577 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) | |
578 | { | |
579 | struct ata_port *ap = qc->ap; | |
580 | ||
581 | if (qc->flags & ATA_QCFLAG_FAILED) | |
582 | qc->err_mask |= AC_ERR_OTHER; | |
583 | ||
584 | /* make DMA engine forget about the failed command */ | |
585 | if (qc->err_mask) | |
586 | pdc_reset_port(ap); | |
587 | } | |
588 | ||
1da177e4 LT |
589 | static inline unsigned int pdc_host_intr( struct ata_port *ap, |
590 | struct ata_queued_cmd *qc) | |
591 | { | |
a22e2eb0 | 592 | unsigned int handled = 0; |
1da177e4 | 593 | u32 tmp; |
0d5ff566 | 594 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
595 | |
596 | tmp = readl(mmio); | |
597 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 598 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
599 | pdc_reset_port(ap); |
600 | } | |
601 | ||
602 | switch (qc->tf.protocol) { | |
603 | case ATA_PROT_DMA: | |
604 | case ATA_PROT_NODATA: | |
95006188 | 605 | case ATA_PROT_ATAPI_DMA: |
fba6edbd | 606 | case ATA_PROT_ATAPI_NODATA: |
a22e2eb0 AL |
607 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
608 | ata_qc_complete(qc); | |
1da177e4 LT |
609 | handled = 1; |
610 | break; | |
611 | ||
612 | default: | |
ee500aab AL |
613 | ap->stats.idle_irq++; |
614 | break; | |
1da177e4 LT |
615 | } |
616 | ||
ee500aab | 617 | return handled; |
1da177e4 LT |
618 | } |
619 | ||
620 | static void pdc_irq_clear(struct ata_port *ap) | |
621 | { | |
cca3974e | 622 | struct ata_host *host = ap->host; |
0d5ff566 | 623 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
624 | |
625 | readl(mmio + PDC_INT_SEQMASK); | |
626 | } | |
627 | ||
7d12e780 | 628 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance) |
1da177e4 | 629 | { |
cca3974e | 630 | struct ata_host *host = dev_instance; |
1da177e4 LT |
631 | struct ata_port *ap; |
632 | u32 mask = 0; | |
633 | unsigned int i, tmp; | |
634 | unsigned int handled = 0; | |
ea6ba10b | 635 | void __iomem *mmio_base; |
1da177e4 LT |
636 | |
637 | VPRINTK("ENTER\n"); | |
638 | ||
0d5ff566 | 639 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
1da177e4 LT |
640 | VPRINTK("QUICK EXIT\n"); |
641 | return IRQ_NONE; | |
642 | } | |
643 | ||
0d5ff566 | 644 | mmio_base = host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
645 | |
646 | /* reading should also clear interrupts */ | |
647 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
648 | ||
649 | if (mask == 0xffffffff) { | |
650 | VPRINTK("QUICK EXIT 2\n"); | |
651 | return IRQ_NONE; | |
652 | } | |
6340f019 | 653 | |
cca3974e | 654 | spin_lock(&host->lock); |
6340f019 | 655 | |
1da177e4 LT |
656 | mask &= 0xffff; /* only 16 tags possible */ |
657 | if (!mask) { | |
658 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 659 | goto done_irq; |
1da177e4 LT |
660 | } |
661 | ||
1da177e4 LT |
662 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
663 | ||
cca3974e | 664 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 665 | VPRINTK("port %u\n", i); |
cca3974e | 666 | ap = host->ports[i]; |
1da177e4 | 667 | tmp = mask & (1 << (i + 1)); |
c1389503 | 668 | if (tmp && ap && |
029f5468 | 669 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
670 | struct ata_queued_cmd *qc; |
671 | ||
672 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 673 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
674 | handled += pdc_host_intr(ap, qc); |
675 | } | |
676 | } | |
677 | ||
1da177e4 LT |
678 | VPRINTK("EXIT\n"); |
679 | ||
6340f019 | 680 | done_irq: |
cca3974e | 681 | spin_unlock(&host->lock); |
1da177e4 LT |
682 | return IRQ_RETVAL(handled); |
683 | } | |
684 | ||
685 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
686 | { | |
687 | struct ata_port *ap = qc->ap; | |
688 | struct pdc_port_priv *pp = ap->private_data; | |
0d5ff566 | 689 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
690 | unsigned int port_no = ap->port_no; |
691 | u8 seq = (u8) (port_no + 1); | |
692 | ||
693 | VPRINTK("ENTER, ap %p\n", ap); | |
694 | ||
0d5ff566 TH |
695 | writel(0x00000001, mmio + (seq * 4)); |
696 | readl(mmio + (seq * 4)); /* flush */ | |
1da177e4 LT |
697 | |
698 | pp->pkt[2] = seq; | |
699 | wmb(); /* flush PRD, pkt writes */ | |
0d5ff566 TH |
700 | writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
701 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
702 | } |
703 | ||
9a3d9eb0 | 704 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
705 | { |
706 | switch (qc->tf.protocol) { | |
fba6edbd MP |
707 | case ATA_PROT_ATAPI_NODATA: |
708 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
709 | break; | |
710 | /*FALLTHROUGH*/ | |
95006188 | 711 | case ATA_PROT_ATAPI_DMA: |
1da177e4 LT |
712 | case ATA_PROT_DMA: |
713 | case ATA_PROT_NODATA: | |
714 | pdc_packet_start(qc); | |
715 | return 0; | |
716 | ||
1da177e4 LT |
717 | default: |
718 | break; | |
719 | } | |
720 | ||
721 | return ata_qc_issue_prot(qc); | |
722 | } | |
723 | ||
057ace5e | 724 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
725 | { |
726 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
727 | tf->protocol == ATA_PROT_NODATA); | |
728 | ata_tf_load(ap, tf); | |
729 | } | |
730 | ||
731 | ||
057ace5e | 732 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
733 | { |
734 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
735 | tf->protocol == ATA_PROT_NODATA); | |
736 | ata_exec_command(ap, tf); | |
737 | } | |
738 | ||
95006188 MP |
739 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
740 | { | |
741 | u8 *scsicmd = qc->scsicmd->cmnd; | |
742 | int pio = 1; /* atapi dma off by default */ | |
743 | ||
744 | /* Whitelist commands that may use DMA. */ | |
745 | switch (scsicmd[0]) { | |
746 | case WRITE_12: | |
747 | case WRITE_10: | |
748 | case WRITE_6: | |
749 | case READ_12: | |
750 | case READ_10: | |
751 | case READ_6: | |
752 | case 0xad: /* READ_DVD_STRUCTURE */ | |
753 | case 0xbe: /* READ_CD */ | |
754 | pio = 0; | |
755 | } | |
756 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
757 | if (scsicmd[0] == WRITE_10) { | |
758 | unsigned int lba; | |
759 | lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; | |
760 | if (lba >= 0xFFFF4FA2) | |
761 | pio = 1; | |
762 | } | |
763 | return pio; | |
764 | } | |
765 | ||
766 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc) | |
767 | { | |
768 | struct ata_port *ap = qc->ap; | |
769 | ||
770 | /* First generation chips cannot use ATAPI DMA on SATA ports */ | |
771 | if (sata_scr_valid(ap)) | |
772 | return 1; | |
773 | return pdc_check_atapi_dma(qc); | |
774 | } | |
1da177e4 | 775 | |
098cdff3 MP |
776 | static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base, |
777 | void __iomem *scr_addr) | |
1da177e4 LT |
778 | { |
779 | port->cmd_addr = base; | |
780 | port->data_addr = base; | |
781 | port->feature_addr = | |
782 | port->error_addr = base + 0x4; | |
783 | port->nsect_addr = base + 0x8; | |
784 | port->lbal_addr = base + 0xc; | |
785 | port->lbam_addr = base + 0x10; | |
786 | port->lbah_addr = base + 0x14; | |
787 | port->device_addr = base + 0x18; | |
788 | port->command_addr = | |
789 | port->status_addr = base + 0x1c; | |
790 | port->altstatus_addr = | |
791 | port->ctl_addr = base + 0x38; | |
098cdff3 | 792 | port->scr_addr = scr_addr; |
1da177e4 LT |
793 | } |
794 | ||
795 | ||
796 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
797 | { | |
0d5ff566 | 798 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
6340f019 | 799 | struct pdc_host_priv *hp = pe->private_data; |
d324d462 | 800 | int hotplug_offset; |
1da177e4 LT |
801 | u32 tmp; |
802 | ||
d324d462 MP |
803 | if (hp->flags & PDC_FLAG_GEN_II) |
804 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
805 | else | |
806 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
807 | ||
1da177e4 LT |
808 | /* |
809 | * Except for the hotplug stuff, this is voodoo from the | |
810 | * Promise driver. Label this entire section | |
811 | * "TODO: figure out why we do this" | |
812 | */ | |
813 | ||
b2d1eee1 | 814 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 815 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 MP |
816 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
817 | if (!(hp->flags & PDC_FLAG_GEN_II)) | |
818 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ | |
1da177e4 LT |
819 | writel(tmp, mmio + PDC_FLASH_CTL); |
820 | ||
821 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
822 | tmp = readl(mmio + hotplug_offset); |
823 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
824 | |
825 | /* mask plug/unplug ints */ | |
6340f019 LK |
826 | tmp = readl(mmio + hotplug_offset); |
827 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 | 828 | |
b2d1eee1 MP |
829 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
830 | if (hp->flags & PDC_FLAG_GEN_II) | |
831 | return; | |
832 | ||
1da177e4 LT |
833 | /* reduce TBG clock to 133 Mhz. */ |
834 | tmp = readl(mmio + PDC_TBG_MODE); | |
835 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
836 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
837 | writel(tmp, mmio + PDC_TBG_MODE); | |
838 | ||
839 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
840 | msleep(10); | |
841 | ||
842 | /* adjust slew rate control register. */ | |
843 | tmp = readl(mmio + PDC_SLEW_CTL); | |
844 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
845 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
846 | writel(tmp, mmio + PDC_SLEW_CTL); | |
847 | } | |
848 | ||
849 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
850 | { | |
851 | static int printed_version; | |
24dc5f33 | 852 | struct ata_probe_ent *probe_ent; |
6340f019 | 853 | struct pdc_host_priv *hp; |
0d5ff566 | 854 | void __iomem *base; |
1da177e4 | 855 | unsigned int board_idx = (unsigned int) ent->driver_data; |
1da177e4 | 856 | int rc; |
870ae337 | 857 | u8 tmp; |
1da177e4 LT |
858 | |
859 | if (!printed_version++) | |
a9524a76 | 860 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 861 | |
24dc5f33 | 862 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
863 | if (rc) |
864 | return rc; | |
865 | ||
0d5ff566 TH |
866 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
867 | if (rc == -EBUSY) | |
24dc5f33 | 868 | pcim_pin_device(pdev); |
0d5ff566 | 869 | if (rc) |
24dc5f33 | 870 | return rc; |
1da177e4 LT |
871 | |
872 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
873 | if (rc) | |
24dc5f33 | 874 | return rc; |
1da177e4 LT |
875 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
876 | if (rc) | |
24dc5f33 | 877 | return rc; |
1da177e4 | 878 | |
24dc5f33 TH |
879 | probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); |
880 | if (probe_ent == NULL) | |
881 | return -ENOMEM; | |
1da177e4 | 882 | |
1da177e4 LT |
883 | probe_ent->dev = pci_dev_to_dev(pdev); |
884 | INIT_LIST_HEAD(&probe_ent->node); | |
885 | ||
24dc5f33 TH |
886 | hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL); |
887 | if (hp == NULL) | |
888 | return -ENOMEM; | |
6340f019 | 889 | |
6340f019 LK |
890 | probe_ent->private_data = hp; |
891 | ||
1da177e4 | 892 | probe_ent->sht = pdc_port_info[board_idx].sht; |
cca3974e | 893 | probe_ent->port_flags = pdc_port_info[board_idx].flags; |
1da177e4 LT |
894 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; |
895 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
896 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
897 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
898 | ||
899 | probe_ent->irq = pdev->irq; | |
1d6f359a | 900 | probe_ent->irq_flags = IRQF_SHARED; |
0d5ff566 TH |
901 | probe_ent->iomap = pcim_iomap_table(pdev); |
902 | ||
903 | base = probe_ent->iomap[PDC_MMIO_BAR]; | |
1da177e4 | 904 | |
098cdff3 MP |
905 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200, base + 0x400); |
906 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280, base + 0x500); | |
1da177e4 LT |
907 | |
908 | /* notice 4-port boards */ | |
909 | switch (board_idx) { | |
6340f019 | 910 | case board_40518: |
b2d1eee1 | 911 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 912 | /* Fall through */ |
1da177e4 LT |
913 | case board_20319: |
914 | probe_ent->n_ports = 4; | |
098cdff3 MP |
915 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, base + 0x600); |
916 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, base + 0x700); | |
1da177e4 | 917 | break; |
6340f019 | 918 | case board_2057x: |
b2d1eee1 | 919 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 920 | /* Fall through */ |
1da177e4 | 921 | case board_2037x: |
870ae337 | 922 | /* TX2plus boards also have a PATA port */ |
0d5ff566 | 923 | tmp = readb(base + PDC_FLASH_CTL+1); |
870ae337 MP |
924 | if (!(tmp & 0x80)) { |
925 | probe_ent->n_ports = 3; | |
098cdff3 | 926 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL); |
870ae337 MP |
927 | hp->port_flags[2] = ATA_FLAG_SLAVE_POSS; |
928 | printk(KERN_INFO DRV_NAME " PATA port found\n"); | |
929 | } else | |
930 | probe_ent->n_ports = 2; | |
931 | hp->port_flags[0] = ATA_FLAG_SATA; | |
932 | hp->port_flags[1] = ATA_FLAG_SATA; | |
1da177e4 | 933 | break; |
f497ba73 TL |
934 | case board_20619: |
935 | probe_ent->n_ports = 4; | |
098cdff3 MP |
936 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL); |
937 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, NULL); | |
6c9e5eb5 | 938 | break; |
1da177e4 LT |
939 | default: |
940 | BUG(); | |
941 | break; | |
942 | } | |
943 | ||
944 | pci_set_master(pdev); | |
945 | ||
946 | /* initialize adapter */ | |
947 | pdc_host_init(board_idx, probe_ent); | |
948 | ||
6340f019 | 949 | if (!ata_device_add(probe_ent)) |
24dc5f33 | 950 | return -ENODEV; |
1da177e4 | 951 | |
24dc5f33 | 952 | devm_kfree(&pdev->dev, probe_ent); |
1da177e4 | 953 | return 0; |
1da177e4 LT |
954 | } |
955 | ||
956 | ||
957 | static int __init pdc_ata_init(void) | |
958 | { | |
b7887196 | 959 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
960 | } |
961 | ||
962 | ||
963 | static void __exit pdc_ata_exit(void) | |
964 | { | |
965 | pci_unregister_driver(&pdc_ata_pci_driver); | |
966 | } | |
967 | ||
968 | ||
969 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 970 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
971 | MODULE_LICENSE("GPL"); |
972 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
973 | MODULE_VERSION(DRV_VERSION); | |
974 | ||
975 | module_init(pdc_ata_init); | |
976 | module_exit(pdc_ata_exit); |