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20f733e7 BR |
1 | /* |
2 | * sata_mv.c - Marvell SATA support | |
3 | * | |
40f21b11 | 4 | * Copyright 2008-2009: Marvell Corporation, all rights reserved. |
8b260248 | 5 | * Copyright 2005: EMC Corporation, all rights reserved. |
e2b1be56 | 6 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
20f733e7 | 7 | * |
40f21b11 ML |
8 | * Originally written by Brett Russ. |
9 | * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. | |
10 | * | |
20f733e7 BR |
11 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; version 2 of the License. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | */ | |
27 | ||
4a05e209 | 28 | /* |
85afb934 ML |
29 | * sata_mv TODO list: |
30 | * | |
85afb934 ML |
31 | * --> Develop a low-power-consumption strategy, and implement it. |
32 | * | |
2b748a0a | 33 | * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. |
85afb934 ML |
34 | * |
35 | * --> [Experiment, Marvell value added] Is it possible to use target | |
36 | * mode to cross-connect two Linux boxes with Marvell cards? If so, | |
37 | * creating LibATA target mode support would be very interesting. | |
38 | * | |
39 | * Target mode, for those without docs, is the ability to directly | |
40 | * connect two SATA ports. | |
41 | */ | |
4a05e209 | 42 | |
65ad7fef ML |
43 | /* |
44 | * 80x1-B2 errata PCI#11: | |
45 | * | |
46 | * Users of the 6041/6081 Rev.B2 chips (current is C0) | |
47 | * should be careful to insert those cards only onto PCI-X bus #0, | |
48 | * and only in device slots 0..7, not higher. The chips may not | |
49 | * work correctly otherwise (note: this is a pretty rare condition). | |
50 | */ | |
51 | ||
20f733e7 BR |
52 | #include <linux/kernel.h> |
53 | #include <linux/module.h> | |
54 | #include <linux/pci.h> | |
55 | #include <linux/init.h> | |
56 | #include <linux/blkdev.h> | |
57 | #include <linux/delay.h> | |
58 | #include <linux/interrupt.h> | |
8d8b6004 | 59 | #include <linux/dmapool.h> |
20f733e7 | 60 | #include <linux/dma-mapping.h> |
a9524a76 | 61 | #include <linux/device.h> |
c77a2f4e | 62 | #include <linux/clk.h> |
f351b2d6 SB |
63 | #include <linux/platform_device.h> |
64 | #include <linux/ata_platform.h> | |
15a32632 | 65 | #include <linux/mbus.h> |
c46938cc | 66 | #include <linux/bitops.h> |
20f733e7 | 67 | #include <scsi/scsi_host.h> |
193515d5 | 68 | #include <scsi/scsi_cmnd.h> |
6c08772e | 69 | #include <scsi/scsi_device.h> |
20f733e7 | 70 | #include <linux/libata.h> |
20f733e7 BR |
71 | |
72 | #define DRV_NAME "sata_mv" | |
cae5a29d | 73 | #define DRV_VERSION "1.28" |
20f733e7 | 74 | |
40f21b11 ML |
75 | /* |
76 | * module options | |
77 | */ | |
78 | ||
79 | static int msi; | |
80 | #ifdef CONFIG_PCI | |
81 | module_param(msi, int, S_IRUGO); | |
82 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); | |
83 | #endif | |
84 | ||
2b748a0a ML |
85 | static int irq_coalescing_io_count; |
86 | module_param(irq_coalescing_io_count, int, S_IRUGO); | |
87 | MODULE_PARM_DESC(irq_coalescing_io_count, | |
88 | "IRQ coalescing I/O count threshold (0..255)"); | |
89 | ||
90 | static int irq_coalescing_usecs; | |
91 | module_param(irq_coalescing_usecs, int, S_IRUGO); | |
92 | MODULE_PARM_DESC(irq_coalescing_usecs, | |
93 | "IRQ coalescing time threshold in usecs"); | |
94 | ||
20f733e7 BR |
95 | enum { |
96 | /* BAR's are enumerated in terms of pci_resource_start() terms */ | |
97 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ | |
98 | MV_IO_BAR = 2, /* offset 0x18: IO space */ | |
99 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ | |
100 | ||
101 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ | |
102 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ | |
103 | ||
2b748a0a ML |
104 | /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ |
105 | COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ | |
106 | MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ | |
107 | MAX_COAL_IO_COUNT = 255, /* completed I/O count */ | |
108 | ||
20f733e7 | 109 | MV_PCI_REG_BASE = 0, |
615ab953 | 110 | |
2b748a0a ML |
111 | /* |
112 | * Per-chip ("all ports") interrupt coalescing feature. | |
113 | * This is only for GEN_II / GEN_IIE hardware. | |
114 | * | |
115 | * Coalescing defers the interrupt until either the IO_THRESHOLD | |
116 | * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. | |
117 | */ | |
cae5a29d ML |
118 | COAL_REG_BASE = 0x18000, |
119 | IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), | |
2b748a0a ML |
120 | ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ |
121 | ||
cae5a29d ML |
122 | IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), |
123 | IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), | |
2b748a0a ML |
124 | |
125 | /* | |
126 | * Registers for the (unused here) transaction coalescing feature: | |
127 | */ | |
cae5a29d ML |
128 | TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), |
129 | TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), | |
2b748a0a | 130 | |
cae5a29d ML |
131 | SATAHC0_REG_BASE = 0x20000, |
132 | FLASH_CTL = 0x1046c, | |
133 | GPIO_PORT_CTL = 0x104f0, | |
134 | RESET_CFG = 0x180d8, | |
20f733e7 BR |
135 | |
136 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
137 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
138 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ | |
139 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, | |
140 | ||
31961943 BR |
141 | MV_MAX_Q_DEPTH = 32, |
142 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, | |
143 | ||
144 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB | |
145 | * CRPB needs alignment on a 256B boundary. Size == 256B | |
31961943 BR |
146 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B |
147 | */ | |
148 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), | |
149 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), | |
da2fa9ba | 150 | MV_MAX_SG_CT = 256, |
31961943 | 151 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), |
31961943 | 152 | |
352fab70 | 153 | /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ |
20f733e7 | 154 | MV_PORT_HC_SHIFT = 2, |
352fab70 ML |
155 | MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ |
156 | /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ | |
157 | MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ | |
20f733e7 BR |
158 | |
159 | /* Host Flags */ | |
160 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ | |
7bb3c529 | 161 | |
c5d3e45a | 162 | MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
91b1a84c | 163 | ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, |
ad3aef51 | 164 | |
91b1a84c | 165 | MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, |
20f733e7 | 166 | |
40f21b11 ML |
167 | MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | |
168 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, | |
91b1a84c ML |
169 | |
170 | MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, | |
ad3aef51 | 171 | |
31961943 BR |
172 | CRQB_FLAG_READ = (1 << 0), |
173 | CRQB_TAG_SHIFT = 1, | |
c5d3e45a | 174 | CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ |
e12bef50 | 175 | CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ |
c5d3e45a | 176 | CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ |
31961943 BR |
177 | CRQB_CMD_ADDR_SHIFT = 8, |
178 | CRQB_CMD_CS = (0x2 << 11), | |
179 | CRQB_CMD_LAST = (1 << 15), | |
180 | ||
181 | CRPB_FLAG_STATUS_SHIFT = 8, | |
c5d3e45a JG |
182 | CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ |
183 | CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ | |
31961943 BR |
184 | |
185 | EPRD_FLAG_END_OF_TBL = (1 << 31), | |
186 | ||
20f733e7 BR |
187 | /* PCI interface registers */ |
188 | ||
cae5a29d ML |
189 | MV_PCI_COMMAND = 0xc00, |
190 | MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ | |
191 | MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ | |
31961943 | 192 | |
cae5a29d | 193 | PCI_MAIN_CMD_STS = 0xd30, |
20f733e7 BR |
194 | STOP_PCI_MASTER = (1 << 2), |
195 | PCI_MASTER_EMPTY = (1 << 3), | |
196 | GLOB_SFT_RST = (1 << 4), | |
197 | ||
cae5a29d | 198 | MV_PCI_MODE = 0xd00, |
8e7decdb ML |
199 | MV_PCI_MODE_MASK = 0x30, |
200 | ||
522479fb JG |
201 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, |
202 | MV_PCI_DISC_TIMER = 0xd04, | |
203 | MV_PCI_MSI_TRIGGER = 0xc38, | |
204 | MV_PCI_SERR_MASK = 0xc28, | |
cae5a29d | 205 | MV_PCI_XBAR_TMOUT = 0x1d04, |
522479fb JG |
206 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, |
207 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, | |
208 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, | |
209 | MV_PCI_ERR_COMMAND = 0x1d50, | |
210 | ||
cae5a29d ML |
211 | PCI_IRQ_CAUSE = 0x1d58, |
212 | PCI_IRQ_MASK = 0x1d5c, | |
20f733e7 BR |
213 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
214 | ||
cae5a29d ML |
215 | PCIE_IRQ_CAUSE = 0x1900, |
216 | PCIE_IRQ_MASK = 0x1910, | |
646a4da5 | 217 | PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ |
02a121da | 218 | |
7368f919 | 219 | /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ |
cae5a29d ML |
220 | PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, |
221 | PCI_HC_MAIN_IRQ_MASK = 0x1d64, | |
222 | SOC_HC_MAIN_IRQ_CAUSE = 0x20020, | |
223 | SOC_HC_MAIN_IRQ_MASK = 0x20024, | |
40f21b11 ML |
224 | ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ |
225 | DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ | |
20f733e7 BR |
226 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ |
227 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ | |
2b748a0a ML |
228 | DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ |
229 | DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ | |
20f733e7 | 230 | PCI_ERR = (1 << 18), |
40f21b11 ML |
231 | TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ |
232 | TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ | |
233 | PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ | |
234 | PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ | |
235 | ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ | |
20f733e7 BR |
236 | GPIO_INT = (1 << 22), |
237 | SELF_INT = (1 << 23), | |
238 | TWSI_INT = (1 << 24), | |
239 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ | |
fb621e2f | 240 | HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ |
e12bef50 | 241 | HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ |
20f733e7 BR |
242 | |
243 | /* SATAHC registers */ | |
cae5a29d | 244 | HC_CFG = 0x00, |
20f733e7 | 245 | |
cae5a29d | 246 | HC_IRQ_CAUSE = 0x14, |
352fab70 ML |
247 | DMA_IRQ = (1 << 0), /* shift by port # */ |
248 | HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ | |
20f733e7 BR |
249 | DEV_IRQ = (1 << 8), /* shift by port # */ |
250 | ||
2b748a0a ML |
251 | /* |
252 | * Per-HC (Host-Controller) interrupt coalescing feature. | |
253 | * This is present on all chip generations. | |
254 | * | |
255 | * Coalescing defers the interrupt until either the IO_THRESHOLD | |
256 | * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. | |
257 | */ | |
cae5a29d ML |
258 | HC_IRQ_COAL_IO_THRESHOLD = 0x000c, |
259 | HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, | |
2b748a0a | 260 | |
cae5a29d | 261 | SOC_LED_CTRL = 0x2c, |
000b344f ML |
262 | SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ |
263 | SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ | |
264 | /* with dev activity LED */ | |
265 | ||
20f733e7 | 266 | /* Shadow block registers */ |
cae5a29d ML |
267 | SHD_BLK = 0x100, |
268 | SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ | |
20f733e7 BR |
269 | |
270 | /* SATA registers */ | |
cae5a29d ML |
271 | SATA_STATUS = 0x300, /* ctrl, err regs follow status */ |
272 | SATA_ACTIVE = 0x350, | |
273 | FIS_IRQ_CAUSE = 0x364, | |
274 | FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ | |
17c5aab5 | 275 | |
cae5a29d | 276 | LTMODE = 0x30c, /* requires read-after-write */ |
17c5aab5 ML |
277 | LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ |
278 | ||
cae5a29d | 279 | PHY_MODE2 = 0x330, |
47c2b677 | 280 | PHY_MODE3 = 0x310, |
cae5a29d ML |
281 | |
282 | PHY_MODE4 = 0x314, /* requires read-after-write */ | |
ba069e37 ML |
283 | PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ |
284 | PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ | |
285 | PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ | |
286 | PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ | |
287 | ||
cae5a29d ML |
288 | SATA_IFCTL = 0x344, |
289 | SATA_TESTCTL = 0x348, | |
290 | SATA_IFSTAT = 0x34c, | |
291 | VENDOR_UNIQUE_FIS = 0x35c, | |
17c5aab5 | 292 | |
cae5a29d | 293 | FISCFG = 0x360, |
8e7decdb ML |
294 | FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ |
295 | FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ | |
17c5aab5 | 296 | |
29b7e43c MM |
297 | PHY_MODE9_GEN2 = 0x398, |
298 | PHY_MODE9_GEN1 = 0x39c, | |
299 | PHYCFG_OFS = 0x3a0, /* only in 65n devices */ | |
300 | ||
c9d39130 | 301 | MV5_PHY_MODE = 0x74, |
cae5a29d ML |
302 | MV5_LTMODE = 0x30, |
303 | MV5_PHY_CTL = 0x0C, | |
304 | SATA_IFCFG = 0x050, | |
bca1c4eb JG |
305 | |
306 | MV_M2_PREAMP_MASK = 0x7e0, | |
20f733e7 BR |
307 | |
308 | /* Port registers */ | |
cae5a29d | 309 | EDMA_CFG = 0, |
0c58912e ML |
310 | EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ |
311 | EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ | |
312 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ | |
313 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ | |
314 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ | |
e12bef50 ML |
315 | EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ |
316 | EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ | |
20f733e7 | 317 | |
cae5a29d ML |
318 | EDMA_ERR_IRQ_CAUSE = 0x8, |
319 | EDMA_ERR_IRQ_MASK = 0xc, | |
6c1153e0 JG |
320 | EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ |
321 | EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ | |
322 | EDMA_ERR_DEV = (1 << 2), /* device error */ | |
323 | EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ | |
324 | EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ | |
325 | EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ | |
c5d3e45a JG |
326 | EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ |
327 | EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ | |
6c1153e0 | 328 | EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ |
c5d3e45a | 329 | EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ |
6c1153e0 JG |
330 | EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ |
331 | EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ | |
332 | EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ | |
333 | EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ | |
646a4da5 | 334 | |
6c1153e0 | 335 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ |
646a4da5 ML |
336 | EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ |
337 | EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ | |
338 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ | |
339 | EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ | |
340 | ||
6c1153e0 | 341 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ |
646a4da5 | 342 | |
6c1153e0 | 343 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ |
646a4da5 ML |
344 | EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ |
345 | EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ | |
346 | EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ | |
347 | EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ | |
348 | EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ | |
349 | ||
6c1153e0 | 350 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ |
646a4da5 | 351 | |
6c1153e0 | 352 | EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ |
c5d3e45a JG |
353 | EDMA_ERR_OVERRUN_5 = (1 << 5), |
354 | EDMA_ERR_UNDERRUN_5 = (1 << 6), | |
646a4da5 ML |
355 | |
356 | EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | | |
357 | EDMA_ERR_LNK_CTRL_RX_1 | | |
358 | EDMA_ERR_LNK_CTRL_RX_3 | | |
85afb934 | 359 | EDMA_ERR_LNK_CTRL_TX, |
646a4da5 | 360 | |
bdd4ddde JG |
361 | EDMA_EH_FREEZE = EDMA_ERR_D_PAR | |
362 | EDMA_ERR_PRD_PAR | | |
363 | EDMA_ERR_DEV_DCON | | |
364 | EDMA_ERR_DEV_CON | | |
365 | EDMA_ERR_SERR | | |
366 | EDMA_ERR_SELF_DIS | | |
6c1153e0 | 367 | EDMA_ERR_CRQB_PAR | |
bdd4ddde JG |
368 | EDMA_ERR_CRPB_PAR | |
369 | EDMA_ERR_INTRL_PAR | | |
370 | EDMA_ERR_IORDY | | |
371 | EDMA_ERR_LNK_CTRL_RX_2 | | |
372 | EDMA_ERR_LNK_DATA_RX | | |
373 | EDMA_ERR_LNK_DATA_TX | | |
374 | EDMA_ERR_TRANS_PROTO, | |
e12bef50 | 375 | |
bdd4ddde JG |
376 | EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | |
377 | EDMA_ERR_PRD_PAR | | |
378 | EDMA_ERR_DEV_DCON | | |
379 | EDMA_ERR_DEV_CON | | |
380 | EDMA_ERR_OVERRUN_5 | | |
381 | EDMA_ERR_UNDERRUN_5 | | |
382 | EDMA_ERR_SELF_DIS_5 | | |
6c1153e0 | 383 | EDMA_ERR_CRQB_PAR | |
bdd4ddde JG |
384 | EDMA_ERR_CRPB_PAR | |
385 | EDMA_ERR_INTRL_PAR | | |
386 | EDMA_ERR_IORDY, | |
20f733e7 | 387 | |
cae5a29d ML |
388 | EDMA_REQ_Q_BASE_HI = 0x10, |
389 | EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ | |
31961943 | 390 | |
cae5a29d | 391 | EDMA_REQ_Q_OUT_PTR = 0x18, |
31961943 BR |
392 | EDMA_REQ_Q_PTR_SHIFT = 5, |
393 | ||
cae5a29d ML |
394 | EDMA_RSP_Q_BASE_HI = 0x1c, |
395 | EDMA_RSP_Q_IN_PTR = 0x20, | |
396 | EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ | |
31961943 BR |
397 | EDMA_RSP_Q_PTR_SHIFT = 3, |
398 | ||
cae5a29d | 399 | EDMA_CMD = 0x28, /* EDMA command register */ |
0ea9e179 JG |
400 | EDMA_EN = (1 << 0), /* enable EDMA */ |
401 | EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ | |
8e7decdb ML |
402 | EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ |
403 | ||
cae5a29d | 404 | EDMA_STATUS = 0x30, /* EDMA engine status */ |
8e7decdb ML |
405 | EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ |
406 | EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ | |
20f733e7 | 407 | |
cae5a29d ML |
408 | EDMA_IORDY_TMOUT = 0x34, |
409 | EDMA_ARB_CFG = 0x38, | |
8e7decdb | 410 | |
cae5a29d ML |
411 | EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ |
412 | EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ | |
da14265e | 413 | |
cae5a29d ML |
414 | BMDMA_CMD = 0x224, /* bmdma command register */ |
415 | BMDMA_STATUS = 0x228, /* bmdma status register */ | |
416 | BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ | |
417 | BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ | |
da14265e | 418 | |
31961943 BR |
419 | /* Host private flags (hp_flags) */ |
420 | MV_HP_FLAG_MSI = (1 << 0), | |
47c2b677 JG |
421 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
422 | MV_HP_ERRATA_50XXB2 = (1 << 2), | |
423 | MV_HP_ERRATA_60X1B2 = (1 << 3), | |
424 | MV_HP_ERRATA_60X1C0 = (1 << 4), | |
0ea9e179 JG |
425 | MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ |
426 | MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ | |
427 | MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ | |
02a121da | 428 | MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ |
616d4a98 | 429 | MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ |
1f398472 | 430 | MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ |
000b344f | 431 | MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ |
20f733e7 | 432 | |
31961943 | 433 | /* Port private flags (pp_flags) */ |
0ea9e179 | 434 | MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ |
72109168 | 435 | MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ |
00f42eab | 436 | MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ |
29d187bb | 437 | MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ |
d16ab3f6 | 438 | MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ |
20f733e7 BR |
439 | }; |
440 | ||
ee9ccdf7 JG |
441 | #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) |
442 | #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) | |
e4e7b892 | 443 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) |
8e7decdb | 444 | #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) |
1f398472 | 445 | #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) |
bca1c4eb | 446 | |
15a32632 LB |
447 | #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) |
448 | #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) | |
449 | ||
095fec88 | 450 | enum { |
baf14aa1 JG |
451 | /* DMA boundary 0xffff is required by the s/g splitting |
452 | * we need on /length/ in mv_fill-sg(). | |
453 | */ | |
454 | MV_DMA_BOUNDARY = 0xffffU, | |
095fec88 | 455 | |
0ea9e179 JG |
456 | /* mask of register bits containing lower 32 bits |
457 | * of EDMA request queue DMA address | |
458 | */ | |
095fec88 JG |
459 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, |
460 | ||
0ea9e179 | 461 | /* ditto, for response queue */ |
095fec88 JG |
462 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, |
463 | }; | |
464 | ||
522479fb JG |
465 | enum chip_type { |
466 | chip_504x, | |
467 | chip_508x, | |
468 | chip_5080, | |
469 | chip_604x, | |
470 | chip_608x, | |
e4e7b892 JG |
471 | chip_6042, |
472 | chip_7042, | |
f351b2d6 | 473 | chip_soc, |
522479fb JG |
474 | }; |
475 | ||
31961943 BR |
476 | /* Command ReQuest Block: 32B */ |
477 | struct mv_crqb { | |
e1469874 ML |
478 | __le32 sg_addr; |
479 | __le32 sg_addr_hi; | |
480 | __le16 ctrl_flags; | |
481 | __le16 ata_cmd[11]; | |
31961943 | 482 | }; |
20f733e7 | 483 | |
e4e7b892 | 484 | struct mv_crqb_iie { |
e1469874 ML |
485 | __le32 addr; |
486 | __le32 addr_hi; | |
487 | __le32 flags; | |
488 | __le32 len; | |
489 | __le32 ata_cmd[4]; | |
e4e7b892 JG |
490 | }; |
491 | ||
31961943 BR |
492 | /* Command ResPonse Block: 8B */ |
493 | struct mv_crpb { | |
e1469874 ML |
494 | __le16 id; |
495 | __le16 flags; | |
496 | __le32 tmstmp; | |
20f733e7 BR |
497 | }; |
498 | ||
31961943 BR |
499 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
500 | struct mv_sg { | |
e1469874 ML |
501 | __le32 addr; |
502 | __le32 flags_size; | |
503 | __le32 addr_hi; | |
504 | __le32 reserved; | |
31961943 | 505 | }; |
20f733e7 | 506 | |
08da1759 ML |
507 | /* |
508 | * We keep a local cache of a few frequently accessed port | |
509 | * registers here, to avoid having to read them (very slow) | |
510 | * when switching between EDMA and non-EDMA modes. | |
511 | */ | |
512 | struct mv_cached_regs { | |
513 | u32 fiscfg; | |
514 | u32 ltmode; | |
515 | u32 haltcond; | |
c01e8a23 | 516 | u32 unknown_rsvd; |
08da1759 ML |
517 | }; |
518 | ||
31961943 BR |
519 | struct mv_port_priv { |
520 | struct mv_crqb *crqb; | |
521 | dma_addr_t crqb_dma; | |
522 | struct mv_crpb *crpb; | |
523 | dma_addr_t crpb_dma; | |
eb73d558 ML |
524 | struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; |
525 | dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; | |
bdd4ddde JG |
526 | |
527 | unsigned int req_idx; | |
528 | unsigned int resp_idx; | |
529 | ||
31961943 | 530 | u32 pp_flags; |
08da1759 | 531 | struct mv_cached_regs cached; |
29d187bb | 532 | unsigned int delayed_eh_pmp_map; |
31961943 BR |
533 | }; |
534 | ||
bca1c4eb JG |
535 | struct mv_port_signal { |
536 | u32 amps; | |
537 | u32 pre; | |
538 | }; | |
539 | ||
02a121da ML |
540 | struct mv_host_priv { |
541 | u32 hp_flags; | |
96e2c487 | 542 | u32 main_irq_mask; |
02a121da ML |
543 | struct mv_port_signal signal[8]; |
544 | const struct mv_hw_ops *ops; | |
f351b2d6 SB |
545 | int n_ports; |
546 | void __iomem *base; | |
7368f919 ML |
547 | void __iomem *main_irq_cause_addr; |
548 | void __iomem *main_irq_mask_addr; | |
cae5a29d ML |
549 | u32 irq_cause_offset; |
550 | u32 irq_mask_offset; | |
02a121da | 551 | u32 unmask_all_irqs; |
c77a2f4e SB |
552 | |
553 | #if defined(CONFIG_HAVE_CLK) | |
554 | struct clk *clk; | |
555 | #endif | |
da2fa9ba ML |
556 | /* |
557 | * These consistent DMA memory pools give us guaranteed | |
558 | * alignment for hardware-accessed data structures, | |
559 | * and less memory waste in accomplishing the alignment. | |
560 | */ | |
561 | struct dma_pool *crqb_pool; | |
562 | struct dma_pool *crpb_pool; | |
563 | struct dma_pool *sg_tbl_pool; | |
02a121da ML |
564 | }; |
565 | ||
47c2b677 | 566 | struct mv_hw_ops { |
2a47ce06 JG |
567 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
568 | unsigned int port); | |
47c2b677 JG |
569 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
570 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, | |
571 | void __iomem *mmio); | |
c9d39130 JG |
572 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, |
573 | unsigned int n_hc); | |
522479fb | 574 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
7bb3c529 | 575 | void (*reset_bus)(struct ata_host *host, void __iomem *mmio); |
47c2b677 JG |
576 | }; |
577 | ||
82ef04fb TH |
578 | static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); |
579 | static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); | |
580 | static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); | |
581 | static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); | |
31961943 BR |
582 | static int mv_port_start(struct ata_port *ap); |
583 | static void mv_port_stop(struct ata_port *ap); | |
3e4a1391 | 584 | static int mv_qc_defer(struct ata_queued_cmd *qc); |
31961943 | 585 | static void mv_qc_prep(struct ata_queued_cmd *qc); |
e4e7b892 | 586 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); |
9a3d9eb0 | 587 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
a1efdaba TH |
588 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
589 | unsigned long deadline); | |
bdd4ddde JG |
590 | static void mv_eh_freeze(struct ata_port *ap); |
591 | static void mv_eh_thaw(struct ata_port *ap); | |
f273827e | 592 | static void mv6_dev_config(struct ata_device *dev); |
20f733e7 | 593 | |
2a47ce06 JG |
594 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
595 | unsigned int port); | |
47c2b677 JG |
596 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
597 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, | |
598 | void __iomem *mmio); | |
c9d39130 JG |
599 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
600 | unsigned int n_hc); | |
522479fb | 601 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
7bb3c529 | 602 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); |
47c2b677 | 603 | |
2a47ce06 JG |
604 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
605 | unsigned int port); | |
47c2b677 JG |
606 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
607 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, | |
608 | void __iomem *mmio); | |
c9d39130 JG |
609 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
610 | unsigned int n_hc); | |
522479fb | 611 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
f351b2d6 SB |
612 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, |
613 | void __iomem *mmio); | |
614 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, | |
615 | void __iomem *mmio); | |
616 | static int mv_soc_reset_hc(struct mv_host_priv *hpriv, | |
617 | void __iomem *mmio, unsigned int n_hc); | |
618 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, | |
619 | void __iomem *mmio); | |
620 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); | |
29b7e43c MM |
621 | static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, |
622 | void __iomem *mmio, unsigned int port); | |
7bb3c529 | 623 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); |
e12bef50 | 624 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
c9d39130 | 625 | unsigned int port_no); |
e12bef50 | 626 | static int mv_stop_edma(struct ata_port *ap); |
b562468c | 627 | static int mv_stop_edma_engine(void __iomem *port_mmio); |
00b81235 | 628 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); |
47c2b677 | 629 | |
e49856d8 ML |
630 | static void mv_pmp_select(struct ata_port *ap, int pmp); |
631 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, | |
632 | unsigned long deadline); | |
633 | static int mv_softreset(struct ata_link *link, unsigned int *class, | |
634 | unsigned long deadline); | |
29d187bb | 635 | static void mv_pmp_error_handler(struct ata_port *ap); |
4c299ca3 ML |
636 | static void mv_process_crpb_entries(struct ata_port *ap, |
637 | struct mv_port_priv *pp); | |
47c2b677 | 638 | |
da14265e ML |
639 | static void mv_sff_irq_clear(struct ata_port *ap); |
640 | static int mv_check_atapi_dma(struct ata_queued_cmd *qc); | |
641 | static void mv_bmdma_setup(struct ata_queued_cmd *qc); | |
642 | static void mv_bmdma_start(struct ata_queued_cmd *qc); | |
643 | static void mv_bmdma_stop(struct ata_queued_cmd *qc); | |
644 | static u8 mv_bmdma_status(struct ata_port *ap); | |
d16ab3f6 | 645 | static u8 mv_sff_check_status(struct ata_port *ap); |
da14265e | 646 | |
eb73d558 ML |
647 | /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below |
648 | * because we have to allow room for worst case splitting of | |
649 | * PRDs for 64K boundaries in mv_fill_sg(). | |
650 | */ | |
c5d3e45a | 651 | static struct scsi_host_template mv5_sht = { |
68d1d07b | 652 | ATA_BASE_SHT(DRV_NAME), |
baf14aa1 | 653 | .sg_tablesize = MV_MAX_SG_CT / 2, |
c5d3e45a | 654 | .dma_boundary = MV_DMA_BOUNDARY, |
c5d3e45a JG |
655 | }; |
656 | ||
657 | static struct scsi_host_template mv6_sht = { | |
68d1d07b | 658 | ATA_NCQ_SHT(DRV_NAME), |
138bfdd0 | 659 | .can_queue = MV_MAX_Q_DEPTH - 1, |
baf14aa1 | 660 | .sg_tablesize = MV_MAX_SG_CT / 2, |
20f733e7 | 661 | .dma_boundary = MV_DMA_BOUNDARY, |
20f733e7 BR |
662 | }; |
663 | ||
029cfd6b TH |
664 | static struct ata_port_operations mv5_ops = { |
665 | .inherits = &ata_sff_port_ops, | |
c9d39130 | 666 | |
c96f1732 AC |
667 | .lost_interrupt = ATA_OP_NULL, |
668 | ||
3e4a1391 | 669 | .qc_defer = mv_qc_defer, |
c9d39130 JG |
670 | .qc_prep = mv_qc_prep, |
671 | .qc_issue = mv_qc_issue, | |
c9d39130 | 672 | |
bdd4ddde JG |
673 | .freeze = mv_eh_freeze, |
674 | .thaw = mv_eh_thaw, | |
a1efdaba | 675 | .hardreset = mv_hardreset, |
a1efdaba | 676 | .error_handler = ata_std_error_handler, /* avoid SFF EH */ |
029cfd6b | 677 | .post_internal_cmd = ATA_OP_NULL, |
bdd4ddde | 678 | |
c9d39130 JG |
679 | .scr_read = mv5_scr_read, |
680 | .scr_write = mv5_scr_write, | |
681 | ||
682 | .port_start = mv_port_start, | |
683 | .port_stop = mv_port_stop, | |
c9d39130 JG |
684 | }; |
685 | ||
029cfd6b TH |
686 | static struct ata_port_operations mv6_ops = { |
687 | .inherits = &mv5_ops, | |
f273827e | 688 | .dev_config = mv6_dev_config, |
20f733e7 BR |
689 | .scr_read = mv_scr_read, |
690 | .scr_write = mv_scr_write, | |
691 | ||
e49856d8 ML |
692 | .pmp_hardreset = mv_pmp_hardreset, |
693 | .pmp_softreset = mv_softreset, | |
694 | .softreset = mv_softreset, | |
29d187bb | 695 | .error_handler = mv_pmp_error_handler, |
da14265e | 696 | |
40f21b11 | 697 | .sff_check_status = mv_sff_check_status, |
da14265e ML |
698 | .sff_irq_clear = mv_sff_irq_clear, |
699 | .check_atapi_dma = mv_check_atapi_dma, | |
700 | .bmdma_setup = mv_bmdma_setup, | |
701 | .bmdma_start = mv_bmdma_start, | |
702 | .bmdma_stop = mv_bmdma_stop, | |
703 | .bmdma_status = mv_bmdma_status, | |
20f733e7 BR |
704 | }; |
705 | ||
029cfd6b TH |
706 | static struct ata_port_operations mv_iie_ops = { |
707 | .inherits = &mv6_ops, | |
708 | .dev_config = ATA_OP_NULL, | |
e4e7b892 | 709 | .qc_prep = mv_qc_prep_iie, |
e4e7b892 JG |
710 | }; |
711 | ||
98ac62de | 712 | static const struct ata_port_info mv_port_info[] = { |
20f733e7 | 713 | { /* chip_504x */ |
91b1a84c | 714 | .flags = MV_GEN_I_FLAGS, |
c361acbc | 715 | .pio_mask = ATA_PIO4, |
bf6263a8 | 716 | .udma_mask = ATA_UDMA6, |
c9d39130 | 717 | .port_ops = &mv5_ops, |
20f733e7 BR |
718 | }, |
719 | { /* chip_508x */ | |
91b1a84c | 720 | .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 721 | .pio_mask = ATA_PIO4, |
bf6263a8 | 722 | .udma_mask = ATA_UDMA6, |
c9d39130 | 723 | .port_ops = &mv5_ops, |
20f733e7 | 724 | }, |
47c2b677 | 725 | { /* chip_5080 */ |
91b1a84c | 726 | .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 727 | .pio_mask = ATA_PIO4, |
bf6263a8 | 728 | .udma_mask = ATA_UDMA6, |
c9d39130 | 729 | .port_ops = &mv5_ops, |
47c2b677 | 730 | }, |
20f733e7 | 731 | { /* chip_604x */ |
91b1a84c | 732 | .flags = MV_GEN_II_FLAGS, |
c361acbc | 733 | .pio_mask = ATA_PIO4, |
bf6263a8 | 734 | .udma_mask = ATA_UDMA6, |
c9d39130 | 735 | .port_ops = &mv6_ops, |
20f733e7 BR |
736 | }, |
737 | { /* chip_608x */ | |
91b1a84c | 738 | .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 739 | .pio_mask = ATA_PIO4, |
bf6263a8 | 740 | .udma_mask = ATA_UDMA6, |
c9d39130 | 741 | .port_ops = &mv6_ops, |
20f733e7 | 742 | }, |
e4e7b892 | 743 | { /* chip_6042 */ |
91b1a84c | 744 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 745 | .pio_mask = ATA_PIO4, |
bf6263a8 | 746 | .udma_mask = ATA_UDMA6, |
e4e7b892 JG |
747 | .port_ops = &mv_iie_ops, |
748 | }, | |
749 | { /* chip_7042 */ | |
91b1a84c | 750 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 751 | .pio_mask = ATA_PIO4, |
bf6263a8 | 752 | .udma_mask = ATA_UDMA6, |
e4e7b892 JG |
753 | .port_ops = &mv_iie_ops, |
754 | }, | |
f351b2d6 | 755 | { /* chip_soc */ |
91b1a84c | 756 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 757 | .pio_mask = ATA_PIO4, |
17c5aab5 ML |
758 | .udma_mask = ATA_UDMA6, |
759 | .port_ops = &mv_iie_ops, | |
f351b2d6 | 760 | }, |
20f733e7 BR |
761 | }; |
762 | ||
3b7d697d | 763 | static const struct pci_device_id mv_pci_tbl[] = { |
2d2744fc JG |
764 | { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, |
765 | { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, | |
766 | { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, | |
767 | { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, | |
46c5784c ML |
768 | /* RocketRAID 1720/174x have different identifiers */ |
769 | { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, | |
4462254a ML |
770 | { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, |
771 | { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, | |
2d2744fc JG |
772 | |
773 | { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, | |
774 | { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, | |
775 | { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, | |
776 | { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, | |
777 | { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, | |
778 | ||
779 | { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, | |
780 | ||
d9f9c6bc FA |
781 | /* Adaptec 1430SA */ |
782 | { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, | |
783 | ||
02a121da | 784 | /* Marvell 7042 support */ |
6a3d586d MT |
785 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, |
786 | ||
02a121da ML |
787 | /* Highpoint RocketRAID PCIe series */ |
788 | { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, | |
789 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, | |
790 | ||
2d2744fc | 791 | { } /* terminate list */ |
20f733e7 BR |
792 | }; |
793 | ||
47c2b677 JG |
794 | static const struct mv_hw_ops mv5xxx_ops = { |
795 | .phy_errata = mv5_phy_errata, | |
796 | .enable_leds = mv5_enable_leds, | |
797 | .read_preamp = mv5_read_preamp, | |
798 | .reset_hc = mv5_reset_hc, | |
522479fb JG |
799 | .reset_flash = mv5_reset_flash, |
800 | .reset_bus = mv5_reset_bus, | |
47c2b677 JG |
801 | }; |
802 | ||
803 | static const struct mv_hw_ops mv6xxx_ops = { | |
804 | .phy_errata = mv6_phy_errata, | |
805 | .enable_leds = mv6_enable_leds, | |
806 | .read_preamp = mv6_read_preamp, | |
807 | .reset_hc = mv6_reset_hc, | |
522479fb JG |
808 | .reset_flash = mv6_reset_flash, |
809 | .reset_bus = mv_reset_pci_bus, | |
47c2b677 JG |
810 | }; |
811 | ||
f351b2d6 SB |
812 | static const struct mv_hw_ops mv_soc_ops = { |
813 | .phy_errata = mv6_phy_errata, | |
814 | .enable_leds = mv_soc_enable_leds, | |
815 | .read_preamp = mv_soc_read_preamp, | |
816 | .reset_hc = mv_soc_reset_hc, | |
817 | .reset_flash = mv_soc_reset_flash, | |
818 | .reset_bus = mv_soc_reset_bus, | |
819 | }; | |
820 | ||
29b7e43c MM |
821 | static const struct mv_hw_ops mv_soc_65n_ops = { |
822 | .phy_errata = mv_soc_65n_phy_errata, | |
823 | .enable_leds = mv_soc_enable_leds, | |
824 | .reset_hc = mv_soc_reset_hc, | |
825 | .reset_flash = mv_soc_reset_flash, | |
826 | .reset_bus = mv_soc_reset_bus, | |
827 | }; | |
828 | ||
20f733e7 BR |
829 | /* |
830 | * Functions | |
831 | */ | |
832 | ||
833 | static inline void writelfl(unsigned long data, void __iomem *addr) | |
834 | { | |
835 | writel(data, addr); | |
836 | (void) readl(addr); /* flush to avoid PCI posted write */ | |
837 | } | |
838 | ||
c9d39130 JG |
839 | static inline unsigned int mv_hc_from_port(unsigned int port) |
840 | { | |
841 | return port >> MV_PORT_HC_SHIFT; | |
842 | } | |
843 | ||
844 | static inline unsigned int mv_hardport_from_port(unsigned int port) | |
845 | { | |
846 | return port & MV_PORT_MASK; | |
847 | } | |
848 | ||
1cfd19ae ML |
849 | /* |
850 | * Consolidate some rather tricky bit shift calculations. | |
851 | * This is hot-path stuff, so not a function. | |
852 | * Simple code, with two return values, so macro rather than inline. | |
853 | * | |
854 | * port is the sole input, in range 0..7. | |
7368f919 ML |
855 | * shift is one output, for use with main_irq_cause / main_irq_mask registers. |
856 | * hardport is the other output, in range 0..3. | |
1cfd19ae ML |
857 | * |
858 | * Note that port and hardport may be the same variable in some cases. | |
859 | */ | |
860 | #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ | |
861 | { \ | |
862 | shift = mv_hc_from_port(port) * HC_SHIFT; \ | |
863 | hardport = mv_hardport_from_port(port); \ | |
864 | shift += hardport * 2; \ | |
865 | } | |
866 | ||
352fab70 ML |
867 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
868 | { | |
cae5a29d | 869 | return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); |
352fab70 ML |
870 | } |
871 | ||
c9d39130 JG |
872 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, |
873 | unsigned int port) | |
874 | { | |
875 | return mv_hc_base(base, mv_hc_from_port(port)); | |
876 | } | |
877 | ||
20f733e7 BR |
878 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
879 | { | |
c9d39130 | 880 | return mv_hc_base_from_port(base, port) + |
8b260248 | 881 | MV_SATAHC_ARBTR_REG_SZ + |
c9d39130 | 882 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
20f733e7 BR |
883 | } |
884 | ||
e12bef50 ML |
885 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
886 | { | |
887 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); | |
888 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; | |
889 | ||
890 | return hc_mmio + ofs; | |
891 | } | |
892 | ||
f351b2d6 SB |
893 | static inline void __iomem *mv_host_base(struct ata_host *host) |
894 | { | |
895 | struct mv_host_priv *hpriv = host->private_data; | |
896 | return hpriv->base; | |
897 | } | |
898 | ||
20f733e7 BR |
899 | static inline void __iomem *mv_ap_base(struct ata_port *ap) |
900 | { | |
f351b2d6 | 901 | return mv_port_base(mv_host_base(ap->host), ap->port_no); |
20f733e7 BR |
902 | } |
903 | ||
cca3974e | 904 | static inline int mv_get_hc_count(unsigned long port_flags) |
31961943 | 905 | { |
cca3974e | 906 | return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
31961943 BR |
907 | } |
908 | ||
08da1759 ML |
909 | /** |
910 | * mv_save_cached_regs - (re-)initialize cached port registers | |
911 | * @ap: the port whose registers we are caching | |
912 | * | |
913 | * Initialize the local cache of port registers, | |
914 | * so that reading them over and over again can | |
915 | * be avoided on the hotter paths of this driver. | |
916 | * This saves a few microseconds each time we switch | |
917 | * to/from EDMA mode to perform (eg.) a drive cache flush. | |
918 | */ | |
919 | static void mv_save_cached_regs(struct ata_port *ap) | |
920 | { | |
921 | void __iomem *port_mmio = mv_ap_base(ap); | |
922 | struct mv_port_priv *pp = ap->private_data; | |
923 | ||
cae5a29d ML |
924 | pp->cached.fiscfg = readl(port_mmio + FISCFG); |
925 | pp->cached.ltmode = readl(port_mmio + LTMODE); | |
926 | pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); | |
927 | pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); | |
08da1759 ML |
928 | } |
929 | ||
930 | /** | |
931 | * mv_write_cached_reg - write to a cached port register | |
932 | * @addr: hardware address of the register | |
933 | * @old: pointer to cached value of the register | |
934 | * @new: new value for the register | |
935 | * | |
936 | * Write a new value to a cached register, | |
937 | * but only if the value is different from before. | |
938 | */ | |
939 | static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) | |
940 | { | |
941 | if (new != *old) { | |
12f3b6d7 | 942 | unsigned long laddr; |
08da1759 | 943 | *old = new; |
12f3b6d7 ML |
944 | /* |
945 | * Workaround for 88SX60x1-B2 FEr SATA#13: | |
946 | * Read-after-write is needed to prevent generating 64-bit | |
947 | * write cycles on the PCI bus for SATA interface registers | |
948 | * at offsets ending in 0x4 or 0xc. | |
949 | * | |
950 | * Looks like a lot of fuss, but it avoids an unnecessary | |
951 | * +1 usec read-after-write delay for unaffected registers. | |
952 | */ | |
953 | laddr = (long)addr & 0xffff; | |
954 | if (laddr >= 0x300 && laddr <= 0x33c) { | |
955 | laddr &= 0x000f; | |
956 | if (laddr == 0x4 || laddr == 0xc) { | |
957 | writelfl(new, addr); /* read after write */ | |
958 | return; | |
959 | } | |
960 | } | |
961 | writel(new, addr); /* unaffected by the errata */ | |
08da1759 ML |
962 | } |
963 | } | |
964 | ||
c5d3e45a JG |
965 | static void mv_set_edma_ptrs(void __iomem *port_mmio, |
966 | struct mv_host_priv *hpriv, | |
967 | struct mv_port_priv *pp) | |
968 | { | |
bdd4ddde JG |
969 | u32 index; |
970 | ||
c5d3e45a JG |
971 | /* |
972 | * initialize request queue | |
973 | */ | |
fcfb1f77 ML |
974 | pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ |
975 | index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; | |
bdd4ddde | 976 | |
c5d3e45a | 977 | WARN_ON(pp->crqb_dma & 0x3ff); |
cae5a29d | 978 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); |
bdd4ddde | 979 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, |
cae5a29d ML |
980 | port_mmio + EDMA_REQ_Q_IN_PTR); |
981 | writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); | |
c5d3e45a JG |
982 | |
983 | /* | |
984 | * initialize response queue | |
985 | */ | |
fcfb1f77 ML |
986 | pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ |
987 | index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; | |
bdd4ddde | 988 | |
c5d3e45a | 989 | WARN_ON(pp->crpb_dma & 0xff); |
cae5a29d ML |
990 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); |
991 | writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); | |
bdd4ddde | 992 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, |
cae5a29d | 993 | port_mmio + EDMA_RSP_Q_OUT_PTR); |
c5d3e45a JG |
994 | } |
995 | ||
2b748a0a ML |
996 | static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) |
997 | { | |
998 | /* | |
999 | * When writing to the main_irq_mask in hardware, | |
1000 | * we must ensure exclusivity between the interrupt coalescing bits | |
1001 | * and the corresponding individual port DONE_IRQ bits. | |
1002 | * | |
1003 | * Note that this register is really an "IRQ enable" register, | |
1004 | * not an "IRQ mask" register as Marvell's naming might suggest. | |
1005 | */ | |
1006 | if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) | |
1007 | mask &= ~DONE_IRQ_0_3; | |
1008 | if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) | |
1009 | mask &= ~DONE_IRQ_4_7; | |
1010 | writelfl(mask, hpriv->main_irq_mask_addr); | |
1011 | } | |
1012 | ||
c4de573b ML |
1013 | static void mv_set_main_irq_mask(struct ata_host *host, |
1014 | u32 disable_bits, u32 enable_bits) | |
1015 | { | |
1016 | struct mv_host_priv *hpriv = host->private_data; | |
1017 | u32 old_mask, new_mask; | |
1018 | ||
96e2c487 | 1019 | old_mask = hpriv->main_irq_mask; |
c4de573b | 1020 | new_mask = (old_mask & ~disable_bits) | enable_bits; |
96e2c487 ML |
1021 | if (new_mask != old_mask) { |
1022 | hpriv->main_irq_mask = new_mask; | |
2b748a0a | 1023 | mv_write_main_irq_mask(new_mask, hpriv); |
96e2c487 | 1024 | } |
c4de573b ML |
1025 | } |
1026 | ||
1027 | static void mv_enable_port_irqs(struct ata_port *ap, | |
1028 | unsigned int port_bits) | |
1029 | { | |
1030 | unsigned int shift, hardport, port = ap->port_no; | |
1031 | u32 disable_bits, enable_bits; | |
1032 | ||
1033 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); | |
1034 | ||
1035 | disable_bits = (DONE_IRQ | ERR_IRQ) << shift; | |
1036 | enable_bits = port_bits << shift; | |
1037 | mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); | |
1038 | } | |
1039 | ||
00b81235 ML |
1040 | static void mv_clear_and_enable_port_irqs(struct ata_port *ap, |
1041 | void __iomem *port_mmio, | |
1042 | unsigned int port_irqs) | |
1043 | { | |
1044 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1045 | int hardport = mv_hardport_from_port(ap->port_no); | |
1046 | void __iomem *hc_mmio = mv_hc_base_from_port( | |
1047 | mv_host_base(ap->host), ap->port_no); | |
1048 | u32 hc_irq_cause; | |
1049 | ||
1050 | /* clear EDMA event indicators, if any */ | |
cae5a29d | 1051 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); |
00b81235 ML |
1052 | |
1053 | /* clear pending irq events */ | |
1054 | hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); | |
cae5a29d | 1055 | writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); |
00b81235 ML |
1056 | |
1057 | /* clear FIS IRQ Cause */ | |
1058 | if (IS_GEN_IIE(hpriv)) | |
cae5a29d | 1059 | writelfl(0, port_mmio + FIS_IRQ_CAUSE); |
00b81235 ML |
1060 | |
1061 | mv_enable_port_irqs(ap, port_irqs); | |
1062 | } | |
1063 | ||
2b748a0a ML |
1064 | static void mv_set_irq_coalescing(struct ata_host *host, |
1065 | unsigned int count, unsigned int usecs) | |
1066 | { | |
1067 | struct mv_host_priv *hpriv = host->private_data; | |
1068 | void __iomem *mmio = hpriv->base, *hc_mmio; | |
1069 | u32 coal_enable = 0; | |
1070 | unsigned long flags; | |
6abf4678 | 1071 | unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; |
2b748a0a ML |
1072 | const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | |
1073 | ALL_PORTS_COAL_DONE; | |
1074 | ||
1075 | /* Disable IRQ coalescing if either threshold is zero */ | |
1076 | if (!usecs || !count) { | |
1077 | clks = count = 0; | |
1078 | } else { | |
1079 | /* Respect maximum limits of the hardware */ | |
1080 | clks = usecs * COAL_CLOCKS_PER_USEC; | |
1081 | if (clks > MAX_COAL_TIME_THRESHOLD) | |
1082 | clks = MAX_COAL_TIME_THRESHOLD; | |
1083 | if (count > MAX_COAL_IO_COUNT) | |
1084 | count = MAX_COAL_IO_COUNT; | |
1085 | } | |
1086 | ||
1087 | spin_lock_irqsave(&host->lock, flags); | |
6abf4678 | 1088 | mv_set_main_irq_mask(host, coal_disable, 0); |
2b748a0a | 1089 | |
6abf4678 | 1090 | if (is_dual_hc && !IS_GEN_I(hpriv)) { |
2b748a0a | 1091 | /* |
6abf4678 ML |
1092 | * GEN_II/GEN_IIE with dual host controllers: |
1093 | * one set of global thresholds for the entire chip. | |
2b748a0a | 1094 | */ |
cae5a29d ML |
1095 | writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); |
1096 | writel(count, mmio + IRQ_COAL_IO_THRESHOLD); | |
2b748a0a | 1097 | /* clear leftover coal IRQ bit */ |
cae5a29d | 1098 | writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); |
6abf4678 ML |
1099 | if (count) |
1100 | coal_enable = ALL_PORTS_COAL_DONE; | |
1101 | clks = count = 0; /* force clearing of regular regs below */ | |
2b748a0a | 1102 | } |
6abf4678 | 1103 | |
2b748a0a ML |
1104 | /* |
1105 | * All chips: independent thresholds for each HC on the chip. | |
1106 | */ | |
1107 | hc_mmio = mv_hc_base_from_port(mmio, 0); | |
cae5a29d ML |
1108 | writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); |
1109 | writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); | |
1110 | writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); | |
6abf4678 ML |
1111 | if (count) |
1112 | coal_enable |= PORTS_0_3_COAL_DONE; | |
1113 | if (is_dual_hc) { | |
2b748a0a | 1114 | hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); |
cae5a29d ML |
1115 | writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); |
1116 | writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); | |
1117 | writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); | |
6abf4678 ML |
1118 | if (count) |
1119 | coal_enable |= PORTS_4_7_COAL_DONE; | |
2b748a0a | 1120 | } |
2b748a0a | 1121 | |
6abf4678 | 1122 | mv_set_main_irq_mask(host, 0, coal_enable); |
2b748a0a ML |
1123 | spin_unlock_irqrestore(&host->lock, flags); |
1124 | } | |
1125 | ||
05b308e1 | 1126 | /** |
00b81235 | 1127 | * mv_start_edma - Enable eDMA engine |
05b308e1 BR |
1128 | * @base: port base address |
1129 | * @pp: port private data | |
1130 | * | |
beec7dbc TH |
1131 | * Verify the local cache of the eDMA state is accurate with a |
1132 | * WARN_ON. | |
05b308e1 BR |
1133 | * |
1134 | * LOCKING: | |
1135 | * Inherited from caller. | |
1136 | */ | |
00b81235 | 1137 | static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, |
72109168 | 1138 | struct mv_port_priv *pp, u8 protocol) |
20f733e7 | 1139 | { |
72109168 ML |
1140 | int want_ncq = (protocol == ATA_PROT_NCQ); |
1141 | ||
1142 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { | |
1143 | int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); | |
1144 | if (want_ncq != using_ncq) | |
b562468c | 1145 | mv_stop_edma(ap); |
72109168 | 1146 | } |
c5d3e45a | 1147 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { |
0c58912e | 1148 | struct mv_host_priv *hpriv = ap->host->private_data; |
0c58912e | 1149 | |
00b81235 | 1150 | mv_edma_cfg(ap, want_ncq, 1); |
0c58912e | 1151 | |
f630d562 | 1152 | mv_set_edma_ptrs(port_mmio, hpriv, pp); |
00b81235 | 1153 | mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); |
bdd4ddde | 1154 | |
cae5a29d | 1155 | writelfl(EDMA_EN, port_mmio + EDMA_CMD); |
afb0edd9 BR |
1156 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; |
1157 | } | |
20f733e7 BR |
1158 | } |
1159 | ||
9b2c4e0b ML |
1160 | static void mv_wait_for_edma_empty_idle(struct ata_port *ap) |
1161 | { | |
1162 | void __iomem *port_mmio = mv_ap_base(ap); | |
1163 | const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); | |
1164 | const int per_loop = 5, timeout = (15 * 1000 / per_loop); | |
1165 | int i; | |
1166 | ||
1167 | /* | |
1168 | * Wait for the EDMA engine to finish transactions in progress. | |
c46938cc ML |
1169 | * No idea what a good "timeout" value might be, but measurements |
1170 | * indicate that it often requires hundreds of microseconds | |
1171 | * with two drives in-use. So we use the 15msec value above | |
1172 | * as a rough guess at what even more drives might require. | |
9b2c4e0b ML |
1173 | */ |
1174 | for (i = 0; i < timeout; ++i) { | |
cae5a29d | 1175 | u32 edma_stat = readl(port_mmio + EDMA_STATUS); |
9b2c4e0b ML |
1176 | if ((edma_stat & empty_idle) == empty_idle) |
1177 | break; | |
1178 | udelay(per_loop); | |
1179 | } | |
1180 | /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ | |
1181 | } | |
1182 | ||
05b308e1 | 1183 | /** |
e12bef50 | 1184 | * mv_stop_edma_engine - Disable eDMA engine |
b562468c | 1185 | * @port_mmio: io base address |
05b308e1 BR |
1186 | * |
1187 | * LOCKING: | |
1188 | * Inherited from caller. | |
1189 | */ | |
b562468c | 1190 | static int mv_stop_edma_engine(void __iomem *port_mmio) |
20f733e7 | 1191 | { |
b562468c | 1192 | int i; |
31961943 | 1193 | |
b562468c | 1194 | /* Disable eDMA. The disable bit auto clears. */ |
cae5a29d | 1195 | writelfl(EDMA_DS, port_mmio + EDMA_CMD); |
8b260248 | 1196 | |
b562468c ML |
1197 | /* Wait for the chip to confirm eDMA is off. */ |
1198 | for (i = 10000; i > 0; i--) { | |
cae5a29d | 1199 | u32 reg = readl(port_mmio + EDMA_CMD); |
4537deb5 | 1200 | if (!(reg & EDMA_EN)) |
b562468c ML |
1201 | return 0; |
1202 | udelay(10); | |
31961943 | 1203 | } |
b562468c | 1204 | return -EIO; |
20f733e7 BR |
1205 | } |
1206 | ||
e12bef50 | 1207 | static int mv_stop_edma(struct ata_port *ap) |
0ea9e179 | 1208 | { |
b562468c ML |
1209 | void __iomem *port_mmio = mv_ap_base(ap); |
1210 | struct mv_port_priv *pp = ap->private_data; | |
66e57a2c | 1211 | int err = 0; |
0ea9e179 | 1212 | |
b562468c ML |
1213 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) |
1214 | return 0; | |
1215 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
9b2c4e0b | 1216 | mv_wait_for_edma_empty_idle(ap); |
b562468c ML |
1217 | if (mv_stop_edma_engine(port_mmio)) { |
1218 | ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); | |
66e57a2c | 1219 | err = -EIO; |
b562468c | 1220 | } |
66e57a2c ML |
1221 | mv_edma_cfg(ap, 0, 0); |
1222 | return err; | |
0ea9e179 JG |
1223 | } |
1224 | ||
8a70f8dc | 1225 | #ifdef ATA_DEBUG |
31961943 | 1226 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
20f733e7 | 1227 | { |
31961943 BR |
1228 | int b, w; |
1229 | for (b = 0; b < bytes; ) { | |
1230 | DPRINTK("%p: ", start + b); | |
1231 | for (w = 0; b < bytes && w < 4; w++) { | |
2dcb407e | 1232 | printk("%08x ", readl(start + b)); |
31961943 BR |
1233 | b += sizeof(u32); |
1234 | } | |
1235 | printk("\n"); | |
1236 | } | |
31961943 | 1237 | } |
8a70f8dc JG |
1238 | #endif |
1239 | ||
31961943 BR |
1240 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
1241 | { | |
1242 | #ifdef ATA_DEBUG | |
1243 | int b, w; | |
1244 | u32 dw; | |
1245 | for (b = 0; b < bytes; ) { | |
1246 | DPRINTK("%02x: ", b); | |
1247 | for (w = 0; b < bytes && w < 4; w++) { | |
2dcb407e JG |
1248 | (void) pci_read_config_dword(pdev, b, &dw); |
1249 | printk("%08x ", dw); | |
31961943 BR |
1250 | b += sizeof(u32); |
1251 | } | |
1252 | printk("\n"); | |
1253 | } | |
1254 | #endif | |
1255 | } | |
1256 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, | |
1257 | struct pci_dev *pdev) | |
1258 | { | |
1259 | #ifdef ATA_DEBUG | |
8b260248 | 1260 | void __iomem *hc_base = mv_hc_base(mmio_base, |
31961943 BR |
1261 | port >> MV_PORT_HC_SHIFT); |
1262 | void __iomem *port_base; | |
1263 | int start_port, num_ports, p, start_hc, num_hcs, hc; | |
1264 | ||
1265 | if (0 > port) { | |
1266 | start_hc = start_port = 0; | |
1267 | num_ports = 8; /* shld be benign for 4 port devs */ | |
1268 | num_hcs = 2; | |
1269 | } else { | |
1270 | start_hc = port >> MV_PORT_HC_SHIFT; | |
1271 | start_port = port; | |
1272 | num_ports = num_hcs = 1; | |
1273 | } | |
8b260248 | 1274 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
31961943 BR |
1275 | num_ports > 1 ? num_ports - 1 : start_port); |
1276 | ||
1277 | if (NULL != pdev) { | |
1278 | DPRINTK("PCI config space regs:\n"); | |
1279 | mv_dump_pci_cfg(pdev, 0x68); | |
1280 | } | |
1281 | DPRINTK("PCI regs:\n"); | |
1282 | mv_dump_mem(mmio_base+0xc00, 0x3c); | |
1283 | mv_dump_mem(mmio_base+0xd00, 0x34); | |
1284 | mv_dump_mem(mmio_base+0xf00, 0x4); | |
1285 | mv_dump_mem(mmio_base+0x1d00, 0x6c); | |
1286 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { | |
d220c37e | 1287 | hc_base = mv_hc_base(mmio_base, hc); |
31961943 BR |
1288 | DPRINTK("HC regs (HC %i):\n", hc); |
1289 | mv_dump_mem(hc_base, 0x1c); | |
1290 | } | |
1291 | for (p = start_port; p < start_port + num_ports; p++) { | |
1292 | port_base = mv_port_base(mmio_base, p); | |
2dcb407e | 1293 | DPRINTK("EDMA regs (port %i):\n", p); |
31961943 | 1294 | mv_dump_mem(port_base, 0x54); |
2dcb407e | 1295 | DPRINTK("SATA regs (port %i):\n", p); |
31961943 BR |
1296 | mv_dump_mem(port_base+0x300, 0x60); |
1297 | } | |
1298 | #endif | |
20f733e7 BR |
1299 | } |
1300 | ||
1301 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) | |
1302 | { | |
1303 | unsigned int ofs; | |
1304 | ||
1305 | switch (sc_reg_in) { | |
1306 | case SCR_STATUS: | |
1307 | case SCR_CONTROL: | |
1308 | case SCR_ERROR: | |
cae5a29d | 1309 | ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); |
20f733e7 BR |
1310 | break; |
1311 | case SCR_ACTIVE: | |
cae5a29d | 1312 | ofs = SATA_ACTIVE; /* active is not with the others */ |
20f733e7 BR |
1313 | break; |
1314 | default: | |
1315 | ofs = 0xffffffffU; | |
1316 | break; | |
1317 | } | |
1318 | return ofs; | |
1319 | } | |
1320 | ||
82ef04fb | 1321 | static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) |
20f733e7 BR |
1322 | { |
1323 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
1324 | ||
da3dbb17 | 1325 | if (ofs != 0xffffffffU) { |
82ef04fb | 1326 | *val = readl(mv_ap_base(link->ap) + ofs); |
da3dbb17 TH |
1327 | return 0; |
1328 | } else | |
1329 | return -EINVAL; | |
20f733e7 BR |
1330 | } |
1331 | ||
82ef04fb | 1332 | static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) |
20f733e7 BR |
1333 | { |
1334 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
1335 | ||
da3dbb17 | 1336 | if (ofs != 0xffffffffU) { |
20091773 ML |
1337 | void __iomem *addr = mv_ap_base(link->ap) + ofs; |
1338 | if (sc_reg_in == SCR_CONTROL) { | |
1339 | /* | |
1340 | * Workaround for 88SX60x1 FEr SATA#26: | |
1341 | * | |
1342 | * COMRESETs have to take care not to accidently | |
1343 | * put the drive to sleep when writing SCR_CONTROL. | |
1344 | * Setting bits 12..15 prevents this problem. | |
1345 | * | |
1346 | * So if we see an outbound COMMRESET, set those bits. | |
1347 | * Ditto for the followup write that clears the reset. | |
1348 | * | |
1349 | * The proprietary driver does this for | |
1350 | * all chip versions, and so do we. | |
1351 | */ | |
1352 | if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) | |
1353 | val |= 0xf000; | |
1354 | } | |
1355 | writelfl(val, addr); | |
da3dbb17 TH |
1356 | return 0; |
1357 | } else | |
1358 | return -EINVAL; | |
20f733e7 BR |
1359 | } |
1360 | ||
f273827e ML |
1361 | static void mv6_dev_config(struct ata_device *adev) |
1362 | { | |
1363 | /* | |
e49856d8 ML |
1364 | * Deal with Gen-II ("mv6") hardware quirks/restrictions: |
1365 | * | |
1366 | * Gen-II does not support NCQ over a port multiplier | |
1367 | * (no FIS-based switching). | |
f273827e | 1368 | */ |
e49856d8 | 1369 | if (adev->flags & ATA_DFLAG_NCQ) { |
352fab70 | 1370 | if (sata_pmp_attached(adev->link->ap)) { |
e49856d8 | 1371 | adev->flags &= ~ATA_DFLAG_NCQ; |
352fab70 ML |
1372 | ata_dev_printk(adev, KERN_INFO, |
1373 | "NCQ disabled for command-based switching\n"); | |
352fab70 | 1374 | } |
e49856d8 | 1375 | } |
f273827e ML |
1376 | } |
1377 | ||
3e4a1391 ML |
1378 | static int mv_qc_defer(struct ata_queued_cmd *qc) |
1379 | { | |
1380 | struct ata_link *link = qc->dev->link; | |
1381 | struct ata_port *ap = link->ap; | |
1382 | struct mv_port_priv *pp = ap->private_data; | |
1383 | ||
29d187bb ML |
1384 | /* |
1385 | * Don't allow new commands if we're in a delayed EH state | |
1386 | * for NCQ and/or FIS-based switching. | |
1387 | */ | |
1388 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) | |
1389 | return ATA_DEFER_PORT; | |
159a7ff7 GG |
1390 | |
1391 | /* PIO commands need exclusive link: no other commands [DMA or PIO] | |
1392 | * can run concurrently. | |
1393 | * set excl_link when we want to send a PIO command in DMA mode | |
1394 | * or a non-NCQ command in NCQ mode. | |
1395 | * When we receive a command from that link, and there are no | |
1396 | * outstanding commands, mark a flag to clear excl_link and let | |
1397 | * the command go through. | |
1398 | */ | |
1399 | if (unlikely(ap->excl_link)) { | |
1400 | if (link == ap->excl_link) { | |
1401 | if (ap->nr_active_links) | |
1402 | return ATA_DEFER_PORT; | |
1403 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; | |
1404 | return 0; | |
1405 | } else | |
1406 | return ATA_DEFER_PORT; | |
1407 | } | |
1408 | ||
3e4a1391 ML |
1409 | /* |
1410 | * If the port is completely idle, then allow the new qc. | |
1411 | */ | |
1412 | if (ap->nr_active_links == 0) | |
1413 | return 0; | |
1414 | ||
4bdee6c5 TH |
1415 | /* |
1416 | * The port is operating in host queuing mode (EDMA) with NCQ | |
1417 | * enabled, allow multiple NCQ commands. EDMA also allows | |
1418 | * queueing multiple DMA commands but libata core currently | |
1419 | * doesn't allow it. | |
1420 | */ | |
1421 | if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && | |
159a7ff7 GG |
1422 | (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { |
1423 | if (ata_is_ncq(qc->tf.protocol)) | |
1424 | return 0; | |
1425 | else { | |
1426 | ap->excl_link = link; | |
1427 | return ATA_DEFER_PORT; | |
1428 | } | |
1429 | } | |
4bdee6c5 | 1430 | |
3e4a1391 ML |
1431 | return ATA_DEFER_PORT; |
1432 | } | |
1433 | ||
08da1759 | 1434 | static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) |
e49856d8 | 1435 | { |
08da1759 ML |
1436 | struct mv_port_priv *pp = ap->private_data; |
1437 | void __iomem *port_mmio; | |
00f42eab | 1438 | |
08da1759 ML |
1439 | u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; |
1440 | u32 ltmode, *old_ltmode = &pp->cached.ltmode; | |
1441 | u32 haltcond, *old_haltcond = &pp->cached.haltcond; | |
00f42eab | 1442 | |
08da1759 ML |
1443 | ltmode = *old_ltmode & ~LTMODE_BIT8; |
1444 | haltcond = *old_haltcond | EDMA_ERR_DEV; | |
00f42eab ML |
1445 | |
1446 | if (want_fbs) { | |
08da1759 ML |
1447 | fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; |
1448 | ltmode = *old_ltmode | LTMODE_BIT8; | |
4c299ca3 | 1449 | if (want_ncq) |
08da1759 | 1450 | haltcond &= ~EDMA_ERR_DEV; |
4c299ca3 | 1451 | else |
08da1759 ML |
1452 | fiscfg |= FISCFG_WAIT_DEV_ERR; |
1453 | } else { | |
1454 | fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); | |
e49856d8 | 1455 | } |
00f42eab | 1456 | |
08da1759 | 1457 | port_mmio = mv_ap_base(ap); |
cae5a29d ML |
1458 | mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); |
1459 | mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); | |
1460 | mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); | |
f273827e ML |
1461 | } |
1462 | ||
dd2890f6 ML |
1463 | static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) |
1464 | { | |
1465 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1466 | u32 old, new; | |
1467 | ||
1468 | /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ | |
cae5a29d | 1469 | old = readl(hpriv->base + GPIO_PORT_CTL); |
dd2890f6 ML |
1470 | if (want_ncq) |
1471 | new = old | (1 << 22); | |
1472 | else | |
1473 | new = old & ~(1 << 22); | |
1474 | if (new != old) | |
cae5a29d | 1475 | writel(new, hpriv->base + GPIO_PORT_CTL); |
dd2890f6 ML |
1476 | } |
1477 | ||
c01e8a23 | 1478 | /** |
40f21b11 ML |
1479 | * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma |
1480 | * @ap: Port being initialized | |
c01e8a23 ML |
1481 | * |
1482 | * There are two DMA modes on these chips: basic DMA, and EDMA. | |
1483 | * | |
1484 | * Bit-0 of the "EDMA RESERVED" register enables/disables use | |
1485 | * of basic DMA on the GEN_IIE versions of the chips. | |
1486 | * | |
1487 | * This bit survives EDMA resets, and must be set for basic DMA | |
1488 | * to function, and should be cleared when EDMA is active. | |
1489 | */ | |
1490 | static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) | |
1491 | { | |
1492 | struct mv_port_priv *pp = ap->private_data; | |
1493 | u32 new, *old = &pp->cached.unknown_rsvd; | |
1494 | ||
1495 | if (enable_bmdma) | |
1496 | new = *old | 1; | |
1497 | else | |
1498 | new = *old & ~1; | |
cae5a29d | 1499 | mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); |
c01e8a23 ML |
1500 | } |
1501 | ||
000b344f ML |
1502 | /* |
1503 | * SOC chips have an issue whereby the HDD LEDs don't always blink | |
1504 | * during I/O when NCQ is enabled. Enabling a special "LED blink" mode | |
1505 | * of the SOC takes care of it, generating a steady blink rate when | |
1506 | * any drive on the chip is active. | |
1507 | * | |
1508 | * Unfortunately, the blink mode is a global hardware setting for the SOC, | |
1509 | * so we must use it whenever at least one port on the SOC has NCQ enabled. | |
1510 | * | |
1511 | * We turn "LED blink" off when NCQ is not in use anywhere, because the normal | |
1512 | * LED operation works then, and provides better (more accurate) feedback. | |
1513 | * | |
1514 | * Note that this code assumes that an SOC never has more than one HC onboard. | |
1515 | */ | |
1516 | static void mv_soc_led_blink_enable(struct ata_port *ap) | |
1517 | { | |
1518 | struct ata_host *host = ap->host; | |
1519 | struct mv_host_priv *hpriv = host->private_data; | |
1520 | void __iomem *hc_mmio; | |
1521 | u32 led_ctrl; | |
1522 | ||
1523 | if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) | |
1524 | return; | |
1525 | hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; | |
1526 | hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); | |
cae5a29d ML |
1527 | led_ctrl = readl(hc_mmio + SOC_LED_CTRL); |
1528 | writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); | |
000b344f ML |
1529 | } |
1530 | ||
1531 | static void mv_soc_led_blink_disable(struct ata_port *ap) | |
1532 | { | |
1533 | struct ata_host *host = ap->host; | |
1534 | struct mv_host_priv *hpriv = host->private_data; | |
1535 | void __iomem *hc_mmio; | |
1536 | u32 led_ctrl; | |
1537 | unsigned int port; | |
1538 | ||
1539 | if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) | |
1540 | return; | |
1541 | ||
1542 | /* disable led-blink only if no ports are using NCQ */ | |
1543 | for (port = 0; port < hpriv->n_ports; port++) { | |
1544 | struct ata_port *this_ap = host->ports[port]; | |
1545 | struct mv_port_priv *pp = this_ap->private_data; | |
1546 | ||
1547 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) | |
1548 | return; | |
1549 | } | |
1550 | ||
1551 | hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; | |
1552 | hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); | |
cae5a29d ML |
1553 | led_ctrl = readl(hc_mmio + SOC_LED_CTRL); |
1554 | writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); | |
000b344f ML |
1555 | } |
1556 | ||
00b81235 | 1557 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) |
e4e7b892 | 1558 | { |
0c58912e | 1559 | u32 cfg; |
e12bef50 ML |
1560 | struct mv_port_priv *pp = ap->private_data; |
1561 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1562 | void __iomem *port_mmio = mv_ap_base(ap); | |
e4e7b892 JG |
1563 | |
1564 | /* set up non-NCQ EDMA configuration */ | |
0c58912e | 1565 | cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ |
d16ab3f6 ML |
1566 | pp->pp_flags &= |
1567 | ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); | |
e4e7b892 | 1568 | |
0c58912e | 1569 | if (IS_GEN_I(hpriv)) |
e4e7b892 JG |
1570 | cfg |= (1 << 8); /* enab config burst size mask */ |
1571 | ||
dd2890f6 | 1572 | else if (IS_GEN_II(hpriv)) { |
e4e7b892 | 1573 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; |
dd2890f6 | 1574 | mv_60x1_errata_sata25(ap, want_ncq); |
e4e7b892 | 1575 | |
dd2890f6 | 1576 | } else if (IS_GEN_IIE(hpriv)) { |
00f42eab ML |
1577 | int want_fbs = sata_pmp_attached(ap); |
1578 | /* | |
1579 | * Possible future enhancement: | |
1580 | * | |
1581 | * The chip can use FBS with non-NCQ, if we allow it, | |
1582 | * But first we need to have the error handling in place | |
1583 | * for this mode (datasheet section 7.3.15.4.2.3). | |
1584 | * So disallow non-NCQ FBS for now. | |
1585 | */ | |
1586 | want_fbs &= want_ncq; | |
1587 | ||
08da1759 | 1588 | mv_config_fbs(ap, want_ncq, want_fbs); |
00f42eab ML |
1589 | |
1590 | if (want_fbs) { | |
1591 | pp->pp_flags |= MV_PP_FLAG_FBS_EN; | |
1592 | cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ | |
1593 | } | |
1594 | ||
e728eabe | 1595 | cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ |
00b81235 ML |
1596 | if (want_edma) { |
1597 | cfg |= (1 << 22); /* enab 4-entry host queue cache */ | |
1598 | if (!IS_SOC(hpriv)) | |
1599 | cfg |= (1 << 18); /* enab early completion */ | |
1600 | } | |
616d4a98 ML |
1601 | if (hpriv->hp_flags & MV_HP_CUT_THROUGH) |
1602 | cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ | |
c01e8a23 | 1603 | mv_bmdma_enable_iie(ap, !want_edma); |
000b344f ML |
1604 | |
1605 | if (IS_SOC(hpriv)) { | |
1606 | if (want_ncq) | |
1607 | mv_soc_led_blink_enable(ap); | |
1608 | else | |
1609 | mv_soc_led_blink_disable(ap); | |
1610 | } | |
e4e7b892 JG |
1611 | } |
1612 | ||
72109168 ML |
1613 | if (want_ncq) { |
1614 | cfg |= EDMA_CFG_NCQ; | |
1615 | pp->pp_flags |= MV_PP_FLAG_NCQ_EN; | |
00b81235 | 1616 | } |
72109168 | 1617 | |
cae5a29d | 1618 | writelfl(cfg, port_mmio + EDMA_CFG); |
e4e7b892 JG |
1619 | } |
1620 | ||
da2fa9ba ML |
1621 | static void mv_port_free_dma_mem(struct ata_port *ap) |
1622 | { | |
1623 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1624 | struct mv_port_priv *pp = ap->private_data; | |
eb73d558 | 1625 | int tag; |
da2fa9ba ML |
1626 | |
1627 | if (pp->crqb) { | |
1628 | dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); | |
1629 | pp->crqb = NULL; | |
1630 | } | |
1631 | if (pp->crpb) { | |
1632 | dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); | |
1633 | pp->crpb = NULL; | |
1634 | } | |
eb73d558 ML |
1635 | /* |
1636 | * For GEN_I, there's no NCQ, so we have only a single sg_tbl. | |
1637 | * For later hardware, we have one unique sg_tbl per NCQ tag. | |
1638 | */ | |
1639 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { | |
1640 | if (pp->sg_tbl[tag]) { | |
1641 | if (tag == 0 || !IS_GEN_I(hpriv)) | |
1642 | dma_pool_free(hpriv->sg_tbl_pool, | |
1643 | pp->sg_tbl[tag], | |
1644 | pp->sg_tbl_dma[tag]); | |
1645 | pp->sg_tbl[tag] = NULL; | |
1646 | } | |
da2fa9ba ML |
1647 | } |
1648 | } | |
1649 | ||
05b308e1 BR |
1650 | /** |
1651 | * mv_port_start - Port specific init/start routine. | |
1652 | * @ap: ATA channel to manipulate | |
1653 | * | |
1654 | * Allocate and point to DMA memory, init port private memory, | |
1655 | * zero indices. | |
1656 | * | |
1657 | * LOCKING: | |
1658 | * Inherited from caller. | |
1659 | */ | |
31961943 BR |
1660 | static int mv_port_start(struct ata_port *ap) |
1661 | { | |
cca3974e JG |
1662 | struct device *dev = ap->host->dev; |
1663 | struct mv_host_priv *hpriv = ap->host->private_data; | |
31961943 | 1664 | struct mv_port_priv *pp; |
933cb8e5 | 1665 | unsigned long flags; |
dde20207 | 1666 | int tag; |
31961943 | 1667 | |
24dc5f33 | 1668 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
6037d6bb | 1669 | if (!pp) |
24dc5f33 | 1670 | return -ENOMEM; |
da2fa9ba | 1671 | ap->private_data = pp; |
31961943 | 1672 | |
da2fa9ba ML |
1673 | pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); |
1674 | if (!pp->crqb) | |
1675 | return -ENOMEM; | |
1676 | memset(pp->crqb, 0, MV_CRQB_Q_SZ); | |
31961943 | 1677 | |
da2fa9ba ML |
1678 | pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); |
1679 | if (!pp->crpb) | |
1680 | goto out_port_free_dma_mem; | |
1681 | memset(pp->crpb, 0, MV_CRPB_Q_SZ); | |
31961943 | 1682 | |
3bd0a70e ML |
1683 | /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ |
1684 | if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) | |
1685 | ap->flags |= ATA_FLAG_AN; | |
eb73d558 ML |
1686 | /* |
1687 | * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. | |
1688 | * For later hardware, we need one unique sg_tbl per NCQ tag. | |
1689 | */ | |
1690 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { | |
1691 | if (tag == 0 || !IS_GEN_I(hpriv)) { | |
1692 | pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, | |
1693 | GFP_KERNEL, &pp->sg_tbl_dma[tag]); | |
1694 | if (!pp->sg_tbl[tag]) | |
1695 | goto out_port_free_dma_mem; | |
1696 | } else { | |
1697 | pp->sg_tbl[tag] = pp->sg_tbl[0]; | |
1698 | pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; | |
1699 | } | |
1700 | } | |
933cb8e5 ML |
1701 | |
1702 | spin_lock_irqsave(ap->lock, flags); | |
08da1759 | 1703 | mv_save_cached_regs(ap); |
66e57a2c | 1704 | mv_edma_cfg(ap, 0, 0); |
933cb8e5 ML |
1705 | spin_unlock_irqrestore(ap->lock, flags); |
1706 | ||
31961943 | 1707 | return 0; |
da2fa9ba ML |
1708 | |
1709 | out_port_free_dma_mem: | |
1710 | mv_port_free_dma_mem(ap); | |
1711 | return -ENOMEM; | |
31961943 BR |
1712 | } |
1713 | ||
05b308e1 BR |
1714 | /** |
1715 | * mv_port_stop - Port specific cleanup/stop routine. | |
1716 | * @ap: ATA channel to manipulate | |
1717 | * | |
1718 | * Stop DMA, cleanup port memory. | |
1719 | * | |
1720 | * LOCKING: | |
cca3974e | 1721 | * This routine uses the host lock to protect the DMA stop. |
05b308e1 | 1722 | */ |
31961943 BR |
1723 | static void mv_port_stop(struct ata_port *ap) |
1724 | { | |
933cb8e5 ML |
1725 | unsigned long flags; |
1726 | ||
1727 | spin_lock_irqsave(ap->lock, flags); | |
e12bef50 | 1728 | mv_stop_edma(ap); |
88e675e1 | 1729 | mv_enable_port_irqs(ap, 0); |
933cb8e5 | 1730 | spin_unlock_irqrestore(ap->lock, flags); |
da2fa9ba | 1731 | mv_port_free_dma_mem(ap); |
31961943 BR |
1732 | } |
1733 | ||
05b308e1 BR |
1734 | /** |
1735 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries | |
1736 | * @qc: queued command whose SG list to source from | |
1737 | * | |
1738 | * Populate the SG list and mark the last entry. | |
1739 | * | |
1740 | * LOCKING: | |
1741 | * Inherited from caller. | |
1742 | */ | |
6c08772e | 1743 | static void mv_fill_sg(struct ata_queued_cmd *qc) |
31961943 BR |
1744 | { |
1745 | struct mv_port_priv *pp = qc->ap->private_data; | |
972c26bd | 1746 | struct scatterlist *sg; |
3be6cbd7 | 1747 | struct mv_sg *mv_sg, *last_sg = NULL; |
ff2aeb1e | 1748 | unsigned int si; |
31961943 | 1749 | |
eb73d558 | 1750 | mv_sg = pp->sg_tbl[qc->tag]; |
ff2aeb1e | 1751 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
d88184fb JG |
1752 | dma_addr_t addr = sg_dma_address(sg); |
1753 | u32 sg_len = sg_dma_len(sg); | |
22374677 | 1754 | |
4007b493 OJ |
1755 | while (sg_len) { |
1756 | u32 offset = addr & 0xffff; | |
1757 | u32 len = sg_len; | |
22374677 | 1758 | |
32cd11a6 | 1759 | if (offset + len > 0x10000) |
4007b493 OJ |
1760 | len = 0x10000 - offset; |
1761 | ||
1762 | mv_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1763 | mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
6c08772e | 1764 | mv_sg->flags_size = cpu_to_le32(len & 0xffff); |
32cd11a6 | 1765 | mv_sg->reserved = 0; |
4007b493 OJ |
1766 | |
1767 | sg_len -= len; | |
1768 | addr += len; | |
1769 | ||
3be6cbd7 | 1770 | last_sg = mv_sg; |
4007b493 | 1771 | mv_sg++; |
4007b493 | 1772 | } |
31961943 | 1773 | } |
3be6cbd7 JG |
1774 | |
1775 | if (likely(last_sg)) | |
1776 | last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); | |
32cd11a6 | 1777 | mb(); /* ensure data structure is visible to the chipset */ |
31961943 BR |
1778 | } |
1779 | ||
5796d1c4 | 1780 | static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) |
31961943 | 1781 | { |
559eedad | 1782 | u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | |
31961943 | 1783 | (last ? CRQB_CMD_LAST : 0); |
559eedad | 1784 | *cmdw = cpu_to_le16(tmp); |
31961943 BR |
1785 | } |
1786 | ||
da14265e ML |
1787 | /** |
1788 | * mv_sff_irq_clear - Clear hardware interrupt after DMA. | |
1789 | * @ap: Port associated with this ATA transaction. | |
1790 | * | |
1791 | * We need this only for ATAPI bmdma transactions, | |
1792 | * as otherwise we experience spurious interrupts | |
1793 | * after libata-sff handles the bmdma interrupts. | |
1794 | */ | |
1795 | static void mv_sff_irq_clear(struct ata_port *ap) | |
1796 | { | |
1797 | mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); | |
1798 | } | |
1799 | ||
1800 | /** | |
1801 | * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. | |
1802 | * @qc: queued command to check for chipset/DMA compatibility. | |
1803 | * | |
1804 | * The bmdma engines cannot handle speculative data sizes | |
1805 | * (bytecount under/over flow). So only allow DMA for | |
1806 | * data transfer commands with known data sizes. | |
1807 | * | |
1808 | * LOCKING: | |
1809 | * Inherited from caller. | |
1810 | */ | |
1811 | static int mv_check_atapi_dma(struct ata_queued_cmd *qc) | |
1812 | { | |
1813 | struct scsi_cmnd *scmd = qc->scsicmd; | |
1814 | ||
1815 | if (scmd) { | |
1816 | switch (scmd->cmnd[0]) { | |
1817 | case READ_6: | |
1818 | case READ_10: | |
1819 | case READ_12: | |
1820 | case WRITE_6: | |
1821 | case WRITE_10: | |
1822 | case WRITE_12: | |
1823 | case GPCMD_READ_CD: | |
1824 | case GPCMD_SEND_DVD_STRUCTURE: | |
1825 | case GPCMD_SEND_CUE_SHEET: | |
1826 | return 0; /* DMA is safe */ | |
1827 | } | |
1828 | } | |
1829 | return -EOPNOTSUPP; /* use PIO instead */ | |
1830 | } | |
1831 | ||
1832 | /** | |
1833 | * mv_bmdma_setup - Set up BMDMA transaction | |
1834 | * @qc: queued command to prepare DMA for. | |
1835 | * | |
1836 | * LOCKING: | |
1837 | * Inherited from caller. | |
1838 | */ | |
1839 | static void mv_bmdma_setup(struct ata_queued_cmd *qc) | |
1840 | { | |
1841 | struct ata_port *ap = qc->ap; | |
1842 | void __iomem *port_mmio = mv_ap_base(ap); | |
1843 | struct mv_port_priv *pp = ap->private_data; | |
1844 | ||
1845 | mv_fill_sg(qc); | |
1846 | ||
1847 | /* clear all DMA cmd bits */ | |
cae5a29d | 1848 | writel(0, port_mmio + BMDMA_CMD); |
da14265e ML |
1849 | |
1850 | /* load PRD table addr. */ | |
1851 | writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, | |
cae5a29d | 1852 | port_mmio + BMDMA_PRD_HIGH); |
da14265e | 1853 | writelfl(pp->sg_tbl_dma[qc->tag], |
cae5a29d | 1854 | port_mmio + BMDMA_PRD_LOW); |
da14265e ML |
1855 | |
1856 | /* issue r/w command */ | |
1857 | ap->ops->sff_exec_command(ap, &qc->tf); | |
1858 | } | |
1859 | ||
1860 | /** | |
1861 | * mv_bmdma_start - Start a BMDMA transaction | |
1862 | * @qc: queued command to start DMA on. | |
1863 | * | |
1864 | * LOCKING: | |
1865 | * Inherited from caller. | |
1866 | */ | |
1867 | static void mv_bmdma_start(struct ata_queued_cmd *qc) | |
1868 | { | |
1869 | struct ata_port *ap = qc->ap; | |
1870 | void __iomem *port_mmio = mv_ap_base(ap); | |
1871 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
1872 | u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; | |
1873 | ||
1874 | /* start host DMA transaction */ | |
cae5a29d | 1875 | writelfl(cmd, port_mmio + BMDMA_CMD); |
da14265e ML |
1876 | } |
1877 | ||
1878 | /** | |
1879 | * mv_bmdma_stop - Stop BMDMA transfer | |
1880 | * @qc: queued command to stop DMA on. | |
1881 | * | |
1882 | * Clears the ATA_DMA_START flag in the bmdma control register | |
1883 | * | |
1884 | * LOCKING: | |
1885 | * Inherited from caller. | |
1886 | */ | |
1887 | static void mv_bmdma_stop(struct ata_queued_cmd *qc) | |
1888 | { | |
1889 | struct ata_port *ap = qc->ap; | |
1890 | void __iomem *port_mmio = mv_ap_base(ap); | |
1891 | u32 cmd; | |
1892 | ||
1893 | /* clear start/stop bit */ | |
cae5a29d | 1894 | cmd = readl(port_mmio + BMDMA_CMD); |
da14265e | 1895 | cmd &= ~ATA_DMA_START; |
cae5a29d | 1896 | writelfl(cmd, port_mmio + BMDMA_CMD); |
da14265e ML |
1897 | |
1898 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
1899 | ata_sff_dma_pause(ap); | |
1900 | } | |
1901 | ||
1902 | /** | |
1903 | * mv_bmdma_status - Read BMDMA status | |
1904 | * @ap: port for which to retrieve DMA status. | |
1905 | * | |
1906 | * Read and return equivalent of the sff BMDMA status register. | |
1907 | * | |
1908 | * LOCKING: | |
1909 | * Inherited from caller. | |
1910 | */ | |
1911 | static u8 mv_bmdma_status(struct ata_port *ap) | |
1912 | { | |
1913 | void __iomem *port_mmio = mv_ap_base(ap); | |
1914 | u32 reg, status; | |
1915 | ||
1916 | /* | |
1917 | * Other bits are valid only if ATA_DMA_ACTIVE==0, | |
1918 | * and the ATA_DMA_INTR bit doesn't exist. | |
1919 | */ | |
cae5a29d | 1920 | reg = readl(port_mmio + BMDMA_STATUS); |
da14265e ML |
1921 | if (reg & ATA_DMA_ACTIVE) |
1922 | status = ATA_DMA_ACTIVE; | |
1923 | else | |
1924 | status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; | |
1925 | return status; | |
1926 | } | |
1927 | ||
299b3f8d ML |
1928 | static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) |
1929 | { | |
1930 | struct ata_taskfile *tf = &qc->tf; | |
1931 | /* | |
1932 | * Workaround for 88SX60x1 FEr SATA#24. | |
1933 | * | |
1934 | * Chip may corrupt WRITEs if multi_count >= 4kB. | |
1935 | * Note that READs are unaffected. | |
1936 | * | |
1937 | * It's not clear if this errata really means "4K bytes", | |
1938 | * or if it always happens for multi_count > 7 | |
1939 | * regardless of device sector_size. | |
1940 | * | |
1941 | * So, for safety, any write with multi_count > 7 | |
1942 | * gets converted here into a regular PIO write instead: | |
1943 | */ | |
1944 | if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { | |
1945 | if (qc->dev->multi_count > 7) { | |
1946 | switch (tf->command) { | |
1947 | case ATA_CMD_WRITE_MULTI: | |
1948 | tf->command = ATA_CMD_PIO_WRITE; | |
1949 | break; | |
1950 | case ATA_CMD_WRITE_MULTI_FUA_EXT: | |
1951 | tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ | |
1952 | /* fall through */ | |
1953 | case ATA_CMD_WRITE_MULTI_EXT: | |
1954 | tf->command = ATA_CMD_PIO_WRITE_EXT; | |
1955 | break; | |
1956 | } | |
1957 | } | |
1958 | } | |
1959 | } | |
1960 | ||
05b308e1 BR |
1961 | /** |
1962 | * mv_qc_prep - Host specific command preparation. | |
1963 | * @qc: queued command to prepare | |
1964 | * | |
1965 | * This routine simply redirects to the general purpose routine | |
1966 | * if command is not DMA. Else, it handles prep of the CRQB | |
1967 | * (command request block), does some sanity checking, and calls | |
1968 | * the SG load routine. | |
1969 | * | |
1970 | * LOCKING: | |
1971 | * Inherited from caller. | |
1972 | */ | |
31961943 BR |
1973 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
1974 | { | |
1975 | struct ata_port *ap = qc->ap; | |
1976 | struct mv_port_priv *pp = ap->private_data; | |
e1469874 | 1977 | __le16 *cw; |
8d2b450d | 1978 | struct ata_taskfile *tf = &qc->tf; |
31961943 | 1979 | u16 flags = 0; |
a6432436 | 1980 | unsigned in_index; |
31961943 | 1981 | |
299b3f8d ML |
1982 | switch (tf->protocol) { |
1983 | case ATA_PROT_DMA: | |
1984 | case ATA_PROT_NCQ: | |
1985 | break; /* continue below */ | |
1986 | case ATA_PROT_PIO: | |
1987 | mv_rw_multi_errata_sata24(qc); | |
31961943 | 1988 | return; |
299b3f8d ML |
1989 | default: |
1990 | return; | |
1991 | } | |
20f733e7 | 1992 | |
31961943 BR |
1993 | /* Fill in command request block |
1994 | */ | |
8d2b450d | 1995 | if (!(tf->flags & ATA_TFLAG_WRITE)) |
31961943 | 1996 | flags |= CRQB_FLAG_READ; |
beec7dbc | 1997 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
31961943 | 1998 | flags |= qc->tag << CRQB_TAG_SHIFT; |
e49856d8 | 1999 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
31961943 | 2000 | |
bdd4ddde | 2001 | /* get current queue index from software */ |
fcfb1f77 | 2002 | in_index = pp->req_idx; |
a6432436 ML |
2003 | |
2004 | pp->crqb[in_index].sg_addr = | |
eb73d558 | 2005 | cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); |
a6432436 | 2006 | pp->crqb[in_index].sg_addr_hi = |
eb73d558 | 2007 | cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); |
a6432436 | 2008 | pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); |
31961943 | 2009 | |
a6432436 | 2010 | cw = &pp->crqb[in_index].ata_cmd[0]; |
31961943 BR |
2011 | |
2012 | /* Sadly, the CRQB cannot accomodate all registers--there are | |
2013 | * only 11 bytes...so we must pick and choose required | |
2014 | * registers based on the command. So, we drop feature and | |
2015 | * hob_feature for [RW] DMA commands, but they are needed for | |
cd12e1f7 ML |
2016 | * NCQ. NCQ will drop hob_nsect, which is not needed there |
2017 | * (nsect is used only for the tag; feat/hob_feat hold true nsect). | |
20f733e7 | 2018 | */ |
31961943 BR |
2019 | switch (tf->command) { |
2020 | case ATA_CMD_READ: | |
2021 | case ATA_CMD_READ_EXT: | |
2022 | case ATA_CMD_WRITE: | |
2023 | case ATA_CMD_WRITE_EXT: | |
c15d85c8 | 2024 | case ATA_CMD_WRITE_FUA_EXT: |
31961943 BR |
2025 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); |
2026 | break; | |
31961943 BR |
2027 | case ATA_CMD_FPDMA_READ: |
2028 | case ATA_CMD_FPDMA_WRITE: | |
8b260248 | 2029 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
31961943 BR |
2030 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
2031 | break; | |
31961943 BR |
2032 | default: |
2033 | /* The only other commands EDMA supports in non-queued and | |
2034 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none | |
2035 | * of which are defined/used by Linux. If we get here, this | |
2036 | * driver needs work. | |
2037 | * | |
2038 | * FIXME: modify libata to give qc_prep a return value and | |
2039 | * return error here. | |
2040 | */ | |
2041 | BUG_ON(tf->command); | |
2042 | break; | |
2043 | } | |
2044 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); | |
2045 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); | |
2046 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); | |
2047 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); | |
2048 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); | |
2049 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); | |
2050 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); | |
2051 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); | |
2052 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ | |
2053 | ||
e4e7b892 JG |
2054 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
2055 | return; | |
2056 | mv_fill_sg(qc); | |
2057 | } | |
2058 | ||
2059 | /** | |
2060 | * mv_qc_prep_iie - Host specific command preparation. | |
2061 | * @qc: queued command to prepare | |
2062 | * | |
2063 | * This routine simply redirects to the general purpose routine | |
2064 | * if command is not DMA. Else, it handles prep of the CRQB | |
2065 | * (command request block), does some sanity checking, and calls | |
2066 | * the SG load routine. | |
2067 | * | |
2068 | * LOCKING: | |
2069 | * Inherited from caller. | |
2070 | */ | |
2071 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) | |
2072 | { | |
2073 | struct ata_port *ap = qc->ap; | |
2074 | struct mv_port_priv *pp = ap->private_data; | |
2075 | struct mv_crqb_iie *crqb; | |
8d2b450d | 2076 | struct ata_taskfile *tf = &qc->tf; |
a6432436 | 2077 | unsigned in_index; |
e4e7b892 JG |
2078 | u32 flags = 0; |
2079 | ||
8d2b450d ML |
2080 | if ((tf->protocol != ATA_PROT_DMA) && |
2081 | (tf->protocol != ATA_PROT_NCQ)) | |
e4e7b892 JG |
2082 | return; |
2083 | ||
e12bef50 | 2084 | /* Fill in Gen IIE command request block */ |
8d2b450d | 2085 | if (!(tf->flags & ATA_TFLAG_WRITE)) |
e4e7b892 JG |
2086 | flags |= CRQB_FLAG_READ; |
2087 | ||
beec7dbc | 2088 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
e4e7b892 | 2089 | flags |= qc->tag << CRQB_TAG_SHIFT; |
8c0aeb4a | 2090 | flags |= qc->tag << CRQB_HOSTQ_SHIFT; |
e49856d8 | 2091 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
e4e7b892 | 2092 | |
bdd4ddde | 2093 | /* get current queue index from software */ |
fcfb1f77 | 2094 | in_index = pp->req_idx; |
a6432436 ML |
2095 | |
2096 | crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; | |
eb73d558 ML |
2097 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); |
2098 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); | |
e4e7b892 JG |
2099 | crqb->flags = cpu_to_le32(flags); |
2100 | ||
e4e7b892 JG |
2101 | crqb->ata_cmd[0] = cpu_to_le32( |
2102 | (tf->command << 16) | | |
2103 | (tf->feature << 24) | |
2104 | ); | |
2105 | crqb->ata_cmd[1] = cpu_to_le32( | |
2106 | (tf->lbal << 0) | | |
2107 | (tf->lbam << 8) | | |
2108 | (tf->lbah << 16) | | |
2109 | (tf->device << 24) | |
2110 | ); | |
2111 | crqb->ata_cmd[2] = cpu_to_le32( | |
2112 | (tf->hob_lbal << 0) | | |
2113 | (tf->hob_lbam << 8) | | |
2114 | (tf->hob_lbah << 16) | | |
2115 | (tf->hob_feature << 24) | |
2116 | ); | |
2117 | crqb->ata_cmd[3] = cpu_to_le32( | |
2118 | (tf->nsect << 0) | | |
2119 | (tf->hob_nsect << 8) | |
2120 | ); | |
2121 | ||
2122 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
31961943 | 2123 | return; |
31961943 BR |
2124 | mv_fill_sg(qc); |
2125 | } | |
2126 | ||
d16ab3f6 ML |
2127 | /** |
2128 | * mv_sff_check_status - fetch device status, if valid | |
2129 | * @ap: ATA port to fetch status from | |
2130 | * | |
2131 | * When using command issue via mv_qc_issue_fis(), | |
2132 | * the initial ATA_BUSY state does not show up in the | |
2133 | * ATA status (shadow) register. This can confuse libata! | |
2134 | * | |
2135 | * So we have a hook here to fake ATA_BUSY for that situation, | |
2136 | * until the first time a BUSY, DRQ, or ERR bit is seen. | |
2137 | * | |
2138 | * The rest of the time, it simply returns the ATA status register. | |
2139 | */ | |
2140 | static u8 mv_sff_check_status(struct ata_port *ap) | |
2141 | { | |
2142 | u8 stat = ioread8(ap->ioaddr.status_addr); | |
2143 | struct mv_port_priv *pp = ap->private_data; | |
2144 | ||
2145 | if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { | |
2146 | if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) | |
2147 | pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; | |
2148 | else | |
2149 | stat = ATA_BUSY; | |
2150 | } | |
2151 | return stat; | |
2152 | } | |
2153 | ||
70f8b79c ML |
2154 | /** |
2155 | * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register | |
2156 | * @fis: fis to be sent | |
2157 | * @nwords: number of 32-bit words in the fis | |
2158 | */ | |
2159 | static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) | |
2160 | { | |
2161 | void __iomem *port_mmio = mv_ap_base(ap); | |
2162 | u32 ifctl, old_ifctl, ifstat; | |
2163 | int i, timeout = 200, final_word = nwords - 1; | |
2164 | ||
2165 | /* Initiate FIS transmission mode */ | |
cae5a29d | 2166 | old_ifctl = readl(port_mmio + SATA_IFCTL); |
70f8b79c | 2167 | ifctl = 0x100 | (old_ifctl & 0xf); |
cae5a29d | 2168 | writelfl(ifctl, port_mmio + SATA_IFCTL); |
70f8b79c ML |
2169 | |
2170 | /* Send all words of the FIS except for the final word */ | |
2171 | for (i = 0; i < final_word; ++i) | |
cae5a29d | 2172 | writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); |
70f8b79c ML |
2173 | |
2174 | /* Flag end-of-transmission, and then send the final word */ | |
cae5a29d ML |
2175 | writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); |
2176 | writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); | |
70f8b79c ML |
2177 | |
2178 | /* | |
2179 | * Wait for FIS transmission to complete. | |
2180 | * This typically takes just a single iteration. | |
2181 | */ | |
2182 | do { | |
cae5a29d | 2183 | ifstat = readl(port_mmio + SATA_IFSTAT); |
70f8b79c ML |
2184 | } while (!(ifstat & 0x1000) && --timeout); |
2185 | ||
2186 | /* Restore original port configuration */ | |
cae5a29d | 2187 | writelfl(old_ifctl, port_mmio + SATA_IFCTL); |
70f8b79c ML |
2188 | |
2189 | /* See if it worked */ | |
2190 | if ((ifstat & 0x3000) != 0x1000) { | |
2191 | ata_port_printk(ap, KERN_WARNING, | |
2192 | "%s transmission error, ifstat=%08x\n", | |
2193 | __func__, ifstat); | |
2194 | return AC_ERR_OTHER; | |
2195 | } | |
2196 | return 0; | |
2197 | } | |
2198 | ||
2199 | /** | |
2200 | * mv_qc_issue_fis - Issue a command directly as a FIS | |
2201 | * @qc: queued command to start | |
2202 | * | |
2203 | * Note that the ATA shadow registers are not updated | |
2204 | * after command issue, so the device will appear "READY" | |
2205 | * if polled, even while it is BUSY processing the command. | |
2206 | * | |
2207 | * So we use a status hook to fake ATA_BUSY until the drive changes state. | |
2208 | * | |
2209 | * Note: we don't get updated shadow regs on *completion* | |
2210 | * of non-data commands. So avoid sending them via this function, | |
2211 | * as they will appear to have completed immediately. | |
2212 | * | |
2213 | * GEN_IIE has special registers that we could get the result tf from, | |
2214 | * but earlier chipsets do not. For now, we ignore those registers. | |
2215 | */ | |
2216 | static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) | |
2217 | { | |
2218 | struct ata_port *ap = qc->ap; | |
2219 | struct mv_port_priv *pp = ap->private_data; | |
2220 | struct ata_link *link = qc->dev->link; | |
2221 | u32 fis[5]; | |
2222 | int err = 0; | |
2223 | ||
2224 | ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); | |
4c4a90fd | 2225 | err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); |
70f8b79c ML |
2226 | if (err) |
2227 | return err; | |
2228 | ||
2229 | switch (qc->tf.protocol) { | |
2230 | case ATAPI_PROT_PIO: | |
2231 | pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; | |
2232 | /* fall through */ | |
2233 | case ATAPI_PROT_NODATA: | |
2234 | ap->hsm_task_state = HSM_ST_FIRST; | |
2235 | break; | |
2236 | case ATA_PROT_PIO: | |
2237 | pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; | |
2238 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
2239 | ap->hsm_task_state = HSM_ST_FIRST; | |
2240 | else | |
2241 | ap->hsm_task_state = HSM_ST; | |
2242 | break; | |
2243 | default: | |
2244 | ap->hsm_task_state = HSM_ST_LAST; | |
2245 | break; | |
2246 | } | |
2247 | ||
2248 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
2249 | ata_pio_queue_task(ap, qc, 0); | |
2250 | return 0; | |
2251 | } | |
2252 | ||
05b308e1 BR |
2253 | /** |
2254 | * mv_qc_issue - Initiate a command to the host | |
2255 | * @qc: queued command to start | |
2256 | * | |
2257 | * This routine simply redirects to the general purpose routine | |
2258 | * if command is not DMA. Else, it sanity checks our local | |
2259 | * caches of the request producer/consumer indices then enables | |
2260 | * DMA and bumps the request producer index. | |
2261 | * | |
2262 | * LOCKING: | |
2263 | * Inherited from caller. | |
2264 | */ | |
9a3d9eb0 | 2265 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
31961943 | 2266 | { |
f48765cc | 2267 | static int limit_warnings = 10; |
c5d3e45a JG |
2268 | struct ata_port *ap = qc->ap; |
2269 | void __iomem *port_mmio = mv_ap_base(ap); | |
2270 | struct mv_port_priv *pp = ap->private_data; | |
bdd4ddde | 2271 | u32 in_index; |
42ed893d | 2272 | unsigned int port_irqs; |
f48765cc | 2273 | |
d16ab3f6 ML |
2274 | pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ |
2275 | ||
f48765cc ML |
2276 | switch (qc->tf.protocol) { |
2277 | case ATA_PROT_DMA: | |
2278 | case ATA_PROT_NCQ: | |
2279 | mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); | |
2280 | pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; | |
2281 | in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; | |
2282 | ||
2283 | /* Write the request in pointer to kick the EDMA to life */ | |
2284 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, | |
cae5a29d | 2285 | port_mmio + EDMA_REQ_Q_IN_PTR); |
f48765cc | 2286 | return 0; |
31961943 | 2287 | |
f48765cc | 2288 | case ATA_PROT_PIO: |
c6112bd8 ML |
2289 | /* |
2290 | * Errata SATA#16, SATA#24: warn if multiple DRQs expected. | |
2291 | * | |
2292 | * Someday, we might implement special polling workarounds | |
2293 | * for these, but it all seems rather unnecessary since we | |
2294 | * normally use only DMA for commands which transfer more | |
2295 | * than a single block of data. | |
2296 | * | |
2297 | * Much of the time, this could just work regardless. | |
2298 | * So for now, just log the incident, and allow the attempt. | |
2299 | */ | |
c7843e8f | 2300 | if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { |
c6112bd8 ML |
2301 | --limit_warnings; |
2302 | ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME | |
2303 | ": attempting PIO w/multiple DRQ: " | |
2304 | "this may fail due to h/w errata\n"); | |
2305 | } | |
f48765cc | 2306 | /* drop through */ |
42ed893d | 2307 | case ATA_PROT_NODATA: |
f48765cc | 2308 | case ATAPI_PROT_PIO: |
42ed893d ML |
2309 | case ATAPI_PROT_NODATA: |
2310 | if (ap->flags & ATA_FLAG_PIO_POLLING) | |
2311 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
2312 | break; | |
31961943 | 2313 | } |
42ed893d ML |
2314 | |
2315 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
2316 | port_irqs = ERR_IRQ; /* mask device interrupt when polling */ | |
2317 | else | |
2318 | port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ | |
2319 | ||
2320 | /* | |
2321 | * We're about to send a non-EDMA capable command to the | |
2322 | * port. Turn off EDMA so there won't be problems accessing | |
2323 | * shadow block, etc registers. | |
2324 | */ | |
2325 | mv_stop_edma(ap); | |
2326 | mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); | |
2327 | mv_pmp_select(ap, qc->dev->link->pmp); | |
70f8b79c ML |
2328 | |
2329 | if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { | |
2330 | struct mv_host_priv *hpriv = ap->host->private_data; | |
2331 | /* | |
2332 | * Workaround for 88SX60x1 FEr SATA#25 (part 2). | |
40f21b11 | 2333 | * |
70f8b79c ML |
2334 | * After any NCQ error, the READ_LOG_EXT command |
2335 | * from libata-eh *must* use mv_qc_issue_fis(). | |
2336 | * Otherwise it might fail, due to chip errata. | |
2337 | * | |
2338 | * Rather than special-case it, we'll just *always* | |
2339 | * use this method here for READ_LOG_EXT, making for | |
2340 | * easier testing. | |
2341 | */ | |
2342 | if (IS_GEN_II(hpriv)) | |
2343 | return mv_qc_issue_fis(qc); | |
2344 | } | |
42ed893d | 2345 | return ata_sff_qc_issue(qc); |
31961943 BR |
2346 | } |
2347 | ||
8f767f8a ML |
2348 | static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) |
2349 | { | |
2350 | struct mv_port_priv *pp = ap->private_data; | |
2351 | struct ata_queued_cmd *qc; | |
2352 | ||
2353 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) | |
2354 | return NULL; | |
2355 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
95db5051 ML |
2356 | if (qc) { |
2357 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
2358 | qc = NULL; | |
2359 | else if (!(qc->flags & ATA_QCFLAG_ACTIVE)) | |
2360 | qc = NULL; | |
2361 | } | |
8f767f8a ML |
2362 | return qc; |
2363 | } | |
2364 | ||
29d187bb ML |
2365 | static void mv_pmp_error_handler(struct ata_port *ap) |
2366 | { | |
2367 | unsigned int pmp, pmp_map; | |
2368 | struct mv_port_priv *pp = ap->private_data; | |
2369 | ||
2370 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { | |
2371 | /* | |
2372 | * Perform NCQ error analysis on failed PMPs | |
2373 | * before we freeze the port entirely. | |
2374 | * | |
2375 | * The failed PMPs are marked earlier by mv_pmp_eh_prep(). | |
2376 | */ | |
2377 | pmp_map = pp->delayed_eh_pmp_map; | |
2378 | pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; | |
2379 | for (pmp = 0; pmp_map != 0; pmp++) { | |
2380 | unsigned int this_pmp = (1 << pmp); | |
2381 | if (pmp_map & this_pmp) { | |
2382 | struct ata_link *link = &ap->pmp_link[pmp]; | |
2383 | pmp_map &= ~this_pmp; | |
2384 | ata_eh_analyze_ncq_error(link); | |
2385 | } | |
2386 | } | |
2387 | ata_port_freeze(ap); | |
2388 | } | |
2389 | sata_pmp_error_handler(ap); | |
2390 | } | |
2391 | ||
4c299ca3 ML |
2392 | static unsigned int mv_get_err_pmp_map(struct ata_port *ap) |
2393 | { | |
2394 | void __iomem *port_mmio = mv_ap_base(ap); | |
2395 | ||
cae5a29d | 2396 | return readl(port_mmio + SATA_TESTCTL) >> 16; |
4c299ca3 ML |
2397 | } |
2398 | ||
4c299ca3 ML |
2399 | static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) |
2400 | { | |
2401 | struct ata_eh_info *ehi; | |
2402 | unsigned int pmp; | |
2403 | ||
2404 | /* | |
2405 | * Initialize EH info for PMPs which saw device errors | |
2406 | */ | |
2407 | ehi = &ap->link.eh_info; | |
2408 | for (pmp = 0; pmp_map != 0; pmp++) { | |
2409 | unsigned int this_pmp = (1 << pmp); | |
2410 | if (pmp_map & this_pmp) { | |
2411 | struct ata_link *link = &ap->pmp_link[pmp]; | |
2412 | ||
2413 | pmp_map &= ~this_pmp; | |
2414 | ehi = &link->eh_info; | |
2415 | ata_ehi_clear_desc(ehi); | |
2416 | ata_ehi_push_desc(ehi, "dev err"); | |
2417 | ehi->err_mask |= AC_ERR_DEV; | |
2418 | ehi->action |= ATA_EH_RESET; | |
2419 | ata_link_abort(link); | |
2420 | } | |
2421 | } | |
2422 | } | |
2423 | ||
06aaca3f ML |
2424 | static int mv_req_q_empty(struct ata_port *ap) |
2425 | { | |
2426 | void __iomem *port_mmio = mv_ap_base(ap); | |
2427 | u32 in_ptr, out_ptr; | |
2428 | ||
cae5a29d | 2429 | in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) |
06aaca3f | 2430 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
cae5a29d | 2431 | out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) |
06aaca3f ML |
2432 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
2433 | return (in_ptr == out_ptr); /* 1 == queue_is_empty */ | |
2434 | } | |
2435 | ||
4c299ca3 ML |
2436 | static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) |
2437 | { | |
2438 | struct mv_port_priv *pp = ap->private_data; | |
2439 | int failed_links; | |
2440 | unsigned int old_map, new_map; | |
2441 | ||
2442 | /* | |
2443 | * Device error during FBS+NCQ operation: | |
2444 | * | |
2445 | * Set a port flag to prevent further I/O being enqueued. | |
2446 | * Leave the EDMA running to drain outstanding commands from this port. | |
2447 | * Perform the post-mortem/EH only when all responses are complete. | |
2448 | * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). | |
2449 | */ | |
2450 | if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { | |
2451 | pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; | |
2452 | pp->delayed_eh_pmp_map = 0; | |
2453 | } | |
2454 | old_map = pp->delayed_eh_pmp_map; | |
2455 | new_map = old_map | mv_get_err_pmp_map(ap); | |
2456 | ||
2457 | if (old_map != new_map) { | |
2458 | pp->delayed_eh_pmp_map = new_map; | |
2459 | mv_pmp_eh_prep(ap, new_map & ~old_map); | |
2460 | } | |
c46938cc | 2461 | failed_links = hweight16(new_map); |
4c299ca3 ML |
2462 | |
2463 | ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " | |
2464 | "failed_links=%d nr_active_links=%d\n", | |
2465 | __func__, pp->delayed_eh_pmp_map, | |
2466 | ap->qc_active, failed_links, | |
2467 | ap->nr_active_links); | |
2468 | ||
06aaca3f | 2469 | if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { |
4c299ca3 ML |
2470 | mv_process_crpb_entries(ap, pp); |
2471 | mv_stop_edma(ap); | |
2472 | mv_eh_freeze(ap); | |
2473 | ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); | |
2474 | return 1; /* handled */ | |
2475 | } | |
2476 | ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); | |
2477 | return 1; /* handled */ | |
2478 | } | |
2479 | ||
2480 | static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) | |
2481 | { | |
2482 | /* | |
2483 | * Possible future enhancement: | |
2484 | * | |
2485 | * FBS+non-NCQ operation is not yet implemented. | |
2486 | * See related notes in mv_edma_cfg(). | |
2487 | * | |
2488 | * Device error during FBS+non-NCQ operation: | |
2489 | * | |
2490 | * We need to snapshot the shadow registers for each failed command. | |
2491 | * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). | |
2492 | */ | |
2493 | return 0; /* not handled */ | |
2494 | } | |
2495 | ||
2496 | static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) | |
2497 | { | |
2498 | struct mv_port_priv *pp = ap->private_data; | |
2499 | ||
2500 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) | |
2501 | return 0; /* EDMA was not active: not handled */ | |
2502 | if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) | |
2503 | return 0; /* FBS was not active: not handled */ | |
2504 | ||
2505 | if (!(edma_err_cause & EDMA_ERR_DEV)) | |
2506 | return 0; /* non DEV error: not handled */ | |
2507 | edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; | |
2508 | if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) | |
2509 | return 0; /* other problems: not handled */ | |
2510 | ||
2511 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { | |
2512 | /* | |
2513 | * EDMA should NOT have self-disabled for this case. | |
2514 | * If it did, then something is wrong elsewhere, | |
2515 | * and we cannot handle it here. | |
2516 | */ | |
2517 | if (edma_err_cause & EDMA_ERR_SELF_DIS) { | |
2518 | ata_port_printk(ap, KERN_WARNING, | |
2519 | "%s: err_cause=0x%x pp_flags=0x%x\n", | |
2520 | __func__, edma_err_cause, pp->pp_flags); | |
2521 | return 0; /* not handled */ | |
2522 | } | |
2523 | return mv_handle_fbs_ncq_dev_err(ap); | |
2524 | } else { | |
2525 | /* | |
2526 | * EDMA should have self-disabled for this case. | |
2527 | * If it did not, then something is wrong elsewhere, | |
2528 | * and we cannot handle it here. | |
2529 | */ | |
2530 | if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { | |
2531 | ata_port_printk(ap, KERN_WARNING, | |
2532 | "%s: err_cause=0x%x pp_flags=0x%x\n", | |
2533 | __func__, edma_err_cause, pp->pp_flags); | |
2534 | return 0; /* not handled */ | |
2535 | } | |
2536 | return mv_handle_fbs_non_ncq_dev_err(ap); | |
2537 | } | |
2538 | return 0; /* not handled */ | |
2539 | } | |
2540 | ||
a9010329 | 2541 | static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) |
8f767f8a | 2542 | { |
8f767f8a | 2543 | struct ata_eh_info *ehi = &ap->link.eh_info; |
a9010329 | 2544 | char *when = "idle"; |
8f767f8a | 2545 | |
8f767f8a | 2546 | ata_ehi_clear_desc(ehi); |
c9abde12 | 2547 | if (ap->flags & ATA_FLAG_DISABLED) { |
a9010329 ML |
2548 | when = "disabled"; |
2549 | } else if (edma_was_enabled) { | |
2550 | when = "EDMA enabled"; | |
8f767f8a ML |
2551 | } else { |
2552 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
2553 | if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) | |
a9010329 | 2554 | when = "polling"; |
8f767f8a | 2555 | } |
a9010329 | 2556 | ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); |
8f767f8a ML |
2557 | ehi->err_mask |= AC_ERR_OTHER; |
2558 | ehi->action |= ATA_EH_RESET; | |
2559 | ata_port_freeze(ap); | |
2560 | } | |
2561 | ||
05b308e1 BR |
2562 | /** |
2563 | * mv_err_intr - Handle error interrupts on the port | |
2564 | * @ap: ATA channel to manipulate | |
2565 | * | |
8d07379d ML |
2566 | * Most cases require a full reset of the chip's state machine, |
2567 | * which also performs a COMRESET. | |
2568 | * Also, if the port disabled DMA, update our cached copy to match. | |
05b308e1 BR |
2569 | * |
2570 | * LOCKING: | |
2571 | * Inherited from caller. | |
2572 | */ | |
37b9046a | 2573 | static void mv_err_intr(struct ata_port *ap) |
31961943 BR |
2574 | { |
2575 | void __iomem *port_mmio = mv_ap_base(ap); | |
bdd4ddde | 2576 | u32 edma_err_cause, eh_freeze_mask, serr = 0; |
e4006077 | 2577 | u32 fis_cause = 0; |
bdd4ddde JG |
2578 | struct mv_port_priv *pp = ap->private_data; |
2579 | struct mv_host_priv *hpriv = ap->host->private_data; | |
bdd4ddde | 2580 | unsigned int action = 0, err_mask = 0; |
9af5c9c9 | 2581 | struct ata_eh_info *ehi = &ap->link.eh_info; |
37b9046a ML |
2582 | struct ata_queued_cmd *qc; |
2583 | int abort = 0; | |
20f733e7 | 2584 | |
8d07379d | 2585 | /* |
37b9046a | 2586 | * Read and clear the SError and err_cause bits. |
e4006077 ML |
2587 | * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear |
2588 | * the FIS_IRQ_CAUSE register before clearing edma_err_cause. | |
8d07379d | 2589 | */ |
37b9046a ML |
2590 | sata_scr_read(&ap->link, SCR_ERROR, &serr); |
2591 | sata_scr_write_flush(&ap->link, SCR_ERROR, serr); | |
2592 | ||
cae5a29d | 2593 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); |
e4006077 | 2594 | if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { |
cae5a29d ML |
2595 | fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); |
2596 | writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); | |
e4006077 | 2597 | } |
cae5a29d | 2598 | writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); |
bdd4ddde | 2599 | |
4c299ca3 ML |
2600 | if (edma_err_cause & EDMA_ERR_DEV) { |
2601 | /* | |
2602 | * Device errors during FIS-based switching operation | |
2603 | * require special handling. | |
2604 | */ | |
2605 | if (mv_handle_dev_err(ap, edma_err_cause)) | |
2606 | return; | |
2607 | } | |
2608 | ||
37b9046a ML |
2609 | qc = mv_get_active_qc(ap); |
2610 | ata_ehi_clear_desc(ehi); | |
2611 | ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", | |
2612 | edma_err_cause, pp->pp_flags); | |
e4006077 | 2613 | |
c443c500 | 2614 | if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { |
e4006077 | 2615 | ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); |
cae5a29d | 2616 | if (fis_cause & FIS_IRQ_CAUSE_AN) { |
c443c500 ML |
2617 | u32 ec = edma_err_cause & |
2618 | ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); | |
2619 | sata_async_notification(ap); | |
2620 | if (!ec) | |
2621 | return; /* Just an AN; no need for the nukes */ | |
2622 | ata_ehi_push_desc(ehi, "SDB notify"); | |
2623 | } | |
2624 | } | |
bdd4ddde | 2625 | /* |
352fab70 | 2626 | * All generations share these EDMA error cause bits: |
bdd4ddde | 2627 | */ |
37b9046a | 2628 | if (edma_err_cause & EDMA_ERR_DEV) { |
bdd4ddde | 2629 | err_mask |= AC_ERR_DEV; |
37b9046a ML |
2630 | action |= ATA_EH_RESET; |
2631 | ata_ehi_push_desc(ehi, "dev error"); | |
2632 | } | |
bdd4ddde | 2633 | if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
6c1153e0 | 2634 | EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | |
bdd4ddde JG |
2635 | EDMA_ERR_INTRL_PAR)) { |
2636 | err_mask |= AC_ERR_ATA_BUS; | |
cf480626 | 2637 | action |= ATA_EH_RESET; |
b64bbc39 | 2638 | ata_ehi_push_desc(ehi, "parity error"); |
bdd4ddde JG |
2639 | } |
2640 | if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { | |
2641 | ata_ehi_hotplugged(ehi); | |
2642 | ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? | |
b64bbc39 | 2643 | "dev disconnect" : "dev connect"); |
cf480626 | 2644 | action |= ATA_EH_RESET; |
bdd4ddde JG |
2645 | } |
2646 | ||
352fab70 ML |
2647 | /* |
2648 | * Gen-I has a different SELF_DIS bit, | |
2649 | * different FREEZE bits, and no SERR bit: | |
2650 | */ | |
ee9ccdf7 | 2651 | if (IS_GEN_I(hpriv)) { |
bdd4ddde | 2652 | eh_freeze_mask = EDMA_EH_FREEZE_5; |
bdd4ddde | 2653 | if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { |
bdd4ddde | 2654 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
b64bbc39 | 2655 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
bdd4ddde JG |
2656 | } |
2657 | } else { | |
2658 | eh_freeze_mask = EDMA_EH_FREEZE; | |
bdd4ddde | 2659 | if (edma_err_cause & EDMA_ERR_SELF_DIS) { |
bdd4ddde | 2660 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
b64bbc39 | 2661 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
bdd4ddde | 2662 | } |
bdd4ddde | 2663 | if (edma_err_cause & EDMA_ERR_SERR) { |
8d07379d ML |
2664 | ata_ehi_push_desc(ehi, "SError=%08x", serr); |
2665 | err_mask |= AC_ERR_ATA_BUS; | |
cf480626 | 2666 | action |= ATA_EH_RESET; |
bdd4ddde | 2667 | } |
afb0edd9 | 2668 | } |
20f733e7 | 2669 | |
bdd4ddde JG |
2670 | if (!err_mask) { |
2671 | err_mask = AC_ERR_OTHER; | |
cf480626 | 2672 | action |= ATA_EH_RESET; |
bdd4ddde JG |
2673 | } |
2674 | ||
2675 | ehi->serror |= serr; | |
2676 | ehi->action |= action; | |
2677 | ||
2678 | if (qc) | |
2679 | qc->err_mask |= err_mask; | |
2680 | else | |
2681 | ehi->err_mask |= err_mask; | |
2682 | ||
37b9046a ML |
2683 | if (err_mask == AC_ERR_DEV) { |
2684 | /* | |
2685 | * Cannot do ata_port_freeze() here, | |
2686 | * because it would kill PIO access, | |
2687 | * which is needed for further diagnosis. | |
2688 | */ | |
2689 | mv_eh_freeze(ap); | |
2690 | abort = 1; | |
2691 | } else if (edma_err_cause & eh_freeze_mask) { | |
2692 | /* | |
2693 | * Note to self: ata_port_freeze() calls ata_port_abort() | |
2694 | */ | |
bdd4ddde | 2695 | ata_port_freeze(ap); |
37b9046a ML |
2696 | } else { |
2697 | abort = 1; | |
2698 | } | |
2699 | ||
2700 | if (abort) { | |
2701 | if (qc) | |
2702 | ata_link_abort(qc->dev->link); | |
2703 | else | |
2704 | ata_port_abort(ap); | |
2705 | } | |
bdd4ddde JG |
2706 | } |
2707 | ||
fcfb1f77 ML |
2708 | static void mv_process_crpb_response(struct ata_port *ap, |
2709 | struct mv_crpb *response, unsigned int tag, int ncq_enabled) | |
2710 | { | |
2711 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); | |
2712 | ||
2713 | if (qc) { | |
2714 | u8 ata_status; | |
2715 | u16 edma_status = le16_to_cpu(response->flags); | |
2716 | /* | |
2717 | * edma_status from a response queue entry: | |
cae5a29d | 2718 | * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). |
fcfb1f77 ML |
2719 | * MSB is saved ATA status from command completion. |
2720 | */ | |
2721 | if (!ncq_enabled) { | |
2722 | u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; | |
2723 | if (err_cause) { | |
2724 | /* | |
2725 | * Error will be seen/handled by mv_err_intr(). | |
2726 | * So do nothing at all here. | |
2727 | */ | |
2728 | return; | |
2729 | } | |
2730 | } | |
2731 | ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; | |
37b9046a ML |
2732 | if (!ac_err_mask(ata_status)) |
2733 | ata_qc_complete(qc); | |
2734 | /* else: leave it for mv_err_intr() */ | |
fcfb1f77 ML |
2735 | } else { |
2736 | ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", | |
2737 | __func__, tag); | |
2738 | } | |
2739 | } | |
2740 | ||
2741 | static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) | |
bdd4ddde JG |
2742 | { |
2743 | void __iomem *port_mmio = mv_ap_base(ap); | |
2744 | struct mv_host_priv *hpriv = ap->host->private_data; | |
fcfb1f77 | 2745 | u32 in_index; |
bdd4ddde | 2746 | bool work_done = false; |
fcfb1f77 | 2747 | int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); |
bdd4ddde | 2748 | |
fcfb1f77 | 2749 | /* Get the hardware queue position index */ |
cae5a29d | 2750 | in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) |
bdd4ddde JG |
2751 | >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
2752 | ||
fcfb1f77 ML |
2753 | /* Process new responses from since the last time we looked */ |
2754 | while (in_index != pp->resp_idx) { | |
6c1153e0 | 2755 | unsigned int tag; |
fcfb1f77 | 2756 | struct mv_crpb *response = &pp->crpb[pp->resp_idx]; |
bdd4ddde | 2757 | |
fcfb1f77 | 2758 | pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; |
bdd4ddde | 2759 | |
fcfb1f77 ML |
2760 | if (IS_GEN_I(hpriv)) { |
2761 | /* 50xx: no NCQ, only one command active at a time */ | |
9af5c9c9 | 2762 | tag = ap->link.active_tag; |
fcfb1f77 ML |
2763 | } else { |
2764 | /* Gen II/IIE: get command tag from CRPB entry */ | |
2765 | tag = le16_to_cpu(response->id) & 0x1f; | |
bdd4ddde | 2766 | } |
fcfb1f77 | 2767 | mv_process_crpb_response(ap, response, tag, ncq_enabled); |
bdd4ddde | 2768 | work_done = true; |
bdd4ddde JG |
2769 | } |
2770 | ||
352fab70 | 2771 | /* Update the software queue position index in hardware */ |
bdd4ddde JG |
2772 | if (work_done) |
2773 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | | |
fcfb1f77 | 2774 | (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), |
cae5a29d | 2775 | port_mmio + EDMA_RSP_Q_OUT_PTR); |
20f733e7 BR |
2776 | } |
2777 | ||
a9010329 ML |
2778 | static void mv_port_intr(struct ata_port *ap, u32 port_cause) |
2779 | { | |
2780 | struct mv_port_priv *pp; | |
2781 | int edma_was_enabled; | |
2782 | ||
2783 | if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { | |
2784 | mv_unexpected_intr(ap, 0); | |
2785 | return; | |
2786 | } | |
2787 | /* | |
2788 | * Grab a snapshot of the EDMA_EN flag setting, | |
2789 | * so that we have a consistent view for this port, | |
2790 | * even if something we call of our routines changes it. | |
2791 | */ | |
2792 | pp = ap->private_data; | |
2793 | edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); | |
2794 | /* | |
2795 | * Process completed CRPB response(s) before other events. | |
2796 | */ | |
2797 | if (edma_was_enabled && (port_cause & DONE_IRQ)) { | |
2798 | mv_process_crpb_entries(ap, pp); | |
4c299ca3 ML |
2799 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) |
2800 | mv_handle_fbs_ncq_dev_err(ap); | |
a9010329 ML |
2801 | } |
2802 | /* | |
2803 | * Handle chip-reported errors, or continue on to handle PIO. | |
2804 | */ | |
2805 | if (unlikely(port_cause & ERR_IRQ)) { | |
2806 | mv_err_intr(ap); | |
2807 | } else if (!edma_was_enabled) { | |
2808 | struct ata_queued_cmd *qc = mv_get_active_qc(ap); | |
2809 | if (qc) | |
2810 | ata_sff_host_intr(ap, qc); | |
2811 | else | |
2812 | mv_unexpected_intr(ap, edma_was_enabled); | |
2813 | } | |
2814 | } | |
2815 | ||
05b308e1 BR |
2816 | /** |
2817 | * mv_host_intr - Handle all interrupts on the given host controller | |
cca3974e | 2818 | * @host: host specific structure |
7368f919 | 2819 | * @main_irq_cause: Main interrupt cause register for the chip. |
05b308e1 BR |
2820 | * |
2821 | * LOCKING: | |
2822 | * Inherited from caller. | |
2823 | */ | |
7368f919 | 2824 | static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) |
20f733e7 | 2825 | { |
f351b2d6 | 2826 | struct mv_host_priv *hpriv = host->private_data; |
eabd5eb1 | 2827 | void __iomem *mmio = hpriv->base, *hc_mmio; |
a3718c1f | 2828 | unsigned int handled = 0, port; |
20f733e7 | 2829 | |
2b748a0a ML |
2830 | /* If asserted, clear the "all ports" IRQ coalescing bit */ |
2831 | if (main_irq_cause & ALL_PORTS_COAL_DONE) | |
cae5a29d | 2832 | writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); |
2b748a0a | 2833 | |
a3718c1f | 2834 | for (port = 0; port < hpriv->n_ports; port++) { |
cca3974e | 2835 | struct ata_port *ap = host->ports[port]; |
eabd5eb1 ML |
2836 | unsigned int p, shift, hardport, port_cause; |
2837 | ||
a3718c1f | 2838 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); |
a3718c1f | 2839 | /* |
eabd5eb1 ML |
2840 | * Each hc within the host has its own hc_irq_cause register, |
2841 | * where the interrupting ports bits get ack'd. | |
a3718c1f | 2842 | */ |
eabd5eb1 ML |
2843 | if (hardport == 0) { /* first port on this hc ? */ |
2844 | u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; | |
2845 | u32 port_mask, ack_irqs; | |
2846 | /* | |
2847 | * Skip this entire hc if nothing pending for any ports | |
2848 | */ | |
2849 | if (!hc_cause) { | |
2850 | port += MV_PORTS_PER_HC - 1; | |
2851 | continue; | |
2852 | } | |
2853 | /* | |
2854 | * We don't need/want to read the hc_irq_cause register, | |
2855 | * because doing so hurts performance, and | |
2856 | * main_irq_cause already gives us everything we need. | |
2857 | * | |
2858 | * But we do have to *write* to the hc_irq_cause to ack | |
2859 | * the ports that we are handling this time through. | |
2860 | * | |
2861 | * This requires that we create a bitmap for those | |
2862 | * ports which interrupted us, and use that bitmap | |
2863 | * to ack (only) those ports via hc_irq_cause. | |
2864 | */ | |
2865 | ack_irqs = 0; | |
2b748a0a ML |
2866 | if (hc_cause & PORTS_0_3_COAL_DONE) |
2867 | ack_irqs = HC_COAL_IRQ; | |
eabd5eb1 ML |
2868 | for (p = 0; p < MV_PORTS_PER_HC; ++p) { |
2869 | if ((port + p) >= hpriv->n_ports) | |
2870 | break; | |
2871 | port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); | |
2872 | if (hc_cause & port_mask) | |
2873 | ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; | |
2874 | } | |
a3718c1f | 2875 | hc_mmio = mv_hc_base_from_port(mmio, port); |
cae5a29d | 2876 | writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); |
a3718c1f ML |
2877 | handled = 1; |
2878 | } | |
8f767f8a | 2879 | /* |
a9010329 | 2880 | * Handle interrupts signalled for this port: |
8f767f8a | 2881 | */ |
a9010329 ML |
2882 | port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); |
2883 | if (port_cause) | |
2884 | mv_port_intr(ap, port_cause); | |
20f733e7 | 2885 | } |
a3718c1f | 2886 | return handled; |
20f733e7 BR |
2887 | } |
2888 | ||
a3718c1f | 2889 | static int mv_pci_error(struct ata_host *host, void __iomem *mmio) |
bdd4ddde | 2890 | { |
02a121da | 2891 | struct mv_host_priv *hpriv = host->private_data; |
bdd4ddde JG |
2892 | struct ata_port *ap; |
2893 | struct ata_queued_cmd *qc; | |
2894 | struct ata_eh_info *ehi; | |
2895 | unsigned int i, err_mask, printed = 0; | |
2896 | u32 err_cause; | |
2897 | ||
cae5a29d | 2898 | err_cause = readl(mmio + hpriv->irq_cause_offset); |
bdd4ddde JG |
2899 | |
2900 | dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", | |
2901 | err_cause); | |
2902 | ||
2903 | DPRINTK("All regs @ PCI error\n"); | |
2904 | mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); | |
2905 | ||
cae5a29d | 2906 | writelfl(0, mmio + hpriv->irq_cause_offset); |
bdd4ddde JG |
2907 | |
2908 | for (i = 0; i < host->n_ports; i++) { | |
2909 | ap = host->ports[i]; | |
936fd732 | 2910 | if (!ata_link_offline(&ap->link)) { |
9af5c9c9 | 2911 | ehi = &ap->link.eh_info; |
bdd4ddde JG |
2912 | ata_ehi_clear_desc(ehi); |
2913 | if (!printed++) | |
2914 | ata_ehi_push_desc(ehi, | |
2915 | "PCI err cause 0x%08x", err_cause); | |
2916 | err_mask = AC_ERR_HOST_BUS; | |
cf480626 | 2917 | ehi->action = ATA_EH_RESET; |
9af5c9c9 | 2918 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
bdd4ddde JG |
2919 | if (qc) |
2920 | qc->err_mask |= err_mask; | |
2921 | else | |
2922 | ehi->err_mask |= err_mask; | |
2923 | ||
2924 | ata_port_freeze(ap); | |
2925 | } | |
2926 | } | |
a3718c1f | 2927 | return 1; /* handled */ |
bdd4ddde JG |
2928 | } |
2929 | ||
05b308e1 | 2930 | /** |
c5d3e45a | 2931 | * mv_interrupt - Main interrupt event handler |
05b308e1 BR |
2932 | * @irq: unused |
2933 | * @dev_instance: private data; in this case the host structure | |
05b308e1 BR |
2934 | * |
2935 | * Read the read only register to determine if any host | |
2936 | * controllers have pending interrupts. If so, call lower level | |
2937 | * routine to handle. Also check for PCI errors which are only | |
2938 | * reported here. | |
2939 | * | |
8b260248 | 2940 | * LOCKING: |
cca3974e | 2941 | * This routine holds the host lock while processing pending |
05b308e1 BR |
2942 | * interrupts. |
2943 | */ | |
7d12e780 | 2944 | static irqreturn_t mv_interrupt(int irq, void *dev_instance) |
20f733e7 | 2945 | { |
cca3974e | 2946 | struct ata_host *host = dev_instance; |
f351b2d6 | 2947 | struct mv_host_priv *hpriv = host->private_data; |
a3718c1f | 2948 | unsigned int handled = 0; |
6d3c30ef | 2949 | int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; |
96e2c487 | 2950 | u32 main_irq_cause, pending_irqs; |
20f733e7 | 2951 | |
646a4da5 | 2952 | spin_lock(&host->lock); |
6d3c30ef ML |
2953 | |
2954 | /* for MSI: block new interrupts while in here */ | |
2955 | if (using_msi) | |
2b748a0a | 2956 | mv_write_main_irq_mask(0, hpriv); |
6d3c30ef | 2957 | |
7368f919 | 2958 | main_irq_cause = readl(hpriv->main_irq_cause_addr); |
96e2c487 | 2959 | pending_irqs = main_irq_cause & hpriv->main_irq_mask; |
352fab70 ML |
2960 | /* |
2961 | * Deal with cases where we either have nothing pending, or have read | |
2962 | * a bogus register value which can indicate HW removal or PCI fault. | |
20f733e7 | 2963 | */ |
a44253d2 | 2964 | if (pending_irqs && main_irq_cause != 0xffffffffU) { |
1f398472 | 2965 | if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) |
a3718c1f ML |
2966 | handled = mv_pci_error(host, hpriv->base); |
2967 | else | |
a44253d2 | 2968 | handled = mv_host_intr(host, pending_irqs); |
bdd4ddde | 2969 | } |
6d3c30ef ML |
2970 | |
2971 | /* for MSI: unmask; interrupt cause bits will retrigger now */ | |
2972 | if (using_msi) | |
2b748a0a | 2973 | mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); |
6d3c30ef | 2974 | |
9d51af7b ML |
2975 | spin_unlock(&host->lock); |
2976 | ||
20f733e7 BR |
2977 | return IRQ_RETVAL(handled); |
2978 | } | |
2979 | ||
c9d39130 JG |
2980 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) |
2981 | { | |
2982 | unsigned int ofs; | |
2983 | ||
2984 | switch (sc_reg_in) { | |
2985 | case SCR_STATUS: | |
2986 | case SCR_ERROR: | |
2987 | case SCR_CONTROL: | |
2988 | ofs = sc_reg_in * sizeof(u32); | |
2989 | break; | |
2990 | default: | |
2991 | ofs = 0xffffffffU; | |
2992 | break; | |
2993 | } | |
2994 | return ofs; | |
2995 | } | |
2996 | ||
82ef04fb | 2997 | static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) |
c9d39130 | 2998 | { |
82ef04fb | 2999 | struct mv_host_priv *hpriv = link->ap->host->private_data; |
f351b2d6 | 3000 | void __iomem *mmio = hpriv->base; |
82ef04fb | 3001 | void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); |
c9d39130 JG |
3002 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
3003 | ||
da3dbb17 TH |
3004 | if (ofs != 0xffffffffU) { |
3005 | *val = readl(addr + ofs); | |
3006 | return 0; | |
3007 | } else | |
3008 | return -EINVAL; | |
c9d39130 JG |
3009 | } |
3010 | ||
82ef04fb | 3011 | static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) |
c9d39130 | 3012 | { |
82ef04fb | 3013 | struct mv_host_priv *hpriv = link->ap->host->private_data; |
f351b2d6 | 3014 | void __iomem *mmio = hpriv->base; |
82ef04fb | 3015 | void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); |
c9d39130 JG |
3016 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
3017 | ||
da3dbb17 | 3018 | if (ofs != 0xffffffffU) { |
0d5ff566 | 3019 | writelfl(val, addr + ofs); |
da3dbb17 TH |
3020 | return 0; |
3021 | } else | |
3022 | return -EINVAL; | |
c9d39130 JG |
3023 | } |
3024 | ||
7bb3c529 | 3025 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) |
522479fb | 3026 | { |
7bb3c529 | 3027 | struct pci_dev *pdev = to_pci_dev(host->dev); |
522479fb JG |
3028 | int early_5080; |
3029 | ||
44c10138 | 3030 | early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); |
522479fb JG |
3031 | |
3032 | if (!early_5080) { | |
3033 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
3034 | tmp |= (1 << 0); | |
3035 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
3036 | } | |
3037 | ||
7bb3c529 | 3038 | mv_reset_pci_bus(host, mmio); |
522479fb JG |
3039 | } |
3040 | ||
3041 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
3042 | { | |
cae5a29d | 3043 | writel(0x0fcfffff, mmio + FLASH_CTL); |
522479fb JG |
3044 | } |
3045 | ||
47c2b677 | 3046 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
3047 | void __iomem *mmio) |
3048 | { | |
c9d39130 JG |
3049 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
3050 | u32 tmp; | |
3051 | ||
3052 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
3053 | ||
3054 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ | |
3055 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ | |
ba3fe8fb JG |
3056 | } |
3057 | ||
47c2b677 | 3058 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 3059 | { |
522479fb JG |
3060 | u32 tmp; |
3061 | ||
cae5a29d | 3062 | writel(0, mmio + GPIO_PORT_CTL); |
522479fb JG |
3063 | |
3064 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ | |
3065 | ||
3066 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
3067 | tmp |= ~(1 << 0); | |
3068 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
ba3fe8fb JG |
3069 | } |
3070 | ||
2a47ce06 JG |
3071 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
3072 | unsigned int port) | |
bca1c4eb | 3073 | { |
c9d39130 JG |
3074 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
3075 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); | |
3076 | u32 tmp; | |
3077 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); | |
3078 | ||
3079 | if (fix_apm_sq) { | |
cae5a29d | 3080 | tmp = readl(phy_mmio + MV5_LTMODE); |
c9d39130 | 3081 | tmp |= (1 << 19); |
cae5a29d | 3082 | writel(tmp, phy_mmio + MV5_LTMODE); |
c9d39130 | 3083 | |
cae5a29d | 3084 | tmp = readl(phy_mmio + MV5_PHY_CTL); |
c9d39130 JG |
3085 | tmp &= ~0x3; |
3086 | tmp |= 0x1; | |
cae5a29d | 3087 | writel(tmp, phy_mmio + MV5_PHY_CTL); |
c9d39130 JG |
3088 | } |
3089 | ||
3090 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
3091 | tmp &= ~mask; | |
3092 | tmp |= hpriv->signal[port].pre; | |
3093 | tmp |= hpriv->signal[port].amps; | |
3094 | writel(tmp, phy_mmio + MV5_PHY_MODE); | |
bca1c4eb JG |
3095 | } |
3096 | ||
c9d39130 JG |
3097 | |
3098 | #undef ZERO | |
3099 | #define ZERO(reg) writel(0, port_mmio + (reg)) | |
3100 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, | |
3101 | unsigned int port) | |
3102 | { | |
3103 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
3104 | ||
e12bef50 | 3105 | mv_reset_channel(hpriv, mmio, port); |
c9d39130 JG |
3106 | |
3107 | ZERO(0x028); /* command */ | |
cae5a29d | 3108 | writel(0x11f, port_mmio + EDMA_CFG); |
c9d39130 JG |
3109 | ZERO(0x004); /* timer */ |
3110 | ZERO(0x008); /* irq err cause */ | |
3111 | ZERO(0x00c); /* irq err mask */ | |
3112 | ZERO(0x010); /* rq bah */ | |
3113 | ZERO(0x014); /* rq inp */ | |
3114 | ZERO(0x018); /* rq outp */ | |
3115 | ZERO(0x01c); /* respq bah */ | |
3116 | ZERO(0x024); /* respq outp */ | |
3117 | ZERO(0x020); /* respq inp */ | |
3118 | ZERO(0x02c); /* test control */ | |
cae5a29d | 3119 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); |
c9d39130 JG |
3120 | } |
3121 | #undef ZERO | |
3122 | ||
3123 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | |
3124 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
3125 | unsigned int hc) | |
47c2b677 | 3126 | { |
c9d39130 JG |
3127 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
3128 | u32 tmp; | |
3129 | ||
3130 | ZERO(0x00c); | |
3131 | ZERO(0x010); | |
3132 | ZERO(0x014); | |
3133 | ZERO(0x018); | |
3134 | ||
3135 | tmp = readl(hc_mmio + 0x20); | |
3136 | tmp &= 0x1c1c1c1c; | |
3137 | tmp |= 0x03030303; | |
3138 | writel(tmp, hc_mmio + 0x20); | |
3139 | } | |
3140 | #undef ZERO | |
3141 | ||
3142 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
3143 | unsigned int n_hc) | |
3144 | { | |
3145 | unsigned int hc, port; | |
3146 | ||
3147 | for (hc = 0; hc < n_hc; hc++) { | |
3148 | for (port = 0; port < MV_PORTS_PER_HC; port++) | |
3149 | mv5_reset_hc_port(hpriv, mmio, | |
3150 | (hc * MV_PORTS_PER_HC) + port); | |
3151 | ||
3152 | mv5_reset_one_hc(hpriv, mmio, hc); | |
3153 | } | |
3154 | ||
3155 | return 0; | |
47c2b677 JG |
3156 | } |
3157 | ||
101ffae2 JG |
3158 | #undef ZERO |
3159 | #define ZERO(reg) writel(0, mmio + (reg)) | |
7bb3c529 | 3160 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) |
101ffae2 | 3161 | { |
02a121da | 3162 | struct mv_host_priv *hpriv = host->private_data; |
101ffae2 JG |
3163 | u32 tmp; |
3164 | ||
cae5a29d | 3165 | tmp = readl(mmio + MV_PCI_MODE); |
101ffae2 | 3166 | tmp &= 0xff00ffff; |
cae5a29d | 3167 | writel(tmp, mmio + MV_PCI_MODE); |
101ffae2 JG |
3168 | |
3169 | ZERO(MV_PCI_DISC_TIMER); | |
3170 | ZERO(MV_PCI_MSI_TRIGGER); | |
cae5a29d | 3171 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); |
101ffae2 | 3172 | ZERO(MV_PCI_SERR_MASK); |
cae5a29d ML |
3173 | ZERO(hpriv->irq_cause_offset); |
3174 | ZERO(hpriv->irq_mask_offset); | |
101ffae2 JG |
3175 | ZERO(MV_PCI_ERR_LOW_ADDRESS); |
3176 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); | |
3177 | ZERO(MV_PCI_ERR_ATTRIBUTE); | |
3178 | ZERO(MV_PCI_ERR_COMMAND); | |
3179 | } | |
3180 | #undef ZERO | |
3181 | ||
3182 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
3183 | { | |
3184 | u32 tmp; | |
3185 | ||
3186 | mv5_reset_flash(hpriv, mmio); | |
3187 | ||
cae5a29d | 3188 | tmp = readl(mmio + GPIO_PORT_CTL); |
101ffae2 JG |
3189 | tmp &= 0x3; |
3190 | tmp |= (1 << 5) | (1 << 6); | |
cae5a29d | 3191 | writel(tmp, mmio + GPIO_PORT_CTL); |
101ffae2 JG |
3192 | } |
3193 | ||
3194 | /** | |
3195 | * mv6_reset_hc - Perform the 6xxx global soft reset | |
3196 | * @mmio: base address of the HBA | |
3197 | * | |
3198 | * This routine only applies to 6xxx parts. | |
3199 | * | |
3200 | * LOCKING: | |
3201 | * Inherited from caller. | |
3202 | */ | |
c9d39130 JG |
3203 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
3204 | unsigned int n_hc) | |
101ffae2 | 3205 | { |
cae5a29d | 3206 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS; |
101ffae2 JG |
3207 | int i, rc = 0; |
3208 | u32 t; | |
3209 | ||
3210 | /* Following procedure defined in PCI "main command and status | |
3211 | * register" table. | |
3212 | */ | |
3213 | t = readl(reg); | |
3214 | writel(t | STOP_PCI_MASTER, reg); | |
3215 | ||
3216 | for (i = 0; i < 1000; i++) { | |
3217 | udelay(1); | |
3218 | t = readl(reg); | |
2dcb407e | 3219 | if (PCI_MASTER_EMPTY & t) |
101ffae2 | 3220 | break; |
101ffae2 JG |
3221 | } |
3222 | if (!(PCI_MASTER_EMPTY & t)) { | |
3223 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); | |
3224 | rc = 1; | |
3225 | goto done; | |
3226 | } | |
3227 | ||
3228 | /* set reset */ | |
3229 | i = 5; | |
3230 | do { | |
3231 | writel(t | GLOB_SFT_RST, reg); | |
3232 | t = readl(reg); | |
3233 | udelay(1); | |
3234 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); | |
3235 | ||
3236 | if (!(GLOB_SFT_RST & t)) { | |
3237 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); | |
3238 | rc = 1; | |
3239 | goto done; | |
3240 | } | |
3241 | ||
3242 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ | |
3243 | i = 5; | |
3244 | do { | |
3245 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); | |
3246 | t = readl(reg); | |
3247 | udelay(1); | |
3248 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); | |
3249 | ||
3250 | if (GLOB_SFT_RST & t) { | |
3251 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); | |
3252 | rc = 1; | |
3253 | } | |
3254 | done: | |
3255 | return rc; | |
3256 | } | |
3257 | ||
47c2b677 | 3258 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
3259 | void __iomem *mmio) |
3260 | { | |
3261 | void __iomem *port_mmio; | |
3262 | u32 tmp; | |
3263 | ||
cae5a29d | 3264 | tmp = readl(mmio + RESET_CFG); |
ba3fe8fb | 3265 | if ((tmp & (1 << 0)) == 0) { |
47c2b677 | 3266 | hpriv->signal[idx].amps = 0x7 << 8; |
ba3fe8fb JG |
3267 | hpriv->signal[idx].pre = 0x1 << 5; |
3268 | return; | |
3269 | } | |
3270 | ||
3271 | port_mmio = mv_port_base(mmio, idx); | |
3272 | tmp = readl(port_mmio + PHY_MODE2); | |
3273 | ||
3274 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
3275 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
3276 | } | |
3277 | ||
47c2b677 | 3278 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 3279 | { |
cae5a29d | 3280 | writel(0x00000060, mmio + GPIO_PORT_CTL); |
ba3fe8fb JG |
3281 | } |
3282 | ||
c9d39130 | 3283 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
2a47ce06 | 3284 | unsigned int port) |
bca1c4eb | 3285 | { |
c9d39130 JG |
3286 | void __iomem *port_mmio = mv_port_base(mmio, port); |
3287 | ||
bca1c4eb | 3288 | u32 hp_flags = hpriv->hp_flags; |
47c2b677 JG |
3289 | int fix_phy_mode2 = |
3290 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); | |
bca1c4eb | 3291 | int fix_phy_mode4 = |
47c2b677 | 3292 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
8c30a8b9 | 3293 | u32 m2, m3; |
47c2b677 JG |
3294 | |
3295 | if (fix_phy_mode2) { | |
3296 | m2 = readl(port_mmio + PHY_MODE2); | |
3297 | m2 &= ~(1 << 16); | |
3298 | m2 |= (1 << 31); | |
3299 | writel(m2, port_mmio + PHY_MODE2); | |
3300 | ||
3301 | udelay(200); | |
3302 | ||
3303 | m2 = readl(port_mmio + PHY_MODE2); | |
3304 | m2 &= ~((1 << 16) | (1 << 31)); | |
3305 | writel(m2, port_mmio + PHY_MODE2); | |
3306 | ||
3307 | udelay(200); | |
3308 | } | |
3309 | ||
8c30a8b9 ML |
3310 | /* |
3311 | * Gen-II/IIe PHY_MODE3 errata RM#2: | |
3312 | * Achieves better receiver noise performance than the h/w default: | |
3313 | */ | |
3314 | m3 = readl(port_mmio + PHY_MODE3); | |
3315 | m3 = (m3 & 0x1f) | (0x5555601 << 5); | |
bca1c4eb | 3316 | |
0388a8c0 ML |
3317 | /* Guideline 88F5182 (GL# SATA-S11) */ |
3318 | if (IS_SOC(hpriv)) | |
3319 | m3 &= ~0x1c; | |
3320 | ||
bca1c4eb | 3321 | if (fix_phy_mode4) { |
ba069e37 ML |
3322 | u32 m4 = readl(port_mmio + PHY_MODE4); |
3323 | /* | |
3324 | * Enforce reserved-bit restrictions on GenIIe devices only. | |
3325 | * For earlier chipsets, force only the internal config field | |
3326 | * (workaround for errata FEr SATA#10 part 1). | |
3327 | */ | |
8c30a8b9 | 3328 | if (IS_GEN_IIE(hpriv)) |
ba069e37 ML |
3329 | m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; |
3330 | else | |
3331 | m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; | |
8c30a8b9 | 3332 | writel(m4, port_mmio + PHY_MODE4); |
bca1c4eb | 3333 | } |
b406c7a6 ML |
3334 | /* |
3335 | * Workaround for 60x1-B2 errata SATA#13: | |
3336 | * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, | |
3337 | * so we must always rewrite PHY_MODE3 after PHY_MODE4. | |
ba68460b | 3338 | * Or ensure we use writelfl() when writing PHY_MODE4. |
b406c7a6 ML |
3339 | */ |
3340 | writel(m3, port_mmio + PHY_MODE3); | |
bca1c4eb JG |
3341 | |
3342 | /* Revert values of pre-emphasis and signal amps to the saved ones */ | |
3343 | m2 = readl(port_mmio + PHY_MODE2); | |
3344 | ||
3345 | m2 &= ~MV_M2_PREAMP_MASK; | |
2a47ce06 JG |
3346 | m2 |= hpriv->signal[port].amps; |
3347 | m2 |= hpriv->signal[port].pre; | |
47c2b677 | 3348 | m2 &= ~(1 << 16); |
bca1c4eb | 3349 | |
e4e7b892 JG |
3350 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
3351 | if (IS_GEN_IIE(hpriv)) { | |
3352 | m2 &= ~0xC30FF01F; | |
3353 | m2 |= 0x0000900F; | |
3354 | } | |
3355 | ||
bca1c4eb JG |
3356 | writel(m2, port_mmio + PHY_MODE2); |
3357 | } | |
3358 | ||
f351b2d6 SB |
3359 | /* TODO: use the generic LED interface to configure the SATA Presence */ |
3360 | /* & Acitivy LEDs on the board */ | |
3361 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, | |
3362 | void __iomem *mmio) | |
3363 | { | |
3364 | return; | |
3365 | } | |
3366 | ||
3367 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, | |
3368 | void __iomem *mmio) | |
3369 | { | |
3370 | void __iomem *port_mmio; | |
3371 | u32 tmp; | |
3372 | ||
3373 | port_mmio = mv_port_base(mmio, idx); | |
3374 | tmp = readl(port_mmio + PHY_MODE2); | |
3375 | ||
3376 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
3377 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
3378 | } | |
3379 | ||
3380 | #undef ZERO | |
3381 | #define ZERO(reg) writel(0, port_mmio + (reg)) | |
3382 | static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, | |
3383 | void __iomem *mmio, unsigned int port) | |
3384 | { | |
3385 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
3386 | ||
e12bef50 | 3387 | mv_reset_channel(hpriv, mmio, port); |
f351b2d6 SB |
3388 | |
3389 | ZERO(0x028); /* command */ | |
cae5a29d | 3390 | writel(0x101f, port_mmio + EDMA_CFG); |
f351b2d6 SB |
3391 | ZERO(0x004); /* timer */ |
3392 | ZERO(0x008); /* irq err cause */ | |
3393 | ZERO(0x00c); /* irq err mask */ | |
3394 | ZERO(0x010); /* rq bah */ | |
3395 | ZERO(0x014); /* rq inp */ | |
3396 | ZERO(0x018); /* rq outp */ | |
3397 | ZERO(0x01c); /* respq bah */ | |
3398 | ZERO(0x024); /* respq outp */ | |
3399 | ZERO(0x020); /* respq inp */ | |
3400 | ZERO(0x02c); /* test control */ | |
d7b0c143 | 3401 | writel(0x800, port_mmio + EDMA_IORDY_TMOUT); |
f351b2d6 SB |
3402 | } |
3403 | ||
3404 | #undef ZERO | |
3405 | ||
3406 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | |
3407 | static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, | |
3408 | void __iomem *mmio) | |
3409 | { | |
3410 | void __iomem *hc_mmio = mv_hc_base(mmio, 0); | |
3411 | ||
3412 | ZERO(0x00c); | |
3413 | ZERO(0x010); | |
3414 | ZERO(0x014); | |
3415 | ||
3416 | } | |
3417 | ||
3418 | #undef ZERO | |
3419 | ||
3420 | static int mv_soc_reset_hc(struct mv_host_priv *hpriv, | |
3421 | void __iomem *mmio, unsigned int n_hc) | |
3422 | { | |
3423 | unsigned int port; | |
3424 | ||
3425 | for (port = 0; port < hpriv->n_ports; port++) | |
3426 | mv_soc_reset_hc_port(hpriv, mmio, port); | |
3427 | ||
3428 | mv_soc_reset_one_hc(hpriv, mmio); | |
3429 | ||
3430 | return 0; | |
3431 | } | |
3432 | ||
3433 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, | |
3434 | void __iomem *mmio) | |
3435 | { | |
3436 | return; | |
3437 | } | |
3438 | ||
3439 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) | |
3440 | { | |
3441 | return; | |
3442 | } | |
3443 | ||
29b7e43c MM |
3444 | static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, |
3445 | void __iomem *mmio, unsigned int port) | |
3446 | { | |
3447 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
3448 | u32 reg; | |
3449 | ||
3450 | reg = readl(port_mmio + PHY_MODE3); | |
3451 | reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ | |
3452 | reg |= (0x1 << 27); | |
3453 | reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ | |
3454 | reg |= (0x1 << 29); | |
3455 | writel(reg, port_mmio + PHY_MODE3); | |
3456 | ||
3457 | reg = readl(port_mmio + PHY_MODE4); | |
3458 | reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ | |
3459 | reg |= (0x1 << 16); | |
3460 | writel(reg, port_mmio + PHY_MODE4); | |
3461 | ||
3462 | reg = readl(port_mmio + PHY_MODE9_GEN2); | |
3463 | reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ | |
3464 | reg |= 0x8; | |
3465 | reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ | |
3466 | writel(reg, port_mmio + PHY_MODE9_GEN2); | |
3467 | ||
3468 | reg = readl(port_mmio + PHY_MODE9_GEN1); | |
3469 | reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ | |
3470 | reg |= 0x8; | |
3471 | reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ | |
3472 | writel(reg, port_mmio + PHY_MODE9_GEN1); | |
3473 | } | |
3474 | ||
3475 | /** | |
3476 | * soc_is_65 - check if the soc is 65 nano device | |
3477 | * | |
3478 | * Detect the type of the SoC, this is done by reading the PHYCFG_OFS | |
3479 | * register, this register should contain non-zero value and it exists only | |
3480 | * in the 65 nano devices, when reading it from older devices we get 0. | |
3481 | */ | |
3482 | static bool soc_is_65n(struct mv_host_priv *hpriv) | |
3483 | { | |
3484 | void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); | |
3485 | ||
3486 | if (readl(port0_mmio + PHYCFG_OFS)) | |
3487 | return true; | |
3488 | return false; | |
3489 | } | |
3490 | ||
8e7decdb | 3491 | static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) |
b67a1064 | 3492 | { |
cae5a29d | 3493 | u32 ifcfg = readl(port_mmio + SATA_IFCFG); |
b67a1064 | 3494 | |
8e7decdb | 3495 | ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ |
b67a1064 | 3496 | if (want_gen2i) |
8e7decdb | 3497 | ifcfg |= (1 << 7); /* enable gen2i speed */ |
cae5a29d | 3498 | writelfl(ifcfg, port_mmio + SATA_IFCFG); |
b67a1064 ML |
3499 | } |
3500 | ||
e12bef50 | 3501 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
c9d39130 JG |
3502 | unsigned int port_no) |
3503 | { | |
3504 | void __iomem *port_mmio = mv_port_base(mmio, port_no); | |
3505 | ||
8e7decdb ML |
3506 | /* |
3507 | * The datasheet warns against setting EDMA_RESET when EDMA is active | |
3508 | * (but doesn't say what the problem might be). So we first try | |
3509 | * to disable the EDMA engine before doing the EDMA_RESET operation. | |
3510 | */ | |
0d8be5cb | 3511 | mv_stop_edma_engine(port_mmio); |
cae5a29d | 3512 | writelfl(EDMA_RESET, port_mmio + EDMA_CMD); |
c9d39130 | 3513 | |
b67a1064 | 3514 | if (!IS_GEN_I(hpriv)) { |
8e7decdb ML |
3515 | /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ |
3516 | mv_setup_ifcfg(port_mmio, 1); | |
c9d39130 | 3517 | } |
b67a1064 | 3518 | /* |
8e7decdb | 3519 | * Strobing EDMA_RESET here causes a hard reset of the SATA transport, |
b67a1064 | 3520 | * link, and physical layers. It resets all SATA interface registers |
cae5a29d | 3521 | * (except for SATA_IFCFG), and issues a COMRESET to the dev. |
c9d39130 | 3522 | */ |
cae5a29d | 3523 | writelfl(EDMA_RESET, port_mmio + EDMA_CMD); |
b67a1064 | 3524 | udelay(25); /* allow reset propagation */ |
cae5a29d | 3525 | writelfl(0, port_mmio + EDMA_CMD); |
c9d39130 JG |
3526 | |
3527 | hpriv->ops->phy_errata(hpriv, mmio, port_no); | |
3528 | ||
ee9ccdf7 | 3529 | if (IS_GEN_I(hpriv)) |
c9d39130 JG |
3530 | mdelay(1); |
3531 | } | |
3532 | ||
e49856d8 | 3533 | static void mv_pmp_select(struct ata_port *ap, int pmp) |
20f733e7 | 3534 | { |
e49856d8 ML |
3535 | if (sata_pmp_supported(ap)) { |
3536 | void __iomem *port_mmio = mv_ap_base(ap); | |
cae5a29d | 3537 | u32 reg = readl(port_mmio + SATA_IFCTL); |
e49856d8 | 3538 | int old = reg & 0xf; |
22374677 | 3539 | |
e49856d8 ML |
3540 | if (old != pmp) { |
3541 | reg = (reg & ~0xf) | pmp; | |
cae5a29d | 3542 | writelfl(reg, port_mmio + SATA_IFCTL); |
e49856d8 | 3543 | } |
22374677 | 3544 | } |
20f733e7 BR |
3545 | } |
3546 | ||
e49856d8 ML |
3547 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, |
3548 | unsigned long deadline) | |
22374677 | 3549 | { |
e49856d8 ML |
3550 | mv_pmp_select(link->ap, sata_srst_pmp(link)); |
3551 | return sata_std_hardreset(link, class, deadline); | |
3552 | } | |
bdd4ddde | 3553 | |
e49856d8 ML |
3554 | static int mv_softreset(struct ata_link *link, unsigned int *class, |
3555 | unsigned long deadline) | |
3556 | { | |
3557 | mv_pmp_select(link->ap, sata_srst_pmp(link)); | |
3558 | return ata_sff_softreset(link, class, deadline); | |
22374677 JG |
3559 | } |
3560 | ||
cc0680a5 | 3561 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
bdd4ddde | 3562 | unsigned long deadline) |
31961943 | 3563 | { |
cc0680a5 | 3564 | struct ata_port *ap = link->ap; |
bdd4ddde | 3565 | struct mv_host_priv *hpriv = ap->host->private_data; |
b562468c | 3566 | struct mv_port_priv *pp = ap->private_data; |
f351b2d6 | 3567 | void __iomem *mmio = hpriv->base; |
0d8be5cb ML |
3568 | int rc, attempts = 0, extra = 0; |
3569 | u32 sstatus; | |
3570 | bool online; | |
31961943 | 3571 | |
e12bef50 | 3572 | mv_reset_channel(hpriv, mmio, ap->port_no); |
b562468c | 3573 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
d16ab3f6 ML |
3574 | pp->pp_flags &= |
3575 | ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); | |
bdd4ddde | 3576 | |
0d8be5cb ML |
3577 | /* Workaround for errata FEr SATA#10 (part 2) */ |
3578 | do { | |
17c5aab5 ML |
3579 | const unsigned long *timing = |
3580 | sata_ehc_deb_timing(&link->eh_context); | |
bdd4ddde | 3581 | |
17c5aab5 ML |
3582 | rc = sata_link_hardreset(link, timing, deadline + extra, |
3583 | &online, NULL); | |
9dcffd99 | 3584 | rc = online ? -EAGAIN : rc; |
17c5aab5 | 3585 | if (rc) |
0d8be5cb | 3586 | return rc; |
0d8be5cb ML |
3587 | sata_scr_read(link, SCR_STATUS, &sstatus); |
3588 | if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { | |
3589 | /* Force 1.5gb/s link speed and try again */ | |
8e7decdb | 3590 | mv_setup_ifcfg(mv_ap_base(ap), 0); |
0d8be5cb ML |
3591 | if (time_after(jiffies + HZ, deadline)) |
3592 | extra = HZ; /* only extend it once, max */ | |
3593 | } | |
3594 | } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); | |
08da1759 | 3595 | mv_save_cached_regs(ap); |
66e57a2c | 3596 | mv_edma_cfg(ap, 0, 0); |
bdd4ddde | 3597 | |
17c5aab5 | 3598 | return rc; |
bdd4ddde JG |
3599 | } |
3600 | ||
bdd4ddde JG |
3601 | static void mv_eh_freeze(struct ata_port *ap) |
3602 | { | |
1cfd19ae | 3603 | mv_stop_edma(ap); |
c4de573b | 3604 | mv_enable_port_irqs(ap, 0); |
bdd4ddde JG |
3605 | } |
3606 | ||
3607 | static void mv_eh_thaw(struct ata_port *ap) | |
3608 | { | |
f351b2d6 | 3609 | struct mv_host_priv *hpriv = ap->host->private_data; |
c4de573b ML |
3610 | unsigned int port = ap->port_no; |
3611 | unsigned int hardport = mv_hardport_from_port(port); | |
1cfd19ae | 3612 | void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); |
bdd4ddde | 3613 | void __iomem *port_mmio = mv_ap_base(ap); |
c4de573b | 3614 | u32 hc_irq_cause; |
bdd4ddde | 3615 | |
bdd4ddde | 3616 | /* clear EDMA errors on this port */ |
cae5a29d | 3617 | writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); |
bdd4ddde JG |
3618 | |
3619 | /* clear pending irq events */ | |
cae6edc3 | 3620 | hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); |
cae5a29d | 3621 | writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); |
bdd4ddde | 3622 | |
88e675e1 | 3623 | mv_enable_port_irqs(ap, ERR_IRQ); |
31961943 BR |
3624 | } |
3625 | ||
05b308e1 BR |
3626 | /** |
3627 | * mv_port_init - Perform some early initialization on a single port. | |
3628 | * @port: libata data structure storing shadow register addresses | |
3629 | * @port_mmio: base address of the port | |
3630 | * | |
3631 | * Initialize shadow register mmio addresses, clear outstanding | |
3632 | * interrupts on the port, and unmask interrupts for the future | |
3633 | * start of the port. | |
3634 | * | |
3635 | * LOCKING: | |
3636 | * Inherited from caller. | |
3637 | */ | |
31961943 | 3638 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
20f733e7 | 3639 | { |
cae5a29d | 3640 | void __iomem *serr, *shd_base = port_mmio + SHD_BLK; |
31961943 | 3641 | |
8b260248 | 3642 | /* PIO related setup |
31961943 BR |
3643 | */ |
3644 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); | |
8b260248 | 3645 | port->error_addr = |
31961943 BR |
3646 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
3647 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); | |
3648 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); | |
3649 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); | |
3650 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); | |
3651 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); | |
8b260248 | 3652 | port->status_addr = |
31961943 BR |
3653 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
3654 | /* special case: control/altstatus doesn't have ATA_REG_ address */ | |
cae5a29d | 3655 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; |
31961943 BR |
3656 | |
3657 | /* unused: */ | |
8d9db2d2 | 3658 | port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; |
20f733e7 | 3659 | |
31961943 | 3660 | /* Clear any currently outstanding port interrupt conditions */ |
cae5a29d ML |
3661 | serr = port_mmio + mv_scr_offset(SCR_ERROR); |
3662 | writelfl(readl(serr), serr); | |
3663 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); | |
31961943 | 3664 | |
646a4da5 | 3665 | /* unmask all non-transient EDMA error interrupts */ |
cae5a29d | 3666 | writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); |
20f733e7 | 3667 | |
8b260248 | 3668 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
cae5a29d ML |
3669 | readl(port_mmio + EDMA_CFG), |
3670 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE), | |
3671 | readl(port_mmio + EDMA_ERR_IRQ_MASK)); | |
20f733e7 BR |
3672 | } |
3673 | ||
616d4a98 ML |
3674 | static unsigned int mv_in_pcix_mode(struct ata_host *host) |
3675 | { | |
3676 | struct mv_host_priv *hpriv = host->private_data; | |
3677 | void __iomem *mmio = hpriv->base; | |
3678 | u32 reg; | |
3679 | ||
1f398472 | 3680 | if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) |
616d4a98 | 3681 | return 0; /* not PCI-X capable */ |
cae5a29d | 3682 | reg = readl(mmio + MV_PCI_MODE); |
616d4a98 ML |
3683 | if ((reg & MV_PCI_MODE_MASK) == 0) |
3684 | return 0; /* conventional PCI mode */ | |
3685 | return 1; /* chip is in PCI-X mode */ | |
3686 | } | |
3687 | ||
3688 | static int mv_pci_cut_through_okay(struct ata_host *host) | |
3689 | { | |
3690 | struct mv_host_priv *hpriv = host->private_data; | |
3691 | void __iomem *mmio = hpriv->base; | |
3692 | u32 reg; | |
3693 | ||
3694 | if (!mv_in_pcix_mode(host)) { | |
cae5a29d ML |
3695 | reg = readl(mmio + MV_PCI_COMMAND); |
3696 | if (reg & MV_PCI_COMMAND_MRDTRIG) | |
616d4a98 ML |
3697 | return 0; /* not okay */ |
3698 | } | |
3699 | return 1; /* okay */ | |
3700 | } | |
3701 | ||
65ad7fef ML |
3702 | static void mv_60x1b2_errata_pci7(struct ata_host *host) |
3703 | { | |
3704 | struct mv_host_priv *hpriv = host->private_data; | |
3705 | void __iomem *mmio = hpriv->base; | |
3706 | ||
3707 | /* workaround for 60x1-B2 errata PCI#7 */ | |
3708 | if (mv_in_pcix_mode(host)) { | |
cae5a29d ML |
3709 | u32 reg = readl(mmio + MV_PCI_COMMAND); |
3710 | writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); | |
65ad7fef ML |
3711 | } |
3712 | } | |
3713 | ||
4447d351 | 3714 | static int mv_chip_id(struct ata_host *host, unsigned int board_idx) |
bca1c4eb | 3715 | { |
4447d351 TH |
3716 | struct pci_dev *pdev = to_pci_dev(host->dev); |
3717 | struct mv_host_priv *hpriv = host->private_data; | |
bca1c4eb JG |
3718 | u32 hp_flags = hpriv->hp_flags; |
3719 | ||
5796d1c4 | 3720 | switch (board_idx) { |
47c2b677 JG |
3721 | case chip_5080: |
3722 | hpriv->ops = &mv5xxx_ops; | |
ee9ccdf7 | 3723 | hp_flags |= MV_HP_GEN_I; |
47c2b677 | 3724 | |
44c10138 | 3725 | switch (pdev->revision) { |
47c2b677 JG |
3726 | case 0x1: |
3727 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
3728 | break; | |
3729 | case 0x3: | |
3730 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3731 | break; | |
3732 | default: | |
3733 | dev_printk(KERN_WARNING, &pdev->dev, | |
3734 | "Applying 50XXB2 workarounds to unknown rev\n"); | |
3735 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3736 | break; | |
3737 | } | |
3738 | break; | |
3739 | ||
bca1c4eb JG |
3740 | case chip_504x: |
3741 | case chip_508x: | |
47c2b677 | 3742 | hpriv->ops = &mv5xxx_ops; |
ee9ccdf7 | 3743 | hp_flags |= MV_HP_GEN_I; |
bca1c4eb | 3744 | |
44c10138 | 3745 | switch (pdev->revision) { |
47c2b677 JG |
3746 | case 0x0: |
3747 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
3748 | break; | |
3749 | case 0x3: | |
3750 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3751 | break; | |
3752 | default: | |
3753 | dev_printk(KERN_WARNING, &pdev->dev, | |
3754 | "Applying B2 workarounds to unknown rev\n"); | |
3755 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3756 | break; | |
bca1c4eb JG |
3757 | } |
3758 | break; | |
3759 | ||
3760 | case chip_604x: | |
3761 | case chip_608x: | |
47c2b677 | 3762 | hpriv->ops = &mv6xxx_ops; |
ee9ccdf7 | 3763 | hp_flags |= MV_HP_GEN_II; |
47c2b677 | 3764 | |
44c10138 | 3765 | switch (pdev->revision) { |
47c2b677 | 3766 | case 0x7: |
65ad7fef | 3767 | mv_60x1b2_errata_pci7(host); |
47c2b677 JG |
3768 | hp_flags |= MV_HP_ERRATA_60X1B2; |
3769 | break; | |
3770 | case 0x9: | |
3771 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
bca1c4eb JG |
3772 | break; |
3773 | default: | |
3774 | dev_printk(KERN_WARNING, &pdev->dev, | |
47c2b677 JG |
3775 | "Applying B2 workarounds to unknown rev\n"); |
3776 | hp_flags |= MV_HP_ERRATA_60X1B2; | |
bca1c4eb JG |
3777 | break; |
3778 | } | |
3779 | break; | |
3780 | ||
e4e7b892 | 3781 | case chip_7042: |
616d4a98 | 3782 | hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; |
306b30f7 ML |
3783 | if (pdev->vendor == PCI_VENDOR_ID_TTI && |
3784 | (pdev->device == 0x2300 || pdev->device == 0x2310)) | |
3785 | { | |
4e520033 ML |
3786 | /* |
3787 | * Highpoint RocketRAID PCIe 23xx series cards: | |
3788 | * | |
3789 | * Unconfigured drives are treated as "Legacy" | |
3790 | * by the BIOS, and it overwrites sector 8 with | |
3791 | * a "Lgcy" metadata block prior to Linux boot. | |
3792 | * | |
3793 | * Configured drives (RAID or JBOD) leave sector 8 | |
3794 | * alone, but instead overwrite a high numbered | |
3795 | * sector for the RAID metadata. This sector can | |
3796 | * be determined exactly, by truncating the physical | |
3797 | * drive capacity to a nice even GB value. | |
3798 | * | |
3799 | * RAID metadata is at: (dev->n_sectors & ~0xfffff) | |
3800 | * | |
3801 | * Warn the user, lest they think we're just buggy. | |
3802 | */ | |
3803 | printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" | |
3804 | " BIOS CORRUPTS DATA on all attached drives," | |
3805 | " regardless of if/how they are configured." | |
3806 | " BEWARE!\n"); | |
3807 | printk(KERN_WARNING DRV_NAME ": For data safety, do not" | |
3808 | " use sectors 8-9 on \"Legacy\" drives," | |
3809 | " and avoid the final two gigabytes on" | |
3810 | " all RocketRAID BIOS initialized drives.\n"); | |
306b30f7 | 3811 | } |
8e7decdb | 3812 | /* drop through */ |
e4e7b892 JG |
3813 | case chip_6042: |
3814 | hpriv->ops = &mv6xxx_ops; | |
e4e7b892 | 3815 | hp_flags |= MV_HP_GEN_IIE; |
616d4a98 ML |
3816 | if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) |
3817 | hp_flags |= MV_HP_CUT_THROUGH; | |
e4e7b892 | 3818 | |
44c10138 | 3819 | switch (pdev->revision) { |
5cf73bfb | 3820 | case 0x2: /* Rev.B0: the first/only public release */ |
e4e7b892 JG |
3821 | hp_flags |= MV_HP_ERRATA_60X1C0; |
3822 | break; | |
3823 | default: | |
3824 | dev_printk(KERN_WARNING, &pdev->dev, | |
3825 | "Applying 60X1C0 workarounds to unknown rev\n"); | |
3826 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
3827 | break; | |
3828 | } | |
3829 | break; | |
f351b2d6 | 3830 | case chip_soc: |
29b7e43c MM |
3831 | if (soc_is_65n(hpriv)) |
3832 | hpriv->ops = &mv_soc_65n_ops; | |
3833 | else | |
3834 | hpriv->ops = &mv_soc_ops; | |
eb3a55a9 SB |
3835 | hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | |
3836 | MV_HP_ERRATA_60X1C0; | |
f351b2d6 | 3837 | break; |
e4e7b892 | 3838 | |
bca1c4eb | 3839 | default: |
f351b2d6 | 3840 | dev_printk(KERN_ERR, host->dev, |
5796d1c4 | 3841 | "BUG: invalid board index %u\n", board_idx); |
bca1c4eb JG |
3842 | return 1; |
3843 | } | |
3844 | ||
3845 | hpriv->hp_flags = hp_flags; | |
02a121da | 3846 | if (hp_flags & MV_HP_PCIE) { |
cae5a29d ML |
3847 | hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; |
3848 | hpriv->irq_mask_offset = PCIE_IRQ_MASK; | |
02a121da ML |
3849 | hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; |
3850 | } else { | |
cae5a29d ML |
3851 | hpriv->irq_cause_offset = PCI_IRQ_CAUSE; |
3852 | hpriv->irq_mask_offset = PCI_IRQ_MASK; | |
02a121da ML |
3853 | hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; |
3854 | } | |
bca1c4eb JG |
3855 | |
3856 | return 0; | |
3857 | } | |
3858 | ||
05b308e1 | 3859 | /** |
47c2b677 | 3860 | * mv_init_host - Perform some early initialization of the host. |
4447d351 TH |
3861 | * @host: ATA host to initialize |
3862 | * @board_idx: controller index | |
05b308e1 BR |
3863 | * |
3864 | * If possible, do an early global reset of the host. Then do | |
3865 | * our port init and clear/unmask all/relevant host interrupts. | |
3866 | * | |
3867 | * LOCKING: | |
3868 | * Inherited from caller. | |
3869 | */ | |
4447d351 | 3870 | static int mv_init_host(struct ata_host *host, unsigned int board_idx) |
20f733e7 BR |
3871 | { |
3872 | int rc = 0, n_hc, port, hc; | |
4447d351 | 3873 | struct mv_host_priv *hpriv = host->private_data; |
f351b2d6 | 3874 | void __iomem *mmio = hpriv->base; |
47c2b677 | 3875 | |
4447d351 | 3876 | rc = mv_chip_id(host, board_idx); |
bca1c4eb | 3877 | if (rc) |
352fab70 | 3878 | goto done; |
f351b2d6 | 3879 | |
1f398472 | 3880 | if (IS_SOC(hpriv)) { |
cae5a29d ML |
3881 | hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; |
3882 | hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; | |
1f398472 | 3883 | } else { |
cae5a29d ML |
3884 | hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; |
3885 | hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; | |
f351b2d6 | 3886 | } |
352fab70 | 3887 | |
5d0fb2e7 TR |
3888 | /* initialize shadow irq mask with register's value */ |
3889 | hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); | |
3890 | ||
352fab70 | 3891 | /* global interrupt mask: 0 == mask everything */ |
c4de573b | 3892 | mv_set_main_irq_mask(host, ~0, 0); |
bca1c4eb | 3893 | |
4447d351 | 3894 | n_hc = mv_get_hc_count(host->ports[0]->flags); |
bca1c4eb | 3895 | |
4447d351 | 3896 | for (port = 0; port < host->n_ports; port++) |
29b7e43c MM |
3897 | if (hpriv->ops->read_preamp) |
3898 | hpriv->ops->read_preamp(hpriv, port, mmio); | |
20f733e7 | 3899 | |
c9d39130 | 3900 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); |
47c2b677 | 3901 | if (rc) |
20f733e7 | 3902 | goto done; |
20f733e7 | 3903 | |
522479fb | 3904 | hpriv->ops->reset_flash(hpriv, mmio); |
7bb3c529 | 3905 | hpriv->ops->reset_bus(host, mmio); |
47c2b677 | 3906 | hpriv->ops->enable_leds(hpriv, mmio); |
20f733e7 | 3907 | |
4447d351 | 3908 | for (port = 0; port < host->n_ports; port++) { |
cbcdd875 | 3909 | struct ata_port *ap = host->ports[port]; |
2a47ce06 | 3910 | void __iomem *port_mmio = mv_port_base(mmio, port); |
cbcdd875 TH |
3911 | |
3912 | mv_port_init(&ap->ioaddr, port_mmio); | |
3913 | ||
7bb3c529 | 3914 | #ifdef CONFIG_PCI |
1f398472 | 3915 | if (!IS_SOC(hpriv)) { |
f351b2d6 SB |
3916 | unsigned int offset = port_mmio - mmio; |
3917 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); | |
3918 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); | |
3919 | } | |
7bb3c529 | 3920 | #endif |
20f733e7 BR |
3921 | } |
3922 | ||
3923 | for (hc = 0; hc < n_hc; hc++) { | |
31961943 BR |
3924 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
3925 | ||
3926 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " | |
3927 | "(before clear)=0x%08x\n", hc, | |
cae5a29d ML |
3928 | readl(hc_mmio + HC_CFG), |
3929 | readl(hc_mmio + HC_IRQ_CAUSE)); | |
31961943 BR |
3930 | |
3931 | /* Clear any currently outstanding hc interrupt conditions */ | |
cae5a29d | 3932 | writelfl(0, hc_mmio + HC_IRQ_CAUSE); |
20f733e7 BR |
3933 | } |
3934 | ||
44c65d16 ML |
3935 | if (!IS_SOC(hpriv)) { |
3936 | /* Clear any currently outstanding host interrupt conditions */ | |
cae5a29d | 3937 | writelfl(0, mmio + hpriv->irq_cause_offset); |
31961943 | 3938 | |
44c65d16 | 3939 | /* and unmask interrupt generation for host regs */ |
cae5a29d | 3940 | writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); |
44c65d16 | 3941 | } |
51de32d2 | 3942 | |
6be96ac1 ML |
3943 | /* |
3944 | * enable only global host interrupts for now. | |
3945 | * The per-port interrupts get done later as ports are set up. | |
3946 | */ | |
3947 | mv_set_main_irq_mask(host, 0, PCI_ERR); | |
2b748a0a ML |
3948 | mv_set_irq_coalescing(host, irq_coalescing_io_count, |
3949 | irq_coalescing_usecs); | |
f351b2d6 SB |
3950 | done: |
3951 | return rc; | |
3952 | } | |
fb621e2f | 3953 | |
fbf14e2f BB |
3954 | static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) |
3955 | { | |
3956 | hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, | |
3957 | MV_CRQB_Q_SZ, 0); | |
3958 | if (!hpriv->crqb_pool) | |
3959 | return -ENOMEM; | |
3960 | ||
3961 | hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, | |
3962 | MV_CRPB_Q_SZ, 0); | |
3963 | if (!hpriv->crpb_pool) | |
3964 | return -ENOMEM; | |
3965 | ||
3966 | hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, | |
3967 | MV_SG_TBL_SZ, 0); | |
3968 | if (!hpriv->sg_tbl_pool) | |
3969 | return -ENOMEM; | |
3970 | ||
3971 | return 0; | |
3972 | } | |
3973 | ||
15a32632 LB |
3974 | static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, |
3975 | struct mbus_dram_target_info *dram) | |
3976 | { | |
3977 | int i; | |
3978 | ||
3979 | for (i = 0; i < 4; i++) { | |
3980 | writel(0, hpriv->base + WINDOW_CTRL(i)); | |
3981 | writel(0, hpriv->base + WINDOW_BASE(i)); | |
3982 | } | |
3983 | ||
3984 | for (i = 0; i < dram->num_cs; i++) { | |
3985 | struct mbus_dram_window *cs = dram->cs + i; | |
3986 | ||
3987 | writel(((cs->size - 1) & 0xffff0000) | | |
3988 | (cs->mbus_attr << 8) | | |
3989 | (dram->mbus_dram_target_id << 4) | 1, | |
3990 | hpriv->base + WINDOW_CTRL(i)); | |
3991 | writel(cs->base, hpriv->base + WINDOW_BASE(i)); | |
3992 | } | |
3993 | } | |
3994 | ||
f351b2d6 SB |
3995 | /** |
3996 | * mv_platform_probe - handle a positive probe of an soc Marvell | |
3997 | * host | |
3998 | * @pdev: platform device found | |
3999 | * | |
4000 | * LOCKING: | |
4001 | * Inherited from caller. | |
4002 | */ | |
4003 | static int mv_platform_probe(struct platform_device *pdev) | |
4004 | { | |
4005 | static int printed_version; | |
4006 | const struct mv_sata_platform_data *mv_platform_data; | |
4007 | const struct ata_port_info *ppi[] = | |
4008 | { &mv_port_info[chip_soc], NULL }; | |
4009 | struct ata_host *host; | |
4010 | struct mv_host_priv *hpriv; | |
4011 | struct resource *res; | |
4012 | int n_ports, rc; | |
20f733e7 | 4013 | |
f351b2d6 SB |
4014 | if (!printed_version++) |
4015 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
bca1c4eb | 4016 | |
f351b2d6 SB |
4017 | /* |
4018 | * Simple resource validation .. | |
4019 | */ | |
4020 | if (unlikely(pdev->num_resources != 2)) { | |
4021 | dev_err(&pdev->dev, "invalid number of resources\n"); | |
4022 | return -EINVAL; | |
4023 | } | |
4024 | ||
4025 | /* | |
4026 | * Get the register base first | |
4027 | */ | |
4028 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
4029 | if (res == NULL) | |
4030 | return -EINVAL; | |
4031 | ||
4032 | /* allocate host */ | |
4033 | mv_platform_data = pdev->dev.platform_data; | |
4034 | n_ports = mv_platform_data->n_ports; | |
4035 | ||
4036 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4037 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
4038 | ||
4039 | if (!host || !hpriv) | |
4040 | return -ENOMEM; | |
4041 | host->private_data = hpriv; | |
4042 | hpriv->n_ports = n_ports; | |
4043 | ||
4044 | host->iomap = NULL; | |
f1cb0ea1 | 4045 | hpriv->base = devm_ioremap(&pdev->dev, res->start, |
041b5eac | 4046 | resource_size(res)); |
cae5a29d | 4047 | hpriv->base -= SATAHC0_REG_BASE; |
f351b2d6 | 4048 | |
c77a2f4e SB |
4049 | #if defined(CONFIG_HAVE_CLK) |
4050 | hpriv->clk = clk_get(&pdev->dev, NULL); | |
4051 | if (IS_ERR(hpriv->clk)) | |
4052 | dev_notice(&pdev->dev, "cannot get clkdev\n"); | |
4053 | else | |
4054 | clk_enable(hpriv->clk); | |
4055 | #endif | |
4056 | ||
15a32632 LB |
4057 | /* |
4058 | * (Re-)program MBUS remapping windows if we are asked to. | |
4059 | */ | |
4060 | if (mv_platform_data->dram != NULL) | |
4061 | mv_conf_mbus_windows(hpriv, mv_platform_data->dram); | |
4062 | ||
fbf14e2f BB |
4063 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
4064 | if (rc) | |
c77a2f4e | 4065 | goto err; |
fbf14e2f | 4066 | |
f351b2d6 SB |
4067 | /* initialize adapter */ |
4068 | rc = mv_init_host(host, chip_soc); | |
4069 | if (rc) | |
c77a2f4e | 4070 | goto err; |
f351b2d6 SB |
4071 | |
4072 | dev_printk(KERN_INFO, &pdev->dev, | |
4073 | "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, | |
4074 | host->n_ports); | |
4075 | ||
4076 | return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, | |
4077 | IRQF_SHARED, &mv6_sht); | |
c77a2f4e SB |
4078 | err: |
4079 | #if defined(CONFIG_HAVE_CLK) | |
4080 | if (!IS_ERR(hpriv->clk)) { | |
4081 | clk_disable(hpriv->clk); | |
4082 | clk_put(hpriv->clk); | |
4083 | } | |
4084 | #endif | |
4085 | ||
4086 | return rc; | |
f351b2d6 SB |
4087 | } |
4088 | ||
4089 | /* | |
4090 | * | |
4091 | * mv_platform_remove - unplug a platform interface | |
4092 | * @pdev: platform device | |
4093 | * | |
4094 | * A platform bus SATA device has been unplugged. Perform the needed | |
4095 | * cleanup. Also called on module unload for any active devices. | |
4096 | */ | |
4097 | static int __devexit mv_platform_remove(struct platform_device *pdev) | |
4098 | { | |
4099 | struct device *dev = &pdev->dev; | |
4100 | struct ata_host *host = dev_get_drvdata(dev); | |
c77a2f4e SB |
4101 | #if defined(CONFIG_HAVE_CLK) |
4102 | struct mv_host_priv *hpriv = host->private_data; | |
4103 | #endif | |
f351b2d6 | 4104 | ata_host_detach(host); |
c77a2f4e SB |
4105 | |
4106 | #if defined(CONFIG_HAVE_CLK) | |
4107 | if (!IS_ERR(hpriv->clk)) { | |
4108 | clk_disable(hpriv->clk); | |
4109 | clk_put(hpriv->clk); | |
4110 | } | |
4111 | #endif | |
f351b2d6 | 4112 | return 0; |
20f733e7 BR |
4113 | } |
4114 | ||
6481f2b5 SB |
4115 | #ifdef CONFIG_PM |
4116 | static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state) | |
4117 | { | |
4118 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
4119 | if (host) | |
4120 | return ata_host_suspend(host, state); | |
4121 | else | |
4122 | return 0; | |
4123 | } | |
4124 | ||
4125 | static int mv_platform_resume(struct platform_device *pdev) | |
4126 | { | |
4127 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
4128 | int ret; | |
4129 | ||
4130 | if (host) { | |
4131 | struct mv_host_priv *hpriv = host->private_data; | |
4132 | const struct mv_sata_platform_data *mv_platform_data = \ | |
4133 | pdev->dev.platform_data; | |
4134 | /* | |
4135 | * (Re-)program MBUS remapping windows if we are asked to. | |
4136 | */ | |
4137 | if (mv_platform_data->dram != NULL) | |
4138 | mv_conf_mbus_windows(hpriv, mv_platform_data->dram); | |
4139 | ||
4140 | /* initialize adapter */ | |
4141 | ret = mv_init_host(host, chip_soc); | |
4142 | if (ret) { | |
4143 | printk(KERN_ERR DRV_NAME ": Error during HW init\n"); | |
4144 | return ret; | |
4145 | } | |
4146 | ata_host_resume(host); | |
4147 | } | |
4148 | ||
4149 | return 0; | |
4150 | } | |
4151 | #else | |
4152 | #define mv_platform_suspend NULL | |
4153 | #define mv_platform_resume NULL | |
4154 | #endif | |
4155 | ||
f351b2d6 SB |
4156 | static struct platform_driver mv_platform_driver = { |
4157 | .probe = mv_platform_probe, | |
4158 | .remove = __devexit_p(mv_platform_remove), | |
6481f2b5 SB |
4159 | .suspend = mv_platform_suspend, |
4160 | .resume = mv_platform_resume, | |
f351b2d6 SB |
4161 | .driver = { |
4162 | .name = DRV_NAME, | |
4163 | .owner = THIS_MODULE, | |
4164 | }, | |
4165 | }; | |
4166 | ||
4167 | ||
7bb3c529 | 4168 | #ifdef CONFIG_PCI |
f351b2d6 SB |
4169 | static int mv_pci_init_one(struct pci_dev *pdev, |
4170 | const struct pci_device_id *ent); | |
4171 | ||
7bb3c529 SB |
4172 | |
4173 | static struct pci_driver mv_pci_driver = { | |
4174 | .name = DRV_NAME, | |
4175 | .id_table = mv_pci_tbl, | |
f351b2d6 | 4176 | .probe = mv_pci_init_one, |
7bb3c529 SB |
4177 | .remove = ata_pci_remove_one, |
4178 | }; | |
4179 | ||
7bb3c529 SB |
4180 | /* move to PCI layer or libata core? */ |
4181 | static int pci_go_64(struct pci_dev *pdev) | |
4182 | { | |
4183 | int rc; | |
4184 | ||
6a35528a YH |
4185 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
4186 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
7bb3c529 | 4187 | if (rc) { |
284901a9 | 4188 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
7bb3c529 SB |
4189 | if (rc) { |
4190 | dev_printk(KERN_ERR, &pdev->dev, | |
4191 | "64-bit DMA enable failed\n"); | |
4192 | return rc; | |
4193 | } | |
4194 | } | |
4195 | } else { | |
284901a9 | 4196 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
7bb3c529 SB |
4197 | if (rc) { |
4198 | dev_printk(KERN_ERR, &pdev->dev, | |
4199 | "32-bit DMA enable failed\n"); | |
4200 | return rc; | |
4201 | } | |
284901a9 | 4202 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
7bb3c529 SB |
4203 | if (rc) { |
4204 | dev_printk(KERN_ERR, &pdev->dev, | |
4205 | "32-bit consistent DMA enable failed\n"); | |
4206 | return rc; | |
4207 | } | |
4208 | } | |
4209 | ||
4210 | return rc; | |
4211 | } | |
4212 | ||
05b308e1 BR |
4213 | /** |
4214 | * mv_print_info - Dump key info to kernel log for perusal. | |
4447d351 | 4215 | * @host: ATA host to print info about |
05b308e1 BR |
4216 | * |
4217 | * FIXME: complete this. | |
4218 | * | |
4219 | * LOCKING: | |
4220 | * Inherited from caller. | |
4221 | */ | |
4447d351 | 4222 | static void mv_print_info(struct ata_host *host) |
31961943 | 4223 | { |
4447d351 TH |
4224 | struct pci_dev *pdev = to_pci_dev(host->dev); |
4225 | struct mv_host_priv *hpriv = host->private_data; | |
44c10138 | 4226 | u8 scc; |
c1e4fe71 | 4227 | const char *scc_s, *gen; |
31961943 BR |
4228 | |
4229 | /* Use this to determine the HW stepping of the chip so we know | |
4230 | * what errata to workaround | |
4231 | */ | |
31961943 BR |
4232 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); |
4233 | if (scc == 0) | |
4234 | scc_s = "SCSI"; | |
4235 | else if (scc == 0x01) | |
4236 | scc_s = "RAID"; | |
4237 | else | |
c1e4fe71 JG |
4238 | scc_s = "?"; |
4239 | ||
4240 | if (IS_GEN_I(hpriv)) | |
4241 | gen = "I"; | |
4242 | else if (IS_GEN_II(hpriv)) | |
4243 | gen = "II"; | |
4244 | else if (IS_GEN_IIE(hpriv)) | |
4245 | gen = "IIE"; | |
4246 | else | |
4247 | gen = "?"; | |
31961943 | 4248 | |
a9524a76 | 4249 | dev_printk(KERN_INFO, &pdev->dev, |
c1e4fe71 JG |
4250 | "Gen-%s %u slots %u ports %s mode IRQ via %s\n", |
4251 | gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, | |
31961943 BR |
4252 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
4253 | } | |
4254 | ||
05b308e1 | 4255 | /** |
f351b2d6 | 4256 | * mv_pci_init_one - handle a positive probe of a PCI Marvell host |
05b308e1 BR |
4257 | * @pdev: PCI device found |
4258 | * @ent: PCI device ID entry for the matched host | |
4259 | * | |
4260 | * LOCKING: | |
4261 | * Inherited from caller. | |
4262 | */ | |
f351b2d6 SB |
4263 | static int mv_pci_init_one(struct pci_dev *pdev, |
4264 | const struct pci_device_id *ent) | |
20f733e7 | 4265 | { |
2dcb407e | 4266 | static int printed_version; |
20f733e7 | 4267 | unsigned int board_idx = (unsigned int)ent->driver_data; |
4447d351 TH |
4268 | const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; |
4269 | struct ata_host *host; | |
4270 | struct mv_host_priv *hpriv; | |
4271 | int n_ports, rc; | |
20f733e7 | 4272 | |
a9524a76 JG |
4273 | if (!printed_version++) |
4274 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
20f733e7 | 4275 | |
4447d351 TH |
4276 | /* allocate host */ |
4277 | n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; | |
4278 | ||
4279 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4280 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
4281 | if (!host || !hpriv) | |
4282 | return -ENOMEM; | |
4283 | host->private_data = hpriv; | |
f351b2d6 | 4284 | hpriv->n_ports = n_ports; |
4447d351 TH |
4285 | |
4286 | /* acquire resources */ | |
24dc5f33 TH |
4287 | rc = pcim_enable_device(pdev); |
4288 | if (rc) | |
20f733e7 | 4289 | return rc; |
20f733e7 | 4290 | |
0d5ff566 TH |
4291 | rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); |
4292 | if (rc == -EBUSY) | |
24dc5f33 | 4293 | pcim_pin_device(pdev); |
0d5ff566 | 4294 | if (rc) |
24dc5f33 | 4295 | return rc; |
4447d351 | 4296 | host->iomap = pcim_iomap_table(pdev); |
f351b2d6 | 4297 | hpriv->base = host->iomap[MV_PRIMARY_BAR]; |
20f733e7 | 4298 | |
d88184fb JG |
4299 | rc = pci_go_64(pdev); |
4300 | if (rc) | |
4301 | return rc; | |
4302 | ||
da2fa9ba ML |
4303 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
4304 | if (rc) | |
4305 | return rc; | |
4306 | ||
20f733e7 | 4307 | /* initialize adapter */ |
4447d351 | 4308 | rc = mv_init_host(host, board_idx); |
24dc5f33 TH |
4309 | if (rc) |
4310 | return rc; | |
20f733e7 | 4311 | |
6d3c30ef ML |
4312 | /* Enable message-switched interrupts, if requested */ |
4313 | if (msi && pci_enable_msi(pdev) == 0) | |
4314 | hpriv->hp_flags |= MV_HP_FLAG_MSI; | |
20f733e7 | 4315 | |
31961943 | 4316 | mv_dump_pci_cfg(pdev, 0x68); |
4447d351 | 4317 | mv_print_info(host); |
20f733e7 | 4318 | |
4447d351 | 4319 | pci_set_master(pdev); |
ea8b4db9 | 4320 | pci_try_set_mwi(pdev); |
4447d351 | 4321 | return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, |
c5d3e45a | 4322 | IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); |
20f733e7 | 4323 | } |
7bb3c529 | 4324 | #endif |
20f733e7 | 4325 | |
f351b2d6 SB |
4326 | static int mv_platform_probe(struct platform_device *pdev); |
4327 | static int __devexit mv_platform_remove(struct platform_device *pdev); | |
4328 | ||
20f733e7 BR |
4329 | static int __init mv_init(void) |
4330 | { | |
7bb3c529 SB |
4331 | int rc = -ENODEV; |
4332 | #ifdef CONFIG_PCI | |
4333 | rc = pci_register_driver(&mv_pci_driver); | |
f351b2d6 SB |
4334 | if (rc < 0) |
4335 | return rc; | |
4336 | #endif | |
4337 | rc = platform_driver_register(&mv_platform_driver); | |
4338 | ||
4339 | #ifdef CONFIG_PCI | |
4340 | if (rc < 0) | |
4341 | pci_unregister_driver(&mv_pci_driver); | |
7bb3c529 SB |
4342 | #endif |
4343 | return rc; | |
20f733e7 BR |
4344 | } |
4345 | ||
4346 | static void __exit mv_exit(void) | |
4347 | { | |
7bb3c529 | 4348 | #ifdef CONFIG_PCI |
20f733e7 | 4349 | pci_unregister_driver(&mv_pci_driver); |
7bb3c529 | 4350 | #endif |
f351b2d6 | 4351 | platform_driver_unregister(&mv_platform_driver); |
20f733e7 BR |
4352 | } |
4353 | ||
4354 | MODULE_AUTHOR("Brett Russ"); | |
4355 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); | |
4356 | MODULE_LICENSE("GPL"); | |
4357 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); | |
4358 | MODULE_VERSION(DRV_VERSION); | |
17c5aab5 | 4359 | MODULE_ALIAS("platform:" DRV_NAME); |
20f733e7 BR |
4360 | |
4361 | module_init(mv_init); | |
4362 | module_exit(mv_exit); |