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sata_mv NCQ-EH for FIS-based switching
[net-next-2.6.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
20f733e7 68#include <scsi/scsi_host.h>
193515d5 69#include <scsi/scsi_cmnd.h>
6c08772e 70#include <scsi/scsi_device.h>
20f733e7 71#include <linux/libata.h>
20f733e7
BR		 72
73#define DRV_NAME "sata_mv"
1fd2e1c2 74#define DRV_VERSION "1.20"
20f733e7
BR		 75
76enum {
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
81
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
84
85 MV_PCI_REG_BASE = 0,
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92
20f733e7 93 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
102
31961943
BR		 103 MV_MAX_Q_DEPTH = 32,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 */
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 112 MV_MAX_SG_CT = 256,
31961943 113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 114
352fab70 115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 116 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 120
121 /* Host Flags */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 124 /* SoC integrated controllers, no PCI interface */
e12bef50 125 MV_FLAG_SOC = (1 << 28),
7bb3c529 126
c5d3e45a 127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
47c2b677 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 131
31961943
BR		 132 CRQB_FLAG_READ = (1 << 0),
133 CRQB_TAG_SHIFT = 1,
c5d3e45a 134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
140
141 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 144
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
146
20f733e7
BR		 147 /* PCI interface registers */
148
31961943 149 PCI_COMMAND_OFS = 0xc00,
8e7decdb 150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 151
20f733e7
BR		 152 PCI_MAIN_CMD_STS_OFS = 0xd30,
153 STOP_PCI_MASTER = (1 << 2),
154 PCI_MASTER_EMPTY = (1 << 3),
155 GLOB_SFT_RST = (1 << 4),
156
8e7decdb
ML		 157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
159
522479fb
JG		 160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
161 MV_PCI_DISC_TIMER = 0xd04,
162 MV_PCI_MSI_TRIGGER = 0xc38,
163 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
168 MV_PCI_ERR_COMMAND = 0x1d50,
169
02a121da
ML		 170 PCI_IRQ_CAUSE_OFS = 0x1d58,
171 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 172 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
173
02a121da
ML		 174 PCIE_IRQ_CAUSE_OFS = 0x1900,
175 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 176 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 177
7368f919
ML		 178 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
179 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
180 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
181 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
182 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 183 ERR_IRQ = (1 << 0), /* shift by port # */
184 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 185 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
186 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
187 PCI_ERR = (1 << 18),
188 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
189 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 190 PORTS_0_3_COAL_DONE = (1 << 8),
191 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 192 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
193 GPIO_INT = (1 << 22),
194 SELF_INT = (1 << 23),
195 TWSI_INT = (1 << 24),
196 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 197 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 198 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
8b260248 199 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
f9f7fe01 200 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
20f733e7
BR		 201 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
202 HC_MAIN_RSVD),
fb621e2f
JG		 203 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
204 HC_MAIN_RSVD_5),
f351b2d6 205 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
20f733e7
BR		 206
207 /* SATAHC registers */
208 HC_CFG_OFS = 0,
209
210 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 211 DMA_IRQ = (1 << 0), /* shift by port # */
212 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 213 DEV_IRQ = (1 << 8), /* shift by port # */
214
215 /* Shadow block registers */
31961943
BR		 216 SHD_BLK_OFS = 0x100,
217 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 218
219 /* SATA registers */
220 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
221 SATA_ACTIVE_OFS = 0x350,
0c58912e 222 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
17c5aab5 223
e12bef50 224 LTMODE_OFS = 0x30c,
17c5aab5
ML		 225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
226
47c2b677 227 PHY_MODE3 = 0x310,
bca1c4eb
JG		 228 PHY_MODE4 = 0x314,
229 PHY_MODE2 = 0x330,
e12bef50 230 SATA_IFCTL_OFS = 0x344,
8e7decdb 231 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 234
8e7decdb
ML		 235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 238
c9d39130 239 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 243
244 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
0c58912e
ML		 248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 272
6c1153e0 273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
6c1153e0 279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 280
6c1153e0 281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
6c1153e0 288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 289
6c1153e0 290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 297 EDMA_ERR_LNK_CTRL_TX,
646a4da5 298
bdd4ddde
JG		 299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
6c1153e0 305 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
e12bef50 313
bdd4ddde
JG		 314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
6c1153e0 321 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
20f733e7 325
31961943
BR		 326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
0ea9e179
JG		 337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 345
8e7decdb
ML		 346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 350
352fab70
ML		 351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
352
31961943
BR		 353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 359 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
20f733e7 365
31961943 366 /* Port private flags (pp_flags) */
0ea9e179 367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 369 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 370 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 371};
372
ee9ccdf7
JG		 373#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
374#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 375#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 376#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
7bb3c529 377#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 378
15a32632
LB		 379#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
380#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
381
095fec88 382enum {
baf14aa1
JG		 383 /* DMA boundary 0xffff is required by the s/g splitting
384 * we need on /length/ in mv_fill-sg().
385 */
386 MV_DMA_BOUNDARY = 0xffffU,
095fec88 387
0ea9e179
JG		 388 /* mask of register bits containing lower 32 bits
389 * of EDMA request queue DMA address
390 */
095fec88
JG		 391 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
392
0ea9e179 393 /* ditto, for response queue */
095fec88
JG		 394 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
395};
396
522479fb
JG		 397enum chip_type {
398 chip_504x,
399 chip_508x,
400 chip_5080,
401 chip_604x,
402 chip_608x,
e4e7b892
JG		 403 chip_6042,
404 chip_7042,
f351b2d6 405 chip_soc,
522479fb
JG		 406};
407
31961943
BR		 408/* Command ReQuest Block: 32B */
409struct mv_crqb {
e1469874
ML		 410 __le32 sg_addr;
411 __le32 sg_addr_hi;
412 __le16 ctrl_flags;
413 __le16 ata_cmd[11];
31961943 414};
20f733e7 415
e4e7b892 416struct mv_crqb_iie {
e1469874
ML		 417 __le32 addr;
418 __le32 addr_hi;
419 __le32 flags;
420 __le32 len;
421 __le32 ata_cmd[4];
e4e7b892
JG		 422};
423
31961943
BR		 424/* Command ResPonse Block: 8B */
425struct mv_crpb {
e1469874
ML		 426 __le16 id;
427 __le16 flags;
428 __le32 tmstmp;
20f733e7
BR		 429};
430
31961943
BR		 431/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
432struct mv_sg {
e1469874
ML		 433 __le32 addr;
434 __le32 flags_size;
435 __le32 addr_hi;
436 __le32 reserved;
31961943 437};
20f733e7 438
31961943
BR		 439struct mv_port_priv {
440 struct mv_crqb *crqb;
441 dma_addr_t crqb_dma;
442 struct mv_crpb *crpb;
443 dma_addr_t crpb_dma;
eb73d558
ML		 444 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
445 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 446
447 unsigned int req_idx;
448 unsigned int resp_idx;
449
31961943 450 u32 pp_flags;
29d187bb 451 unsigned int delayed_eh_pmp_map;
31961943
BR		 452};
453
bca1c4eb
JG		 454struct mv_port_signal {
455 u32 amps;
456 u32 pre;
457};
458
02a121da
ML		 459struct mv_host_priv {
460 u32 hp_flags;
461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
f351b2d6
SB		 463 int n_ports;
464 void __iomem *base;
7368f919
ML		 465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
02a121da
ML		 467 u32 irq_cause_ofs;
468 u32 irq_mask_ofs;
469 u32 unmask_all_irqs;
da2fa9ba
ML		 470 /*
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
474 */
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
02a121da
ML		 478};
479
47c2b677 480struct mv_hw_ops {
2a47ce06
JG		 481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
482 unsigned int port);
47c2b677
JG		 483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
485 void __iomem *mmio);
c9d39130
JG		 486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
487 unsigned int n_hc);
522479fb 488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 490};
491
da3dbb17
TH		 492static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
493static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
494static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
495static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 496static int mv_port_start(struct ata_port *ap);
497static void mv_port_stop(struct ata_port *ap);
3e4a1391 498static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 499static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 500static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 501static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 502static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
bdd4ddde
JG		 504static void mv_eh_freeze(struct ata_port *ap);
505static void mv_eh_thaw(struct ata_port *ap);
f273827e 506static void mv6_dev_config(struct ata_device *dev);
20f733e7 507
2a47ce06
JG		 508static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
509 unsigned int port);
47c2b677
JG		 510static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
512 void __iomem *mmio);
c9d39130
JG		 513static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
514 unsigned int n_hc);
522479fb 515static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 516static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 517
2a47ce06
JG		 518static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
519 unsigned int port);
47c2b677
JG		 520static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
522 void __iomem *mmio);
c9d39130
JG		 523static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
524 unsigned int n_hc);
522479fb 525static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 526static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
527 void __iomem *mmio);
528static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
529 void __iomem *mmio);
530static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
533 void __iomem *mmio);
534static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 535static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 536static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 537 unsigned int port_no);
e12bef50 538static int mv_stop_edma(struct ata_port *ap);
b562468c 539static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 540static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 541
e49856d8
ML		 542static void mv_pmp_select(struct ata_port *ap, int pmp);
543static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
29d187bb 547static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 548static void mv_process_crpb_entries(struct ata_port *ap,
549 struct mv_port_priv *pp);
47c2b677 550
eb73d558
ML		 551/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
552 * because we have to allow room for worst case splitting of
553 * PRDs for 64K boundaries in mv_fill_sg().
554 */
c5d3e45a 555static struct scsi_host_template mv5_sht = {
68d1d07b 556 ATA_BASE_SHT(DRV_NAME),
baf14aa1 557 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 558 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 559};
560
561static struct scsi_host_template mv6_sht = {
68d1d07b 562 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 563 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 564 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 565 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 566};
567
029cfd6b
TH		 568static struct ata_port_operations mv5_ops = {
569 .inherits = &ata_sff_port_ops,
c9d39130 570
3e4a1391 571 .qc_defer = mv_qc_defer,
c9d39130
JG		 572 .qc_prep = mv_qc_prep,
573 .qc_issue = mv_qc_issue,
c9d39130 574
bdd4ddde
JG		 575 .freeze = mv_eh_freeze,
576 .thaw = mv_eh_thaw,
a1efdaba 577 .hardreset = mv_hardreset,
a1efdaba 578 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 579 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 580
c9d39130
JG		 581 .scr_read = mv5_scr_read,
582 .scr_write = mv5_scr_write,
583
584 .port_start = mv_port_start,
585 .port_stop = mv_port_stop,
c9d39130
JG		 586};
587
029cfd6b
TH		 588static struct ata_port_operations mv6_ops = {
589 .inherits = &mv5_ops,
f273827e 590 .dev_config = mv6_dev_config,
20f733e7
BR		 591 .scr_read = mv_scr_read,
592 .scr_write = mv_scr_write,
593
e49856d8
ML		 594 .pmp_hardreset = mv_pmp_hardreset,
595 .pmp_softreset = mv_softreset,
596 .softreset = mv_softreset,
29d187bb 597 .error_handler = mv_pmp_error_handler,
20f733e7
BR		 598};
599
029cfd6b
TH		 600static struct ata_port_operations mv_iie_ops = {
601 .inherits = &mv6_ops,
602 .dev_config = ATA_OP_NULL,
e4e7b892 603 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 604};
605
98ac62de 606static const struct ata_port_info mv_port_info[] = {
20f733e7 607 { /* chip_504x */
cca3974e 608 .flags = MV_COMMON_FLAGS,
31961943 609 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 610 .udma_mask = ATA_UDMA6,
c9d39130 611 .port_ops = &mv5_ops,
20f733e7
BR		 612 },
613 { /* chip_508x */
c5d3e45a 614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 615 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
c9d39130 617 .port_ops = &mv5_ops,
20f733e7 618 },
47c2b677 619 { /* chip_5080 */
c5d3e45a 620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 621 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 622 .udma_mask = ATA_UDMA6,
c9d39130 623 .port_ops = &mv5_ops,
47c2b677 624 },
20f733e7 625 { /* chip_604x */
138bfdd0 626 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 627 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 628 ATA_FLAG_NCQ,
31961943 629 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 630 .udma_mask = ATA_UDMA6,
c9d39130 631 .port_ops = &mv6_ops,
20f733e7
BR		 632 },
633 { /* chip_608x */
c5d3e45a 634 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 635 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 636 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 637 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 638 .udma_mask = ATA_UDMA6,
c9d39130 639 .port_ops = &mv6_ops,
20f733e7 640 },
e4e7b892 641 { /* chip_6042 */
138bfdd0 642 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 643 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 644 ATA_FLAG_NCQ,
e4e7b892 645 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 646 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 647 .port_ops = &mv_iie_ops,
648 },
649 { /* chip_7042 */
138bfdd0 650 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 651 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 652 ATA_FLAG_NCQ,
e4e7b892 653 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 654 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 655 .port_ops = &mv_iie_ops,
656 },
f351b2d6 657 { /* chip_soc */
02c1f32f 658 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 659 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
02c1f32f 660 ATA_FLAG_NCQ | MV_FLAG_SOC,
17c5aab5
ML		 661 .pio_mask = 0x1f, /* pio0-4 */
662 .udma_mask = ATA_UDMA6,
663 .port_ops = &mv_iie_ops,
f351b2d6 664 },
20f733e7
BR		 665};
666
3b7d697d 667static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 668 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
669 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
670 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
671 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 672 /* RocketRAID 1740/174x have different identifiers */
673 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
674 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 675
676 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
677 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
678 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
679 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
680 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
681
682 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
683
d9f9c6bc
FA		 684 /* Adaptec 1430SA */
685 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
686
02a121da 687 /* Marvell 7042 support */
6a3d586d
MT		 688 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
689
02a121da
ML		 690 /* Highpoint RocketRAID PCIe series */
691 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
692 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
693
2d2744fc 694 { } /* terminate list */
20f733e7
BR		 695};
696
47c2b677
JG		 697static const struct mv_hw_ops mv5xxx_ops = {
698 .phy_errata = mv5_phy_errata,
699 .enable_leds = mv5_enable_leds,
700 .read_preamp = mv5_read_preamp,
701 .reset_hc = mv5_reset_hc,
522479fb
JG		 702 .reset_flash = mv5_reset_flash,
703 .reset_bus = mv5_reset_bus,
47c2b677
JG		 704};
705
706static const struct mv_hw_ops mv6xxx_ops = {
707 .phy_errata = mv6_phy_errata,
708 .enable_leds = mv6_enable_leds,
709 .read_preamp = mv6_read_preamp,
710 .reset_hc = mv6_reset_hc,
522479fb
JG		 711 .reset_flash = mv6_reset_flash,
712 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 713};
714
f351b2d6
SB		 715static const struct mv_hw_ops mv_soc_ops = {
716 .phy_errata = mv6_phy_errata,
717 .enable_leds = mv_soc_enable_leds,
718 .read_preamp = mv_soc_read_preamp,
719 .reset_hc = mv_soc_reset_hc,
720 .reset_flash = mv_soc_reset_flash,
721 .reset_bus = mv_soc_reset_bus,
722};
723
20f733e7
BR		 724/*
725 * Functions
726 */
727
728static inline void writelfl(unsigned long data, void __iomem *addr)
729{
730 writel(data, addr);
731 (void) readl(addr); /* flush to avoid PCI posted write */
732}
733
c9d39130
JG		 734static inline unsigned int mv_hc_from_port(unsigned int port)
735{
736 return port >> MV_PORT_HC_SHIFT;
737}
738
739static inline unsigned int mv_hardport_from_port(unsigned int port)
740{
741 return port & MV_PORT_MASK;
742}
743
1cfd19ae
ML		 744/*
745 * Consolidate some rather tricky bit shift calculations.
746 * This is hot-path stuff, so not a function.
747 * Simple code, with two return values, so macro rather than inline.
748 *
749 * port is the sole input, in range 0..7.
7368f919
ML		 750 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
751 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 752 *
753 * Note that port and hardport may be the same variable in some cases.
754 */
755#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
756{ \
757 shift = mv_hc_from_port(port) * HC_SHIFT; \
758 hardport = mv_hardport_from_port(port); \
759 shift += hardport * 2; \
760}
761
352fab70
ML		 762static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
763{
764 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
765}
766
c9d39130
JG		 767static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
768 unsigned int port)
769{
770 return mv_hc_base(base, mv_hc_from_port(port));
771}
772
20f733e7
BR		 773static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
774{
c9d39130 775 return mv_hc_base_from_port(base, port) +
8b260248 776 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 777 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 778}
779
e12bef50
ML		 780static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
781{
782 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
783 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
784
785 return hc_mmio + ofs;
786}
787
f351b2d6
SB		 788static inline void __iomem *mv_host_base(struct ata_host *host)
789{
790 struct mv_host_priv *hpriv = host->private_data;
791 return hpriv->base;
792}
793
20f733e7
BR		 794static inline void __iomem *mv_ap_base(struct ata_port *ap)
795{
f351b2d6 796 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 797}
798
cca3974e 799static inline int mv_get_hc_count(unsigned long port_flags)
31961943 800{
cca3974e 801 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 802}
803
c5d3e45a
JG		 804static void mv_set_edma_ptrs(void __iomem *port_mmio,
805 struct mv_host_priv *hpriv,
806 struct mv_port_priv *pp)
807{
bdd4ddde
JG		 808 u32 index;
809
c5d3e45a
JG		 810 /*
811 * initialize request queue
812 */
fcfb1f77
ML		 813 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
814 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 815
c5d3e45a
JG		 816 WARN_ON(pp->crqb_dma & 0x3ff);
817 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 818 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 819 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
820
821 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 822 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 823 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
824 else
bdd4ddde 825 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 826
827 /*
828 * initialize response queue
829 */
fcfb1f77
ML		 830 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
831 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 832
c5d3e45a
JG		 833 WARN_ON(pp->crpb_dma & 0xff);
834 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
835
836 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 837 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 838 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
839 else
bdd4ddde 840 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 841
bdd4ddde 842 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 843 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 844}
845
05b308e1
BR		 846/**
847 * mv_start_dma - Enable eDMA engine
848 * @base: port base address
849 * @pp: port private data
850 *
beec7dbc
TH		 851 * Verify the local cache of the eDMA state is accurate with a
852 * WARN_ON.
05b308e1
BR		 853 *
854 * LOCKING:
855 * Inherited from caller.
856 */
0c58912e 857static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 858 struct mv_port_priv *pp, u8 protocol)
20f733e7 859{
72109168
ML		 860 int want_ncq = (protocol == ATA_PROT_NCQ);
861
862 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
863 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
864 if (want_ncq != using_ncq)
b562468c 865 mv_stop_edma(ap);
72109168 866 }
c5d3e45a 867 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 868 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 869 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 870 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 871 mv_host_base(ap->host), hardport);
0c58912e
ML		 872 u32 hc_irq_cause, ipending;
873
bdd4ddde 874 /* clear EDMA event indicators, if any */
f630d562 875 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 876
0c58912e
ML		 877 /* clear EDMA interrupt indicator, if any */
878 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 879 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 880 if (hc_irq_cause & ipending) {
881 writelfl(hc_irq_cause & ~ipending,
882 hc_mmio + HC_IRQ_CAUSE_OFS);
883 }
884
e12bef50 885 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 886
887 /* clear FIS IRQ Cause */
888 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
889
f630d562 890 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 891
f630d562 892 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 893 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
894 }
20f733e7
BR		 895}
896
9b2c4e0b
ML		 897static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
898{
899 void __iomem *port_mmio = mv_ap_base(ap);
900 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
901 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
902 int i;
903
904 /*
905 * Wait for the EDMA engine to finish transactions in progress.
906 */
907 for (i = 0; i < timeout; ++i) {
908 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
909 if ((edma_stat & empty_idle) == empty_idle)
910 break;
911 udelay(per_loop);
912 }
913 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
914}
915
05b308e1 916/**
e12bef50 917 * mv_stop_edma_engine - Disable eDMA engine
b562468c 918 * @port_mmio: io base address
05b308e1
BR		 919 *
920 * LOCKING:
921 * Inherited from caller.
922 */
b562468c 923static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 924{
b562468c 925 int i;
31961943 926
b562468c
ML		 927 /* Disable eDMA. The disable bit auto clears. */
928 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 929
b562468c
ML		 930 /* Wait for the chip to confirm eDMA is off. */
931 for (i = 10000; i > 0; i--) {
932 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 933 if (!(reg & EDMA_EN))
b562468c
ML		 934 return 0;
935 udelay(10);
31961943 936 }
b562468c 937 return -EIO;
20f733e7
BR		 938}
939
e12bef50 940static int mv_stop_edma(struct ata_port *ap)
0ea9e179 941{
b562468c
ML		 942 void __iomem *port_mmio = mv_ap_base(ap);
943 struct mv_port_priv *pp = ap->private_data;
0ea9e179 944
b562468c
ML		 945 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
946 return 0;
947 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 948 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 949 if (mv_stop_edma_engine(port_mmio)) {
950 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
951 return -EIO;
952 }
953 return 0;
0ea9e179
JG		 954}
955
8a70f8dc 956#ifdef ATA_DEBUG
31961943 957static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 958{
31961943
BR		 959 int b, w;
960 for (b = 0; b < bytes; ) {
961 DPRINTK("%p: ", start + b);
962 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 963 printk("%08x ", readl(start + b));
31961943
BR		 964 b += sizeof(u32);
965 }
966 printk("\n");
967 }
31961943 968}
8a70f8dc
JG		 969#endif
970
31961943
BR		 971static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
972{
973#ifdef ATA_DEBUG
974 int b, w;
975 u32 dw;
976 for (b = 0; b < bytes; ) {
977 DPRINTK("%02x: ", b);
978 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 979 (void) pci_read_config_dword(pdev, b, &dw);
980 printk("%08x ", dw);
31961943
BR		 981 b += sizeof(u32);
982 }
983 printk("\n");
984 }
985#endif
986}
987static void mv_dump_all_regs(void __iomem *mmio_base, int port,
988 struct pci_dev *pdev)
989{
990#ifdef ATA_DEBUG
8b260248 991 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 992 port >> MV_PORT_HC_SHIFT);
993 void __iomem *port_base;
994 int start_port, num_ports, p, start_hc, num_hcs, hc;
995
996 if (0 > port) {
997 start_hc = start_port = 0;
998 num_ports = 8; /* shld be benign for 4 port devs */
999 num_hcs = 2;
1000 } else {
1001 start_hc = port >> MV_PORT_HC_SHIFT;
1002 start_port = port;
1003 num_ports = num_hcs = 1;
1004 }
8b260248 1005 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1006 num_ports > 1 ? num_ports - 1 : start_port);
1007
1008 if (NULL != pdev) {
1009 DPRINTK("PCI config space regs:\n");
1010 mv_dump_pci_cfg(pdev, 0x68);
1011 }
1012 DPRINTK("PCI regs:\n");
1013 mv_dump_mem(mmio_base+0xc00, 0x3c);
1014 mv_dump_mem(mmio_base+0xd00, 0x34);
1015 mv_dump_mem(mmio_base+0xf00, 0x4);
1016 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1017 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1018 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1019 DPRINTK("HC regs (HC %i):\n", hc);
1020 mv_dump_mem(hc_base, 0x1c);
1021 }
1022 for (p = start_port; p < start_port + num_ports; p++) {
1023 port_base = mv_port_base(mmio_base, p);
2dcb407e 1024 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1025 mv_dump_mem(port_base, 0x54);
2dcb407e 1026 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1027 mv_dump_mem(port_base+0x300, 0x60);
1028 }
1029#endif
20f733e7
BR		 1030}
1031
1032static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1033{
1034 unsigned int ofs;
1035
1036 switch (sc_reg_in) {
1037 case SCR_STATUS:
1038 case SCR_CONTROL:
1039 case SCR_ERROR:
1040 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1041 break;
1042 case SCR_ACTIVE:
1043 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1044 break;
1045 default:
1046 ofs = 0xffffffffU;
1047 break;
1048 }
1049 return ofs;
1050}
1051
da3dbb17 1052static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1053{
1054 unsigned int ofs = mv_scr_offset(sc_reg_in);
1055
da3dbb17
TH		 1056 if (ofs != 0xffffffffU) {
1057 *val = readl(mv_ap_base(ap) + ofs);
1058 return 0;
1059 } else
1060 return -EINVAL;
20f733e7
BR		 1061}
1062
da3dbb17 1063static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1064{
1065 unsigned int ofs = mv_scr_offset(sc_reg_in);
1066
da3dbb17 1067 if (ofs != 0xffffffffU) {
20f733e7 1068 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1069 return 0;
1070 } else
1071 return -EINVAL;
20f733e7
BR		 1072}
1073
f273827e
ML		 1074static void mv6_dev_config(struct ata_device *adev)
1075{
1076 /*
e49856d8
ML		 1077 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1078 *
1079 * Gen-II does not support NCQ over a port multiplier
1080 * (no FIS-based switching).
1081 *
f273827e
ML		 1082 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1083 * See mv_qc_prep() for more info.
1084 */
e49856d8 1085 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1086 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1087 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1088 ata_dev_printk(adev, KERN_INFO,
1089 "NCQ disabled for command-based switching\n");
1090 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1091 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1092 ata_dev_printk(adev, KERN_INFO,
1093 "max_sectors limited to %u for NCQ\n",
1094 adev->max_sectors);
1095 }
e49856d8 1096 }
f273827e
ML		 1097}
1098
3e4a1391
ML		 1099static int mv_qc_defer(struct ata_queued_cmd *qc)
1100{
1101 struct ata_link *link = qc->dev->link;
1102 struct ata_port *ap = link->ap;
1103 struct mv_port_priv *pp = ap->private_data;
1104
29d187bb
ML		 1105 /*
1106 * Don't allow new commands if we're in a delayed EH state
1107 * for NCQ and/or FIS-based switching.
1108 */
1109 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1110 return ATA_DEFER_PORT;
3e4a1391
ML		 1111 /*
1112 * If the port is completely idle, then allow the new qc.
1113 */
1114 if (ap->nr_active_links == 0)
1115 return 0;
1116
1117 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1118 /*
1119 * The port is operating in host queuing mode (EDMA).
1120 * It can accomodate a new qc if the qc protocol
1121 * is compatible with the current host queue mode.
1122 */
1123 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1124 /*
1125 * The host queue (EDMA) is in NCQ mode.
1126 * If the new qc is also an NCQ command,
1127 * then allow the new qc.
1128 */
1129 if (qc->tf.protocol == ATA_PROT_NCQ)
1130 return 0;
1131 } else {
1132 /*
1133 * The host queue (EDMA) is in non-NCQ, DMA mode.
1134 * If the new qc is also a non-NCQ, DMA command,
1135 * then allow the new qc.
1136 */
1137 if (qc->tf.protocol == ATA_PROT_DMA)
1138 return 0;
1139 }
1140 }
1141 return ATA_DEFER_PORT;
1142}
1143
00f42eab 1144static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1145{
00f42eab
ML		 1146 u32 new_fiscfg, old_fiscfg;
1147 u32 new_ltmode, old_ltmode;
1148 u32 new_haltcond, old_haltcond;
1149
1150 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1151 old_ltmode = readl(port_mmio + LTMODE_OFS);
1152 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1153
1154 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1155 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1156 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1157
1158 if (want_fbs) {
1159 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1160 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1161 if (want_ncq)
1162 new_haltcond &= ~EDMA_ERR_DEV;
1163 else
1164 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1165 }
00f42eab 1166
8e7decdb
ML		 1167 if (new_fiscfg != old_fiscfg)
1168 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1169 if (new_ltmode != old_ltmode)
1170 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1171 if (new_haltcond != old_haltcond)
1172 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1173}
1174
dd2890f6
ML		 1175static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1176{
1177 struct mv_host_priv *hpriv = ap->host->private_data;
1178 u32 old, new;
1179
1180 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1181 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1182 if (want_ncq)
1183 new = old | (1 << 22);
1184 else
1185 new = old & ~(1 << 22);
1186 if (new != old)
1187 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1188}
1189
e12bef50 1190static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1191{
0c58912e 1192 u32 cfg;
e12bef50
ML		 1193 struct mv_port_priv *pp = ap->private_data;
1194 struct mv_host_priv *hpriv = ap->host->private_data;
1195 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1196
1197 /* set up non-NCQ EDMA configuration */
0c58912e 1198 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00f42eab 1199 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
e4e7b892 1200
0c58912e 1201 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1202 cfg |= (1 << 8); /* enab config burst size mask */
1203
dd2890f6 1204 else if (IS_GEN_II(hpriv)) {
e4e7b892 1205 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1206 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1207
dd2890f6 1208 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1209 int want_fbs = sata_pmp_attached(ap);
1210 /*
1211 * Possible future enhancement:
1212 *
1213 * The chip can use FBS with non-NCQ, if we allow it,
1214 * But first we need to have the error handling in place
1215 * for this mode (datasheet section 7.3.15.4.2.3).
1216 * So disallow non-NCQ FBS for now.
1217 */
1218 want_fbs &= want_ncq;
1219
1220 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1221
1222 if (want_fbs) {
1223 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1224 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1225 }
1226
e728eabe
JG		 1227 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1228 cfg |= (1 << 22); /* enab 4-entry host queue cache */
616d4a98
ML		 1229 if (HAS_PCI(ap->host))
1230 cfg |= (1 << 18); /* enab early completion */
1231 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1232 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1233 }
1234
72109168
ML		 1235 if (want_ncq) {
1236 cfg |= EDMA_CFG_NCQ;
1237 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1238 } else
1239 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1240
e4e7b892
JG		 1241 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1242}
1243
da2fa9ba
ML		 1244static void mv_port_free_dma_mem(struct ata_port *ap)
1245{
1246 struct mv_host_priv *hpriv = ap->host->private_data;
1247 struct mv_port_priv *pp = ap->private_data;
eb73d558 1248 int tag;
da2fa9ba
ML		 1249
1250 if (pp->crqb) {
1251 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1252 pp->crqb = NULL;
1253 }
1254 if (pp->crpb) {
1255 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1256 pp->crpb = NULL;
1257 }
eb73d558
ML		 1258 /*
1259 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1260 * For later hardware, we have one unique sg_tbl per NCQ tag.
1261 */
1262 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1263 if (pp->sg_tbl[tag]) {
1264 if (tag == 0 || !IS_GEN_I(hpriv))
1265 dma_pool_free(hpriv->sg_tbl_pool,
1266 pp->sg_tbl[tag],
1267 pp->sg_tbl_dma[tag]);
1268 pp->sg_tbl[tag] = NULL;
1269 }
da2fa9ba
ML		 1270 }
1271}
1272
05b308e1
BR		 1273/**
1274 * mv_port_start - Port specific init/start routine.
1275 * @ap: ATA channel to manipulate
1276 *
1277 * Allocate and point to DMA memory, init port private memory,
1278 * zero indices.
1279 *
1280 * LOCKING:
1281 * Inherited from caller.
1282 */
31961943
BR		 1283static int mv_port_start(struct ata_port *ap)
1284{
cca3974e
JG		 1285 struct device *dev = ap->host->dev;
1286 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1287 struct mv_port_priv *pp;
dde20207 1288 int tag;
31961943 1289
24dc5f33 1290 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1291 if (!pp)
24dc5f33 1292 return -ENOMEM;
da2fa9ba 1293 ap->private_data = pp;
31961943 1294
da2fa9ba
ML		 1295 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1296 if (!pp->crqb)
1297 return -ENOMEM;
1298 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1299
da2fa9ba
ML		 1300 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1301 if (!pp->crpb)
1302 goto out_port_free_dma_mem;
1303 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1304
eb73d558
ML		 1305 /*
1306 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1307 * For later hardware, we need one unique sg_tbl per NCQ tag.
1308 */
1309 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1310 if (tag == 0 || !IS_GEN_I(hpriv)) {
1311 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1312 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1313 if (!pp->sg_tbl[tag])
1314 goto out_port_free_dma_mem;
1315 } else {
1316 pp->sg_tbl[tag] = pp->sg_tbl[0];
1317 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1318 }
1319 }
31961943 1320 return 0;
da2fa9ba
ML		 1321
1322out_port_free_dma_mem:
1323 mv_port_free_dma_mem(ap);
1324 return -ENOMEM;
31961943
BR		 1325}
1326
05b308e1
BR		 1327/**
1328 * mv_port_stop - Port specific cleanup/stop routine.
1329 * @ap: ATA channel to manipulate
1330 *
1331 * Stop DMA, cleanup port memory.
1332 *
1333 * LOCKING:
cca3974e 1334 * This routine uses the host lock to protect the DMA stop.
05b308e1 1335 */
31961943
BR		 1336static void mv_port_stop(struct ata_port *ap)
1337{
e12bef50 1338 mv_stop_edma(ap);
da2fa9ba 1339 mv_port_free_dma_mem(ap);
31961943
BR		 1340}
1341
05b308e1
BR		 1342/**
1343 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1344 * @qc: queued command whose SG list to source from
1345 *
1346 * Populate the SG list and mark the last entry.
1347 *
1348 * LOCKING:
1349 * Inherited from caller.
1350 */
6c08772e 1351static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1352{
1353 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1354 struct scatterlist *sg;
3be6cbd7 1355 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1356 unsigned int si;
31961943 1357
eb73d558 1358 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1359 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1360 dma_addr_t addr = sg_dma_address(sg);
1361 u32 sg_len = sg_dma_len(sg);
22374677 1362
4007b493
OJ		 1363 while (sg_len) {
1364 u32 offset = addr & 0xffff;
1365 u32 len = sg_len;
22374677 1366
4007b493
OJ		 1367 if ((offset + sg_len > 0x10000))
1368 len = 0x10000 - offset;
1369
1370 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1371 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1372 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1373
1374 sg_len -= len;
1375 addr += len;
1376
3be6cbd7 1377 last_sg = mv_sg;
4007b493 1378 mv_sg++;
4007b493 1379 }
31961943 1380 }
3be6cbd7
JG		 1381
1382 if (likely(last_sg))
1383 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1384}
1385
5796d1c4 1386static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1387{
559eedad 1388 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1389 (last ? CRQB_CMD_LAST : 0);
559eedad 1390 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1391}
1392
05b308e1
BR		 1393/**
1394 * mv_qc_prep - Host specific command preparation.
1395 * @qc: queued command to prepare
1396 *
1397 * This routine simply redirects to the general purpose routine
1398 * if command is not DMA. Else, it handles prep of the CRQB
1399 * (command request block), does some sanity checking, and calls
1400 * the SG load routine.
1401 *
1402 * LOCKING:
1403 * Inherited from caller.
1404 */
31961943
BR		 1405static void mv_qc_prep(struct ata_queued_cmd *qc)
1406{
1407 struct ata_port *ap = qc->ap;
1408 struct mv_port_priv *pp = ap->private_data;
e1469874 1409 __le16 *cw;
31961943
BR		 1410 struct ata_taskfile *tf;
1411 u16 flags = 0;
a6432436 1412 unsigned in_index;
31961943 1413
138bfdd0
ML		 1414 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1415 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1416 return;
20f733e7 1417
31961943
BR		 1418 /* Fill in command request block
1419 */
e4e7b892 1420 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1421 flags |= CRQB_FLAG_READ;
beec7dbc 1422 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1423 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1424 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1425
bdd4ddde 1426 /* get current queue index from software */
fcfb1f77 1427 in_index = pp->req_idx;
a6432436
ML		 1428
1429 pp->crqb[in_index].sg_addr =
eb73d558 1430 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1431 pp->crqb[in_index].sg_addr_hi =
eb73d558 1432 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1433 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1434
a6432436 1435 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1436 tf = &qc->tf;
1437
1438 /* Sadly, the CRQB cannot accomodate all registers--there are
1439 * only 11 bytes...so we must pick and choose required
1440 * registers based on the command. So, we drop feature and
1441 * hob_feature for [RW] DMA commands, but they are needed for
1442 * NCQ. NCQ will drop hob_nsect.
20f733e7 1443 */
31961943
BR		 1444 switch (tf->command) {
1445 case ATA_CMD_READ:
1446 case ATA_CMD_READ_EXT:
1447 case ATA_CMD_WRITE:
1448 case ATA_CMD_WRITE_EXT:
c15d85c8 1449 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1450 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1451 break;
31961943
BR		 1452 case ATA_CMD_FPDMA_READ:
1453 case ATA_CMD_FPDMA_WRITE:
8b260248 1454 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1455 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1456 break;
31961943
BR		 1457 default:
1458 /* The only other commands EDMA supports in non-queued and
1459 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1460 * of which are defined/used by Linux. If we get here, this
1461 * driver needs work.
1462 *
1463 * FIXME: modify libata to give qc_prep a return value and
1464 * return error here.
1465 */
1466 BUG_ON(tf->command);
1467 break;
1468 }
1469 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1470 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1471 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1472 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1473 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1474 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1475 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1476 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1477 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1478
e4e7b892
JG		 1479 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1480 return;
1481 mv_fill_sg(qc);
1482}
1483
1484/**
1485 * mv_qc_prep_iie - Host specific command preparation.
1486 * @qc: queued command to prepare
1487 *
1488 * This routine simply redirects to the general purpose routine
1489 * if command is not DMA. Else, it handles prep of the CRQB
1490 * (command request block), does some sanity checking, and calls
1491 * the SG load routine.
1492 *
1493 * LOCKING:
1494 * Inherited from caller.
1495 */
1496static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1497{
1498 struct ata_port *ap = qc->ap;
1499 struct mv_port_priv *pp = ap->private_data;
1500 struct mv_crqb_iie *crqb;
1501 struct ata_taskfile *tf;
a6432436 1502 unsigned in_index;
e4e7b892
JG		 1503 u32 flags = 0;
1504
138bfdd0
ML		 1505 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1506 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1507 return;
1508
e12bef50 1509 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1510 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1511 flags |= CRQB_FLAG_READ;
1512
beec7dbc 1513 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1514 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1515 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1516 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1517
bdd4ddde 1518 /* get current queue index from software */
fcfb1f77 1519 in_index = pp->req_idx;
a6432436
ML		 1520
1521 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1522 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1523 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1524 crqb->flags = cpu_to_le32(flags);
1525
1526 tf = &qc->tf;
1527 crqb->ata_cmd[0] = cpu_to_le32(
1528 (tf->command << 16) |
1529 (tf->feature << 24)
1530 );
1531 crqb->ata_cmd[1] = cpu_to_le32(
1532 (tf->lbal << 0) |
1533 (tf->lbam << 8) |
1534 (tf->lbah << 16) |
1535 (tf->device << 24)
1536 );
1537 crqb->ata_cmd[2] = cpu_to_le32(
1538 (tf->hob_lbal << 0) |
1539 (tf->hob_lbam << 8) |
1540 (tf->hob_lbah << 16) |
1541 (tf->hob_feature << 24)
1542 );
1543 crqb->ata_cmd[3] = cpu_to_le32(
1544 (tf->nsect << 0) |
1545 (tf->hob_nsect << 8)
1546 );
1547
1548 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1549 return;
31961943
BR		 1550 mv_fill_sg(qc);
1551}
1552
05b308e1
BR		 1553/**
1554 * mv_qc_issue - Initiate a command to the host
1555 * @qc: queued command to start
1556 *
1557 * This routine simply redirects to the general purpose routine
1558 * if command is not DMA. Else, it sanity checks our local
1559 * caches of the request producer/consumer indices then enables
1560 * DMA and bumps the request producer index.
1561 *
1562 * LOCKING:
1563 * Inherited from caller.
1564 */
9a3d9eb0 1565static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1566{
c5d3e45a
JG		 1567 struct ata_port *ap = qc->ap;
1568 void __iomem *port_mmio = mv_ap_base(ap);
1569 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1570 u32 in_index;
31961943 1571
138bfdd0
ML		 1572 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1573 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1574 /*
1575 * We're about to send a non-EDMA capable command to the
31961943
BR		 1576 * port. Turn off EDMA so there won't be problems accessing
1577 * shadow block, etc registers.
1578 */
b562468c 1579 mv_stop_edma(ap);
e49856d8 1580 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1581 return ata_sff_qc_issue(qc);
31961943
BR		 1582 }
1583
72109168 1584 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1585
fcfb1f77
ML		 1586 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1587 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1588
1589 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1590 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1591 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1592
1593 return 0;
1594}
1595
8f767f8a
ML		 1596static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1597{
1598 struct mv_port_priv *pp = ap->private_data;
1599 struct ata_queued_cmd *qc;
1600
1601 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1602 return NULL;
1603 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1604 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1605 qc = NULL;
1606 return qc;
1607}
1608
29d187bb
ML		 1609static void mv_pmp_error_handler(struct ata_port *ap)
1610{
1611 unsigned int pmp, pmp_map;
1612 struct mv_port_priv *pp = ap->private_data;
1613
1614 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1615 /*
1616 * Perform NCQ error analysis on failed PMPs
1617 * before we freeze the port entirely.
1618 *
1619 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1620 */
1621 pmp_map = pp->delayed_eh_pmp_map;
1622 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1623 for (pmp = 0; pmp_map != 0; pmp++) {
1624 unsigned int this_pmp = (1 << pmp);
1625 if (pmp_map & this_pmp) {
1626 struct ata_link *link = &ap->pmp_link[pmp];
1627 pmp_map &= ~this_pmp;
1628 ata_eh_analyze_ncq_error(link);
1629 }
1630 }
1631 ata_port_freeze(ap);
1632 }
1633 sata_pmp_error_handler(ap);
1634}
1635
4c299ca3
ML		 1636static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1637{
1638 void __iomem *port_mmio = mv_ap_base(ap);
1639
1640 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1641}
1642
1643static int mv_count_pmp_links(unsigned int pmp_map)
1644{
1645 unsigned int link_count = 0;
1646
1647 while (pmp_map) {
1648 link_count += (pmp_map & 1);
1649 pmp_map >>= 1;
1650 }
1651 return link_count;
1652}
1653
1654static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1655{
1656 struct ata_eh_info *ehi;
1657 unsigned int pmp;
1658
1659 /*
1660 * Initialize EH info for PMPs which saw device errors
1661 */
1662 ehi = &ap->link.eh_info;
1663 for (pmp = 0; pmp_map != 0; pmp++) {
1664 unsigned int this_pmp = (1 << pmp);
1665 if (pmp_map & this_pmp) {
1666 struct ata_link *link = &ap->pmp_link[pmp];
1667
1668 pmp_map &= ~this_pmp;
1669 ehi = &link->eh_info;
1670 ata_ehi_clear_desc(ehi);
1671 ata_ehi_push_desc(ehi, "dev err");
1672 ehi->err_mask |= AC_ERR_DEV;
1673 ehi->action |= ATA_EH_RESET;
1674 ata_link_abort(link);
1675 }
1676 }
1677}
1678
1679static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1680{
1681 struct mv_port_priv *pp = ap->private_data;
1682 int failed_links;
1683 unsigned int old_map, new_map;
1684
1685 /*
1686 * Device error during FBS+NCQ operation:
1687 *
1688 * Set a port flag to prevent further I/O being enqueued.
1689 * Leave the EDMA running to drain outstanding commands from this port.
1690 * Perform the post-mortem/EH only when all responses are complete.
1691 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1692 */
1693 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1694 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1695 pp->delayed_eh_pmp_map = 0;
1696 }
1697 old_map = pp->delayed_eh_pmp_map;
1698 new_map = old_map | mv_get_err_pmp_map(ap);
1699
1700 if (old_map != new_map) {
1701 pp->delayed_eh_pmp_map = new_map;
1702 mv_pmp_eh_prep(ap, new_map & ~old_map);
1703 }
1704 failed_links = mv_count_pmp_links(new_map);
1705
1706 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1707 "failed_links=%d nr_active_links=%d\n",
1708 __func__, pp->delayed_eh_pmp_map,
1709 ap->qc_active, failed_links,
1710 ap->nr_active_links);
1711
1712 if (ap->nr_active_links <= failed_links) {
1713 mv_process_crpb_entries(ap, pp);
1714 mv_stop_edma(ap);
1715 mv_eh_freeze(ap);
1716 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1717 return 1; /* handled */
1718 }
1719 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1720 return 1; /* handled */
1721}
1722
1723static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1724{
1725 /*
1726 * Possible future enhancement:
1727 *
1728 * FBS+non-NCQ operation is not yet implemented.
1729 * See related notes in mv_edma_cfg().
1730 *
1731 * Device error during FBS+non-NCQ operation:
1732 *
1733 * We need to snapshot the shadow registers for each failed command.
1734 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1735 */
1736 return 0; /* not handled */
1737}
1738
1739static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1740{
1741 struct mv_port_priv *pp = ap->private_data;
1742
1743 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1744 return 0; /* EDMA was not active: not handled */
1745 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1746 return 0; /* FBS was not active: not handled */
1747
1748 if (!(edma_err_cause & EDMA_ERR_DEV))
1749 return 0; /* non DEV error: not handled */
1750 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1751 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1752 return 0; /* other problems: not handled */
1753
1754 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1755 /*
1756 * EDMA should NOT have self-disabled for this case.
1757 * If it did, then something is wrong elsewhere,
1758 * and we cannot handle it here.
1759 */
1760 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1761 ata_port_printk(ap, KERN_WARNING,
1762 "%s: err_cause=0x%x pp_flags=0x%x\n",
1763 __func__, edma_err_cause, pp->pp_flags);
1764 return 0; /* not handled */
1765 }
1766 return mv_handle_fbs_ncq_dev_err(ap);
1767 } else {
1768 /*
1769 * EDMA should have self-disabled for this case.
1770 * If it did not, then something is wrong elsewhere,
1771 * and we cannot handle it here.
1772 */
1773 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1774 ata_port_printk(ap, KERN_WARNING,
1775 "%s: err_cause=0x%x pp_flags=0x%x\n",
1776 __func__, edma_err_cause, pp->pp_flags);
1777 return 0; /* not handled */
1778 }
1779 return mv_handle_fbs_non_ncq_dev_err(ap);
1780 }
1781 return 0; /* not handled */
1782}
1783
a9010329 1784static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 1785{
8f767f8a 1786 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 1787 char *when = "idle";
8f767f8a 1788
8f767f8a 1789 ata_ehi_clear_desc(ehi);
a9010329
ML		 1790 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1791 when = "disabled";
1792 } else if (edma_was_enabled) {
1793 when = "EDMA enabled";
8f767f8a
ML		 1794 } else {
1795 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1796 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 1797 when = "polling";
8f767f8a 1798 }
a9010329 1799 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 1800 ehi->err_mask |= AC_ERR_OTHER;
1801 ehi->action |= ATA_EH_RESET;
1802 ata_port_freeze(ap);
1803}
1804
05b308e1
BR		 1805/**
1806 * mv_err_intr - Handle error interrupts on the port
1807 * @ap: ATA channel to manipulate
8d07379d 1808 * @qc: affected command (non-NCQ), or NULL
05b308e1 1809 *
8d07379d
ML		 1810 * Most cases require a full reset of the chip's state machine,
1811 * which also performs a COMRESET.
1812 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1813 *
1814 * LOCKING:
1815 * Inherited from caller.
1816 */
37b9046a 1817static void mv_err_intr(struct ata_port *ap)
31961943
BR		 1818{
1819 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde
JG		 1820 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1821 struct mv_port_priv *pp = ap->private_data;
1822 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1823 unsigned int action = 0, err_mask = 0;
9af5c9c9 1824 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 1825 struct ata_queued_cmd *qc;
1826 int abort = 0;
20f733e7 1827
8d07379d 1828 /*
37b9046a 1829 * Read and clear the SError and err_cause bits.
8d07379d 1830 */
37b9046a
ML		 1831 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1832 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1833
bdd4ddde 1834 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
8d07379d 1835 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1836
37b9046a
ML		 1837 ata_port_printk(ap, KERN_INFO, "%s: err_cause=%08x pp_flags=0x%x\n",
1838 __func__, edma_err_cause, pp->pp_flags);
bdd4ddde 1839
4c299ca3
ML		 1840 if (edma_err_cause & EDMA_ERR_DEV) {
1841 /*
1842 * Device errors during FIS-based switching operation
1843 * require special handling.
1844 */
1845 if (mv_handle_dev_err(ap, edma_err_cause))
1846 return;
1847 }
1848
37b9046a
ML		 1849 qc = mv_get_active_qc(ap);
1850 ata_ehi_clear_desc(ehi);
1851 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1852 edma_err_cause, pp->pp_flags);
bdd4ddde 1853 /*
352fab70 1854 * All generations share these EDMA error cause bits:
bdd4ddde 1855 */
37b9046a 1856 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 1857 err_mask |= AC_ERR_DEV;
37b9046a
ML		 1858 action |= ATA_EH_RESET;
1859 ata_ehi_push_desc(ehi, "dev error");
1860 }
bdd4ddde 1861 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1862 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1863 EDMA_ERR_INTRL_PAR)) {
1864 err_mask |= AC_ERR_ATA_BUS;
cf480626 1865 action |= ATA_EH_RESET;
b64bbc39 1866 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1867 }
1868 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1869 ata_ehi_hotplugged(ehi);
1870 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1871 "dev disconnect" : "dev connect");
cf480626 1872 action |= ATA_EH_RESET;
bdd4ddde
JG		 1873 }
1874
352fab70
ML		 1875 /*
1876 * Gen-I has a different SELF_DIS bit,
1877 * different FREEZE bits, and no SERR bit:
1878 */
ee9ccdf7 1879 if (IS_GEN_I(hpriv)) {
bdd4ddde 1880 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1881 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1882 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1883 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1884 }
1885 } else {
1886 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1887 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1888 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1889 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1890 }
bdd4ddde 1891 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1892 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1893 err_mask |= AC_ERR_ATA_BUS;
cf480626 1894 action |= ATA_EH_RESET;
bdd4ddde 1895 }
afb0edd9 1896 }
20f733e7 1897
bdd4ddde
JG		 1898 if (!err_mask) {
1899 err_mask = AC_ERR_OTHER;
cf480626 1900 action |= ATA_EH_RESET;
bdd4ddde
JG		 1901 }
1902
1903 ehi->serror |= serr;
1904 ehi->action |= action;
1905
1906 if (qc)
1907 qc->err_mask |= err_mask;
1908 else
1909 ehi->err_mask |= err_mask;
1910
37b9046a
ML		 1911 if (err_mask == AC_ERR_DEV) {
1912 /*
1913 * Cannot do ata_port_freeze() here,
1914 * because it would kill PIO access,
1915 * which is needed for further diagnosis.
1916 */
1917 mv_eh_freeze(ap);
1918 abort = 1;
1919 } else if (edma_err_cause & eh_freeze_mask) {
1920 /*
1921 * Note to self: ata_port_freeze() calls ata_port_abort()
1922 */
bdd4ddde 1923 ata_port_freeze(ap);
37b9046a
ML		 1924 } else {
1925 abort = 1;
1926 }
1927
1928 if (abort) {
1929 if (qc)
1930 ata_link_abort(qc->dev->link);
1931 else
1932 ata_port_abort(ap);
1933 }
bdd4ddde
JG		 1934}
1935
fcfb1f77
ML		 1936static void mv_process_crpb_response(struct ata_port *ap,
1937 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1938{
1939 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1940
1941 if (qc) {
1942 u8 ata_status;
1943 u16 edma_status = le16_to_cpu(response->flags);
1944 /*
1945 * edma_status from a response queue entry:
1946 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1947 * MSB is saved ATA status from command completion.
1948 */
1949 if (!ncq_enabled) {
1950 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1951 if (err_cause) {
1952 /*
1953 * Error will be seen/handled by mv_err_intr().
1954 * So do nothing at all here.
1955 */
1956 return;
1957 }
1958 }
1959 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 1960 if (!ac_err_mask(ata_status))
1961 ata_qc_complete(qc);
1962 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 1963 } else {
1964 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1965 __func__, tag);
1966 }
1967}
1968
1969static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 1970{
1971 void __iomem *port_mmio = mv_ap_base(ap);
1972 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 1973 u32 in_index;
bdd4ddde 1974 bool work_done = false;
fcfb1f77 1975 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 1976
fcfb1f77 1977 /* Get the hardware queue position index */
bdd4ddde
JG		 1978 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1979 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1980
fcfb1f77
ML		 1981 /* Process new responses from since the last time we looked */
1982 while (in_index != pp->resp_idx) {
6c1153e0 1983 unsigned int tag;
fcfb1f77 1984 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 1985
fcfb1f77 1986 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 1987
fcfb1f77
ML		 1988 if (IS_GEN_I(hpriv)) {
1989 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 1990 tag = ap->link.active_tag;
fcfb1f77
ML		 1991 } else {
1992 /* Gen II/IIE: get command tag from CRPB entry */
1993 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 1994 }
fcfb1f77 1995 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 1996 work_done = true;
bdd4ddde
JG		 1997 }
1998
352fab70 1999 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2000 if (work_done)
2001 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2002 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2003 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2004}
2005
a9010329
ML		 2006static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2007{
2008 struct mv_port_priv *pp;
2009 int edma_was_enabled;
2010
2011 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2012 mv_unexpected_intr(ap, 0);
2013 return;
2014 }
2015 /*
2016 * Grab a snapshot of the EDMA_EN flag setting,
2017 * so that we have a consistent view for this port,
2018 * even if something we call of our routines changes it.
2019 */
2020 pp = ap->private_data;
2021 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2022 /*
2023 * Process completed CRPB response(s) before other events.
2024 */
2025 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2026 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2027 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2028 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2029 }
2030 /*
2031 * Handle chip-reported errors, or continue on to handle PIO.
2032 */
2033 if (unlikely(port_cause & ERR_IRQ)) {
2034 mv_err_intr(ap);
2035 } else if (!edma_was_enabled) {
2036 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2037 if (qc)
2038 ata_sff_host_intr(ap, qc);
2039 else
2040 mv_unexpected_intr(ap, edma_was_enabled);
2041 }
2042}
2043
05b308e1
BR		 2044/**
2045 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2046 * @host: host specific structure
7368f919 2047 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2048 *
2049 * LOCKING:
2050 * Inherited from caller.
2051 */
7368f919 2052static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2053{
f351b2d6 2054 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2055 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2056 unsigned int handled = 0, port;
20f733e7 2057
a3718c1f 2058 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2059 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2060 unsigned int p, shift, hardport, port_cause;
2061
a3718c1f 2062 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2063 /*
eabd5eb1
ML		 2064 * Each hc within the host has its own hc_irq_cause register,
2065 * where the interrupting ports bits get ack'd.
a3718c1f 2066 */
eabd5eb1
ML		 2067 if (hardport == 0) { /* first port on this hc ? */
2068 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2069 u32 port_mask, ack_irqs;
2070 /*
2071 * Skip this entire hc if nothing pending for any ports
2072 */
2073 if (!hc_cause) {
2074 port += MV_PORTS_PER_HC - 1;
2075 continue;
2076 }
2077 /*
2078 * We don't need/want to read the hc_irq_cause register,
2079 * because doing so hurts performance, and
2080 * main_irq_cause already gives us everything we need.
2081 *
2082 * But we do have to *write* to the hc_irq_cause to ack
2083 * the ports that we are handling this time through.
2084 *
2085 * This requires that we create a bitmap for those
2086 * ports which interrupted us, and use that bitmap
2087 * to ack (only) those ports via hc_irq_cause.
2088 */
2089 ack_irqs = 0;
2090 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2091 if ((port + p) >= hpriv->n_ports)
2092 break;
2093 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2094 if (hc_cause & port_mask)
2095 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2096 }
a3718c1f 2097 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2098 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2099 handled = 1;
2100 }
8f767f8a 2101 /*
a9010329 2102 * Handle interrupts signalled for this port:
8f767f8a 2103 */
a9010329
ML		 2104 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2105 if (port_cause)
2106 mv_port_intr(ap, port_cause);
20f733e7 2107 }
a3718c1f 2108 return handled;
20f733e7
BR		 2109}
2110
a3718c1f 2111static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2112{
02a121da 2113 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2114 struct ata_port *ap;
2115 struct ata_queued_cmd *qc;
2116 struct ata_eh_info *ehi;
2117 unsigned int i, err_mask, printed = 0;
2118 u32 err_cause;
2119
02a121da 2120 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2121
2122 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2123 err_cause);
2124
2125 DPRINTK("All regs @ PCI error\n");
2126 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2127
02a121da 2128 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2129
2130 for (i = 0; i < host->n_ports; i++) {
2131 ap = host->ports[i];
936fd732 2132 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2133 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2134 ata_ehi_clear_desc(ehi);
2135 if (!printed++)
2136 ata_ehi_push_desc(ehi,
2137 "PCI err cause 0x%08x", err_cause);
2138 err_mask = AC_ERR_HOST_BUS;
cf480626 2139 ehi->action = ATA_EH_RESET;
9af5c9c9 2140 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2141 if (qc)
2142 qc->err_mask |= err_mask;
2143 else
2144 ehi->err_mask |= err_mask;
2145
2146 ata_port_freeze(ap);
2147 }
2148 }
a3718c1f 2149 return 1; /* handled */
bdd4ddde
JG		 2150}
2151
05b308e1 2152/**
c5d3e45a 2153 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2154 * @irq: unused
2155 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2156 *
2157 * Read the read only register to determine if any host
2158 * controllers have pending interrupts. If so, call lower level
2159 * routine to handle. Also check for PCI errors which are only
2160 * reported here.
2161 *
8b260248 2162 * LOCKING:
cca3974e 2163 * This routine holds the host lock while processing pending
05b308e1
BR		 2164 * interrupts.
2165 */
7d12e780 2166static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2167{
cca3974e 2168 struct ata_host *host = dev_instance;
f351b2d6 2169 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2170 unsigned int handled = 0;
7368f919 2171 u32 main_irq_cause, main_irq_mask;
20f733e7 2172
646a4da5 2173 spin_lock(&host->lock);
7368f919
ML		 2174 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2175 main_irq_mask = readl(hpriv->main_irq_mask_addr);
352fab70
ML		 2176 /*
2177 * Deal with cases where we either have nothing pending, or have read
2178 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2179 */
7368f919
ML		 2180 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2181 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 2182 handled = mv_pci_error(host, hpriv->base);
2183 else
7368f919 2184 handled = mv_host_intr(host, main_irq_cause);
bdd4ddde 2185 }
cca3974e 2186 spin_unlock(&host->lock);
20f733e7
BR		 2187 return IRQ_RETVAL(handled);
2188}
2189
c9d39130
JG		 2190static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2191{
2192 unsigned int ofs;
2193
2194 switch (sc_reg_in) {
2195 case SCR_STATUS:
2196 case SCR_ERROR:
2197 case SCR_CONTROL:
2198 ofs = sc_reg_in * sizeof(u32);
2199 break;
2200 default:
2201 ofs = 0xffffffffU;
2202 break;
2203 }
2204 return ofs;
2205}
2206
da3dbb17 2207static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 2208{
f351b2d6
SB		 2209 struct mv_host_priv *hpriv = ap->host->private_data;
2210 void __iomem *mmio = hpriv->base;
0d5ff566 2211 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2212 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2213
da3dbb17
TH		 2214 if (ofs != 0xffffffffU) {
2215 *val = readl(addr + ofs);
2216 return 0;
2217 } else
2218 return -EINVAL;
c9d39130
JG		 2219}
2220
da3dbb17 2221static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 2222{
f351b2d6
SB		 2223 struct mv_host_priv *hpriv = ap->host->private_data;
2224 void __iomem *mmio = hpriv->base;
0d5ff566 2225 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2226 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2227
da3dbb17 2228 if (ofs != 0xffffffffU) {
0d5ff566 2229 writelfl(val, addr + ofs);
da3dbb17
TH		 2230 return 0;
2231 } else
2232 return -EINVAL;
c9d39130
JG		 2233}
2234
7bb3c529 2235static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2236{
7bb3c529 2237 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2238 int early_5080;
2239
44c10138 2240 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2241
2242 if (!early_5080) {
2243 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2244 tmp |= (1 << 0);
2245 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2246 }
2247
7bb3c529 2248 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2249}
2250
2251static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2252{
8e7decdb 2253 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2254}
2255
47c2b677 2256static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2257 void __iomem *mmio)
2258{
c9d39130
JG		 2259 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2260 u32 tmp;
2261
2262 tmp = readl(phy_mmio + MV5_PHY_MODE);
2263
2264 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2265 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2266}
2267
47c2b677 2268static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2269{
522479fb
JG		 2270 u32 tmp;
2271
8e7decdb 2272 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2273
2274 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2275
2276 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2277 tmp |= ~(1 << 0);
2278 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2279}
2280
2a47ce06
JG		 2281static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2282 unsigned int port)
bca1c4eb 2283{
c9d39130
JG		 2284 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2285 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2286 u32 tmp;
2287 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2288
2289 if (fix_apm_sq) {
8e7decdb 2290 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2291 tmp |= (1 << 19);
8e7decdb 2292 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2293
8e7decdb 2294 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2295 tmp &= ~0x3;
2296 tmp |= 0x1;
8e7decdb 2297 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2298 }
2299
2300 tmp = readl(phy_mmio + MV5_PHY_MODE);
2301 tmp &= ~mask;
2302 tmp |= hpriv->signal[port].pre;
2303 tmp |= hpriv->signal[port].amps;
2304 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2305}
2306
c9d39130
JG		 2307
2308#undef ZERO
2309#define ZERO(reg) writel(0, port_mmio + (reg))
2310static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2311 unsigned int port)
2312{
2313 void __iomem *port_mmio = mv_port_base(mmio, port);
2314
e12bef50 2315 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2316
2317 ZERO(0x028); /* command */
2318 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2319 ZERO(0x004); /* timer */
2320 ZERO(0x008); /* irq err cause */
2321 ZERO(0x00c); /* irq err mask */
2322 ZERO(0x010); /* rq bah */
2323 ZERO(0x014); /* rq inp */
2324 ZERO(0x018); /* rq outp */
2325 ZERO(0x01c); /* respq bah */
2326 ZERO(0x024); /* respq outp */
2327 ZERO(0x020); /* respq inp */
2328 ZERO(0x02c); /* test control */
8e7decdb 2329 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2330}
2331#undef ZERO
2332
2333#define ZERO(reg) writel(0, hc_mmio + (reg))
2334static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2335 unsigned int hc)
47c2b677 2336{
c9d39130
JG		 2337 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2338 u32 tmp;
2339
2340 ZERO(0x00c);
2341 ZERO(0x010);
2342 ZERO(0x014);
2343 ZERO(0x018);
2344
2345 tmp = readl(hc_mmio + 0x20);
2346 tmp &= 0x1c1c1c1c;
2347 tmp |= 0x03030303;
2348 writel(tmp, hc_mmio + 0x20);
2349}
2350#undef ZERO
2351
2352static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2353 unsigned int n_hc)
2354{
2355 unsigned int hc, port;
2356
2357 for (hc = 0; hc < n_hc; hc++) {
2358 for (port = 0; port < MV_PORTS_PER_HC; port++)
2359 mv5_reset_hc_port(hpriv, mmio,
2360 (hc * MV_PORTS_PER_HC) + port);
2361
2362 mv5_reset_one_hc(hpriv, mmio, hc);
2363 }
2364
2365 return 0;
47c2b677
JG		 2366}
2367
101ffae2
JG		 2368#undef ZERO
2369#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2370static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2371{
02a121da 2372 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2373 u32 tmp;
2374
8e7decdb 2375 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2376 tmp &= 0xff00ffff;
8e7decdb 2377 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2378
2379 ZERO(MV_PCI_DISC_TIMER);
2380 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2381 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
7368f919 2382 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
101ffae2 2383 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2384 ZERO(hpriv->irq_cause_ofs);
2385 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2386 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2387 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2388 ZERO(MV_PCI_ERR_ATTRIBUTE);
2389 ZERO(MV_PCI_ERR_COMMAND);
2390}
2391#undef ZERO
2392
2393static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2394{
2395 u32 tmp;
2396
2397 mv5_reset_flash(hpriv, mmio);
2398
8e7decdb 2399 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2400 tmp &= 0x3;
2401 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2402 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2403}
2404
2405/**
2406 * mv6_reset_hc - Perform the 6xxx global soft reset
2407 * @mmio: base address of the HBA
2408 *
2409 * This routine only applies to 6xxx parts.
2410 *
2411 * LOCKING:
2412 * Inherited from caller.
2413 */
c9d39130
JG		 2414static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2415 unsigned int n_hc)
101ffae2
JG		 2416{
2417 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2418 int i, rc = 0;
2419 u32 t;
2420
2421 /* Following procedure defined in PCI "main command and status
2422 * register" table.
2423 */
2424 t = readl(reg);
2425 writel(t | STOP_PCI_MASTER, reg);
2426
2427 for (i = 0; i < 1000; i++) {
2428 udelay(1);
2429 t = readl(reg);
2dcb407e 2430 if (PCI_MASTER_EMPTY & t)
101ffae2 2431 break;
101ffae2
JG		 2432 }
2433 if (!(PCI_MASTER_EMPTY & t)) {
2434 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2435 rc = 1;
2436 goto done;
2437 }
2438
2439 /* set reset */
2440 i = 5;
2441 do {
2442 writel(t | GLOB_SFT_RST, reg);
2443 t = readl(reg);
2444 udelay(1);
2445 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2446
2447 if (!(GLOB_SFT_RST & t)) {
2448 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2449 rc = 1;
2450 goto done;
2451 }
2452
2453 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2454 i = 5;
2455 do {
2456 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2457 t = readl(reg);
2458 udelay(1);
2459 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2460
2461 if (GLOB_SFT_RST & t) {
2462 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2463 rc = 1;
2464 }
2465done:
2466 return rc;
2467}
2468
47c2b677 2469static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2470 void __iomem *mmio)
2471{
2472 void __iomem *port_mmio;
2473 u32 tmp;
2474
8e7decdb 2475 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2476 if ((tmp & (1 << 0)) == 0) {
47c2b677 2477 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2478 hpriv->signal[idx].pre = 0x1 << 5;
2479 return;
2480 }
2481
2482 port_mmio = mv_port_base(mmio, idx);
2483 tmp = readl(port_mmio + PHY_MODE2);
2484
2485 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2486 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2487}
2488
47c2b677 2489static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2490{
8e7decdb 2491 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2492}
2493
c9d39130 2494static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2495 unsigned int port)
bca1c4eb 2496{
c9d39130
JG		 2497 void __iomem *port_mmio = mv_port_base(mmio, port);
2498
bca1c4eb 2499 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2500 int fix_phy_mode2 =
2501 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2502 int fix_phy_mode4 =
47c2b677
JG		 2503 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2504 u32 m2, tmp;
2505
2506 if (fix_phy_mode2) {
2507 m2 = readl(port_mmio + PHY_MODE2);
2508 m2 &= ~(1 << 16);
2509 m2 |= (1 << 31);
2510 writel(m2, port_mmio + PHY_MODE2);
2511
2512 udelay(200);
2513
2514 m2 = readl(port_mmio + PHY_MODE2);
2515 m2 &= ~((1 << 16) | (1 << 31));
2516 writel(m2, port_mmio + PHY_MODE2);
2517
2518 udelay(200);
2519 }
2520
2521 /* who knows what this magic does */
2522 tmp = readl(port_mmio + PHY_MODE3);
2523 tmp &= ~0x7F800000;
2524 tmp |= 0x2A800000;
2525 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2526
2527 if (fix_phy_mode4) {
47c2b677 2528 u32 m4;
bca1c4eb
JG		 2529
2530 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2531
2532 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2533 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2534
e12bef50 2535 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2536 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2537
2538 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2539
2540 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2541 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2542 }
2543
2544 /* Revert values of pre-emphasis and signal amps to the saved ones */
2545 m2 = readl(port_mmio + PHY_MODE2);
2546
2547 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2548 m2 |= hpriv->signal[port].amps;
2549 m2 |= hpriv->signal[port].pre;
47c2b677 2550 m2 &= ~(1 << 16);
bca1c4eb 2551
e4e7b892
JG		 2552 /* according to mvSata 3.6.1, some IIE values are fixed */
2553 if (IS_GEN_IIE(hpriv)) {
2554 m2 &= ~0xC30FF01F;
2555 m2 |= 0x0000900F;
2556 }
2557
bca1c4eb
JG		 2558 writel(m2, port_mmio + PHY_MODE2);
2559}
2560
f351b2d6
SB		 2561/* TODO: use the generic LED interface to configure the SATA Presence */
2562/* & Acitivy LEDs on the board */
2563static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2564 void __iomem *mmio)
2565{
2566 return;
2567}
2568
2569static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2570 void __iomem *mmio)
2571{
2572 void __iomem *port_mmio;
2573 u32 tmp;
2574
2575 port_mmio = mv_port_base(mmio, idx);
2576 tmp = readl(port_mmio + PHY_MODE2);
2577
2578 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2579 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2580}
2581
2582#undef ZERO
2583#define ZERO(reg) writel(0, port_mmio + (reg))
2584static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2585 void __iomem *mmio, unsigned int port)
2586{
2587 void __iomem *port_mmio = mv_port_base(mmio, port);
2588
e12bef50 2589 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2590
2591 ZERO(0x028); /* command */
2592 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2593 ZERO(0x004); /* timer */
2594 ZERO(0x008); /* irq err cause */
2595 ZERO(0x00c); /* irq err mask */
2596 ZERO(0x010); /* rq bah */
2597 ZERO(0x014); /* rq inp */
2598 ZERO(0x018); /* rq outp */
2599 ZERO(0x01c); /* respq bah */
2600 ZERO(0x024); /* respq outp */
2601 ZERO(0x020); /* respq inp */
2602 ZERO(0x02c); /* test control */
8e7decdb 2603 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2604}
2605
2606#undef ZERO
2607
2608#define ZERO(reg) writel(0, hc_mmio + (reg))
2609static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2610 void __iomem *mmio)
2611{
2612 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2613
2614 ZERO(0x00c);
2615 ZERO(0x010);
2616 ZERO(0x014);
2617
2618}
2619
2620#undef ZERO
2621
2622static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2623 void __iomem *mmio, unsigned int n_hc)
2624{
2625 unsigned int port;
2626
2627 for (port = 0; port < hpriv->n_ports; port++)
2628 mv_soc_reset_hc_port(hpriv, mmio, port);
2629
2630 mv_soc_reset_one_hc(hpriv, mmio);
2631
2632 return 0;
2633}
2634
2635static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2636 void __iomem *mmio)
2637{
2638 return;
2639}
2640
2641static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2642{
2643 return;
2644}
2645
8e7decdb 2646static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2647{
8e7decdb 2648 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2649
8e7decdb 2650 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2651 if (want_gen2i)
8e7decdb
ML		 2652 ifcfg |= (1 << 7); /* enable gen2i speed */
2653 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2654}
2655
e12bef50 2656static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2657 unsigned int port_no)
2658{
2659 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2660
8e7decdb
ML		 2661 /*
2662 * The datasheet warns against setting EDMA_RESET when EDMA is active
2663 * (but doesn't say what the problem might be). So we first try
2664 * to disable the EDMA engine before doing the EDMA_RESET operation.
2665 */
0d8be5cb 2666 mv_stop_edma_engine(port_mmio);
8e7decdb 2667 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2668
b67a1064 2669 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2670 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2671 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2672 }
b67a1064 2673 /*
8e7decdb 2674 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2675 * link, and physical layers. It resets all SATA interface registers
2676 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2677 */
8e7decdb 2678 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2679 udelay(25); /* allow reset propagation */
c9d39130
JG		 2680 writelfl(0, port_mmio + EDMA_CMD_OFS);
2681
2682 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2683
ee9ccdf7 2684 if (IS_GEN_I(hpriv))
c9d39130
JG		 2685 mdelay(1);
2686}
2687
e49856d8 2688static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2689{
e49856d8
ML		 2690 if (sata_pmp_supported(ap)) {
2691 void __iomem *port_mmio = mv_ap_base(ap);
2692 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2693 int old = reg & 0xf;
22374677 2694
e49856d8
ML		 2695 if (old != pmp) {
2696 reg = (reg & ~0xf) | pmp;
2697 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2698 }
22374677 2699 }
20f733e7
BR		 2700}
2701
e49856d8
ML		 2702static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2703 unsigned long deadline)
22374677 2704{
e49856d8
ML		 2705 mv_pmp_select(link->ap, sata_srst_pmp(link));
2706 return sata_std_hardreset(link, class, deadline);
2707}
bdd4ddde 2708
e49856d8
ML		 2709static int mv_softreset(struct ata_link *link, unsigned int *class,
2710 unsigned long deadline)
2711{
2712 mv_pmp_select(link->ap, sata_srst_pmp(link));
2713 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2714}
2715
cc0680a5 2716static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2717 unsigned long deadline)
31961943 2718{
cc0680a5 2719 struct ata_port *ap = link->ap;
bdd4ddde 2720 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2721 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2722 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2723 int rc, attempts = 0, extra = 0;
2724 u32 sstatus;
2725 bool online;
31961943 2726
e12bef50 2727 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2728 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2729
0d8be5cb
ML		 2730 /* Workaround for errata FEr SATA#10 (part 2) */
2731 do {
17c5aab5
ML		 2732 const unsigned long *timing =
2733 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2734
17c5aab5
ML		 2735 rc = sata_link_hardreset(link, timing, deadline + extra,
2736 &online, NULL);
2737 if (rc)
0d8be5cb 2738 return rc;
0d8be5cb
ML		 2739 sata_scr_read(link, SCR_STATUS, &sstatus);
2740 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2741 /* Force 1.5gb/s link speed and try again */
8e7decdb 2742 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2743 if (time_after(jiffies + HZ, deadline))
2744 extra = HZ; /* only extend it once, max */
2745 }
2746 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2747
17c5aab5 2748 return rc;
bdd4ddde
JG		 2749}
2750
bdd4ddde
JG		 2751static void mv_eh_freeze(struct ata_port *ap)
2752{
f351b2d6 2753 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae 2754 unsigned int shift, hardport, port = ap->port_no;
7368f919 2755 u32 main_irq_mask;
bdd4ddde
JG		 2756
2757 /* FIXME: handle coalescing completion events properly */
2758
1cfd19ae
ML		 2759 mv_stop_edma(ap);
2760 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2761
bdd4ddde 2762 /* disable assertion of portN err, done events */
7368f919
ML		 2763 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2764 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2765 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
bdd4ddde
JG		 2766}
2767
2768static void mv_eh_thaw(struct ata_port *ap)
2769{
f351b2d6 2770 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae
ML		 2771 unsigned int shift, hardport, port = ap->port_no;
2772 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2773 void __iomem *port_mmio = mv_ap_base(ap);
7368f919 2774 u32 main_irq_mask, hc_irq_cause;
bdd4ddde
JG		 2775
2776 /* FIXME: handle coalescing completion events properly */
2777
1cfd19ae 2778 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2779
bdd4ddde
JG		 2780 /* clear EDMA errors on this port */
2781 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2782
2783 /* clear pending irq events */
2784 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2785 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2786 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 2787
2788 /* enable assertion of portN err, done events */
7368f919
ML		 2789 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2790 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2791 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
31961943
BR		 2792}
2793
05b308e1
BR		 2794/**
2795 * mv_port_init - Perform some early initialization on a single port.
2796 * @port: libata data structure storing shadow register addresses
2797 * @port_mmio: base address of the port
2798 *
2799 * Initialize shadow register mmio addresses, clear outstanding
2800 * interrupts on the port, and unmask interrupts for the future
2801 * start of the port.
2802 *
2803 * LOCKING:
2804 * Inherited from caller.
2805 */
31961943 2806static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2807{
0d5ff566 2808 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2809 unsigned serr_ofs;
2810
8b260248 2811 /* PIO related setup
31961943
BR		 2812 */
2813 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2814 port->error_addr =
31961943
BR		 2815 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2816 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2817 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2818 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2819 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2820 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2821 port->status_addr =
31961943
BR		 2822 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2823 /* special case: control/altstatus doesn't have ATA_REG_ address */
2824 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2825
2826 /* unused: */
8d9db2d2 2827 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2828
31961943
BR		 2829 /* Clear any currently outstanding port interrupt conditions */
2830 serr_ofs = mv_scr_offset(SCR_ERROR);
2831 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2832 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2833
646a4da5
ML		 2834 /* unmask all non-transient EDMA error interrupts */
2835 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2836
8b260248 2837 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2838 readl(port_mmio + EDMA_CFG_OFS),
2839 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2840 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2841}
2842
616d4a98
ML		 2843static unsigned int mv_in_pcix_mode(struct ata_host *host)
2844{
2845 struct mv_host_priv *hpriv = host->private_data;
2846 void __iomem *mmio = hpriv->base;
2847 u32 reg;
2848
2849 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2850 return 0; /* not PCI-X capable */
2851 reg = readl(mmio + MV_PCI_MODE_OFS);
2852 if ((reg & MV_PCI_MODE_MASK) == 0)
2853 return 0; /* conventional PCI mode */
2854 return 1; /* chip is in PCI-X mode */
2855}
2856
2857static int mv_pci_cut_through_okay(struct ata_host *host)
2858{
2859 struct mv_host_priv *hpriv = host->private_data;
2860 void __iomem *mmio = hpriv->base;
2861 u32 reg;
2862
2863 if (!mv_in_pcix_mode(host)) {
2864 reg = readl(mmio + PCI_COMMAND_OFS);
2865 if (reg & PCI_COMMAND_MRDTRIG)
2866 return 0; /* not okay */
2867 }
2868 return 1; /* okay */
2869}
2870
4447d351 2871static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2872{
4447d351
TH		 2873 struct pci_dev *pdev = to_pci_dev(host->dev);
2874 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2875 u32 hp_flags = hpriv->hp_flags;
2876
5796d1c4 2877 switch (board_idx) {
47c2b677
JG		 2878 case chip_5080:
2879 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2880 hp_flags |= MV_HP_GEN_I;
47c2b677 2881
44c10138 2882 switch (pdev->revision) {
47c2b677
JG		 2883 case 0x1:
2884 hp_flags |= MV_HP_ERRATA_50XXB0;
2885 break;
2886 case 0x3:
2887 hp_flags |= MV_HP_ERRATA_50XXB2;
2888 break;
2889 default:
2890 dev_printk(KERN_WARNING, &pdev->dev,
2891 "Applying 50XXB2 workarounds to unknown rev\n");
2892 hp_flags |= MV_HP_ERRATA_50XXB2;
2893 break;
2894 }
2895 break;
2896
bca1c4eb
JG		 2897 case chip_504x:
2898 case chip_508x:
47c2b677 2899 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2900 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2901
44c10138 2902 switch (pdev->revision) {
47c2b677
JG		 2903 case 0x0:
2904 hp_flags |= MV_HP_ERRATA_50XXB0;
2905 break;
2906 case 0x3:
2907 hp_flags |= MV_HP_ERRATA_50XXB2;
2908 break;
2909 default:
2910 dev_printk(KERN_WARNING, &pdev->dev,
2911 "Applying B2 workarounds to unknown rev\n");
2912 hp_flags |= MV_HP_ERRATA_50XXB2;
2913 break;
bca1c4eb
JG		 2914 }
2915 break;
2916
2917 case chip_604x:
2918 case chip_608x:
47c2b677 2919 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2920 hp_flags |= MV_HP_GEN_II;
47c2b677 2921
44c10138 2922 switch (pdev->revision) {
47c2b677
JG		 2923 case 0x7:
2924 hp_flags |= MV_HP_ERRATA_60X1B2;
2925 break;
2926 case 0x9:
2927 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2928 break;
2929 default:
2930 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2931 "Applying B2 workarounds to unknown rev\n");
2932 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2933 break;
2934 }
2935 break;
2936
e4e7b892 2937 case chip_7042:
616d4a98 2938 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2939 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2940 (pdev->device == 0x2300 || pdev->device == 0x2310))
2941 {
4e520033
ML		 2942 /*
2943 * Highpoint RocketRAID PCIe 23xx series cards:
2944 *
2945 * Unconfigured drives are treated as "Legacy"
2946 * by the BIOS, and it overwrites sector 8 with
2947 * a "Lgcy" metadata block prior to Linux boot.
2948 *
2949 * Configured drives (RAID or JBOD) leave sector 8
2950 * alone, but instead overwrite a high numbered
2951 * sector for the RAID metadata. This sector can
2952 * be determined exactly, by truncating the physical
2953 * drive capacity to a nice even GB value.
2954 *
2955 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2956 *
2957 * Warn the user, lest they think we're just buggy.
2958 */
2959 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2960 " BIOS CORRUPTS DATA on all attached drives,"
2961 " regardless of if/how they are configured."
2962 " BEWARE!\n");
2963 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2964 " use sectors 8-9 on \"Legacy\" drives,"
2965 " and avoid the final two gigabytes on"
2966 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2967 }
8e7decdb 2968 /* drop through */
e4e7b892
JG		 2969 case chip_6042:
2970 hpriv->ops = &mv6xxx_ops;
e4e7b892 2971 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2972 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2973 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2974
44c10138 2975 switch (pdev->revision) {
e4e7b892
JG		 2976 case 0x0:
2977 hp_flags |= MV_HP_ERRATA_XX42A0;
2978 break;
2979 case 0x1:
2980 hp_flags |= MV_HP_ERRATA_60X1C0;
2981 break;
2982 default:
2983 dev_printk(KERN_WARNING, &pdev->dev,
2984 "Applying 60X1C0 workarounds to unknown rev\n");
2985 hp_flags |= MV_HP_ERRATA_60X1C0;
2986 break;
2987 }
2988 break;
f351b2d6
SB		 2989 case chip_soc:
2990 hpriv->ops = &mv_soc_ops;
2991 hp_flags |= MV_HP_ERRATA_60X1C0;
2992 break;
e4e7b892 2993
bca1c4eb 2994 default:
f351b2d6 2995 dev_printk(KERN_ERR, host->dev,
5796d1c4 2996 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 2997 return 1;
2998 }
2999
3000 hpriv->hp_flags = hp_flags;
02a121da
ML		 3001 if (hp_flags & MV_HP_PCIE) {
3002 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3003 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3004 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3005 } else {
3006 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3007 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3008 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3009 }
bca1c4eb
JG		 3010
3011 return 0;
3012}
3013
05b308e1 3014/**
47c2b677 3015 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3016 * @host: ATA host to initialize
3017 * @board_idx: controller index
05b308e1
BR		 3018 *
3019 * If possible, do an early global reset of the host. Then do
3020 * our port init and clear/unmask all/relevant host interrupts.
3021 *
3022 * LOCKING:
3023 * Inherited from caller.
3024 */
4447d351 3025static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3026{
3027 int rc = 0, n_hc, port, hc;
4447d351 3028 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3029 void __iomem *mmio = hpriv->base;
47c2b677 3030
4447d351 3031 rc = mv_chip_id(host, board_idx);
bca1c4eb 3032 if (rc)
352fab70 3033 goto done;
f351b2d6
SB		 3034
3035 if (HAS_PCI(host)) {
7368f919
ML		 3036 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3037 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3038 } else {
7368f919
ML		 3039 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3040 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3041 }
352fab70
ML		 3042
3043 /* global interrupt mask: 0 == mask everything */
7368f919 3044 writel(0, hpriv->main_irq_mask_addr);
bca1c4eb 3045
4447d351 3046 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3047
4447d351 3048 for (port = 0; port < host->n_ports; port++)
47c2b677 3049 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3050
c9d39130 3051 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3052 if (rc)
20f733e7 3053 goto done;
20f733e7 3054
522479fb 3055 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3056 hpriv->ops->reset_bus(host, mmio);
47c2b677 3057 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3058
4447d351 3059 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3060 struct ata_port *ap = host->ports[port];
2a47ce06 3061 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3062
3063 mv_port_init(&ap->ioaddr, port_mmio);
3064
7bb3c529 3065#ifdef CONFIG_PCI
f351b2d6
SB		 3066 if (HAS_PCI(host)) {
3067 unsigned int offset = port_mmio - mmio;
3068 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3069 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3070 }
7bb3c529 3071#endif
20f733e7
BR		 3072 }
3073
3074 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3075 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3076
3077 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3078 "(before clear)=0x%08x\n", hc,
3079 readl(hc_mmio + HC_CFG_OFS),
3080 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3081
3082 /* Clear any currently outstanding hc interrupt conditions */
3083 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3084 }
3085
f351b2d6
SB		 3086 if (HAS_PCI(host)) {
3087 /* Clear any currently outstanding host interrupt conditions */
3088 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3089
f351b2d6
SB		 3090 /* and unmask interrupt generation for host regs */
3091 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3092 if (IS_GEN_I(hpriv))
3093 writelfl(~HC_MAIN_MASKED_IRQS_5,
7368f919 3094 hpriv->main_irq_mask_addr);
f351b2d6
SB		 3095 else
3096 writelfl(~HC_MAIN_MASKED_IRQS,
7368f919 3097 hpriv->main_irq_mask_addr);
f351b2d6
SB		 3098
3099 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
3100 "PCI int cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 3101 readl(hpriv->main_irq_cause_addr),
3102 readl(hpriv->main_irq_mask_addr),
f351b2d6
SB		 3103 readl(mmio + hpriv->irq_cause_ofs),
3104 readl(mmio + hpriv->irq_mask_ofs));
3105 } else {
3106 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
7368f919 3107 hpriv->main_irq_mask_addr);
f351b2d6 3108 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 3109 readl(hpriv->main_irq_cause_addr),
3110 readl(hpriv->main_irq_mask_addr));
f351b2d6
SB		 3111 }
3112done:
3113 return rc;
3114}
fb621e2f 3115
fbf14e2f
BB		 3116static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3117{
3118 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3119 MV_CRQB_Q_SZ, 0);
3120 if (!hpriv->crqb_pool)
3121 return -ENOMEM;
3122
3123 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3124 MV_CRPB_Q_SZ, 0);
3125 if (!hpriv->crpb_pool)
3126 return -ENOMEM;
3127
3128 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3129 MV_SG_TBL_SZ, 0);
3130 if (!hpriv->sg_tbl_pool)
3131 return -ENOMEM;
3132
3133 return 0;
3134}
3135
15a32632
LB		 3136static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3137 struct mbus_dram_target_info *dram)
3138{
3139 int i;
3140
3141 for (i = 0; i < 4; i++) {
3142 writel(0, hpriv->base + WINDOW_CTRL(i));
3143 writel(0, hpriv->base + WINDOW_BASE(i));
3144 }
3145
3146 for (i = 0; i < dram->num_cs; i++) {
3147 struct mbus_dram_window *cs = dram->cs + i;
3148
3149 writel(((cs->size - 1) & 0xffff0000) |
3150 (cs->mbus_attr << 8) |
3151 (dram->mbus_dram_target_id << 4) | 1,
3152 hpriv->base + WINDOW_CTRL(i));
3153 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3154 }
3155}
3156
f351b2d6
SB		 3157/**
3158 * mv_platform_probe - handle a positive probe of an soc Marvell
3159 * host
3160 * @pdev: platform device found
3161 *
3162 * LOCKING:
3163 * Inherited from caller.
3164 */
3165static int mv_platform_probe(struct platform_device *pdev)
3166{
3167 static int printed_version;
3168 const struct mv_sata_platform_data *mv_platform_data;
3169 const struct ata_port_info *ppi[] =
3170 { &mv_port_info[chip_soc], NULL };
3171 struct ata_host *host;
3172 struct mv_host_priv *hpriv;
3173 struct resource *res;
3174 int n_ports, rc;
20f733e7 3175
f351b2d6
SB		 3176 if (!printed_version++)
3177 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3178
f351b2d6
SB		 3179 /*
3180 * Simple resource validation ..
3181 */
3182 if (unlikely(pdev->num_resources != 2)) {
3183 dev_err(&pdev->dev, "invalid number of resources\n");
3184 return -EINVAL;
3185 }
3186
3187 /*
3188 * Get the register base first
3189 */
3190 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3191 if (res == NULL)
3192 return -EINVAL;
3193
3194 /* allocate host */
3195 mv_platform_data = pdev->dev.platform_data;
3196 n_ports = mv_platform_data->n_ports;
3197
3198 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3199 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3200
3201 if (!host || !hpriv)
3202 return -ENOMEM;
3203 host->private_data = hpriv;
3204 hpriv->n_ports = n_ports;
3205
3206 host->iomap = NULL;
f1cb0ea1
SB		 3207 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3208 res->end - res->start + 1);
f351b2d6
SB		 3209 hpriv->base -= MV_SATAHC0_REG_BASE;
3210
15a32632
LB		 3211 /*
3212 * (Re-)program MBUS remapping windows if we are asked to.
3213 */
3214 if (mv_platform_data->dram != NULL)
3215 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3216
fbf14e2f
BB		 3217 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3218 if (rc)
3219 return rc;
3220
f351b2d6
SB		 3221 /* initialize adapter */
3222 rc = mv_init_host(host, chip_soc);
3223 if (rc)
3224 return rc;
3225
3226 dev_printk(KERN_INFO, &pdev->dev,
3227 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3228 host->n_ports);
3229
3230 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3231 IRQF_SHARED, &mv6_sht);
3232}
3233
3234/*
3235 *
3236 * mv_platform_remove - unplug a platform interface
3237 * @pdev: platform device
3238 *
3239 * A platform bus SATA device has been unplugged. Perform the needed
3240 * cleanup. Also called on module unload for any active devices.
3241 */
3242static int __devexit mv_platform_remove(struct platform_device *pdev)
3243{
3244 struct device *dev = &pdev->dev;
3245 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3246
3247 ata_host_detach(host);
f351b2d6 3248 return 0;
20f733e7
BR		 3249}
3250
f351b2d6
SB		 3251static struct platform_driver mv_platform_driver = {
3252 .probe = mv_platform_probe,
3253 .remove = __devexit_p(mv_platform_remove),
3254 .driver = {
3255 .name = DRV_NAME,
3256 .owner = THIS_MODULE,
3257 },
3258};
3259
3260
7bb3c529 3261#ifdef CONFIG_PCI
f351b2d6
SB		 3262static int mv_pci_init_one(struct pci_dev *pdev,
3263 const struct pci_device_id *ent);
3264
7bb3c529
SB		 3265
3266static struct pci_driver mv_pci_driver = {
3267 .name = DRV_NAME,
3268 .id_table = mv_pci_tbl,
f351b2d6 3269 .probe = mv_pci_init_one,
7bb3c529
SB		 3270 .remove = ata_pci_remove_one,
3271};
3272
3273/*
3274 * module options
3275 */
3276static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3277
3278
3279/* move to PCI layer or libata core? */
3280static int pci_go_64(struct pci_dev *pdev)
3281{
3282 int rc;
3283
3284 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3285 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3286 if (rc) {
3287 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3288 if (rc) {
3289 dev_printk(KERN_ERR, &pdev->dev,
3290 "64-bit DMA enable failed\n");
3291 return rc;
3292 }
3293 }
3294 } else {
3295 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3296 if (rc) {
3297 dev_printk(KERN_ERR, &pdev->dev,
3298 "32-bit DMA enable failed\n");
3299 return rc;
3300 }
3301 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3302 if (rc) {
3303 dev_printk(KERN_ERR, &pdev->dev,
3304 "32-bit consistent DMA enable failed\n");
3305 return rc;
3306 }
3307 }
3308
3309 return rc;
3310}
3311
05b308e1
BR		 3312/**
3313 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3314 * @host: ATA host to print info about
05b308e1
BR		 3315 *
3316 * FIXME: complete this.
3317 *
3318 * LOCKING:
3319 * Inherited from caller.
3320 */
4447d351 3321static void mv_print_info(struct ata_host *host)
31961943 3322{
4447d351
TH		 3323 struct pci_dev *pdev = to_pci_dev(host->dev);
3324 struct mv_host_priv *hpriv = host->private_data;
44c10138 3325 u8 scc;
c1e4fe71 3326 const char *scc_s, *gen;
31961943
BR		 3327
3328 /* Use this to determine the HW stepping of the chip so we know
3329 * what errata to workaround
3330 */
31961943
BR		 3331 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3332 if (scc == 0)
3333 scc_s = "SCSI";
3334 else if (scc == 0x01)
3335 scc_s = "RAID";
3336 else
c1e4fe71
JG		 3337 scc_s = "?";
3338
3339 if (IS_GEN_I(hpriv))
3340 gen = "I";
3341 else if (IS_GEN_II(hpriv))
3342 gen = "II";
3343 else if (IS_GEN_IIE(hpriv))
3344 gen = "IIE";
3345 else
3346 gen = "?";
31961943 3347
a9524a76 3348 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3349 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3350 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3351 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3352}
3353
05b308e1 3354/**
f351b2d6 3355 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3356 * @pdev: PCI device found
3357 * @ent: PCI device ID entry for the matched host
3358 *
3359 * LOCKING:
3360 * Inherited from caller.
3361 */
f351b2d6
SB		 3362static int mv_pci_init_one(struct pci_dev *pdev,
3363 const struct pci_device_id *ent)
20f733e7 3364{
2dcb407e 3365 static int printed_version;
20f733e7 3366 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3367 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3368 struct ata_host *host;
3369 struct mv_host_priv *hpriv;
3370 int n_ports, rc;
20f733e7 3371
a9524a76
JG		 3372 if (!printed_version++)
3373 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3374
4447d351
TH		 3375 /* allocate host */
3376 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3377
3378 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3379 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3380 if (!host || !hpriv)
3381 return -ENOMEM;
3382 host->private_data = hpriv;
f351b2d6 3383 hpriv->n_ports = n_ports;
4447d351
TH		 3384
3385 /* acquire resources */
24dc5f33
TH		 3386 rc = pcim_enable_device(pdev);
3387 if (rc)
20f733e7 3388 return rc;
20f733e7 3389
0d5ff566
TH		 3390 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3391 if (rc == -EBUSY)
24dc5f33 3392 pcim_pin_device(pdev);
0d5ff566 3393 if (rc)
24dc5f33 3394 return rc;
4447d351 3395 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3396 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3397
d88184fb
JG		 3398 rc = pci_go_64(pdev);
3399 if (rc)
3400 return rc;
3401
da2fa9ba
ML		 3402 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3403 if (rc)
3404 return rc;
3405
20f733e7 3406 /* initialize adapter */
4447d351 3407 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3408 if (rc)
3409 return rc;
20f733e7 3410
31961943 3411 /* Enable interrupts */
6a59dcf8 3412 if (msi && pci_enable_msi(pdev))
31961943 3413 pci_intx(pdev, 1);
20f733e7 3414
31961943 3415 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3416 mv_print_info(host);
20f733e7 3417
4447d351 3418 pci_set_master(pdev);
ea8b4db9 3419 pci_try_set_mwi(pdev);
4447d351 3420 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3421 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3422}
7bb3c529 3423#endif
20f733e7 3424
f351b2d6
SB		 3425static int mv_platform_probe(struct platform_device *pdev);
3426static int __devexit mv_platform_remove(struct platform_device *pdev);
3427
20f733e7
BR		 3428static int __init mv_init(void)
3429{
7bb3c529
SB		 3430 int rc = -ENODEV;
3431#ifdef CONFIG_PCI
3432 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3433 if (rc < 0)
3434 return rc;
3435#endif
3436 rc = platform_driver_register(&mv_platform_driver);
3437
3438#ifdef CONFIG_PCI
3439 if (rc < 0)
3440 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3441#endif
3442 return rc;
20f733e7
BR		 3443}
3444
3445static void __exit mv_exit(void)
3446{
7bb3c529 3447#ifdef CONFIG_PCI
20f733e7 3448 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3449#endif
f351b2d6 3450 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3451}
3452
3453MODULE_AUTHOR("Brett Russ");
3454MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3455MODULE_LICENSE("GPL");
3456MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3457MODULE_VERSION(DRV_VERSION);
17c5aab5 3458MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3459
7bb3c529 3460#ifdef CONFIG_PCI
ddef9bb3
JG		 3461module_param(msi, int, 0444);
3462MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3463#endif
ddef9bb3 3464
20f733e7
BR		 3465module_init(mv_init);
3466module_exit(mv_exit);
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