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[net-next-2.6.git] / drivers / ata / pata_via.c
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669a5db4
JG		 1/*
2 * pata_via.c - VIA PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
05c39e50 26 * VIA VT8237S - UDMA133
75f609d2 27 * VIA VT8251 - UDMA133
669a5db4
JG		 28 *
29 * Most registers remain compatible across chips. Others start reserved
30 * and acquire sensible semantics if set to 1 (eg cable detect). A few
31 * exceptions exist, notably around the FIFO settings.
32 *
33 * One additional quirk of the VIA design is that like ALi they use few
34 * PCI IDs for a lot of chips.
35 *
36 * Based heavily on:
37 *
38 * Version 3.38
39 *
40 * VIA IDE driver for Linux. Supported southbridges:
41 *
42 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
43 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
44 * vt8235, vt8237
45 *
46 * Copyright (c) 2000-2002 Vojtech Pavlik
47 *
48 * Based on the work of:
49 * Michel Aubry
50 * Jeff Garzik
51 * Andre Hedrick
52
53 */
54
55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <scsi/scsi_host.h>
62#include <linux/libata.h>
cf5792d2 63#include <linux/dmi.h>
669a5db4
JG		 64
65#define DRV_NAME "pata_via"
943547ab 66#define DRV_VERSION "0.3.3"
669a5db4
JG		 67
68/*
69 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
70 * driver.
71 */
72
73enum {
74 VIA_UDMA = 0x007,
75 VIA_UDMA_NONE = 0x000,
76 VIA_UDMA_33 = 0x001,
77 VIA_UDMA_66 = 0x002,
78 VIA_UDMA_100 = 0x003,
79 VIA_UDMA_133 = 0x004,
80 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
81 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
82 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
83 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
84 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
85 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
86 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
7585eb1b 87 VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */
669a5db4
JG		 88};
89
90/*
91 * VIA SouthBridge chips.
92 */
93
94static const struct via_isa_bridge {
95 const char *name;
96 u16 id;
97 u8 rev_min;
98 u8 rev_max;
99 u16 flags;
100} via_isa_bridges[] = {
b311ec4a 101 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
e0b874df 102 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
75f609d2 103 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
7585eb1b 104 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA },
669a5db4
JG		 105 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
106 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
107 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
108 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
109 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
110 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
111 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
112 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
113 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
114 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
115 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
116 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
117 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
118 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
119 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
120 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
121 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
122 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
123 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
124 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
125 { NULL }
126};
127
cf5792d2
AC		 128
129/*
130 * Cable special cases
131 */
132
1855256c 133static const struct dmi_system_id cable_dmi_table[] = {
cf5792d2
AC		 134 {
135 .ident = "Acer Ferrari 3400",
136 .matches = {
137 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
138 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
139 },
140 },
141 { }
142};
143
144static int via_cable_override(struct pci_dev *pdev)
145{
146 /* Systems by DMI */
147 if (dmi_check_system(cable_dmi_table))
148 return 1;
9edbdbea
AC		 149 /* Arima W730-K8/Targa Visionary 811/... */
150 if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
151 return 1;
cf5792d2
AC		 152 return 0;
153}
154
155
669a5db4
JG		 156/**
157 * via_cable_detect - cable detection
158 * @ap: ATA port
159 *
160 * Perform cable detection. Actually for the VIA case the BIOS
161 * already did this for us. We read the values provided by the
162 * BIOS. If you are using an 8235 in a non-PC configuration you
163 * may need to update this code.
164 *
165 * Hotplug also impacts on this.
166 */
167
168static int via_cable_detect(struct ata_port *ap) {
97cb81c3 169 const struct via_isa_bridge *config = ap->host->private_data;
669a5db4
JG		 170 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
171 u32 ata66;
172
cf5792d2
AC		 173 if (via_cable_override(pdev))
174 return ATA_CBL_PATA40_SHORT;
175
7585eb1b
TH		 176 if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
177 return ATA_CBL_SATA;
178
97cb81c3
AC		 179 /* Early chips are 40 wire */
180 if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
181 return ATA_CBL_PATA40;
182 /* UDMA 66 chips have only drive side logic */
b447916e 183 else if ((config->flags & VIA_UDMA) < VIA_UDMA_100)
97cb81c3
AC		 184 return ATA_CBL_PATA_UNK;
185 /* UDMA 100 or later */
669a5db4
JG		 186 pci_read_config_dword(pdev, 0x50, &ata66);
187 /* Check both the drive cable reporting bits, we might not have
188 two drives */
189 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
190 return ATA_CBL_PATA80;
7d73a363 191 /* Check with ACPI so we can spot BIOS reported SATA bridges */
021ee9a6
TH		 192 if (ata_acpi_init_gtm(ap) &&
193 ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
7d73a363 194 return ATA_CBL_PATA80;
97cb81c3 195 return ATA_CBL_PATA40;
669a5db4
JG		 196}
197
cc0680a5 198static int via_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 199{
cc0680a5 200 struct ata_port *ap = link->ap;
669a5db4
JG		 201 const struct via_isa_bridge *config = ap->host->private_data;
202
203 if (!(config->flags & VIA_NO_ENABLES)) {
204 static const struct pci_bits via_enable_bits[] = {
205 { 0x40, 1, 0x02, 0x02 },
206 { 0x40, 1, 0x01, 0x01 }
207 };
669a5db4 208 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
c961922b
AC		 209 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
210 return -ENOENT;
669a5db4 211 }
d4b2bab4 212
cc0680a5 213 return ata_std_prereset(link, deadline);
669a5db4
JG		 214}
215
216
217/**
218 * via_error_handler - reset for VIA chips
219 * @ap: ATA port
220 *
221 * Handle the reset callback for the later chips with cable detect
222 */
223
224static void via_error_handler(struct ata_port *ap)
225{
226 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
227}
228
229/**
230 * via_do_set_mode - set initial PIO mode data
231 * @ap: ATA interface
232 * @adev: ATA device
233 * @mode: ATA mode being programmed
234 * @tdiv: Clocks per PCI clock
235 * @set_ast: Set to program address setup
236 * @udma_type: UDMA mode/format of registers
237 *
238 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
239 * support in order to compute modes.
240 *
241 * FIXME: Hotplug will require we serialize multiple mode changes
242 * on the two channels.
243 */
244
245static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
246{
247 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
248 struct ata_device *peer = ata_dev_pair(adev);
249 struct ata_timing t, p;
250 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
251 unsigned long T = 1000000000 / via_clock;
252 unsigned long UT = T/tdiv;
253 int ut;
254 int offset = 3 - (2*ap->port_no) - adev->devno;
255
669a5db4
JG		 256 /* Calculate the timing values we require */
257 ata_timing_compute(adev, mode, &t, T, UT);
258
259 /* We share 8bit timing so we must merge the constraints */
260 if (peer) {
261 if (peer->pio_mode) {
262 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
263 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
264 }
265 }
266
267 /* Address setup is programmable but breaks on UDMA133 setups */
268 if (set_ast) {
269 u8 setup; /* 2 bits per drive */
270 int shift = 2 * offset;
271
272 pci_read_config_byte(pdev, 0x4C, &setup);
273 setup &= ~(3 << shift);
274 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
275 pci_write_config_byte(pdev, 0x4C, setup);
276 }
277
278 /* Load the PIO mode bits */
279 pci_write_config_byte(pdev, 0x4F - ap->port_no,
280 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
281 pci_write_config_byte(pdev, 0x48 + offset,
282 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));
283
284 /* Load the UDMA bits according to type */
285 switch(udma_type) {
286 default:
287 /* BUG() ? */
288 /* fall through */
289 case 33:
290 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
291 break;
292 case 66:
293 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
294 break;
295 case 100:
296 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
297 break;
298 case 133:
299 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
300 break;
301 }
08ebd43d 302
669a5db4 303 /* Set UDMA unless device is not UDMA capable */
943547ab 304 if (udma_type && t.udma) {
08ebd43d
LR		 305 u8 cable80_status;
306
307 /* Get 80-wire cable detection bit */
308 pci_read_config_byte(pdev, 0x50 + offset, &cable80_status);
309 cable80_status &= 0x10;
310
311 pci_write_config_byte(pdev, 0x50 + offset, ut | cable80_status);
312 }
669a5db4
JG		 313}
314
315static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
316{
317 const struct via_isa_bridge *config = ap->host->private_data;
318 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
319 int mode = config->flags & VIA_UDMA;
320 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
321 static u8 udma[5] = { 0, 33, 66, 100, 133 };
322
323 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
324}
325
326static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
327{
328 const struct via_isa_bridge *config = ap->host->private_data;
329 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
330 int mode = config->flags & VIA_UDMA;
331 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
332 static u8 udma[5] = { 0, 33, 66, 100, 133 };
333
334 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
335}
336
337static struct scsi_host_template via_sht = {
338 .module = THIS_MODULE,
339 .name = DRV_NAME,
340 .ioctl = ata_scsi_ioctl,
341 .queuecommand = ata_scsi_queuecmd,
342 .can_queue = ATA_DEF_QUEUE,
343 .this_id = ATA_SHT_THIS_ID,
344 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 345 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
346 .emulated = ATA_SHT_EMULATED,
347 .use_clustering = ATA_SHT_USE_CLUSTERING,
348 .proc_name = DRV_NAME,
349 .dma_boundary = ATA_DMA_BOUNDARY,
350 .slave_configure = ata_scsi_slave_config,
afdfe899 351 .slave_destroy = ata_scsi_slave_destroy,
669a5db4
JG		 352 .bios_param = ata_std_bios_param,
353};
354
355static struct ata_port_operations via_port_ops = {
669a5db4
JG		 356 .set_piomode = via_set_piomode,
357 .set_dmamode = via_set_dmamode,
358 .mode_filter = ata_pci_default_filter,
359
360 .tf_load = ata_tf_load,
361 .tf_read = ata_tf_read,
362 .check_status = ata_check_status,
363 .exec_command = ata_exec_command,
364 .dev_select = ata_std_dev_select,
365
366 .freeze = ata_bmdma_freeze,
367 .thaw = ata_bmdma_thaw,
368 .error_handler = via_error_handler,
369 .post_internal_cmd = ata_bmdma_post_internal_cmd,
97cb81c3 370 .cable_detect = via_cable_detect,
669a5db4
JG		 371
372 .bmdma_setup = ata_bmdma_setup,
373 .bmdma_start = ata_bmdma_start,
374 .bmdma_stop = ata_bmdma_stop,
375 .bmdma_status = ata_bmdma_status,
376
377 .qc_prep = ata_qc_prep,
378 .qc_issue = ata_qc_issue_prot,
bda30288 379
0d5ff566 380 .data_xfer = ata_data_xfer,
669a5db4
JG		 381
382 .irq_handler = ata_interrupt,
383 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 384 .irq_on = ata_irq_on,
669a5db4 385
81ad1837 386 .port_start = ata_sff_port_start,
669a5db4
JG		 387};
388
389static struct ata_port_operations via_port_ops_noirq = {
669a5db4
JG		 390 .set_piomode = via_set_piomode,
391 .set_dmamode = via_set_dmamode,
392 .mode_filter = ata_pci_default_filter,
393
394 .tf_load = ata_tf_load,
395 .tf_read = ata_tf_read,
396 .check_status = ata_check_status,
397 .exec_command = ata_exec_command,
398 .dev_select = ata_std_dev_select,
399
400 .freeze = ata_bmdma_freeze,
401 .thaw = ata_bmdma_thaw,
402 .error_handler = via_error_handler,
403 .post_internal_cmd = ata_bmdma_post_internal_cmd,
97cb81c3 404 .cable_detect = via_cable_detect,
669a5db4
JG		 405
406 .bmdma_setup = ata_bmdma_setup,
407 .bmdma_start = ata_bmdma_start,
408 .bmdma_stop = ata_bmdma_stop,
409 .bmdma_status = ata_bmdma_status,
410
411 .qc_prep = ata_qc_prep,
412 .qc_issue = ata_qc_issue_prot,
bda30288 413
0d5ff566 414 .data_xfer = ata_data_xfer_noirq,
669a5db4
JG		 415
416 .irq_handler = ata_interrupt,
417 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 418 .irq_on = ata_irq_on,
669a5db4 419
81ad1837 420 .port_start = ata_sff_port_start,
669a5db4
JG		 421};
422
627d2d32
AC		 423/**
424 * via_config_fifo - set up the FIFO
425 * @pdev: PCI device
426 * @flags: configuration flags
427 *
3a4fa0a2 428 * Set the FIFO properties for this device if necessary. Used both on
627d2d32
AC		 429 * set up and on and the resume path
430 */
431
432static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
433{
434 u8 enable;
f20b16ff 435
627d2d32
AC		 436 /* 0x40 low bits indicate enabled channels */
437 pci_read_config_byte(pdev, 0x40 , &enable);
438 enable &= 3;
f20b16ff 439
627d2d32 440 if (flags & VIA_SET_FIFO) {
73720861 441 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
627d2d32
AC		 442 u8 fifo;
443
444 pci_read_config_byte(pdev, 0x43, &fifo);
445
446 /* Clear PREQ# until DDACK# for errata */
447 if (flags & VIA_BAD_PREQ)
448 fifo &= 0x7F;
449 else
450 fifo &= 0x9f;
451 /* Turn on FIFO for enabled channels */
452 fifo |= fifo_setting[enable];
453 pci_write_config_byte(pdev, 0x43, fifo);
454 }
455}
456
669a5db4
JG		 457/**
458 * via_init_one - discovery callback
627d2d32 459 * @pdev: PCI device
669a5db4
JG		 460 * @id: PCI table info
461 *
462 * A VIA IDE interface has been discovered. Figure out what revision
463 * and perform configuration work before handing it to the ATA layer
464 */
465
466static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
467{
468 /* Early VIA without UDMA support */
1626aeb8 469 static const struct ata_port_info via_mwdma_info = {
669a5db4 470 .sht = &via_sht,
464cf177 471 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 472 .pio_mask = 0x1f,
473 .mwdma_mask = 0x07,
474 .port_ops = &via_port_ops
475 };
476 /* Ditto with IRQ masking required */
1626aeb8 477 static const struct ata_port_info via_mwdma_info_borked = {
669a5db4 478 .sht = &via_sht,
464cf177 479 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 480 .pio_mask = 0x1f,
481 .mwdma_mask = 0x07,
482 .port_ops = &via_port_ops_noirq,
483 };
484 /* VIA UDMA 33 devices (and borked 66) */
1626aeb8 485 static const struct ata_port_info via_udma33_info = {
669a5db4 486 .sht = &via_sht,
464cf177 487 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 488 .pio_mask = 0x1f,
489 .mwdma_mask = 0x07,
bf6263a8 490 .udma_mask = ATA_UDMA2,
669a5db4
JG		 491 .port_ops = &via_port_ops
492 };
493 /* VIA UDMA 66 devices */
1626aeb8 494 static const struct ata_port_info via_udma66_info = {
669a5db4 495 .sht = &via_sht,
464cf177 496 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 497 .pio_mask = 0x1f,
498 .mwdma_mask = 0x07,
bf6263a8 499 .udma_mask = ATA_UDMA4,
669a5db4
JG		 500 .port_ops = &via_port_ops
501 };
502 /* VIA UDMA 100 devices */
1626aeb8 503 static const struct ata_port_info via_udma100_info = {
669a5db4 504 .sht = &via_sht,
464cf177 505 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 506 .pio_mask = 0x1f,
507 .mwdma_mask = 0x07,
bf6263a8 508 .udma_mask = ATA_UDMA5,
669a5db4
JG		 509 .port_ops = &via_port_ops
510 };
511 /* UDMA133 with bad AST (All current 133) */
1626aeb8 512 static const struct ata_port_info via_udma133_info = {
669a5db4 513 .sht = &via_sht,
464cf177 514 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 515 .pio_mask = 0x1f,
516 .mwdma_mask = 0x07,
bf6263a8 517 .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
669a5db4
JG		 518 .port_ops = &via_port_ops
519 };
1626aeb8
TH		 520 struct ata_port_info type;
521 const struct ata_port_info *ppi[] = { &type, NULL };
669a5db4
JG		 522 struct pci_dev *isa = NULL;
523 const struct via_isa_bridge *config;
524 static int printed_version;
669a5db4
JG		 525 u8 enable;
526 u32 timing;
527
528 if (!printed_version++)
529 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
530
531 /* To find out how the IDE will behave and what features we
532 actually have to look at the bridge not the IDE controller */
533 for (config = via_isa_bridges; config->id; config++)
534 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
535 !!(config->flags & VIA_BAD_ID),
536 config->id, NULL))) {
537
44c10138
AK		 538 if (isa->revision >= config->rev_min &&
539 isa->revision <= config->rev_max)
669a5db4
JG		 540 break;
541 pci_dev_put(isa);
542 }
543
544 if (!config->id) {
545 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
546 return -ENODEV;
547 }
548 pci_dev_put(isa);
549
550 /* 0x40 low bits indicate enabled channels */
551 pci_read_config_byte(pdev, 0x40 , &enable);
552 enable &= 3;
553 if (enable == 0) {
554 return -ENODEV;
555 }
556
557 /* Initialise the FIFO for the enabled channels. */
627d2d32 558 via_config_fifo(pdev, config->flags);
f20b16ff 559
669a5db4
JG		 560 /* Clock set up */
561 switch(config->flags & VIA_UDMA) {
562 case VIA_UDMA_NONE:
563 if (config->flags & VIA_NO_UNMASK)
1626aeb8 564 type = via_mwdma_info_borked;
669a5db4 565 else
1626aeb8 566 type = via_mwdma_info;
669a5db4
JG		 567 break;
568 case VIA_UDMA_33:
1626aeb8 569 type = via_udma33_info;
669a5db4
JG		 570 break;
571 case VIA_UDMA_66:
1626aeb8 572 type = via_udma66_info;
669a5db4
JG		 573 /* The 66 MHz devices require we enable the clock */
574 pci_read_config_dword(pdev, 0x50, &timing);
575 timing |= 0x80008;
576 pci_write_config_dword(pdev, 0x50, timing);
577 break;
578 case VIA_UDMA_100:
1626aeb8 579 type = via_udma100_info;
669a5db4
JG		 580 break;
581 case VIA_UDMA_133:
1626aeb8 582 type = via_udma133_info;
669a5db4
JG		 583 break;
584 default:
585 WARN_ON(1);
586 return -ENODEV;
587 }
588
589 if (config->flags & VIA_BAD_CLK66) {
590 /* Disable the 66MHz clock on problem devices */
591 pci_read_config_dword(pdev, 0x50, &timing);
592 timing &= ~0x80008;
593 pci_write_config_dword(pdev, 0x50, timing);
594 }
595
596 /* We have established the device type, now fire it up */
1626aeb8 597 type.private_data = (void *)config;
669a5db4 598
1626aeb8 599 return ata_pci_init_one(pdev, ppi);
669a5db4
JG		 600}
601
438ac6d5 602#ifdef CONFIG_PM
627d2d32
AC		 603/**
604 * via_reinit_one - reinit after resume
605 * @pdev; PCI device
606 *
607 * Called when the VIA PATA device is resumed. We must then
608 * reconfigure the fifo and other setup we may have altered. In
609 * addition the kernel needs to have the resume methods on PCI
610 * quirk supported.
611 */
612
613static int via_reinit_one(struct pci_dev *pdev)
614{
615 u32 timing;
616 struct ata_host *host = dev_get_drvdata(&pdev->dev);
617 const struct via_isa_bridge *config = host->private_data;
f20b16ff 618
627d2d32
AC		 619 via_config_fifo(pdev, config->flags);
620
621 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
622 /* The 66 MHz devices require we enable the clock */
623 pci_read_config_dword(pdev, 0x50, &timing);
624 timing |= 0x80008;
625 pci_write_config_dword(pdev, 0x50, timing);
626 }
627 if (config->flags & VIA_BAD_CLK66) {
628 /* Disable the 66MHz clock on problem devices */
629 pci_read_config_dword(pdev, 0x50, &timing);
630 timing &= ~0x80008;
631 pci_write_config_dword(pdev, 0x50, timing);
632 }
f20b16ff 633 return ata_pci_device_resume(pdev);
627d2d32 634}
438ac6d5 635#endif
627d2d32 636
669a5db4 637static const struct pci_device_id via[] = {
52df0ee0
JG		 638 { PCI_VDEVICE(VIA, 0x0571), },
639 { PCI_VDEVICE(VIA, 0x0581), },
640 { PCI_VDEVICE(VIA, 0x1571), },
641 { PCI_VDEVICE(VIA, 0x3164), },
642 { PCI_VDEVICE(VIA, 0x5324), },
2d2744fc
JG		 643
644 { },
669a5db4
JG		 645};
646
647static struct pci_driver via_pci_driver = {
2d2744fc 648 .name = DRV_NAME,
669a5db4
JG		 649 .id_table = via,
650 .probe = via_init_one,
627d2d32 651 .remove = ata_pci_remove_one,
438ac6d5 652#ifdef CONFIG_PM
627d2d32
AC		 653 .suspend = ata_pci_device_suspend,
654 .resume = via_reinit_one,
438ac6d5 655#endif
669a5db4
JG		 656};
657
658static int __init via_init(void)
659{
660 return pci_register_driver(&via_pci_driver);
661}
662
669a5db4
JG		 663static void __exit via_exit(void)
664{
665 pci_unregister_driver(&via_pci_driver);
666}
667
669a5db4
JG		 668MODULE_AUTHOR("Alan Cox");
669MODULE_DESCRIPTION("low-level driver for VIA PATA");
670MODULE_LICENSE("GPL");
671MODULE_DEVICE_TABLE(pci, via);
672MODULE_VERSION(DRV_VERSION);
673
674module_init(via_init);
675module_exit(via_exit);
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