[net-next-2.6.git] / drivers / ata / pata_serverworks.c

/*
 * pata_serverworks.c 	- Serverworks PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  (C) 2010 Bartlomiej Zolnierkiewicz
 *
 * based upon
 *
 * serverworks.c
 *
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_serverworks"
#define DRV_VERSION "0.4.3"

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */

static const char *csb_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

/**
 *	dell_cable	-	Dell serverworks cable detection
 *	@ap: ATA port to do cable detect
 *
 *	Dell hide the 40/80 pin select for their interfaces in the top two
 *	bits of the subsystem ID.
 */

static int dell_cable(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	sun_cable	-	Sun Cobalt 'Alpine' cable detection
 *	@ap: ATA port to do cable select
 *
 *	Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
 *	subsystem ID the same as dell. We could use one function but we may
 *	need to extend the Dell one in future
 */

static int sun_cable(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	osb4_cable	-	OSB4 cable detect
 *	@ap: ATA port to check
 *
 *	The OSB4 isn't UDMA66 capable so this is easy
 */

static int osb4_cable(struct ata_port *ap) {
	return ATA_CBL_PATA40;
}

/**
 *	csb_cable	-	CSB5/6 cable detect
 *	@ap: ATA port to check
 *
 *	Serverworks default arrangement is to use the drive side detection
 *	only.
 */

static int csb_cable(struct ata_port *ap) {
	return ATA_CBL_PATA_UNK;
}

struct sv_cable_table {
	int device;
	int subvendor;
	int (*cable_detect)(struct ata_port *ap);
};

/*
 *	Note that we don't copy the old serverworks code because the old
 *	code contains obvious mistakes
 */

static struct sv_cable_table cable_detect[] = {
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN,  sun_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
	{ }
};

/**
 *	serverworks_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection according to the device and subvendor
 *	identifications
 */

static int serverworks_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct sv_cable_table *cb = cable_detect;

	while(cb->device) {
		if (cb->device == pdev->device &&
		    (cb->subvendor == pdev->subsystem_vendor ||
		      cb->subvendor == PCI_ANY_ID)) {
			return cb->cable_detect(ap);
		}
		cb++;
	}

	BUG();
	return -1;	/* kill compiler warning */
}

/**
 *	serverworks_is_csb	-	Check for CSB or OSB
 *	@pdev: PCI device to check
 *
 *	Returns true if the device being checked is known to be a CSB
 *	series device.
 */

static u8 serverworks_is_csb(struct pci_dev *pdev)
{
	switch (pdev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}

/**
 *	serverworks_osb4_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: Mask of proposed modes
 *
 *	Filter the offered modes for the device to apply controller
 *	specific rules. OSB4 requires no UDMA for disks due to a FIFO
 *	bug we hit.
 */

static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA)
		mask &= ~ATA_MASK_UDMA;
	return mask;
}


/**
 *	serverworks_csb_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: Mask of proposed modes
 *
 *	Check the blacklist and disable UDMA5 if matched
 */

static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
{
	const char *p;
	char model_num[ATA_ID_PROD_LEN + 1];
	int i;

	/* Disk, UDMA */
	if (adev->class != ATA_DEV_ATA)
		return mask;

	/* Actually do need to check */
	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
		if (!strcmp(p, model_num))
			mask &= ~(0xE0 << ATA_SHIFT_UDMA);
	}
	return mask;
}

/**
 *	serverworks_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the OSB4/CSB5 timing registers for PIO. The PIO register
 *	load is done as a simple lookup.
 */
static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	int offset = 1 + 2 * ap->port_no - adev->devno;
	int devbits = (2 * ap->port_no + adev->devno) * 4;
	u16 csb5_pio;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;

	pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);

	/* The OSB4 just requires the timing but the CSB series want the
	   mode number as well */
	if (serverworks_is_csb(pdev)) {
		pci_read_config_word(pdev, 0x4A, &csb5_pio);
		csb5_pio &= ~(0x0F << devbits);
		pci_write_config_word(pdev, 0x4A, csb5_pio | (pio << devbits));
	}
}

/**
 *	serverworks_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
 *	chipset. The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
	int offset = 1 + 2 * ap->port_no - adev->devno;
	int devbits = 2 * ap->port_no + adev->devno;
	u8 ultra;
	u8 ultra_cfg;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	pci_read_config_byte(pdev, 0x54, &ultra_cfg);
	pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
	ultra &= ~(0x0F << (adev->devno * 4));

	if (adev->dma_mode >= XFER_UDMA_0) {
		pci_write_config_byte(pdev, 0x44 + offset,  0x20);

		ultra |= (adev->dma_mode - XFER_UDMA_0)
					<< (adev->devno * 4);
		ultra_cfg |=  (1 << devbits);
	} else {
		pci_write_config_byte(pdev, 0x44 + offset,
			dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
		ultra_cfg &= ~(1 << devbits);
	}
	pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
	pci_write_config_byte(pdev, 0x54, ultra_cfg);
}

static struct scsi_host_template serverworks_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations serverworks_osb4_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= serverworks_cable_detect,
	.mode_filter	= serverworks_osb4_filter,
	.set_piomode	= serverworks_set_piomode,
	.set_dmamode	= serverworks_set_dmamode,
};

static struct ata_port_operations serverworks_csb_port_ops = {
	.inherits	= &serverworks_osb4_port_ops,
	.mode_filter	= serverworks_csb_filter,
};

static int serverworks_fixup_osb4(struct pci_dev *pdev)
{
	u32 reg;
	struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
		  PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	if (isa_dev) {
		pci_read_config_dword(isa_dev, 0x64, &reg);
		reg &= ~0x00002000; /* disable 600ns interrupt mask */
		if (!(reg & 0x00004000))
			printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
		reg |=  0x00004000; /* enable UDMA/33 support */
		pci_write_config_dword(isa_dev, 0x64, reg);
		pci_dev_put(isa_dev);
		return 0;
	}
	printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n");
	return -ENODEV;
}

static int serverworks_fixup_csb(struct pci_dev *pdev)
{
	u8 btr;

	/* Third Channel Test */
	if (!(PCI_FUNC(pdev->devfn) & 1)) {
		struct pci_dev * findev = NULL;
		u32 reg4c = 0;
		findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
			PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
		if (findev) {
			pci_read_config_dword(findev, 0x4C, &reg4c);
			reg4c &= ~0x000007FF;
			reg4c |=  0x00000040;
			reg4c |=  0x00000020;
			pci_write_config_dword(findev, 0x4C, reg4c);
			pci_dev_put(findev);
		}
	} else {
		struct pci_dev * findev = NULL;
		u8 reg41 = 0;

		findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
		if (findev) {
			pci_read_config_byte(findev, 0x41, &reg41);
			reg41 &= ~0x40;
			pci_write_config_byte(findev, 0x41, reg41);
			pci_dev_put(findev);
		}
	}
	/* setup the UDMA Control register
	 *
	 * 1. clear bit 6 to enable DMA
	 * 2. enable DMA modes with bits 0-1
	 * 	00 : legacy
	 * 	01 : udma2
	 * 	10 : udma2/udma4
	 * 	11 : udma2/udma4/udma5
	 */
	pci_read_config_byte(pdev, 0x5A, &btr);
	btr &= ~0x40;
	if (!(PCI_FUNC(pdev->devfn) & 1))
		btr |= 0x2;
	else
		btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
	pci_write_config_byte(pdev, 0x5A, btr);

	return btr;
}

static void serverworks_fixup_ht1000(struct pci_dev *pdev)
{
	u8 btr;
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	pci_read_config_byte(pdev, 0x5A, &btr);
	btr &= ~0x40;
	btr |= 0x3;
	pci_write_config_byte(pdev, 0x5A, btr);
}


static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[4] = {
		{ /* OSB4 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &serverworks_osb4_port_ops
		}, { /* OSB4 no UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			/* No UDMA */
			.port_ops = &serverworks_osb4_port_ops
		}, { /* CSB5 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &serverworks_csb_port_ops
		}, { /* CSB5 - later revisions*/
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &serverworks_csb_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
	int rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* Force master latency timer to 64 PCI clocks */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);

	/* OSB4 : South Bridge and IDE */
	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		/* Select non UDMA capable OSB4 if we can't do fixups */
		if ( serverworks_fixup_osb4(pdev) < 0)
			ppi[0] = &info[1];
	}
	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		 /* If the returned btr is the newer revision then
		    select the right info block */
		 if (serverworks_fixup_csb(pdev) == 3)
		 	ppi[0] = &info[3];

		/* Is this the 3rd channel CSB6 IDE ? */
		if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
			ppi[1] = &ata_dummy_port_info;
	}
	/* setup HT1000E */
	else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
		serverworks_fixup_ht1000(pdev);

	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
		ata_pci_bmdma_clear_simplex(pdev);

	return ata_pci_bmdma_init_one(pdev, ppi, &serverworks_sht, NULL, 0);
}

#ifdef CONFIG_PM
static int serverworks_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	/* Force master latency timer to 64 PCI clocks */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);

	switch (pdev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
			serverworks_fixup_osb4(pdev);
			break;
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
			ata_pci_bmdma_clear_simplex(pdev);
			/* fall through */
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
			serverworks_fixup_csb(pdev);
			break;
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			serverworks_fixup_ht1000(pdev);
			break;
	}

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id serverworks[] = {
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},

	{ },
};

static struct pci_driver serverworks_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= serverworks,
	.probe 		= serverworks_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= serverworks_reinit_one,
#endif
};

static int __init serverworks_init(void)
{
	return pci_register_driver(&serverworks_pci_driver);
}

static void __exit serverworks_exit(void)
{
	pci_unregister_driver(&serverworks_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, serverworks);
MODULE_VERSION(DRV_VERSION);

module_init(serverworks_init);
module_exit(serverworks_exit);
Commit	Line	Data
669a5db4	1	/*
a0fcdc02	2	* pata_serverworks.c - Serverworks PATA for new ATA layer
669a5db4	3	* (C) 2005 Red Hat Inc
8490377a	4	* (C) 2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	5	*
	6	* based upon
	7	*
	8	* serverworks.c
85cd7251	9	*
669a5db4 JG	10	* Copyright (C) 1998-2000 Michel Aubry
	11	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	12	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	13	* Portions copyright (c) 2001 Sun Microsystems
	14	*
	15	*
	16	* RCC/ServerWorks IDE driver for Linux
	17	*
	18	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	19	* supports UDMA mode 2 (33 MB/s)
	20	*
	21	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	22	* all revisions support UDMA mode 4 (66 MB/s)
	23	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	24	*
	25	* * The CSB5 does not provide ANY register *
	26	* * to detect 80-conductor cable presence. *
	27	*
	28	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	29	*
	30	* Documentation:
	31	* Available under NDA only. Errata info very hard to get.
	32	*/
	33
	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/pci.h>
	37	#include <linux/init.h>
	38	#include <linux/blkdev.h>
	39	#include <linux/delay.h>
	40	#include <scsi/scsi_host.h>
	41	#include <linux/libata.h>
	42
	43	#define DRV_NAME "pata_serverworks"
0f069788	44	#define DRV_VERSION "0.4.3"
669a5db4 JG	45
	46	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	47	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	48
	49	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	50	* can overrun their FIFOs when used with the CSB5 */
	51
	52	static const char *csb_bad_ata100[] = {
	53	"ST320011A",
	54	"ST340016A",
	55	"ST360021A",
	56	"ST380021A",
	57	NULL
	58	};
	59
	60	/**
	61	* dell_cable - Dell serverworks cable detection
	62	* @ap: ATA port to do cable detect
	63	*
	64	* Dell hide the 40/80 pin select for their interfaces in the top two
85cd7251	65	* bits of the subsystem ID.
669a5db4	66	*/
85cd7251	67
669a5db4 JG	68	static int dell_cable(struct ata_port *ap) {
669a5db4 JG	69	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	70
669a5db4 JG	71	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
	72	return ATA_CBL_PATA80;
	73	return ATA_CBL_PATA40;
	74	}
	75
	76	/**
	77	* sun_cable - Sun Cobalt 'Alpine' cable detection
	78	* @ap: ATA port to do cable select
	79	*
	80	* Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
	81	* subsystem ID the same as dell. We could use one function but we may
	82	* need to extend the Dell one in future
	83	*/
85cd7251	84
669a5db4 JG	85	static int sun_cable(struct ata_port *ap) {
669a5db4 JG	86	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	87
669a5db4 JG	88	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
	89	return ATA_CBL_PATA80;
	90	return ATA_CBL_PATA40;
	91	}
	92
	93	/**
	94	* osb4_cable - OSB4 cable detect
	95	* @ap: ATA port to check
	96	*
	97	* The OSB4 isn't UDMA66 capable so this is easy
	98	*/
	99
	100	static int osb4_cable(struct ata_port *ap) {
	101	return ATA_CBL_PATA40;
	102	}
	103
	104	/**
0f069788	105	* csb_cable - CSB5/6 cable detect
669a5db4 JG	106	* @ap: ATA port to check
	107	*
	108	* Serverworks default arrangement is to use the drive side detection
	109	* only.
	110	*/
	111
	112	static int csb_cable(struct ata_port *ap) {
0f069788	113	return ATA_CBL_PATA_UNK;
669a5db4 JG	114	}
	115
	116	struct sv_cable_table {
	117	int device;
	118	int subvendor;
	119	int (cable_detect)(struct ata_port ap);
	120	};
	121
	122	/*
	123	* Note that we don't copy the old serverworks code because the old
	124	* code contains obvious mistakes
	125	*/
85cd7251	126
669a5db4 JG	127	static struct sv_cable_table cable_detect[] = {
	128	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
	129	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
	130	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable },
68d0d7ab	131	{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
669a5db4 JG	132	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
	133	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
	134	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
	135	{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
	136	{ }
	137	};
	138
	139	/**
a0fcdc02	140	* serverworks_cable_detect - cable detection
669a5db4 JG	141	* @ap: ATA port
669a5db4 JG	142	*
85cd7251	143	* Perform cable detection according to the device and subvendor
669a5db4 JG	144	* identifications
669a5db4 JG	145	*/
85cd7251	146
d4b2bab4 TH	147	static int serverworks_cable_detect(struct ata_port *ap)
d4b2bab4 TH	148	{
669a5db4 JG	149	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	150	struct sv_cable_table *cb = cable_detect;
	151
	152	while(cb->device) {
85cd7251	153	if (cb->device == pdev->device &&
669a5db4 JG	154	(cb->subvendor == pdev->subsystem_vendor \|\|
669a5db4 JG	155	cb->subvendor == PCI_ANY_ID)) {
a0fcdc02	156	return cb->cable_detect(ap);
669a5db4 JG	157	}
	158	cb++;
	159	}
	160
	161	BUG();
	162	return -1; /* kill compiler warning */
	163	}
	164
669a5db4 JG	165	/**
	166	* serverworks_is_csb - Check for CSB or OSB
	167	* @pdev: PCI device to check
	168	*
	169	* Returns true if the device being checked is known to be a CSB
	170	* series device.
	171	*/
85cd7251	172
669a5db4 JG	173	static u8 serverworks_is_csb(struct pci_dev *pdev)
	174	{
	175	switch (pdev->device) {
	176	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	177	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	178	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
	179	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
	180	return 1;
	181	default:
	182	break;
	183	}
	184	return 0;
	185	}
	186
	187	/**
	188	* serverworks_osb4_filter - mode selection filter
669a5db4	189	* @adev: ATA device
a76b62ca	190	* @mask: Mask of proposed modes
669a5db4 JG	191	*
	192	* Filter the offered modes for the device to apply controller
	193	* specific rules. OSB4 requires no UDMA for disks due to a FIFO
	194	* bug we hit.
	195	*/
85cd7251	196
a76b62ca	197	static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	198	{
	199	if (adev->class == ATA_DEV_ATA)
	200	mask &= ~ATA_MASK_UDMA;
c7087652	201	return mask;
669a5db4 JG	202	}
	203
	204
	205	/**
	206	* serverworks_csb_filter - mode selection filter
669a5db4	207	* @adev: ATA device
a76b62ca	208	* @mask: Mask of proposed modes
669a5db4 JG	209	*
	210	* Check the blacklist and disable UDMA5 if matched
	211	*/
	212
a76b62ca	213	static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	214	{
669a5db4 JG	215	const char *p;
8bfa79fc TH	216	char model_num[ATA_ID_PROD_LEN + 1];
8bfa79fc TH	217	int i;
669a5db4	218
85cd7251	219	/* Disk, UDMA */
669a5db4	220	if (adev->class != ATA_DEV_ATA)
c7087652	221	return mask;
669a5db4 JG	222
669a5db4 JG	223	/* Actually do need to check */
8bfa79fc	224	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
85cd7251	225
8bfa79fc TH	226	for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
8bfa79fc TH	227	if (!strcmp(p, model_num))
6ddd6861	228	mask &= ~(0xE0 << ATA_SHIFT_UDMA);
669a5db4	229	}
c7087652	230	return mask;
669a5db4 JG	231	}
669a5db4 JG	232
669a5db4 JG	233	/**
	234	* serverworks_set_piomode - set initial PIO mode data
	235	* @ap: ATA interface
	236	* @adev: ATA device
	237	*
	238	* Program the OSB4/CSB5 timing registers for PIO. The PIO register
	239	* load is done as a simple lookup.
	240	*/
	241	static void serverworks_set_piomode(struct ata_port ap, struct ata_device adev)
	242	{
	243	static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
0f069788	244	int offset = 1 + 2 * ap->port_no - adev->devno;
669a5db4 JG	245	int devbits = (2 * ap->port_no + adev->devno) * 4;
	246	u16 csb5_pio;
	247	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	248	int pio = adev->pio_mode - XFER_PIO_0;
	249
	250	pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
85cd7251	251
669a5db4 JG	252	/* The OSB4 just requires the timing but the CSB series want the
	253	mode number as well */
	254	if (serverworks_is_csb(pdev)) {
	255	pci_read_config_word(pdev, 0x4A, &csb5_pio);
	256	csb5_pio &= ~(0x0F << devbits);
8490377a	257	pci_write_config_word(pdev, 0x4A, csb5_pio \| (pio << devbits));
669a5db4 JG	258	}
	259	}
	260
	261	/**
	262	* serverworks_set_dmamode - set initial DMA mode data
	263	* @ap: ATA interface
	264	* @adev: ATA device
	265	*
	266	* Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
	267	* chipset. The MWDMA mode values are pulled from a lookup table
	268	* while the chipset uses mode number for UDMA.
	269	*/
	270
	271	static void serverworks_set_dmamode(struct ata_port ap, struct ata_device adev)
	272	{
	273	static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
	274	int offset = 1 + 2 * ap->port_no - adev->devno;
36beb823	275	int devbits = 2 * ap->port_no + adev->devno;
669a5db4 JG	276	u8 ultra;
	277	u8 ultra_cfg;
	278	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	279
	280	pci_read_config_byte(pdev, 0x54, &ultra_cfg);
36beb823 AC	281	pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
36beb823 AC	282	ultra &= ~(0x0F << (adev->devno * 4));
669a5db4 JG	283
	284	if (adev->dma_mode >= XFER_UDMA_0) {
	285	pci_write_config_byte(pdev, 0x44 + offset, 0x20);
	286
669a5db4	287	ultra \|= (adev->dma_mode - XFER_UDMA_0)
36beb823	288	<< (adev->devno * 4);
669a5db4 JG	289	ultra_cfg \|= (1 << devbits);
669a5db4 JG	290	} else {
85cd7251	291	pci_write_config_byte(pdev, 0x44 + offset,
669a5db4 JG	292	dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
	293	ultra_cfg &= ~(1 << devbits);
	294	}
36beb823	295	pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
669a5db4 JG	296	pci_write_config_byte(pdev, 0x54, ultra_cfg);
	297	}
	298
	299	static struct scsi_host_template serverworks_sht = {
68d1d07b	300	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	301	};
	302
	303	static struct ata_port_operations serverworks_osb4_port_ops = {
029cfd6b TH	304	.inherits = &ata_bmdma_port_ops,
	305	.cable_detect = serverworks_cable_detect,
	306	.mode_filter = serverworks_osb4_filter,
669a5db4 JG	307	.set_piomode = serverworks_set_piomode,
669a5db4 JG	308	.set_dmamode = serverworks_set_dmamode,
85cd7251	309	};
669a5db4 JG	310
669a5db4 JG	311	static struct ata_port_operations serverworks_csb_port_ops = {
029cfd6b	312	.inherits = &serverworks_osb4_port_ops,
669a5db4	313	.mode_filter = serverworks_csb_filter,
85cd7251	314	};
669a5db4 JG	315
	316	static int serverworks_fixup_osb4(struct pci_dev *pdev)
	317	{
	318	u32 reg;
	319	struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	320	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	321	if (isa_dev) {
	322	pci_read_config_dword(isa_dev, 0x64, &reg);
	323	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	324	if (!(reg & 0x00004000))
	325	printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
	326	reg \|= 0x00004000; /* enable UDMA/33 support */
	327	pci_write_config_dword(isa_dev, 0x64, reg);
	328	pci_dev_put(isa_dev);
	329	return 0;
	330	}
cfcf9ee2	331	printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n");
669a5db4 JG	332	return -ENODEV;
	333	}
	334
	335	static int serverworks_fixup_csb(struct pci_dev *pdev)
	336	{
669a5db4	337	u8 btr;
85cd7251	338
669a5db4 JG	339	/* Third Channel Test */
	340	if (!(PCI_FUNC(pdev->devfn) & 1)) {
	341	struct pci_dev * findev = NULL;
	342	u32 reg4c = 0;
	343	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	344	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	345	if (findev) {
	346	pci_read_config_dword(findev, 0x4C, &reg4c);
	347	reg4c &= ~0x000007FF;
	348	reg4c \|= 0x00000040;
	349	reg4c \|= 0x00000020;
	350	pci_write_config_dword(findev, 0x4C, reg4c);
	351	pci_dev_put(findev);
	352	}
	353	} else {
	354	struct pci_dev * findev = NULL;
	355	u8 reg41 = 0;
	356
	357	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	358	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	359	if (findev) {
	360	pci_read_config_byte(findev, 0x41, &reg41);
	361	reg41 &= ~0x40;
	362	pci_write_config_byte(findev, 0x41, reg41);
	363	pci_dev_put(findev);
	364	}
	365	}
	366	/* setup the UDMA Control register
	367	*
	368	* 1. clear bit 6 to enable DMA
	369	* 2. enable DMA modes with bits 0-1
	370	* 00 : legacy
	371	* 01 : udma2
	372	* 10 : udma2/udma4
	373	* 11 : udma2/udma4/udma5
	374	*/
	375	pci_read_config_byte(pdev, 0x5A, &btr);
	376	btr &= ~0x40;
	377	if (!(PCI_FUNC(pdev->devfn) & 1))
	378	btr \|= 0x2;
	379	else
44c10138	380	btr \|= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
669a5db4	381	pci_write_config_byte(pdev, 0x5A, btr);
85cd7251	382
669a5db4 JG	383	return btr;
	384	}
	385
	386	static void serverworks_fixup_ht1000(struct pci_dev *pdev)
	387	{
	388	u8 btr;
	389	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	390	pci_read_config_byte(pdev, 0x5A, &btr);
	391	btr &= ~0x40;
	392	btr \|= 0x3;
	393	pci_write_config_byte(pdev, 0x5A, btr);
	394	}
	395
	396
	397	static int serverworks_init_one(struct pci_dev pdev, const struct pci_device_id id)
	398	{
1626aeb8	399	static const struct ata_port_info info[4] = {
669a5db4	400	{ /* OSB4 */
1d2808fd	401	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	402	.pio_mask = ATA_PIO4,
	403	.mwdma_mask = ATA_MWDMA2,
	404	.udma_mask = ATA_UDMA2,
669a5db4 JG	405	.port_ops = &serverworks_osb4_port_ops
669a5db4 JG	406	}, { /* OSB4 no UDMA */
1d2808fd	407	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	408	.pio_mask = ATA_PIO4,
	409	.mwdma_mask = ATA_MWDMA2,
	410	/* No UDMA */
669a5db4 JG	411	.port_ops = &serverworks_osb4_port_ops
669a5db4 JG	412	}, { /* CSB5 */
1d2808fd	413	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	414	.pio_mask = ATA_PIO4,
14bdef98 EIB	415	.mwdma_mask = ATA_MWDMA2,
bf6263a8	416	.udma_mask = ATA_UDMA4,
669a5db4 JG	417	.port_ops = &serverworks_csb_port_ops
669a5db4 JG	418	}, { /* CSB5 - later revisions*/
1d2808fd	419	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	420	.pio_mask = ATA_PIO4,
14bdef98 EIB	421	.mwdma_mask = ATA_MWDMA2,
bf6263a8	422	.udma_mask = ATA_UDMA5,
669a5db4 JG	423	.port_ops = &serverworks_csb_port_ops
	424	}
	425	};
1626aeb8	426	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
f08048e9 TH	427	int rc;
	428
	429	rc = pcim_enable_device(pdev);
	430	if (rc)
	431	return rc;
85cd7251	432
669a5db4 JG	433	/* Force master latency timer to 64 PCI clocks */
	434	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
	435
	436	/* OSB4 : South Bridge and IDE */
	437	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
	438	/* Select non UDMA capable OSB4 if we can't do fixups */
	439	if ( serverworks_fixup_osb4(pdev) < 0)
1626aeb8	440	ppi[0] = &info[1];
669a5db4 JG	441	}
	442	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	443	else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	444	(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	445	(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
85cd7251	446
669a5db4 JG	447	/* If the returned btr is the newer revision then
	448	select the right info block */
	449	if (serverworks_fixup_csb(pdev) == 3)
1626aeb8	450	ppi[0] = &info[3];
85cd7251	451
669a5db4 JG	452	/* Is this the 3rd channel CSB6 IDE ? */
669a5db4 JG	453	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
1626aeb8	454	ppi[1] = &ata_dummy_port_info;
669a5db4 JG	455	}
	456	/* setup HT1000E */
	457	else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
	458	serverworks_fixup_ht1000(pdev);
85cd7251	459
669a5db4	460	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
9363c382	461	ata_pci_bmdma_clear_simplex(pdev);
85cd7251	462
1c5afdf7	463	return ata_pci_bmdma_init_one(pdev, ppi, &serverworks_sht, NULL, 0);
669a5db4 JG	464	}
669a5db4 JG	465
438ac6d5	466	#ifdef CONFIG_PM
38e0d56e AC	467	static int serverworks_reinit_one(struct pci_dev *pdev)
38e0d56e AC	468	{
f08048e9 TH	469	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	470	int rc;
	471
	472	rc = ata_pci_device_do_resume(pdev);
	473	if (rc)
	474	return rc;
	475
38e0d56e AC	476	/* Force master latency timer to 64 PCI clocks */
38e0d56e AC	477	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
f20b16ff	478
f08048e9	479	switch (pdev->device) {
38e0d56e AC	480	case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
	481	serverworks_fixup_osb4(pdev);
	482	break;
	483	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
9363c382	484	ata_pci_bmdma_clear_simplex(pdev);
38e0d56e AC	485	/* fall through */
	486	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	487	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
	488	serverworks_fixup_csb(pdev);
	489	break;
	490	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
	491	serverworks_fixup_ht1000(pdev);
	492	break;
	493	}
f08048e9 TH	494
	495	ata_host_resume(host);
	496	return 0;
38e0d56e	497	}
438ac6d5	498	#endif
38e0d56e	499
2d2744fc JG	500	static const struct pci_device_id serverworks[] = {
	501	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
	502	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
	503	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
	504	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
	505	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
	506
	507	{ },
669a5db4 JG	508	};
	509
	510	static struct pci_driver serverworks_pci_driver = {
	511	.name = DRV_NAME,
	512	.id_table = serverworks,
	513	.probe = serverworks_init_one,
38e0d56e	514	.remove = ata_pci_remove_one,
438ac6d5	515	#ifdef CONFIG_PM
38e0d56e AC	516	.suspend = ata_pci_device_suspend,
38e0d56e AC	517	.resume = serverworks_reinit_one,
438ac6d5	518	#endif
669a5db4 JG	519	};
	520
	521	static int __init serverworks_init(void)
	522	{
	523	return pci_register_driver(&serverworks_pci_driver);
	524	}
	525
669a5db4 JG	526	static void __exit serverworks_exit(void)
	527	{
	528	pci_unregister_driver(&serverworks_pci_driver);
	529	}
	530
669a5db4 JG	531	MODULE_AUTHOR("Alan Cox");
	532	MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
	533	MODULE_LICENSE("GPL");
	534	MODULE_DEVICE_TABLE(pci, serverworks);
	535	MODULE_VERSION(DRV_VERSION);
	536
	537	module_init(serverworks_init);
	538	module_exit(serverworks_exit);