[net-next-2.6.git] / drivers / ata / pata_hpt366.c

/*
 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
 *
 * This driver is heavily based upon:
 *
 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
 *
 *
 * TODO
 *	Look into engine reset on timeout errors. Should not be required.
 */


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt366"
#define DRV_VERSION	"0.6.8"

struct hpt_clock {
	u8	xfer_mode;
	u32	timing;
};

/* key for bus clock timings
 * bit
 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *        register access.
 * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *        register access.
 * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
 * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
 * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
 *        register access.
 * 28     UDMA enable.
 * 29     DMA  enable.
 * 30     PIO_MST enable. If set, the chip is in bus master mode during
 *        PIO xfer.
 * 31     FIFO enable.
 */

static const struct hpt_clock hpt366_40[] = {
	{	XFER_UDMA_4,	0x900fd943	},
	{	XFER_UDMA_3,	0x900ad943	},
	{	XFER_UDMA_2,	0x900bd943	},
	{	XFER_UDMA_1,	0x9008d943	},
	{	XFER_UDMA_0,	0x9008d943	},

	{	XFER_MW_DMA_2,	0xa008d943	},
	{	XFER_MW_DMA_1,	0xa010d955	},
	{	XFER_MW_DMA_0,	0xa010d9fc	},

	{	XFER_PIO_4,	0xc008d963	},
	{	XFER_PIO_3,	0xc010d974	},
	{	XFER_PIO_2,	0xc010d997	},
	{	XFER_PIO_1,	0xc010d9c7	},
	{	XFER_PIO_0,	0xc018d9d9	},
	{	0,		0x0120d9d9	}
};

static const struct hpt_clock hpt366_33[] = {
	{	XFER_UDMA_4,	0x90c9a731	},
	{	XFER_UDMA_3,	0x90cfa731	},
	{	XFER_UDMA_2,	0x90caa731	},
	{	XFER_UDMA_1,	0x90cba731	},
	{	XFER_UDMA_0,	0x90c8a731	},

	{	XFER_MW_DMA_2,	0xa0c8a731	},
	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
	{	XFER_MW_DMA_0,	0xa0c8a797	},

	{	XFER_PIO_4,	0xc0c8a731	},
	{	XFER_PIO_3,	0xc0c8a742	},
	{	XFER_PIO_2,	0xc0d0a753	},
	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
	{	0,		0x0120a7a7	}
};

static const struct hpt_clock hpt366_25[] = {
	{	XFER_UDMA_4,	0x90c98521	},
	{	XFER_UDMA_3,	0x90cf8521	},
	{	XFER_UDMA_2,	0x90cf8521	},
	{	XFER_UDMA_1,	0x90cb8521	},
	{	XFER_UDMA_0,	0x90cb8521	},

	{	XFER_MW_DMA_2,	0xa0ca8521	},
	{	XFER_MW_DMA_1,	0xa0ca8532	},
	{	XFER_MW_DMA_0,	0xa0ca8575	},

	{	XFER_PIO_4,	0xc0ca8521	},
	{	XFER_PIO_3,	0xc0ca8532	},
	{	XFER_PIO_2,	0xc0ca8542	},
	{	XFER_PIO_1,	0xc0d08572	},
	{	XFER_PIO_0,	0xc0d08585	},
	{	0,		0x01208585	}
};

static const char *bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

static const char *bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
{
	unsigned char model_num[ATA_ID_PROD_LEN + 1];
	int i = 0;

	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	while (list[i] != NULL) {
		if (!strcmp(list[i], model_num)) {
			printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
				modestr, list[i]);
			return 1;
		}
		i++;
	}
	return 0;
}

/**
 *	hpt366_filter	-	mode selection filter
 *	@adev: ATA device
 *
 *	Block UDMA on devices that cause trouble with this controller.
 */

static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA) {
		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
			mask &= ~ATA_MASK_UDMA;
		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
	} else if (adev->class == ATA_DEV_ATAPI)
		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);

	return mask;
}

static int hpt36x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	/*
	 * Each channel of pata_hpt366 occupies separate PCI function
	 * as the primary channel and bit1 indicates the cable type.
	 */
	pci_read_config_byte(pdev, 0x5A, &ata66);
	if (ata66 & 2)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
			    u8 mode)
{
	struct hpt_clock *clocks = ap->host->private_data;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr = 0x40 + 4 * adev->devno;
	u32 mask, reg;

	/* determine timing mask and find matching clock entry */
	if (mode < XFER_MW_DMA_0)
		mask = 0xc1f8ffff;
	else if (mode < XFER_UDMA_0)
		mask = 0x303800ff;
	else
		mask = 0x30070000;

	while (clocks->xfer_mode) {
		if (clocks->xfer_mode == mode)
			break;
		clocks++;
	}
	if (!clocks->xfer_mode)
		BUG();

	/*
	 * Combine new mode bits with old config bits and disable
	 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	 * problems handling I/O errors later.
	 */
	pci_read_config_dword(pdev, addr, &reg);
	reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
	pci_write_config_dword(pdev, addr, reg);
}

/**
 *	hpt366_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Perform PIO mode setup.
 */

static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->pio_mode);
}

/**
 *	hpt366_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 */

static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->dma_mode);
}

static struct scsi_host_template hpt36x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

/*
 *	Configuration for HPT366/68
 */

static struct ata_port_operations hpt366_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= hpt36x_cable_detect,
	.mode_filter	= hpt366_filter,
	.set_piomode	= hpt366_set_piomode,
	.set_dmamode	= hpt366_set_dmamode,
};

/**
 *	hpt36x_init_chipset	-	common chip setup
 *	@dev: PCI device
 *
 *	Perform the chip setup work that must be done at both init and
 *	resume time
 */

static void hpt36x_init_chipset(struct pci_dev *dev)
{
	u8 drive_fast;
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	pci_read_config_byte(dev, 0x51, &drive_fast);
	if (drive_fast & 0x80)
		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
}

/**
 *	hpt36x_init_one		-	Initialise an HPT366/368
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Initialise an HPT36x device. There are some interesting complications
 *	here. Firstly the chip may report 366 and be one of several variants.
 *	Secondly all the timings depend on the clock for the chip which we must
 *	detect and look up
 *
 *	This is the known chip mappings. It may be missing a couple of later
 *	releases.
 *
 *	Chip version		PCI		Rev	Notes
 *	HPT366			4 (HPT366)	0	UDMA66
 *	HPT366			4 (HPT366)	1	UDMA66
 *	HPT368			4 (HPT366)	2	UDMA66
 *	HPT37x/30x		4 (HPT366)	3+	Other driver
 *
 */

static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_hpt366 = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA4,
		.port_ops = &hpt366_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };

	void *hpriv = NULL;
	u32 reg1;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	/* May be a later chip in disguise. Check */
	/* Newer chips are not in the HPT36x driver. Ignore them */
	if (dev->revision > 2)
		return -ENODEV;

	hpt36x_init_chipset(dev);

	pci_read_config_dword(dev, 0x40,  &reg1);

	/* PCI clocking determines the ATA timing values to use */
	/* info_hpt366 is safe against re-entry so we can scribble on it */
	switch((reg1 & 0x700) >> 8) {
		case 9:
			hpriv = &hpt366_40;
			break;
		case 5:
			hpriv = &hpt366_25;
			break;
		default:
			hpriv = &hpt366_33;
			break;
	}
	/* Now kick off ATA set up */
	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
}

#ifdef CONFIG_PM
static int hpt36x_reinit_one(struct pci_dev *dev)
{
	struct ata_host *host = dev_get_drvdata(&dev->dev);
	int rc;

	rc = ata_pci_device_do_resume(dev);
	if (rc)
		return rc;
	hpt36x_init_chipset(dev);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id hpt36x[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
	{ },
};

static struct pci_driver hpt36x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= hpt36x,
	.probe 		= hpt36x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt36x_reinit_one,
#endif
};

static int __init hpt36x_init(void)
{
	return pci_register_driver(&hpt36x_pci_driver);
}

static void __exit hpt36x_exit(void)
{
	pci_unregister_driver(&hpt36x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt36x);
MODULE_VERSION(DRV_VERSION);

module_init(hpt36x_init);
module_exit(hpt36x_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
	3	*
	4	* This driver is heavily based upon:
	5	*
	6	* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
	7	*
	8	* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
	9	* Portions Copyright (C) 2001 Sun Microsystems, Inc.
	10	* Portions Copyright (C) 2003 Red Hat Inc
	11	*
	12	*
	13	* TODO
d817898c	14	* Look into engine reset on timeout errors. Should not be required.
669a5db4 JG	15	*/
	16
	17
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/pci.h>
	21	#include <linux/init.h>
	22	#include <linux/blkdev.h>
	23	#include <linux/delay.h>
	24	#include <scsi/scsi_host.h>
	25	#include <linux/libata.h>
	26
	27	#define DRV_NAME "pata_hpt366"
859faa87	28	#define DRV_VERSION "0.6.8"
669a5db4 JG	29
669a5db4 JG	30	struct hpt_clock {
6ecb6f25	31	u8 xfer_mode;
669a5db4 JG	32	u32 timing;
	33	};
	34
	35	/* key for bus clock timings
	36	* bit
82beb5d8 SS	37	* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
	38	* cycles = value + 1
	39	* 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
	40	* cycles = value + 1
	41	* 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
669a5db4	42	* register access.
82beb5d8	43	* 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
669a5db4	44	* register access.
82beb5d8 SS	45	* 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
	46	* 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
	47	* 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
669a5db4	48	* register access.
82beb5d8 SS	49	* 28 UDMA enable.
	50	* 29 DMA enable.
	51	* 30 PIO_MST enable. If set, the chip is in bus master mode during
	52	* PIO xfer.
669a5db4 JG	53	* 31 FIFO enable.
	54	*/
	55
	56	static const struct hpt_clock hpt366_40[] = {
	57	{ XFER_UDMA_4, 0x900fd943 },
	58	{ XFER_UDMA_3, 0x900ad943 },
	59	{ XFER_UDMA_2, 0x900bd943 },
	60	{ XFER_UDMA_1, 0x9008d943 },
	61	{ XFER_UDMA_0, 0x9008d943 },
	62
	63	{ XFER_MW_DMA_2, 0xa008d943 },
	64	{ XFER_MW_DMA_1, 0xa010d955 },
	65	{ XFER_MW_DMA_0, 0xa010d9fc },
	66
	67	{ XFER_PIO_4, 0xc008d963 },
	68	{ XFER_PIO_3, 0xc010d974 },
	69	{ XFER_PIO_2, 0xc010d997 },
	70	{ XFER_PIO_1, 0xc010d9c7 },
	71	{ XFER_PIO_0, 0xc018d9d9 },
	72	{ 0, 0x0120d9d9 }
	73	};
	74
	75	static const struct hpt_clock hpt366_33[] = {
	76	{ XFER_UDMA_4, 0x90c9a731 },
	77	{ XFER_UDMA_3, 0x90cfa731 },
	78	{ XFER_UDMA_2, 0x90caa731 },
	79	{ XFER_UDMA_1, 0x90cba731 },
	80	{ XFER_UDMA_0, 0x90c8a731 },
	81
	82	{ XFER_MW_DMA_2, 0xa0c8a731 },
	83	{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
	84	{ XFER_MW_DMA_0, 0xa0c8a797 },
	85
	86	{ XFER_PIO_4, 0xc0c8a731 },
	87	{ XFER_PIO_3, 0xc0c8a742 },
	88	{ XFER_PIO_2, 0xc0d0a753 },
	89	{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
	90	{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
	91	{ 0, 0x0120a7a7 }
	92	};
	93
	94	static const struct hpt_clock hpt366_25[] = {
	95	{ XFER_UDMA_4, 0x90c98521 },
	96	{ XFER_UDMA_3, 0x90cf8521 },
	97	{ XFER_UDMA_2, 0x90cf8521 },
	98	{ XFER_UDMA_1, 0x90cb8521 },
	99	{ XFER_UDMA_0, 0x90cb8521 },
	100
	101	{ XFER_MW_DMA_2, 0xa0ca8521 },
	102	{ XFER_MW_DMA_1, 0xa0ca8532 },
	103	{ XFER_MW_DMA_0, 0xa0ca8575 },
	104
	105	{ XFER_PIO_4, 0xc0ca8521 },
	106	{ XFER_PIO_3, 0xc0ca8532 },
	107	{ XFER_PIO_2, 0xc0ca8542 },
	108	{ XFER_PIO_1, 0xc0d08572 },
	109	{ XFER_PIO_0, 0xc0d08585 },
	110	{ 0, 0x01208585 }
	111	};
	112
	113	static const char *bad_ata33[] = {
	114	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	115	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	116	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
117	"Maxtor 90510D4",
118	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
119	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
120	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
121	NULL
122	};
123
124	static const char *bad_ata66_4[] = {
125	"IBM-DTLA-307075",
126	"IBM-DTLA-307060",
127	"IBM-DTLA-307045",
128	"IBM-DTLA-307030",
129	"IBM-DTLA-307020",
130	"IBM-DTLA-307015",
131	"IBM-DTLA-305040",
132	"IBM-DTLA-305030",
133	"IBM-DTLA-305020",
134	"IC35L010AVER07-0",
135	"IC35L020AVER07-0",
136	"IC35L030AVER07-0",
137	"IC35L040AVER07-0",
138	"IC35L060AVER07-0",
139	"WDC AC310200R",
140	NULL
141	};
142
143	static const char *bad_ata66_3[] = {
144	"WDC AC310200R",
145	NULL
146	};
147
148	static int hpt_dma_blacklisted(const struct ata_device dev, char modestr, const char *list[])
149	{
8bfa79fc	150	unsigned char model_num[ATA_ID_PROD_LEN + 1];
669a5db4 JG	151	int i = 0;
669a5db4 JG	152
8bfa79fc	153	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
669a5db4	154
8bfa79fc TH	155	while (list[i] != NULL) {
8bfa79fc TH	156	if (!strcmp(list[i], model_num)) {
85cd7251	157	printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
669a5db4 JG	158	modestr, list[i]);
	159	return 1;
	160	}
	161	i++;
	162	}
	163	return 0;
	164	}
	165
	166	/**
	167	* hpt366_filter - mode selection filter
669a5db4 JG	168	* @adev: ATA device
	169	*
	170	* Block UDMA on devices that cause trouble with this controller.
	171	*/
85cd7251	172
a76b62ca	173	static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	174	{
	175	if (adev->class == ATA_DEV_ATA) {
	176	if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
	177	mask &= ~ATA_MASK_UDMA;
	178	if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
6ddd6861	179	mask &= ~(0xF8 << ATA_SHIFT_UDMA);
669a5db4	180	if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
6ddd6861	181	mask &= ~(0xF0 << ATA_SHIFT_UDMA);
3ee89f17 TH	182	} else if (adev->class == ATA_DEV_ATAPI)
	183	mask &= ~(ATA_MASK_MWDMA \| ATA_MASK_UDMA);
	184
c7087652	185	return mask;
669a5db4 JG	186	}
669a5db4 JG	187
fecfda5d AC	188	static int hpt36x_cable_detect(struct ata_port *ap)
fecfda5d AC	189	{
fecfda5d	190	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
bab5b32a	191	u8 ata66;
fecfda5d	192
bab5b32a TH	193	/*
	194	* Each channel of pata_hpt366 occupies separate PCI function
	195	* as the primary channel and bit1 indicates the cable type.
	196	*/
fecfda5d	197	pci_read_config_byte(pdev, 0x5A, &ata66);
bab5b32a	198	if (ata66 & 2)
fecfda5d AC	199	return ATA_CBL_PATA40;
	200	return ATA_CBL_PATA80;
	201	}
	202
6ecb6f25 TH	203	static void hpt366_set_mode(struct ata_port ap, struct ata_device adev,
6ecb6f25 TH	204	u8 mode)
669a5db4	205	{
6ecb6f25	206	struct hpt_clock *clocks = ap->host->private_data;
669a5db4	207	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
859faa87	208	u32 addr = 0x40 + 4 * adev->devno;
6ecb6f25	209	u32 mask, reg;
85cd7251	210
6ecb6f25 TH	211	/* determine timing mask and find matching clock entry */
	212	if (mode < XFER_MW_DMA_0)
	213	mask = 0xc1f8ffff;
	214	else if (mode < XFER_UDMA_0)
	215	mask = 0x303800ff;
	216	else
	217	mask = 0x30070000;
	218
	219	while (clocks->xfer_mode) {
	220	if (clocks->xfer_mode == mode)
	221	break;
	222	clocks++;
	223	}
	224	if (!clocks->xfer_mode)
	225	BUG();
	226
	227	/*
	228	* Combine new mode bits with old config bits and disable
	229	* on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	230	* problems handling I/O errors later.
	231	*/
859faa87	232	pci_read_config_dword(pdev, addr, &reg);
6ecb6f25	233	reg = ((reg & ~mask) \| (clocks->timing & mask)) & ~0xc0000000;
859faa87	234	pci_write_config_dword(pdev, addr, reg);
6ecb6f25 TH	235	}
	236
	237	/**
	238	* hpt366_set_piomode - PIO setup
	239	* @ap: ATA interface
	240	* @adev: device on the interface
	241	*
	242	* Perform PIO mode setup.
	243	*/
	244
	245	static void hpt366_set_piomode(struct ata_port ap, struct ata_device adev)
	246	{
	247	hpt366_set_mode(ap, adev, adev->pio_mode);
669a5db4 JG	248	}
	249
	250	/**
	251	* hpt366_set_dmamode - DMA timing setup
	252	* @ap: ATA interface
	253	* @adev: Device being configured
	254	*
	255	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	256	* PIO, load the mode number and then set MWDMA or UDMA flag.
	257	*/
85cd7251	258
669a5db4 JG	259	static void hpt366_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	260	{
6ecb6f25	261	hpt366_set_mode(ap, adev, adev->dma_mode);
669a5db4 JG	262	}
	263
	264	static struct scsi_host_template hpt36x_sht = {
68d1d07b	265	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	266	};
	267
	268	/*
	269	* Configuration for HPT366/68
	270	*/
85cd7251	271
669a5db4	272	static struct ata_port_operations hpt366_port_ops = {
029cfd6b TH	273	.inherits = &ata_bmdma_port_ops,
	274	.cable_detect = hpt36x_cable_detect,
	275	.mode_filter = hpt366_filter,
669a5db4 JG	276	.set_piomode = hpt366_set_piomode,
669a5db4 JG	277	.set_dmamode = hpt366_set_dmamode,
85cd7251	278	};
669a5db4	279
aa54ab1e AC	280	/**
	281	* hpt36x_init_chipset - common chip setup
	282	* @dev: PCI device
	283	*
	284	* Perform the chip setup work that must be done at both init and
	285	* resume time
	286	*/
	287
	288	static void hpt36x_init_chipset(struct pci_dev *dev)
	289	{
	290	u8 drive_fast;
	291	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	292	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	293	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	294	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
	295
	296	pci_read_config_byte(dev, 0x51, &drive_fast);
	297	if (drive_fast & 0x80)
	298	pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
	299	}
	300
669a5db4 JG	301	/**
	302	* hpt36x_init_one - Initialise an HPT366/368
	303	* @dev: PCI device
	304	* @id: Entry in match table
	305	*
	306	* Initialise an HPT36x device. There are some interesting complications
	307	* here. Firstly the chip may report 366 and be one of several variants.
	308	* Secondly all the timings depend on the clock for the chip which we must
	309	* detect and look up
	310	*
	311	* This is the known chip mappings. It may be missing a couple of later
	312	* releases.
	313	*
	314	* Chip version PCI Rev Notes
	315	* HPT366 4 (HPT366) 0 UDMA66
	316	* HPT366 4 (HPT366) 1 UDMA66
	317	* HPT368 4 (HPT366) 2 UDMA66
	318	* HPT37x/30x 4 (HPT366) 3+ Other driver
	319	*
	320	*/
85cd7251	321
669a5db4 JG	322	static int hpt36x_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	323	{
1626aeb8	324	static const struct ata_port_info info_hpt366 = {
1d2808fd	325	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	326	.pio_mask = ATA_PIO4,
14bdef98 EIB	327	.mwdma_mask = ATA_MWDMA2,
bf6263a8	328	.udma_mask = ATA_UDMA4,
669a5db4 JG	329	.port_ops = &hpt366_port_ops
669a5db4 JG	330	};
887125e3	331	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
669a5db4	332
887125e3	333	void *hpriv = NULL;
669a5db4	334	u32 reg1;
f08048e9 TH	335	int rc;
	336
	337	rc = pcim_enable_device(dev);
	338	if (rc)
	339	return rc;
669a5db4	340
669a5db4 JG	341	/* May be a later chip in disguise. Check */
669a5db4 JG	342	/* Newer chips are not in the HPT36x driver. Ignore them */
89d3b360 SS	343	if (dev->revision > 2)
89d3b360 SS	344	return -ENODEV;
669a5db4	345
aa54ab1e	346	hpt36x_init_chipset(dev);
669a5db4 JG	347
669a5db4 JG	348	pci_read_config_dword(dev, 0x40, &reg1);
85cd7251	349
669a5db4 JG	350	/* PCI clocking determines the ATA timing values to use */
669a5db4 JG	351	/* info_hpt366 is safe against re-entry so we can scribble on it */
2c136efc	352	switch((reg1 & 0x700) >> 8) {
2456eb81	353	case 9:
887125e3	354	hpriv = &hpt366_40;
669a5db4	355	break;
2456eb81	356	case 5:
887125e3	357	hpriv = &hpt366_25;
669a5db4 JG	358	break;
669a5db4 JG	359	default:
887125e3	360	hpriv = &hpt366_33;
669a5db4 JG	361	break;
	362	}
	363	/* Now kick off ATA set up */
1c5afdf7	364	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
669a5db4 JG	365	}
669a5db4 JG	366
438ac6d5	367	#ifdef CONFIG_PM
aa54ab1e AC	368	static int hpt36x_reinit_one(struct pci_dev *dev)
aa54ab1e AC	369	{
f08048e9 TH	370	struct ata_host *host = dev_get_drvdata(&dev->dev);
	371	int rc;
	372
	373	rc = ata_pci_device_do_resume(dev);
	374	if (rc)
	375	return rc;
aa54ab1e	376	hpt36x_init_chipset(dev);
f08048e9 TH	377	ata_host_resume(host);
f08048e9 TH	378	return 0;
aa54ab1e	379	}
438ac6d5	380	#endif
aa54ab1e	381
2d2744fc JG	382	static const struct pci_device_id hpt36x[] = {
2d2744fc JG	383	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
2d2744fc	384	{ },
669a5db4 JG	385	};
	386
	387	static struct pci_driver hpt36x_pci_driver = {
2d2744fc	388	.name = DRV_NAME,
669a5db4 JG	389	.id_table = hpt36x,
669a5db4 JG	390	.probe = hpt36x_init_one,
aa54ab1e	391	.remove = ata_pci_remove_one,
438ac6d5	392	#ifdef CONFIG_PM
aa54ab1e AC	393	.suspend = ata_pci_device_suspend,
aa54ab1e AC	394	.resume = hpt36x_reinit_one,
438ac6d5	395	#endif
669a5db4 JG	396	};
	397
	398	static int __init hpt36x_init(void)
	399	{
	400	return pci_register_driver(&hpt36x_pci_driver);
	401	}
	402
669a5db4 JG	403	static void __exit hpt36x_exit(void)
	404	{
	405	pci_unregister_driver(&hpt36x_pci_driver);
	406	}
	407
669a5db4 JG	408	MODULE_AUTHOR("Alan Cox");
	409	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
	410	MODULE_LICENSE("GPL");
	411	MODULE_DEVICE_TABLE(pci, hpt36x);
	412	MODULE_VERSION(DRV_VERSION);
	413
	414	module_init(hpt36x_init);
	415	module_exit(hpt36x_exit);