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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
38 | ||
39 | #include "libata.h" | |
40 | ||
90088bb4 TH |
41 | /** |
42 | * ata_irq_on - Enable interrupts on a port. | |
43 | * @ap: Port on which interrupts are enabled. | |
44 | * | |
45 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
46 | * wait for idle, clear any pending interrupts. | |
47 | * | |
48 | * LOCKING: | |
49 | * Inherited from caller. | |
50 | */ | |
51 | u8 ata_irq_on(struct ata_port *ap) | |
52 | { | |
53 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
54 | u8 tmp; | |
55 | ||
56 | ap->ctl &= ~ATA_NIEN; | |
57 | ap->last_ctl = ap->ctl; | |
58 | ||
f659f0e4 TH |
59 | if (ioaddr->ctl_addr) |
60 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
90088bb4 TH |
61 | tmp = ata_wait_idle(ap); |
62 | ||
63 | ap->ops->irq_clear(ap); | |
64 | ||
65 | return tmp; | |
66 | } | |
67 | ||
1fdffbce | 68 | /** |
0d5ff566 | 69 | * ata_tf_load - send taskfile registers to host controller |
1fdffbce JG |
70 | * @ap: Port to which output is sent |
71 | * @tf: ATA taskfile register set | |
72 | * | |
73 | * Outputs ATA taskfile to standard ATA host controller. | |
74 | * | |
75 | * LOCKING: | |
76 | * Inherited from caller. | |
77 | */ | |
78 | ||
0d5ff566 | 79 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce JG |
80 | { |
81 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
82 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
83 | ||
84 | if (tf->ctl != ap->last_ctl) { | |
f659f0e4 TH |
85 | if (ioaddr->ctl_addr) |
86 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
1fdffbce JG |
87 | ap->last_ctl = tf->ctl; |
88 | ata_wait_idle(ap); | |
89 | } | |
90 | ||
91 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
f659f0e4 | 92 | WARN_ON(!ioaddr->ctl_addr); |
0d5ff566 TH |
93 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
94 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
95 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
96 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
97 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
98 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", |
99 | tf->hob_feature, | |
100 | tf->hob_nsect, | |
101 | tf->hob_lbal, | |
102 | tf->hob_lbam, | |
103 | tf->hob_lbah); | |
104 | } | |
105 | ||
106 | if (is_addr) { | |
0d5ff566 TH |
107 | iowrite8(tf->feature, ioaddr->feature_addr); |
108 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
109 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
110 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
111 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
1fdffbce JG |
112 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", |
113 | tf->feature, | |
114 | tf->nsect, | |
115 | tf->lbal, | |
116 | tf->lbam, | |
117 | tf->lbah); | |
118 | } | |
119 | ||
120 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
0d5ff566 | 121 | iowrite8(tf->device, ioaddr->device_addr); |
1fdffbce JG |
122 | VPRINTK("device 0x%X\n", tf->device); |
123 | } | |
124 | ||
125 | ata_wait_idle(ap); | |
126 | } | |
127 | ||
1fdffbce | 128 | /** |
0d5ff566 | 129 | * ata_exec_command - issue ATA command to host controller |
1fdffbce JG |
130 | * @ap: port to which command is being issued |
131 | * @tf: ATA taskfile register set | |
132 | * | |
0d5ff566 TH |
133 | * Issues ATA command, with proper synchronization with interrupt |
134 | * handler / other threads. | |
7c74ffd0 | 135 | * |
1fdffbce | 136 | * LOCKING: |
cca3974e | 137 | * spin_lock_irqsave(host lock) |
1fdffbce | 138 | */ |
0d5ff566 | 139 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
1fdffbce | 140 | { |
44877b4e | 141 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); |
1fdffbce | 142 | |
0d5ff566 | 143 | iowrite8(tf->command, ap->ioaddr.command_addr); |
1fdffbce JG |
144 | ata_pause(ap); |
145 | } | |
146 | ||
1fdffbce | 147 | /** |
0d5ff566 | 148 | * ata_tf_read - input device's ATA taskfile shadow registers |
1fdffbce JG |
149 | * @ap: Port from which input is read |
150 | * @tf: ATA taskfile register set for storing input | |
151 | * | |
152 | * Reads ATA taskfile registers for currently-selected device | |
76548eda AC |
153 | * into @tf. Assumes the device has a fully SFF compliant task file |
154 | * layout and behaviour. If you device does not (eg has a different | |
155 | * status method) then you will need to provide a replacement tf_read | |
1fdffbce JG |
156 | * |
157 | * LOCKING: | |
158 | * Inherited from caller. | |
159 | */ | |
0d5ff566 | 160 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1fdffbce JG |
161 | { |
162 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
163 | ||
76548eda | 164 | tf->command = ata_check_status(ap); |
0d5ff566 TH |
165 | tf->feature = ioread8(ioaddr->error_addr); |
166 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
167 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
168 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
169 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
170 | tf->device = ioread8(ioaddr->device_addr); | |
1fdffbce JG |
171 | |
172 | if (tf->flags & ATA_TFLAG_LBA48) { | |
f659f0e4 TH |
173 | if (likely(ioaddr->ctl_addr)) { |
174 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
175 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
176 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
177 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
178 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
179 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
180 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
181 | ap->last_ctl = tf->ctl; | |
182 | } else | |
183 | WARN_ON(1); | |
1fdffbce JG |
184 | } |
185 | } | |
186 | ||
1fdffbce JG |
187 | /** |
188 | * ata_check_status - Read device status reg & clear interrupt | |
189 | * @ap: port where the device is | |
190 | * | |
191 | * Reads ATA taskfile status register for currently-selected device | |
192 | * and return its value. This also clears pending interrupts | |
193 | * from this device | |
194 | * | |
1fdffbce JG |
195 | * LOCKING: |
196 | * Inherited from caller. | |
197 | */ | |
198 | u8 ata_check_status(struct ata_port *ap) | |
199 | { | |
0d5ff566 | 200 | return ioread8(ap->ioaddr.status_addr); |
1fdffbce JG |
201 | } |
202 | ||
1fdffbce JG |
203 | /** |
204 | * ata_altstatus - Read device alternate status reg | |
205 | * @ap: port where the device is | |
206 | * | |
207 | * Reads ATA taskfile alternate status register for | |
208 | * currently-selected device and return its value. | |
209 | * | |
210 | * Note: may NOT be used as the check_altstatus() entry in | |
211 | * ata_port_operations. | |
212 | * | |
213 | * LOCKING: | |
214 | * Inherited from caller. | |
215 | */ | |
216 | u8 ata_altstatus(struct ata_port *ap) | |
217 | { | |
218 | if (ap->ops->check_altstatus) | |
219 | return ap->ops->check_altstatus(ap); | |
220 | ||
0d5ff566 | 221 | return ioread8(ap->ioaddr.altstatus_addr); |
1fdffbce JG |
222 | } |
223 | ||
2cc432ee | 224 | /** |
0d5ff566 | 225 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction |
2cc432ee JG |
226 | * @qc: Info associated with this ATA transaction. |
227 | * | |
228 | * LOCKING: | |
cca3974e | 229 | * spin_lock_irqsave(host lock) |
2cc432ee | 230 | */ |
0d5ff566 | 231 | void ata_bmdma_setup(struct ata_queued_cmd *qc) |
2cc432ee JG |
232 | { |
233 | struct ata_port *ap = qc->ap; | |
234 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
235 | u8 dmactl; | |
2cc432ee JG |
236 | |
237 | /* load PRD table addr. */ | |
238 | mb(); /* make sure PRD table writes are visible to controller */ | |
0d5ff566 | 239 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
2cc432ee JG |
240 | |
241 | /* specify data direction, triple-check start bit is clear */ | |
0d5ff566 | 242 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
2cc432ee JG |
243 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
244 | if (!rw) | |
245 | dmactl |= ATA_DMA_WR; | |
0d5ff566 | 246 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
2cc432ee JG |
247 | |
248 | /* issue r/w command */ | |
249 | ap->ops->exec_command(ap, &qc->tf); | |
250 | } | |
251 | ||
252 | /** | |
0d5ff566 | 253 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction |
2cc432ee JG |
254 | * @qc: Info associated with this ATA transaction. |
255 | * | |
256 | * LOCKING: | |
cca3974e | 257 | * spin_lock_irqsave(host lock) |
2cc432ee | 258 | */ |
2dcb407e | 259 | void ata_bmdma_start(struct ata_queued_cmd *qc) |
2cc432ee JG |
260 | { |
261 | struct ata_port *ap = qc->ap; | |
2cc432ee JG |
262 | u8 dmactl; |
263 | ||
264 | /* start host DMA transaction */ | |
0d5ff566 TH |
265 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
266 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2cc432ee | 267 | |
e1cc9de8 | 268 | /* Strictly, one may wish to issue an ioread8() here, to |
2cc432ee JG |
269 | * flush the mmio write. However, control also passes |
270 | * to the hardware at this point, and it will interrupt | |
271 | * us when we are to resume control. So, in effect, | |
272 | * we don't care when the mmio write flushes. | |
273 | * Further, a read of the DMA status register _immediately_ | |
274 | * following the write may not be what certain flaky hardware | |
275 | * is expected, so I think it is best to not add a readb() | |
276 | * without first all the MMIO ATA cards/mobos. | |
277 | * Or maybe I'm just being paranoid. | |
e1cc9de8 AC |
278 | * |
279 | * FIXME: The posting of this write means I/O starts are | |
280 | * unneccessarily delayed for MMIO | |
2cc432ee JG |
281 | */ |
282 | } | |
283 | ||
2cc432ee JG |
284 | /** |
285 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
286 | * @ap: Port associated with this ATA transaction. | |
287 | * | |
288 | * Clear interrupt and error flags in DMA status register. | |
289 | * | |
290 | * May be used as the irq_clear() entry in ata_port_operations. | |
291 | * | |
292 | * LOCKING: | |
cca3974e | 293 | * spin_lock_irqsave(host lock) |
2cc432ee | 294 | */ |
2cc432ee JG |
295 | void ata_bmdma_irq_clear(struct ata_port *ap) |
296 | { | |
0d5ff566 TH |
297 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
298 | ||
299 | if (!mmio) | |
2cc432ee JG |
300 | return; |
301 | ||
0d5ff566 | 302 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); |
2cc432ee JG |
303 | } |
304 | ||
358f9a77 TH |
305 | /** |
306 | * ata_noop_irq_clear - Noop placeholder for irq_clear | |
307 | * @ap: Port associated with this ATA transaction. | |
308 | */ | |
309 | void ata_noop_irq_clear(struct ata_port *ap) | |
310 | { | |
311 | } | |
312 | ||
2cc432ee JG |
313 | /** |
314 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
315 | * @ap: Port associated with this ATA transaction. | |
316 | * | |
317 | * Read and return BMDMA status register. | |
318 | * | |
319 | * May be used as the bmdma_status() entry in ata_port_operations. | |
320 | * | |
321 | * LOCKING: | |
cca3974e | 322 | * spin_lock_irqsave(host lock) |
2cc432ee | 323 | */ |
2cc432ee JG |
324 | u8 ata_bmdma_status(struct ata_port *ap) |
325 | { | |
0d5ff566 | 326 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
2cc432ee JG |
327 | } |
328 | ||
2cc432ee JG |
329 | /** |
330 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
331 | * @qc: Command we are ending DMA for | |
332 | * | |
333 | * Clears the ATA_DMA_START flag in the dma control register | |
334 | * | |
335 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
336 | * | |
337 | * LOCKING: | |
cca3974e | 338 | * spin_lock_irqsave(host lock) |
2cc432ee | 339 | */ |
2cc432ee JG |
340 | void ata_bmdma_stop(struct ata_queued_cmd *qc) |
341 | { | |
342 | struct ata_port *ap = qc->ap; | |
0d5ff566 TH |
343 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
344 | ||
345 | /* clear start/stop bit */ | |
346 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
347 | mmio + ATA_DMA_CMD); | |
2cc432ee JG |
348 | |
349 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
350 | ata_altstatus(ap); /* dummy read */ | |
351 | } | |
352 | ||
6d97dbd7 TH |
353 | /** |
354 | * ata_bmdma_freeze - Freeze BMDMA controller port | |
355 | * @ap: port to freeze | |
356 | * | |
357 | * Freeze BMDMA controller port. | |
358 | * | |
359 | * LOCKING: | |
360 | * Inherited from caller. | |
361 | */ | |
362 | void ata_bmdma_freeze(struct ata_port *ap) | |
363 | { | |
364 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
365 | ||
366 | ap->ctl |= ATA_NIEN; | |
367 | ap->last_ctl = ap->ctl; | |
368 | ||
f659f0e4 TH |
369 | if (ioaddr->ctl_addr) |
370 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
0f0a3ad3 TH |
371 | |
372 | /* Under certain circumstances, some controllers raise IRQ on | |
373 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
374 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
375 | */ | |
376 | ata_chk_status(ap); | |
377 | ||
378 | ap->ops->irq_clear(ap); | |
6d97dbd7 TH |
379 | } |
380 | ||
381 | /** | |
382 | * ata_bmdma_thaw - Thaw BMDMA controller port | |
383 | * @ap: port to thaw | |
384 | * | |
385 | * Thaw BMDMA controller port. | |
386 | * | |
387 | * LOCKING: | |
388 | * Inherited from caller. | |
389 | */ | |
390 | void ata_bmdma_thaw(struct ata_port *ap) | |
391 | { | |
392 | /* clear & re-enable interrupts */ | |
393 | ata_chk_status(ap); | |
394 | ap->ops->irq_clear(ap); | |
83625006 | 395 | ap->ops->irq_on(ap); |
6d97dbd7 TH |
396 | } |
397 | ||
398 | /** | |
399 | * ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller | |
400 | * @ap: port to handle error for | |
f5914a46 | 401 | * @prereset: prereset method (can be NULL) |
6d97dbd7 TH |
402 | * @softreset: softreset method (can be NULL) |
403 | * @hardreset: hardreset method (can be NULL) | |
404 | * @postreset: postreset method (can be NULL) | |
405 | * | |
406 | * Handle error for ATA BMDMA controller. It can handle both | |
407 | * PATA and SATA controllers. Many controllers should be able to | |
408 | * use this EH as-is or with some added handling before and | |
409 | * after. | |
410 | * | |
411 | * This function is intended to be used for constructing | |
412 | * ->error_handler callback by low level drivers. | |
413 | * | |
414 | * LOCKING: | |
415 | * Kernel thread context (may sleep) | |
416 | */ | |
f5914a46 TH |
417 | void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset, |
418 | ata_reset_fn_t softreset, ata_reset_fn_t hardreset, | |
419 | ata_postreset_fn_t postreset) | |
6d97dbd7 | 420 | { |
6d97dbd7 TH |
421 | struct ata_queued_cmd *qc; |
422 | unsigned long flags; | |
423 | int thaw = 0; | |
424 | ||
9af5c9c9 | 425 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
426 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
427 | qc = NULL; | |
428 | ||
429 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 430 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 431 | |
6d97dbd7 TH |
432 | ap->hsm_task_state = HSM_ST_IDLE; |
433 | ||
434 | if (qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 435 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
436 | u8 host_stat; |
437 | ||
fbbb262d | 438 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 439 | |
6d97dbd7 TH |
440 | /* BMDMA controllers indicate host bus error by |
441 | * setting DMA_ERR bit and timing out. As it wasn't | |
442 | * really a timeout event, adjust error mask and | |
443 | * cancel frozen state. | |
444 | */ | |
18d90deb | 445 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
446 | qc->err_mask = AC_ERR_HOST_BUS; |
447 | thaw = 1; | |
448 | } | |
449 | ||
450 | ap->ops->bmdma_stop(qc); | |
451 | } | |
452 | ||
453 | ata_altstatus(ap); | |
454 | ata_chk_status(ap); | |
455 | ap->ops->irq_clear(ap); | |
456 | ||
ba6a1308 | 457 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
458 | |
459 | if (thaw) | |
460 | ata_eh_thaw_port(ap); | |
461 | ||
462 | /* PIO and DMA engines have been stopped, perform recovery */ | |
f5914a46 | 463 | ata_do_eh(ap, prereset, softreset, hardreset, postreset); |
6d97dbd7 TH |
464 | } |
465 | ||
466 | /** | |
467 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller | |
468 | * @ap: port to handle error for | |
469 | * | |
470 | * Stock error handler for BMDMA controller. | |
471 | * | |
472 | * LOCKING: | |
473 | * Kernel thread context (may sleep) | |
474 | */ | |
475 | void ata_bmdma_error_handler(struct ata_port *ap) | |
476 | { | |
f659f0e4 | 477 | ata_reset_fn_t softreset = NULL, hardreset = NULL; |
6d97dbd7 | 478 | |
f659f0e4 TH |
479 | if (ap->ioaddr.ctl_addr) |
480 | softreset = ata_std_softreset; | |
936fd732 | 481 | if (sata_scr_valid(&ap->link)) |
6d97dbd7 TH |
482 | hardreset = sata_std_hardreset; |
483 | ||
f659f0e4 | 484 | ata_bmdma_drive_eh(ap, ata_std_prereset, softreset, hardreset, |
f5914a46 | 485 | ata_std_postreset); |
6d97dbd7 TH |
486 | } |
487 | ||
488 | /** | |
489 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for | |
490 | * BMDMA controller | |
491 | * @qc: internal command to clean up | |
492 | * | |
493 | * LOCKING: | |
494 | * Kernel thread context (may sleep) | |
495 | */ | |
496 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
497 | { | |
61dd08c6 AC |
498 | if (qc->ap->ioaddr.bmdma_addr) |
499 | ata_bmdma_stop(qc); | |
6d97dbd7 TH |
500 | } |
501 | ||
d92e74d3 AC |
502 | /** |
503 | * ata_sff_port_start - Set port up for dma. | |
504 | * @ap: Port to initialize | |
505 | * | |
506 | * Called just after data structures for each port are | |
507 | * initialized. Allocates space for PRD table if the device | |
508 | * is DMA capable SFF. | |
509 | * | |
510 | * May be used as the port_start() entry in ata_port_operations. | |
511 | * | |
512 | * LOCKING: | |
513 | * Inherited from caller. | |
514 | */ | |
515 | ||
516 | int ata_sff_port_start(struct ata_port *ap) | |
517 | { | |
518 | if (ap->ioaddr.bmdma_addr) | |
519 | return ata_port_start(ap); | |
520 | return 0; | |
521 | } | |
522 | ||
1fdffbce | 523 | #ifdef CONFIG_PCI |
4112e16a AC |
524 | |
525 | static int ata_resources_present(struct pci_dev *pdev, int port) | |
526 | { | |
527 | int i; | |
a84471fe | 528 | |
4112e16a AC |
529 | /* Check the PCI resources for this channel are enabled */ |
530 | port = port * 2; | |
531 | for (i = 0; i < 2; i ++) { | |
532 | if (pci_resource_start(pdev, port + i) == 0 || | |
55a6adee TH |
533 | pci_resource_len(pdev, port + i) == 0) |
534 | return 0; | |
4112e16a AC |
535 | } |
536 | return 1; | |
537 | } | |
a84471fe | 538 | |
0f834de3 TH |
539 | /** |
540 | * ata_pci_init_bmdma - acquire PCI BMDMA resources and init ATA host | |
541 | * @host: target ATA host | |
542 | * | |
543 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
544 | * | |
545 | * LOCKING: | |
546 | * Inherited from calling layer (may sleep). | |
547 | * | |
548 | * RETURNS: | |
549 | * 0 on success, -errno otherwise. | |
550 | */ | |
1626aeb8 | 551 | int ata_pci_init_bmdma(struct ata_host *host) |
1fdffbce | 552 | { |
0f834de3 TH |
553 | struct device *gdev = host->dev; |
554 | struct pci_dev *pdev = to_pci_dev(gdev); | |
555 | int i, rc; | |
0d5ff566 | 556 | |
6fdc99a2 AC |
557 | /* No BAR4 allocation: No DMA */ |
558 | if (pci_resource_start(pdev, 4) == 0) | |
559 | return 0; | |
560 | ||
0f834de3 TH |
561 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
562 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
563 | if (rc) | |
564 | return rc; | |
565 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
566 | if (rc) | |
567 | return rc; | |
568 | ||
569 | /* request and iomap DMA region */ | |
35a10a80 | 570 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); |
0f834de3 TH |
571 | if (rc) { |
572 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
573 | return -ENOMEM; | |
0d5ff566 | 574 | } |
0f834de3 | 575 | host->iomap = pcim_iomap_table(pdev); |
0d5ff566 | 576 | |
1626aeb8 | 577 | for (i = 0; i < 2; i++) { |
0f834de3 | 578 | struct ata_port *ap = host->ports[i]; |
0f834de3 TH |
579 | void __iomem *bmdma = host->iomap[4] + 8 * i; |
580 | ||
581 | if (ata_port_is_dummy(ap)) | |
582 | continue; | |
583 | ||
21b0ad4f | 584 | ap->ioaddr.bmdma_addr = bmdma; |
0f834de3 TH |
585 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && |
586 | (ioread8(bmdma + 2) & 0x80)) | |
587 | host->flags |= ATA_HOST_SIMPLEX; | |
cbcdd875 TH |
588 | |
589 | ata_port_desc(ap, "bmdma 0x%llx", | |
590 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
0d5ff566 TH |
591 | } |
592 | ||
0f834de3 TH |
593 | return 0; |
594 | } | |
2ec7df04 | 595 | |
d491b27b | 596 | /** |
d583bc18 | 597 | * ata_pci_init_sff_host - acquire native PCI ATA resources and init host |
d491b27b | 598 | * @host: target ATA host |
d491b27b | 599 | * |
1626aeb8 TH |
600 | * Acquire native PCI ATA resources for @host and initialize the |
601 | * first two ports of @host accordingly. Ports marked dummy are | |
602 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 603 | * |
d583bc18 TH |
604 | * Note that native PCI resources are valid even for legacy hosts |
605 | * as we fix up pdev resources array early in boot, so this | |
606 | * function can be used for both native and legacy SFF hosts. | |
607 | * | |
d491b27b TH |
608 | * LOCKING: |
609 | * Inherited from calling layer (may sleep). | |
610 | * | |
611 | * RETURNS: | |
1626aeb8 TH |
612 | * 0 if at least one port is initialized, -ENODEV if no port is |
613 | * available. | |
d491b27b | 614 | */ |
d583bc18 | 615 | int ata_pci_init_sff_host(struct ata_host *host) |
d491b27b TH |
616 | { |
617 | struct device *gdev = host->dev; | |
618 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 619 | unsigned int mask = 0; |
d491b27b TH |
620 | int i, rc; |
621 | ||
d491b27b TH |
622 | /* request, iomap BARs and init port addresses accordingly */ |
623 | for (i = 0; i < 2; i++) { | |
624 | struct ata_port *ap = host->ports[i]; | |
625 | int base = i * 2; | |
626 | void __iomem * const *iomap; | |
627 | ||
1626aeb8 TH |
628 | if (ata_port_is_dummy(ap)) |
629 | continue; | |
630 | ||
631 | /* Discard disabled ports. Some controllers show | |
632 | * their unused channels this way. Disabled ports are | |
633 | * made dummy. | |
634 | */ | |
635 | if (!ata_resources_present(pdev, i)) { | |
636 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 637 | continue; |
1626aeb8 | 638 | } |
d491b27b | 639 | |
35a10a80 TH |
640 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
641 | dev_driver_string(gdev)); | |
d491b27b | 642 | if (rc) { |
1626aeb8 TH |
643 | dev_printk(KERN_WARNING, gdev, |
644 | "failed to request/iomap BARs for port %d " | |
645 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
646 | if (rc == -EBUSY) |
647 | pcim_pin_device(pdev); | |
1626aeb8 TH |
648 | ap->ops = &ata_dummy_port_ops; |
649 | continue; | |
d491b27b TH |
650 | } |
651 | host->iomap = iomap = pcim_iomap_table(pdev); | |
652 | ||
653 | ap->ioaddr.cmd_addr = iomap[base]; | |
654 | ap->ioaddr.altstatus_addr = | |
655 | ap->ioaddr.ctl_addr = (void __iomem *) | |
656 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
657 | ata_std_ports(&ap->ioaddr); | |
1626aeb8 | 658 | |
cbcdd875 TH |
659 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
660 | (unsigned long long)pci_resource_start(pdev, base), | |
661 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
662 | ||
1626aeb8 TH |
663 | mask |= 1 << i; |
664 | } | |
665 | ||
666 | if (!mask) { | |
667 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
668 | return -ENODEV; | |
d491b27b TH |
669 | } |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
21b0ad4f | 674 | /** |
d583bc18 | 675 | * ata_pci_prepare_sff_host - helper to prepare native PCI ATA host |
21b0ad4f | 676 | * @pdev: target PCI device |
1626aeb8 | 677 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
678 | * @r_host: out argument for the initialized ATA host |
679 | * | |
680 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
681 | * resources and initialize it accordingly in one go. | |
682 | * | |
683 | * LOCKING: | |
684 | * Inherited from calling layer (may sleep). | |
685 | * | |
686 | * RETURNS: | |
687 | * 0 on success, -errno otherwise. | |
688 | */ | |
d583bc18 TH |
689 | int ata_pci_prepare_sff_host(struct pci_dev *pdev, |
690 | const struct ata_port_info * const * ppi, | |
691 | struct ata_host **r_host) | |
21b0ad4f TH |
692 | { |
693 | struct ata_host *host; | |
21b0ad4f TH |
694 | int rc; |
695 | ||
696 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
697 | return -ENOMEM; | |
698 | ||
699 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
700 | if (!host) { | |
701 | dev_printk(KERN_ERR, &pdev->dev, | |
702 | "failed to allocate ATA host\n"); | |
703 | rc = -ENOMEM; | |
704 | goto err_out; | |
705 | } | |
706 | ||
d583bc18 | 707 | rc = ata_pci_init_sff_host(host); |
21b0ad4f TH |
708 | if (rc) |
709 | goto err_out; | |
710 | ||
711 | /* init DMA related stuff */ | |
712 | rc = ata_pci_init_bmdma(host); | |
713 | if (rc) | |
714 | goto err_bmdma; | |
715 | ||
716 | devres_remove_group(&pdev->dev, NULL); | |
717 | *r_host = host; | |
718 | return 0; | |
719 | ||
720 | err_bmdma: | |
721 | /* This is necessary because PCI and iomap resources are | |
722 | * merged and releasing the top group won't release the | |
723 | * acquired resources if some of those have been acquired | |
724 | * before entering this function. | |
725 | */ | |
726 | pcim_iounmap_regions(pdev, 0xf); | |
727 | err_out: | |
728 | devres_release_group(&pdev->dev, NULL); | |
729 | return rc; | |
730 | } | |
731 | ||
4e6b79fa TH |
732 | /** |
733 | * ata_pci_activate_sff_host - start SFF host, request IRQ and register it | |
734 | * @host: target SFF ATA host | |
735 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
736 | * @sht: scsi_host_template to use when registering the host | |
737 | * | |
738 | * This is the counterpart of ata_host_activate() for SFF ATA | |
739 | * hosts. This separate helper is necessary because SFF hosts | |
740 | * use two separate interrupts in legacy mode. | |
741 | * | |
742 | * LOCKING: | |
743 | * Inherited from calling layer (may sleep). | |
744 | * | |
745 | * RETURNS: | |
746 | * 0 on success, -errno otherwise. | |
747 | */ | |
748 | int ata_pci_activate_sff_host(struct ata_host *host, | |
749 | irq_handler_t irq_handler, | |
750 | struct scsi_host_template *sht) | |
751 | { | |
752 | struct device *dev = host->dev; | |
753 | struct pci_dev *pdev = to_pci_dev(dev); | |
754 | const char *drv_name = dev_driver_string(host->dev); | |
755 | int legacy_mode = 0, rc; | |
756 | ||
757 | rc = ata_host_start(host); | |
758 | if (rc) | |
759 | return rc; | |
760 | ||
761 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
762 | u8 tmp8, mask; | |
763 | ||
764 | /* TODO: What if one channel is in native mode ... */ | |
765 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
766 | mask = (1 << 2) | (1 << 0); | |
767 | if ((tmp8 & mask) != mask) | |
768 | legacy_mode = 1; | |
769 | #if defined(CONFIG_NO_ATA_LEGACY) | |
770 | /* Some platforms with PCI limits cannot address compat | |
771 | port space. In that case we punt if their firmware has | |
772 | left a device in compatibility mode */ | |
773 | if (legacy_mode) { | |
774 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
775 | return -EOPNOTSUPP; | |
776 | } | |
777 | #endif | |
778 | } | |
779 | ||
780 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
781 | return -ENOMEM; | |
782 | ||
783 | if (!legacy_mode && pdev->irq) { | |
784 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
785 | IRQF_SHARED, drv_name, host); | |
786 | if (rc) | |
787 | goto out; | |
788 | ||
789 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
790 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
791 | } else if (legacy_mode) { | |
792 | if (!ata_port_is_dummy(host->ports[0])) { | |
793 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
794 | irq_handler, IRQF_SHARED, | |
795 | drv_name, host); | |
796 | if (rc) | |
797 | goto out; | |
798 | ||
799 | ata_port_desc(host->ports[0], "irq %d", | |
800 | ATA_PRIMARY_IRQ(pdev)); | |
801 | } | |
802 | ||
803 | if (!ata_port_is_dummy(host->ports[1])) { | |
804 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
805 | irq_handler, IRQF_SHARED, | |
806 | drv_name, host); | |
807 | if (rc) | |
808 | goto out; | |
809 | ||
810 | ata_port_desc(host->ports[1], "irq %d", | |
811 | ATA_SECONDARY_IRQ(pdev)); | |
812 | } | |
813 | } | |
814 | ||
815 | rc = ata_host_register(host, sht); | |
816 | out: | |
817 | if (rc == 0) | |
818 | devres_remove_group(dev, NULL); | |
819 | else | |
820 | devres_release_group(dev, NULL); | |
821 | ||
822 | return rc; | |
823 | } | |
824 | ||
1fdffbce JG |
825 | /** |
826 | * ata_pci_init_one - Initialize/register PCI IDE host controller | |
827 | * @pdev: Controller to be initialized | |
1626aeb8 | 828 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 829 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 830 | * @host_priv: host private_data |
1fdffbce JG |
831 | * |
832 | * This is a helper function which can be called from a driver's | |
833 | * xxx_init_one() probe function if the hardware uses traditional | |
834 | * IDE taskfile registers. | |
835 | * | |
836 | * This function calls pci_enable_device(), reserves its register | |
837 | * regions, sets the dma mask, enables bus master mode, and calls | |
838 | * ata_device_add() | |
839 | * | |
2ec7df04 AC |
840 | * ASSUMPTION: |
841 | * Nobody makes a single channel controller that appears solely as | |
842 | * the secondary legacy port on PCI. | |
843 | * | |
1fdffbce JG |
844 | * LOCKING: |
845 | * Inherited from PCI layer (may sleep). | |
846 | * | |
847 | * RETURNS: | |
848 | * Zero on success, negative on errno-based value on error. | |
849 | */ | |
1626aeb8 | 850 | int ata_pci_init_one(struct pci_dev *pdev, |
1bd5b715 | 851 | const struct ata_port_info * const * ppi, |
887125e3 | 852 | struct scsi_host_template *sht, void *host_priv) |
1fdffbce | 853 | { |
f0d36efd | 854 | struct device *dev = &pdev->dev; |
1626aeb8 | 855 | const struct ata_port_info *pi = NULL; |
0f834de3 | 856 | struct ata_host *host = NULL; |
1626aeb8 | 857 | int i, rc; |
1fdffbce JG |
858 | |
859 | DPRINTK("ENTER\n"); | |
860 | ||
1626aeb8 TH |
861 | /* look up the first valid port_info */ |
862 | for (i = 0; i < 2 && ppi[i]; i++) { | |
863 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
864 | pi = ppi[i]; | |
865 | break; | |
866 | } | |
867 | } | |
f0d36efd | 868 | |
1626aeb8 TH |
869 | if (!pi) { |
870 | dev_printk(KERN_ERR, &pdev->dev, | |
871 | "no valid port_info specified\n"); | |
872 | return -EINVAL; | |
873 | } | |
c791c306 | 874 | |
1626aeb8 TH |
875 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
876 | return -ENOMEM; | |
1fdffbce | 877 | |
f0d36efd | 878 | rc = pcim_enable_device(pdev); |
1fdffbce | 879 | if (rc) |
4e6b79fa | 880 | goto out; |
1fdffbce | 881 | |
4e6b79fa | 882 | /* prepare and activate SFF host */ |
d583bc18 TH |
883 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
884 | if (rc) | |
4e6b79fa | 885 | goto out; |
887125e3 | 886 | host->private_data = host_priv; |
d491b27b | 887 | |
d491b27b | 888 | pci_set_master(pdev); |
1bd5b715 | 889 | rc = ata_pci_activate_sff_host(host, ata_interrupt, sht); |
4e6b79fa TH |
890 | out: |
891 | if (rc == 0) | |
892 | devres_remove_group(&pdev->dev, NULL); | |
893 | else | |
894 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 895 | |
1fdffbce JG |
896 | return rc; |
897 | } | |
898 | ||
d33d44fa AC |
899 | /** |
900 | * ata_pci_clear_simplex - attempt to kick device out of simplex | |
901 | * @pdev: PCI device | |
902 | * | |
903 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
3a4fa0a2 | 904 | * enter non simplex mode. This implements the necessary logic to |
d33d44fa AC |
905 | * perform the task on such devices. Calling it on other devices will |
906 | * have -undefined- behaviour. | |
907 | */ | |
908 | ||
909 | int ata_pci_clear_simplex(struct pci_dev *pdev) | |
910 | { | |
911 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
912 | u8 simplex; | |
913 | ||
914 | if (bmdma == 0) | |
915 | return -ENOENT; | |
916 | ||
917 | simplex = inb(bmdma + 0x02); | |
918 | outb(simplex & 0x60, bmdma + 0x02); | |
919 | simplex = inb(bmdma + 0x02); | |
920 | if (simplex & 0x80) | |
921 | return -EOPNOTSUPP; | |
922 | return 0; | |
923 | } | |
924 | ||
a76b62ca | 925 | unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask) |
d33d44fa AC |
926 | { |
927 | /* Filter out DMA modes if the device has been configured by | |
928 | the BIOS as PIO only */ | |
2e9edbf8 | 929 | |
c80544dc | 930 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) |
d33d44fa AC |
931 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); |
932 | return xfer_mask; | |
933 | } | |
934 | ||
1fdffbce JG |
935 | #endif /* CONFIG_PCI */ |
936 |