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sata_promise: handle ATAPI_NODATA ourselves
[net-next-2.6.git] / drivers / ata / ata_piix.c
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1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
fc085150 96#define DRV_VERSION "2.00ac7"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
d4358048 104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 107
800b3996
TH		 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 110
1da177e4
LT		 111 /* combined mode. if set, PATA is channel 0.
112 * if clear, PATA is channel 1.
113 */
6a690df5
HR		 114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 116
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119
1d076e5b 120 /* controller IDs */
669a5db4
JG		 121 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
123 ich_pata_66 = 2, /* ICH up to 66 Mhz */
124 ich_pata_100 = 3, /* ICH up to UDMA 100 */
125 ich_pata_133 = 4, /* ICH up to UDMA 133 */
126 ich5_sata = 5,
5e56a37c
TH		 127 ich6_sata = 6,
128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9,
85cd7251 131
d33f58b8
TH		 132 /* constants for mapping table */
133 P0 = 0, /* port 0 */
134 P1 = 1, /* port 1 */
135 P2 = 2, /* port 2 */
136 P3 = 3, /* port 3 */
137 IDE = -1, /* IDE */
138 NA = -2, /* not avaliable */
139 RV = -3, /* reserved */
140
7b6dbd68 141 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 142};
143
d33f58b8
TH		 144struct piix_map_db {
145 const u32 mask;
73291a1c 146 const u16 port_enable;
d33f58b8
TH		 147 const int map[][4];
148};
149
d96715c1
TH		 150struct piix_host_priv {
151 const int *map;
152};
153
1da177e4
LT		 154static int piix_init_one (struct pci_dev *pdev,
155 const struct pci_device_id *ent);
cca3974e 156static void piix_host_stop(struct ata_host *host);
ccc4672a 157static void piix_pata_error_handler(struct ata_port *ap);
669a5db4 158static void ich_pata_error_handler(struct ata_port *ap);
ccc4672a 159static void piix_sata_error_handler(struct ata_port *ap);
669a5db4
JG		 160static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
161static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
162static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
1da177e4
LT		 163
164static unsigned int in_module_init = 1;
165
3b7d697d 166static const struct pci_device_id piix_pci_tbl[] = {
1da177e4 167#ifdef ATA_ENABLE_PATA
669a5db4
JG		 168 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
169 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
170 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
171 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
172 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
173 /* Intel PIIX4 */
174 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
175 /* Intel PIIX4 */
176 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
177 /* Intel PIIX */
178 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 /* Intel ICH (i810, i815, i840) UDMA 66*/
180 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
181 /* Intel ICH0 : UDMA 33*/
182 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
183 /* Intel ICH2M */
184 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
185 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
186 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
187 /* Intel ICH3M */
188 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH3 (E7500/1) UDMA 100 */
190 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
192 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH5 */
195 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
196 /* C-ICH (i810E2) */
197 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 198 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 199 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* ICH6 (and 6) (i915) UDMA 100 */
201 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* ICH7/7-R (i945, i975) UDMA 100*/
203 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
204 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 205#endif
206
207 /* NOTE: The following PCI ids must be kept in sync with the
208 * list in drivers/pci/quirks.c.
209 */
210
1d076e5b 211 /* 82801EB (ICH5) */
1da177e4 212 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 213 /* 82801EB (ICH5) */
1da177e4 214 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 215 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 216 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 217 /* 6300ESB pretending RAID */
5e56a37c 218 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 219 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 220 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 221 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 222 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 223 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
224 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
225 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 226 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 227 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 228 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 229 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 230 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 231 /* SATA Controller 1 IDE (ICH8) */
08f12edc 232 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 233 /* SATA Controller 2 IDE (ICH8) */
08f12edc 234 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 235 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 236 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573
JG		 237 /* SATA Controller IDE (ICH9) */
238 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
239 /* SATA Controller IDE (ICH9) */
240 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
241 /* SATA Controller IDE (ICH9) */
242 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
243 /* SATA Controller IDE (ICH9M) */
244 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
245 /* SATA Controller IDE (ICH9M) */
246 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
247 /* SATA Controller IDE (ICH9M) */
248 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1da177e4
LT		 249
250 { } /* terminate list */
251};
252
253static struct pci_driver piix_pci_driver = {
254 .name = DRV_NAME,
255 .id_table = piix_pci_tbl,
256 .probe = piix_init_one,
257 .remove = ata_pci_remove_one,
9b847548
JA		 258 .suspend = ata_pci_device_suspend,
259 .resume = ata_pci_device_resume,
1da177e4
LT		 260};
261
193515d5 262static struct scsi_host_template piix_sht = {
1da177e4
LT		 263 .module = THIS_MODULE,
264 .name = DRV_NAME,
265 .ioctl = ata_scsi_ioctl,
266 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 267 .can_queue = ATA_DEF_QUEUE,
268 .this_id = ATA_SHT_THIS_ID,
269 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 270 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
271 .emulated = ATA_SHT_EMULATED,
272 .use_clustering = ATA_SHT_USE_CLUSTERING,
273 .proc_name = DRV_NAME,
274 .dma_boundary = ATA_DMA_BOUNDARY,
275 .slave_configure = ata_scsi_slave_config,
ccf68c34 276 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 277 .bios_param = ata_std_bios_param,
9b847548
JA		 278 .resume = ata_scsi_device_resume,
279 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 280};
281
057ace5e 282static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 283 .port_disable = ata_port_disable,
284 .set_piomode = piix_set_piomode,
285 .set_dmamode = piix_set_dmamode,
89bad589 286 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 287
288 .tf_load = ata_tf_load,
289 .tf_read = ata_tf_read,
290 .check_status = ata_check_status,
291 .exec_command = ata_exec_command,
292 .dev_select = ata_std_dev_select,
293
1da177e4
LT		 294 .bmdma_setup = ata_bmdma_setup,
295 .bmdma_start = ata_bmdma_start,
296 .bmdma_stop = ata_bmdma_stop,
297 .bmdma_status = ata_bmdma_status,
298 .qc_prep = ata_qc_prep,
299 .qc_issue = ata_qc_issue_prot,
89bad589 300 .data_xfer = ata_pio_data_xfer,
1da177e4 301
3f037db0
TH		 302 .freeze = ata_bmdma_freeze,
303 .thaw = ata_bmdma_thaw,
ccc4672a 304 .error_handler = piix_pata_error_handler,
3f037db0 305 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 306
307 .irq_handler = ata_interrupt,
308 .irq_clear = ata_bmdma_irq_clear,
309
310 .port_start = ata_port_start,
311 .port_stop = ata_port_stop,
d96715c1 312 .host_stop = piix_host_stop,
1da177e4
LT		 313};
314
669a5db4
JG		 315static const struct ata_port_operations ich_pata_ops = {
316 .port_disable = ata_port_disable,
317 .set_piomode = piix_set_piomode,
318 .set_dmamode = ich_set_dmamode,
319 .mode_filter = ata_pci_default_filter,
320
321 .tf_load = ata_tf_load,
322 .tf_read = ata_tf_read,
323 .check_status = ata_check_status,
324 .exec_command = ata_exec_command,
325 .dev_select = ata_std_dev_select,
326
327 .bmdma_setup = ata_bmdma_setup,
328 .bmdma_start = ata_bmdma_start,
329 .bmdma_stop = ata_bmdma_stop,
330 .bmdma_status = ata_bmdma_status,
331 .qc_prep = ata_qc_prep,
332 .qc_issue = ata_qc_issue_prot,
333 .data_xfer = ata_pio_data_xfer,
334
335 .freeze = ata_bmdma_freeze,
336 .thaw = ata_bmdma_thaw,
337 .error_handler = ich_pata_error_handler,
338 .post_internal_cmd = ata_bmdma_post_internal_cmd,
339
340 .irq_handler = ata_interrupt,
341 .irq_clear = ata_bmdma_irq_clear,
342
343 .port_start = ata_port_start,
344 .port_stop = ata_port_stop,
fae07dc3 345 .host_stop = piix_host_stop,
669a5db4
JG		 346};
347
057ace5e 348static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 349 .port_disable = ata_port_disable,
350
351 .tf_load = ata_tf_load,
352 .tf_read = ata_tf_read,
353 .check_status = ata_check_status,
354 .exec_command = ata_exec_command,
355 .dev_select = ata_std_dev_select,
356
1da177e4
LT		 357 .bmdma_setup = ata_bmdma_setup,
358 .bmdma_start = ata_bmdma_start,
359 .bmdma_stop = ata_bmdma_stop,
360 .bmdma_status = ata_bmdma_status,
361 .qc_prep = ata_qc_prep,
362 .qc_issue = ata_qc_issue_prot,
89bad589 363 .data_xfer = ata_pio_data_xfer,
1da177e4 364
3f037db0
TH		 365 .freeze = ata_bmdma_freeze,
366 .thaw = ata_bmdma_thaw,
ccc4672a 367 .error_handler = piix_sata_error_handler,
3f037db0 368 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 369
370 .irq_handler = ata_interrupt,
371 .irq_clear = ata_bmdma_irq_clear,
372
373 .port_start = ata_port_start,
374 .port_stop = ata_port_stop,
d96715c1 375 .host_stop = piix_host_stop,
1da177e4
LT		 376};
377
d96715c1 378static const struct piix_map_db ich5_map_db = {
d33f58b8 379 .mask = 0x7,
ea35d29e 380 .port_enable = 0x3,
d33f58b8
TH		 381 .map = {
382 /* PM PS SM SS MAP */
383 { P0, NA, P1, NA }, /* 000b */
384 { P1, NA, P0, NA }, /* 001b */
385 { RV, RV, RV, RV },
386 { RV, RV, RV, RV },
387 { P0, P1, IDE, IDE }, /* 100b */
388 { P1, P0, IDE, IDE }, /* 101b */
389 { IDE, IDE, P0, P1 }, /* 110b */
390 { IDE, IDE, P1, P0 }, /* 111b */
391 },
392};
393
d96715c1 394static const struct piix_map_db ich6_map_db = {
d33f58b8 395 .mask = 0x3,
ea35d29e 396 .port_enable = 0xf,
d33f58b8
TH		 397 .map = {
398 /* PM PS SM SS MAP */
79ea24e7 399 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 400 { IDE, IDE, P1, P3 }, /* 01b */
401 { P0, P2, IDE, IDE }, /* 10b */
402 { RV, RV, RV, RV },
403 },
404};
405
d96715c1 406static const struct piix_map_db ich6m_map_db = {
d33f58b8 407 .mask = 0x3,
ea35d29e 408 .port_enable = 0x5,
67083741
TH		 409
410 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 411 * it anyway. MAP 01b have been spotted on both ICH6M and
412 * ICH7M.
67083741
TH		 413 */
414 .map = {
415 /* PM PS SM SS MAP */
416 { P0, P2, RV, RV }, /* 00b */
417 { IDE, IDE, P1, P3 }, /* 01b */
418 { P0, P2, IDE, IDE }, /* 10b */
419 { RV, RV, RV, RV },
420 },
421};
422
08f12edc
JG		 423static const struct piix_map_db ich8_map_db = {
424 .mask = 0x3,
425 .port_enable = 0x3,
08f12edc
JG		 426 .map = {
427 /* PM PS SM SS MAP */
158f30c8 428 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 429 { RV, RV, RV, RV },
158f30c8 430 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
08f12edc
JG		 431 { RV, RV, RV, RV },
432 },
433};
434
d96715c1
TH		 435static const struct piix_map_db *piix_map_db_table[] = {
436 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 437 [ich6_sata] = &ich6_map_db,
438 [ich6_sata_ahci] = &ich6_map_db,
439 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 440 [ich8_sata_ahci] = &ich8_map_db,
d96715c1
TH		 441};
442
1da177e4 443static struct ata_port_info piix_port_info[] = {
669a5db4 444 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
1d076e5b
TH		 445 {
446 .sht = &piix_sht,
b3362f88 447 .flags = PIIX_PATA_FLAGS,
1d076e5b 448 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 449 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 450 .udma_mask = ATA_UDMA_MASK_40C,
451 .port_ops = &piix_pata_ops,
452 },
453
669a5db4
JG		 454 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
455 {
456 .sht = &piix_sht,
b3362f88 457 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 458 .pio_mask = 0x1f, /* pio 0-4 */
459 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
460 .udma_mask = ATA_UDMA2, /* UDMA33 */
461 .port_ops = &ich_pata_ops,
462 },
463 /* ich_pata_66: 2 ICH controllers up to 66MHz */
1da177e4
LT		 464 {
465 .sht = &piix_sht,
b3362f88 466 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 467 .pio_mask = 0x1f, /* pio 0-4 */
468 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
469 .udma_mask = ATA_UDMA4,
470 .port_ops = &ich_pata_ops,
471 },
85cd7251 472
669a5db4
JG		 473 /* ich_pata_100: 3 */
474 {
475 .sht = &piix_sht,
b3362f88 476 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 477 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 478 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 479 .udma_mask = ATA_UDMA5, /* udma0-5 */
480 .port_ops = &ich_pata_ops,
1da177e4
LT		 481 },
482
669a5db4
JG		 483 /* ich_pata_133: 4 ICH with full UDMA6 */
484 {
485 .sht = &piix_sht,
b3362f88 486 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
669a5db4
JG		 487 .pio_mask = 0x1f, /* pio 0-4 */
488 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
489 .udma_mask = ATA_UDMA6, /* UDMA133 */
490 .port_ops = &ich_pata_ops,
491 },
492
493 /* ich5_sata: 5 */
1da177e4
LT		 494 {
495 .sht = &piix_sht,
228c1590 496 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 497 .pio_mask = 0x1f, /* pio0-4 */
498 .mwdma_mask = 0x07, /* mwdma0-2 */
499 .udma_mask = 0x7f, /* udma0-6 */
500 .port_ops = &piix_sata_ops,
501 },
502
5e56a37c 503 /* ich6_sata: 6 */
1da177e4
LT		 504 {
505 .sht = &piix_sht,
b3362f88 506 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 507 .pio_mask = 0x1f, /* pio0-4 */
508 .mwdma_mask = 0x07, /* mwdma0-2 */
509 .udma_mask = 0x7f, /* udma0-6 */
510 .port_ops = &piix_sata_ops,
511 },
512
5e56a37c 513 /* ich6_sata_ahci: 7 */
c368ca4e
JG		 514 {
515 .sht = &piix_sht,
b3362f88 516 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 517 PIIX_FLAG_AHCI,
c368ca4e
JG		 518 .pio_mask = 0x1f, /* pio0-4 */
519 .mwdma_mask = 0x07, /* mwdma0-2 */
520 .udma_mask = 0x7f, /* udma0-6 */
521 .port_ops = &piix_sata_ops,
522 },
1d076e5b 523
5e56a37c 524 /* ich6m_sata_ahci: 8 */
1d076e5b
TH		 525 {
526 .sht = &piix_sht,
b3362f88 527 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 528 PIIX_FLAG_AHCI,
1d076e5b
TH		 529 .pio_mask = 0x1f, /* pio0-4 */
530 .mwdma_mask = 0x07, /* mwdma0-2 */
531 .udma_mask = 0x7f, /* udma0-6 */
532 .port_ops = &piix_sata_ops,
533 },
08f12edc 534
5e56a37c 535 /* ich8_sata_ahci: 9 */
08f12edc
JG		 536 {
537 .sht = &piix_sht,
b3362f88 538 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 539 PIIX_FLAG_AHCI,
540 .pio_mask = 0x1f, /* pio0-4 */
541 .mwdma_mask = 0x07, /* mwdma0-2 */
542 .udma_mask = 0x7f, /* udma0-6 */
543 .port_ops = &piix_sata_ops,
544 },
669a5db4 545
1da177e4
LT		 546};
547
548static struct pci_bits piix_enable_bits[] = {
549 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
550 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
551};
552
553MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
554MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
555MODULE_LICENSE("GPL");
556MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
557MODULE_VERSION(DRV_VERSION);
558
fc085150
AC		 559struct ich_laptop {
560 u16 device;
561 u16 subvendor;
562 u16 subdevice;
563};
564
565/*
566 * List of laptops that use short cables rather than 80 wire
567 */
568
569static const struct ich_laptop ich_laptop[] = {
570 /* devid, subvendor, subdev */
571 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
babfb682 572 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
fc085150
AC		 573 /* end marker */
574 { 0, }
575};
576
1da177e4
LT		 577/**
578 * piix_pata_cbl_detect - Probe host controller cable detect info
579 * @ap: Port for which cable detect info is desired
580 *
581 * Read 80c cable indicator from ATA PCI device's PCI config
582 * register. This register is normally set by firmware (BIOS).
583 *
584 * LOCKING:
585 * None (inherited from caller).
586 */
669a5db4
JG		 587
588static void ich_pata_cbl_detect(struct ata_port *ap)
1da177e4 589{
cca3974e 590 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 591 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 592 u8 tmp, mask;
593
594 /* no 80c support in host controller? */
595 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
596 goto cbl40;
597
fc085150
AC		 598 /* Check for specials - Acer Aspire 5602WLMi */
599 while (lap->device) {
600 if (lap->device == pdev->device &&
601 lap->subvendor == pdev->subsystem_vendor &&
602 lap->subdevice == pdev->subsystem_device) {
603 ap->cbl = ATA_CBL_PATA40_SHORT;
604 return;
605 }
606 lap++;
607 }
608
1da177e4 609 /* check BIOS cable detect results */
2a88d1ac 610 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 611 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
612 if ((tmp & mask) == 0)
613 goto cbl40;
614
615 ap->cbl = ATA_CBL_PATA80;
616 return;
617
618cbl40:
619 ap->cbl = ATA_CBL_PATA40;
1da177e4
LT		 620}
621
622/**
ccc4672a 623 * piix_pata_prereset - prereset for PATA host controller
573db6b8 624 * @ap: Target port
1da177e4 625 *
573db6b8
TH		 626 *
627 * LOCKING:
628 * None (inherited from caller).
629 */
ccc4672a 630static int piix_pata_prereset(struct ata_port *ap)
1da177e4 631{
cca3974e 632 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 633
c961922b
AC		 634 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
635 return -ENOENT;
f20b16ff 636
669a5db4 637 ap->cbl = ATA_CBL_PATA40;
ccc4672a
TH		 638 return ata_std_prereset(ap);
639}
640
641static void piix_pata_error_handler(struct ata_port *ap)
642{
643 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
644 ata_std_postreset);
1da177e4
LT		 645}
646
669a5db4
JG		 647
648/**
649 * ich_pata_prereset - prereset for PATA host controller
650 * @ap: Target port
651 *
652 *
653 * LOCKING:
654 * None (inherited from caller).
655 */
656static int ich_pata_prereset(struct ata_port *ap)
657{
658 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
659
660 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
661 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
662 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
663 return 0;
664 }
665
666 ich_pata_cbl_detect(ap);
667
668 return ata_std_prereset(ap);
669}
670
671static void ich_pata_error_handler(struct ata_port *ap)
672{
673 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
674 ata_std_postreset);
675}
676
ccc4672a
TH		 677static void piix_sata_error_handler(struct ata_port *ap)
678{
228c1590 679 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
ccc4672a 680 ata_std_postreset);
1da177e4
LT		 681}
682
683/**
684 * piix_set_piomode - Initialize host controller PATA PIO timings
685 * @ap: Port whose timings we are configuring
686 * @adev: um
1da177e4
LT		 687 *
688 * Set PIO mode for device, in host controller PCI config space.
689 *
690 * LOCKING:
691 * None (inherited from caller).
692 */
693
694static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
695{
696 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 697 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 698 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 699 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 700 unsigned int slave_port = 0x44;
701 u16 master_data;
702 u8 slave_data;
669a5db4
JG		 703 u8 udma_enable;
704 int control = 0;
85cd7251 705
669a5db4
JG		 706 /*
707 * See Intel Document 298600-004 for the timing programing rules
708 * for ICH controllers.
709 */
1da177e4
LT		 710
711 static const /* ISP RTC */
712 u8 timings[][2] = { { 0, 0 },
713 { 0, 0 },
714 { 1, 0 },
715 { 2, 1 },
716 { 2, 3 }, };
717
669a5db4
JG		 718 if (pio >= 2)
719 control |= 1; /* TIME1 enable */
720 if (ata_pio_need_iordy(adev))
721 control |= 2; /* IE enable */
722
85cd7251 723 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 724 if (adev->class == ATA_DEV_ATA)
725 control |= 4; /* PPE enable */
726
1da177e4
LT		 727 pci_read_config_word(dev, master_port, &master_data);
728 if (is_slave) {
669a5db4 729 /* Enable SITRE (seperate slave timing register) */
1da177e4 730 master_data |= 0x4000;
669a5db4
JG		 731 /* enable PPE1, IE1 and TIME1 as needed */
732 master_data |= (control << 4);
1da177e4 733 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 734 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 735 /* Load the timing nibble for this slave */
736 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
1da177e4 737 } else {
669a5db4 738 /* Master keeps the bits in a different format */
1da177e4 739 master_data &= 0xccf8;
669a5db4
JG		 740 /* Enable PPE, IE and TIME as appropriate */
741 master_data |= control;
1da177e4
LT		 742 master_data |=
743 (timings[pio][0] << 12) |
744 (timings[pio][1] << 8);
745 }
746 pci_write_config_word(dev, master_port, master_data);
747 if (is_slave)
748 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 749
750 /* Ensure the UDMA bit is off - it will be turned back on if
751 UDMA is selected */
85cd7251 752
669a5db4
JG		 753 if (ap->udma_mask) {
754 pci_read_config_byte(dev, 0x48, &udma_enable);
755 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
756 pci_write_config_byte(dev, 0x48, udma_enable);
757 }
1da177e4
LT		 758}
759
760/**
669a5db4 761 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 762 * @ap: Port whose timings we are configuring
669a5db4 763 * @adev: Drive in question
1da177e4 764 * @udma: udma mode, 0 - 6
c32a8fd7 765 * @isich: set if the chip is an ICH device
1da177e4
LT		 766 *
767 * Set UDMA mode for device, in host controller PCI config space.
768 *
769 * LOCKING:
770 * None (inherited from caller).
771 */
772
669a5db4 773static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 774{
cca3974e 775 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 776 u8 master_port = ap->port_no ? 0x42 : 0x40;
777 u16 master_data;
778 u8 speed = adev->dma_mode;
779 int devid = adev->devno + 2 * ap->port_no;
780 u8 udma_enable;
85cd7251 781
669a5db4
JG		 782 static const /* ISP RTC */
783 u8 timings[][2] = { { 0, 0 },
784 { 0, 0 },
785 { 1, 0 },
786 { 2, 1 },
787 { 2, 3 }, };
788
789 pci_read_config_word(dev, master_port, &master_data);
790 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 791
792 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 793 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
794 u16 udma_timing;
795 u16 ideconf;
796 int u_clock, u_speed;
85cd7251 797
669a5db4
JG		 798 /*
799 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 800 * selection of dividers
801 *
669a5db4 802 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 803 * except UDMA0 which is 00
669a5db4
JG		 804 */
805 u_speed = min(2 - (udma & 1), udma);
806 if (udma == 5)
807 u_clock = 0x1000; /* 100Mhz */
808 else if (udma > 2)
809 u_clock = 1; /* 66Mhz */
810 else
811 u_clock = 0; /* 33Mhz */
85cd7251 812
669a5db4 813 udma_enable |= (1 << devid);
85cd7251 814
669a5db4
JG		 815 /* Load the CT/RP selection */
816 pci_read_config_word(dev, 0x4A, &udma_timing);
817 udma_timing &= ~(3 << (4 * devid));
818 udma_timing |= u_speed << (4 * devid);
819 pci_write_config_word(dev, 0x4A, udma_timing);
820
85cd7251 821 if (isich) {
669a5db4
JG		 822 /* Select a 33/66/100Mhz clock */
823 pci_read_config_word(dev, 0x54, &ideconf);
824 ideconf &= ~(0x1001 << devid);
825 ideconf |= u_clock << devid;
826 /* For ICH or later we should set bit 10 for better
827 performance (WR_PingPong_En) */
828 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 829 }
1da177e4 830 } else {
669a5db4
JG		 831 /*
832 * MWDMA is driven by the PIO timings. We must also enable
833 * IORDY unconditionally along with TIME1. PPE has already
834 * been set when the PIO timing was set.
835 */
836 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
837 unsigned int control;
838 u8 slave_data;
839 const unsigned int needed_pio[3] = {
840 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
841 };
842 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 843
669a5db4 844 control = 3; /* IORDY|TIME1 */
85cd7251 845
669a5db4
JG		 846 /* If the drive MWDMA is faster than it can do PIO then
847 we must force PIO into PIO0 */
85cd7251 848
669a5db4
JG		 849 if (adev->pio_mode < needed_pio[mwdma])
850 /* Enable DMA timing only */
851 control |= 8; /* PIO cycles in PIO0 */
852
853 if (adev->devno) { /* Slave */
854 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
855 master_data |= control << 4;
856 pci_read_config_byte(dev, 0x44, &slave_data);
857 slave_data &= (0x0F + 0xE1 * ap->port_no);
858 /* Load the matching timing */
859 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
860 pci_write_config_byte(dev, 0x44, slave_data);
861 } else { /* Master */
85cd7251 862 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 863 and master timing bits */
864 master_data |= control;
865 master_data |=
866 (timings[pio][0] << 12) |
867 (timings[pio][1] << 8);
868 }
869 udma_enable &= ~(1 << devid);
870 pci_write_config_word(dev, master_port, master_data);
1da177e4 871 }
669a5db4
JG		 872 /* Don't scribble on 0x48 if the controller does not support UDMA */
873 if (ap->udma_mask)
874 pci_write_config_byte(dev, 0x48, udma_enable);
875}
876
877/**
878 * piix_set_dmamode - Initialize host controller PATA DMA timings
879 * @ap: Port whose timings we are configuring
880 * @adev: um
881 *
882 * Set MW/UDMA mode for device, in host controller PCI config space.
883 *
884 * LOCKING:
885 * None (inherited from caller).
886 */
887
888static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
889{
890 do_pata_set_dmamode(ap, adev, 0);
891}
892
893/**
894 * ich_set_dmamode - Initialize host controller PATA DMA timings
895 * @ap: Port whose timings we are configuring
896 * @adev: um
897 *
898 * Set MW/UDMA mode for device, in host controller PCI config space.
899 *
900 * LOCKING:
901 * None (inherited from caller).
902 */
903
904static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
905{
906 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 907}
908
1da177e4
LT		 909#define AHCI_PCI_BAR 5
910#define AHCI_GLOBAL_CTL 0x04
911#define AHCI_ENABLE (1 << 31)
912static int piix_disable_ahci(struct pci_dev *pdev)
913{
ea6ba10b 914 void __iomem *mmio;
1da177e4
LT		 915 u32 tmp;
916 int rc = 0;
917
918 /* BUG: pci_enable_device has not yet been called. This
919 * works because this device is usually set up by BIOS.
920 */
921
374b1873
JG		 922 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
923 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 924 return 0;
7b6dbd68 925
374b1873 926 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 927 if (!mmio)
928 return -ENOMEM;
7b6dbd68 929
1da177e4
LT		 930 tmp = readl(mmio + AHCI_GLOBAL_CTL);
931 if (tmp & AHCI_ENABLE) {
932 tmp &= ~AHCI_ENABLE;
933 writel(tmp, mmio + AHCI_GLOBAL_CTL);
934
935 tmp = readl(mmio + AHCI_GLOBAL_CTL);
936 if (tmp & AHCI_ENABLE)
937 rc = -EIO;
938 }
7b6dbd68 939
374b1873 940 pci_iounmap(pdev, mmio);
1da177e4
LT		 941 return rc;
942}
943
c621b140
AC		 944/**
945 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 946 * @ata_dev: the PCI device to check
2e9edbf8 947 *
c621b140
AC		 948 * Check for the present of 450NX errata #19 and errata #25. If
949 * they are found return an error code so we can turn off DMA
950 */
951
952static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
953{
954 struct pci_dev *pdev = NULL;
955 u16 cfg;
956 u8 rev;
957 int no_piix_dma = 0;
2e9edbf8 958
c621b140
AC		 959 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
960 {
961 /* Look for 450NX PXB. Check for problem configurations
962 A PCI quirk checks bit 6 already */
963 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
964 pci_read_config_word(pdev, 0x41, &cfg);
965 /* Only on the original revision: IDE DMA can hang */
31a34fe7 966 if (rev == 0x00)
c621b140
AC		 967 no_piix_dma = 1;
968 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
31a34fe7 969 else if (cfg & (1<<14) && rev < 5)
c621b140
AC		 970 no_piix_dma = 2;
971 }
31a34fe7 972 if (no_piix_dma)
c621b140 973 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 974 if (no_piix_dma == 2)
c621b140
AC		 975 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
976 return no_piix_dma;
2e9edbf8 977}
c621b140 978
ea35d29e 979static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 980 struct ata_port_info *pinfo,
ea35d29e
JG		 981 const struct piix_map_db *map_db)
982{
983 u16 pcs, new_pcs;
984
985 pci_read_config_word(pdev, ICH5_PCS, &pcs);
986
987 new_pcs = pcs | map_db->port_enable;
988
989 if (new_pcs != pcs) {
990 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
991 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
992 msleep(150);
993 }
994}
995
d33f58b8 996static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 997 struct ata_port_info *pinfo,
998 const struct piix_map_db *map_db)
d33f58b8 999{
d96715c1 1000 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 1001 const unsigned int *map;
1002 int i, invalid_map = 0;
1003 u8 map_value;
1004
1005 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1006
1007 map = map_db->map[map_value & map_db->mask];
1008
1009 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1010 for (i = 0; i < 4; i++) {
1011 switch (map[i]) {
1012 case RV:
1013 invalid_map = 1;
1014 printk(" XX");
1015 break;
1016
1017 case NA:
1018 printk(" --");
1019 break;
1020
1021 case IDE:
1022 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1023 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1024 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1025 i++;
1026 printk(" IDE IDE");
1027 break;
1028
1029 default:
1030 printk(" P%d", map[i]);
1031 if (i & 1)
cca3974e 1032 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1033 break;
1034 }
1035 }
1036 printk(" ]\n");
1037
1038 if (invalid_map)
1039 dev_printk(KERN_ERR, &pdev->dev,
1040 "invalid MAP value %u\n", map_value);
1041
d96715c1 1042 hpriv->map = map;
d33f58b8
TH		 1043}
1044
1da177e4
LT		 1045/**
1046 * piix_init_one - Register PIIX ATA PCI device with kernel services
1047 * @pdev: PCI device to register
1048 * @ent: Entry in piix_pci_tbl matching with @pdev
1049 *
1050 * Called from kernel PCI layer. We probe for combined mode (sigh),
1051 * and then hand over control to libata, for it to do the rest.
1052 *
1053 * LOCKING:
1054 * Inherited from PCI layer (may sleep).
1055 *
1056 * RETURNS:
1057 * Zero on success, or -ERRNO value.
1058 */
1059
1060static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1061{
1062 static int printed_version;
d33f58b8
TH		 1063 struct ata_port_info port_info[2];
1064 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
d96715c1 1065 struct piix_host_priv *hpriv;
cca3974e 1066 unsigned long port_flags;
1da177e4
LT		 1067
1068 if (!printed_version++)
6248e647
JG		 1069 dev_printk(KERN_DEBUG, &pdev->dev,
1070 "version " DRV_VERSION "\n");
1da177e4
LT		 1071
1072 /* no hotplugging support (FIXME) */
1073 if (!in_module_init)
1074 return -ENODEV;
1075
d96715c1
TH		 1076 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1077 if (!hpriv)
1078 return -ENOMEM;
1079
d33f58b8
TH		 1080 port_info[0] = piix_port_info[ent->driver_data];
1081 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1082 port_info[0].private_data = hpriv;
1083 port_info[1].private_data = hpriv;
1da177e4 1084
cca3974e 1085 port_flags = port_info[0].flags;
ff0fc146 1086
cca3974e 1087 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1088 u8 tmp;
1089 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1090 if (tmp == PIIX_AHCI_DEVICE) {
1091 int rc = piix_disable_ahci(pdev);
1092 if (rc)
1093 return rc;
1094 }
1da177e4
LT		 1095 }
1096
d33f58b8 1097 /* Initialize SATA map */
cca3974e 1098 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1099 piix_init_sata_map(pdev, port_info,
1100 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1101 piix_init_pcs(pdev, port_info,
1102 piix_map_db_table[ent->driver_data]);
ea35d29e 1103 }
1da177e4
LT		 1104
1105 /* On ICH5, some BIOSen disable the interrupt using the
1106 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1107 * On ICH6, this bit has the same effect, but only when
1108 * MSI is disabled (and it is disabled, as we don't use
1109 * message-signalled interrupts currently).
1110 */
cca3974e 1111 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1112 pci_intx(pdev, 1);
1da177e4 1113
c621b140
AC		 1114 if (piix_check_450nx_errata(pdev)) {
1115 /* This writes into the master table but it does not
1116 really matter for this errata as we will apply it to
1117 all the PIIX devices on the board */
d33f58b8
TH		 1118 port_info[0].mwdma_mask = 0;
1119 port_info[0].udma_mask = 0;
1120 port_info[1].mwdma_mask = 0;
1121 port_info[1].udma_mask = 0;
c621b140 1122 }
d33f58b8 1123 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 1124}
1125
cca3974e 1126static void piix_host_stop(struct ata_host *host)
d96715c1 1127{
cca3974e 1128 struct piix_host_priv *hpriv = host->private_data;
24dd01bf 1129
cca3974e 1130 ata_host_stop(host);
24dd01bf
JG		 1131
1132 kfree(hpriv);
d96715c1
TH		 1133}
1134
1da177e4
LT		 1135static int __init piix_init(void)
1136{
1137 int rc;
1138
b7887196
PR		 1139 DPRINTK("pci_register_driver\n");
1140 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1141 if (rc)
1142 return rc;
1143
1144 in_module_init = 0;
1145
1146 DPRINTK("done\n");
1147 return 0;
1148}
1149
1da177e4
LT		 1150static void __exit piix_exit(void)
1151{
1152 pci_unregister_driver(&piix_pci_driver);
1153}
1154
1155module_init(piix_init);
1156module_exit(piix_exit);
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