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libata: More IVB horkage from TSST
[net-next-2.6.git] / drivers / ata / ata_piix.c
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1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
b8b275ef 94#include <linux/dmi.h>
1da177e4
LT		 95
96#define DRV_NAME "ata_piix"
2a3103ce 97#define DRV_VERSION "2.12"
1da177e4
LT		 98
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 103 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 104
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 108
800b3996
TH		 109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 111
1da177e4
LT		 112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b 121 /* controller IDs */
00242ec8
TH		 122 piix_pata_mwdma = 0, /* PIIX3 MWDMA only */
123 piix_pata_33, /* PIIX4 at 33Mhz */
124 ich_pata_33, /* ICH up to UDMA 33 only */
125 ich_pata_66, /* ICH up to 66 Mhz */
126 ich_pata_100, /* ICH up to UDMA 100 */
127 ich5_sata,
128 ich6_sata,
129 ich6_sata_ahci,
130 ich6m_sata_ahci,
131 ich8_sata_ahci,
132 ich8_2port_sata,
8d8ef2fb 133 ich8m_apple_sata_ahci, /* locks up on second port enable */
00242ec8 134 tolapai_sata_ahci,
85cd7251 135
d33f58b8
TH		 136 /* constants for mapping table */
137 P0 = 0, /* port 0 */
138 P1 = 1, /* port 1 */
139 P2 = 2, /* port 2 */
140 P3 = 3, /* port 3 */
141 IDE = -1, /* IDE */
142 NA = -2, /* not avaliable */
143 RV = -3, /* reserved */
144
7b6dbd68 145 PIIX_AHCI_DEVICE = 6,
b8b275ef
TH		 146
147 /* host->flags bits */
148 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
1da177e4
LT		 149};
150
d33f58b8
TH		 151struct piix_map_db {
152 const u32 mask;
73291a1c 153 const u16 port_enable;
d33f58b8
TH		 154 const int map[][4];
155};
156
d96715c1
TH		 157struct piix_host_priv {
158 const int *map;
159};
160
2dcb407e
JG		 161static int piix_init_one(struct pci_dev *pdev,
162 const struct pci_device_id *ent);
ccc4672a 163static void piix_pata_error_handler(struct ata_port *ap);
2dcb407e
JG		 164static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
165static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
166static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
eb4a2c7f 167static int ich_pata_cable_detect(struct ata_port *ap);
b8b275ef
TH		 168#ifdef CONFIG_PM
169static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
170static int piix_pci_device_resume(struct pci_dev *pdev);
171#endif
1da177e4
LT		 172
173static unsigned int in_module_init = 1;
174
3b7d697d 175static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
AC		 176 /* Intel PIIX3 for the 430HX etc */
177 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
669a5db4
JG		 178 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
179 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
180 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 181 /* Intel PIIX4 */
182 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel PIIX4 */
184 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
185 /* Intel PIIX */
186 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
187 /* Intel ICH (i810, i815, i840) UDMA 66*/
188 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
189 /* Intel ICH0 : UDMA 33*/
190 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
191 /* Intel ICH2M */
192 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
194 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH3M */
196 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH3 (E7500/1) UDMA 100 */
198 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
200 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* Intel ICH5 */
2eb829e9 203 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4
JG		 204 /* C-ICH (i810E2) */
205 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 206 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 207 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* ICH6 (and 6) (i915) UDMA 100 */
209 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* ICH7/7-R (i945, i975) UDMA 100*/
2eb829e9 211 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4 212 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
c1e6f28c
CL		 213 /* ICH8 Mobile PATA Controller */
214 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 215
216 /* NOTE: The following PCI ids must be kept in sync with the
217 * list in drivers/pci/quirks.c.
218 */
219
1d076e5b 220 /* 82801EB (ICH5) */
1da177e4 221 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 222 /* 82801EB (ICH5) */
1da177e4 223 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 224 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 225 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 226 /* 6300ESB pretending RAID */
5e56a37c 227 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 228 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 229 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 230 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 231 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 232 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
233 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
234 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 235 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 236 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 237 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 238 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 239 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 240 /* SATA Controller 1 IDE (ICH8) */
08f12edc 241 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 242 /* SATA Controller 2 IDE (ICH8) */
00242ec8 243 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 244 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 245 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
8d8ef2fb
TR		 246 /* Mobile SATA Controller IDE (ICH8M), Apple */
247 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
f98b6573
JG		 248 /* SATA Controller IDE (ICH9) */
249 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
250 /* SATA Controller IDE (ICH9) */
00242ec8 251 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 252 /* SATA Controller IDE (ICH9) */
00242ec8 253 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 254 /* SATA Controller IDE (ICH9M) */
00242ec8 255 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 256 /* SATA Controller IDE (ICH9M) */
00242ec8 257 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573
JG		 258 /* SATA Controller IDE (ICH9M) */
259 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
c5cf0ffa
JG		 260 /* SATA Controller IDE (Tolapai) */
261 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
1da177e4
LT		 262
263 { } /* terminate list */
264};
265
266static struct pci_driver piix_pci_driver = {
267 .name = DRV_NAME,
268 .id_table = piix_pci_tbl,
269 .probe = piix_init_one,
270 .remove = ata_pci_remove_one,
438ac6d5 271#ifdef CONFIG_PM
b8b275ef
TH		 272 .suspend = piix_pci_device_suspend,
273 .resume = piix_pci_device_resume,
438ac6d5 274#endif
1da177e4
LT		 275};
276
193515d5 277static struct scsi_host_template piix_sht = {
1da177e4
LT		 278 .module = THIS_MODULE,
279 .name = DRV_NAME,
280 .ioctl = ata_scsi_ioctl,
281 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 282 .can_queue = ATA_DEF_QUEUE,
283 .this_id = ATA_SHT_THIS_ID,
284 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 285 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
286 .emulated = ATA_SHT_EMULATED,
287 .use_clustering = ATA_SHT_USE_CLUSTERING,
288 .proc_name = DRV_NAME,
289 .dma_boundary = ATA_DMA_BOUNDARY,
290 .slave_configure = ata_scsi_slave_config,
ccf68c34 291 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 292 .bios_param = ata_std_bios_param,
1da177e4
LT		 293};
294
057ace5e 295static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 296 .set_piomode = piix_set_piomode,
297 .set_dmamode = piix_set_dmamode,
89bad589 298 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 299
300 .tf_load = ata_tf_load,
301 .tf_read = ata_tf_read,
302 .check_status = ata_check_status,
303 .exec_command = ata_exec_command,
304 .dev_select = ata_std_dev_select,
305
1da177e4
LT		 306 .bmdma_setup = ata_bmdma_setup,
307 .bmdma_start = ata_bmdma_start,
308 .bmdma_stop = ata_bmdma_stop,
309 .bmdma_status = ata_bmdma_status,
310 .qc_prep = ata_qc_prep,
311 .qc_issue = ata_qc_issue_prot,
0d5ff566 312 .data_xfer = ata_data_xfer,
1da177e4 313
3f037db0
TH		 314 .freeze = ata_bmdma_freeze,
315 .thaw = ata_bmdma_thaw,
ccc4672a 316 .error_handler = piix_pata_error_handler,
3f037db0 317 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 318 .cable_detect = ata_cable_40wire,
1da177e4
LT		 319
320 .irq_handler = ata_interrupt,
321 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 322 .irq_on = ata_irq_on,
1da177e4
LT		 323
324 .port_start = ata_port_start,
1da177e4
LT		 325};
326
669a5db4 327static const struct ata_port_operations ich_pata_ops = {
669a5db4
JG		 328 .set_piomode = piix_set_piomode,
329 .set_dmamode = ich_set_dmamode,
330 .mode_filter = ata_pci_default_filter,
331
332 .tf_load = ata_tf_load,
333 .tf_read = ata_tf_read,
334 .check_status = ata_check_status,
335 .exec_command = ata_exec_command,
336 .dev_select = ata_std_dev_select,
337
338 .bmdma_setup = ata_bmdma_setup,
339 .bmdma_start = ata_bmdma_start,
340 .bmdma_stop = ata_bmdma_stop,
341 .bmdma_status = ata_bmdma_status,
342 .qc_prep = ata_qc_prep,
343 .qc_issue = ata_qc_issue_prot,
0d5ff566 344 .data_xfer = ata_data_xfer,
669a5db4
JG		 345
346 .freeze = ata_bmdma_freeze,
347 .thaw = ata_bmdma_thaw,
eb4a2c7f 348 .error_handler = piix_pata_error_handler,
669a5db4 349 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 350 .cable_detect = ich_pata_cable_detect,
669a5db4
JG		 351
352 .irq_handler = ata_interrupt,
353 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 354 .irq_on = ata_irq_on,
669a5db4
JG		 355
356 .port_start = ata_port_start,
669a5db4
JG		 357};
358
057ace5e 359static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 360 .tf_load = ata_tf_load,
361 .tf_read = ata_tf_read,
362 .check_status = ata_check_status,
363 .exec_command = ata_exec_command,
364 .dev_select = ata_std_dev_select,
365
1da177e4
LT		 366 .bmdma_setup = ata_bmdma_setup,
367 .bmdma_start = ata_bmdma_start,
368 .bmdma_stop = ata_bmdma_stop,
369 .bmdma_status = ata_bmdma_status,
370 .qc_prep = ata_qc_prep,
371 .qc_issue = ata_qc_issue_prot,
0d5ff566 372 .data_xfer = ata_data_xfer,
1da177e4 373
3f037db0
TH		 374 .freeze = ata_bmdma_freeze,
375 .thaw = ata_bmdma_thaw,
2f91d81d 376 .error_handler = ata_bmdma_error_handler,
3f037db0 377 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 378
379 .irq_handler = ata_interrupt,
380 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 381 .irq_on = ata_irq_on,
1da177e4
LT		 382
383 .port_start = ata_port_start,
1da177e4
LT		 384};
385
d96715c1 386static const struct piix_map_db ich5_map_db = {
d33f58b8 387 .mask = 0x7,
ea35d29e 388 .port_enable = 0x3,
d33f58b8
TH		 389 .map = {
390 /* PM PS SM SS MAP */
391 { P0, NA, P1, NA }, /* 000b */
392 { P1, NA, P0, NA }, /* 001b */
393 { RV, RV, RV, RV },
394 { RV, RV, RV, RV },
395 { P0, P1, IDE, IDE }, /* 100b */
396 { P1, P0, IDE, IDE }, /* 101b */
397 { IDE, IDE, P0, P1 }, /* 110b */
398 { IDE, IDE, P1, P0 }, /* 111b */
399 },
400};
401
d96715c1 402static const struct piix_map_db ich6_map_db = {
d33f58b8 403 .mask = 0x3,
ea35d29e 404 .port_enable = 0xf,
d33f58b8
TH		 405 .map = {
406 /* PM PS SM SS MAP */
79ea24e7 407 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 408 { IDE, IDE, P1, P3 }, /* 01b */
409 { P0, P2, IDE, IDE }, /* 10b */
410 { RV, RV, RV, RV },
411 },
412};
413
d96715c1 414static const struct piix_map_db ich6m_map_db = {
d33f58b8 415 .mask = 0x3,
ea35d29e 416 .port_enable = 0x5,
67083741
TH		 417
418 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 419 * it anyway. MAP 01b have been spotted on both ICH6M and
420 * ICH7M.
67083741
TH		 421 */
422 .map = {
423 /* PM PS SM SS MAP */
e04b3b9d 424 { P0, P2, NA, NA }, /* 00b */
67083741
TH		 425 { IDE, IDE, P1, P3 }, /* 01b */
426 { P0, P2, IDE, IDE }, /* 10b */
427 { RV, RV, RV, RV },
428 },
429};
430
08f12edc
JG		 431static const struct piix_map_db ich8_map_db = {
432 .mask = 0x3,
a0ce9aca 433 .port_enable = 0xf,
08f12edc
JG		 434 .map = {
435 /* PM PS SM SS MAP */
158f30c8 436 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 437 { RV, RV, RV, RV },
ac2b0437 438 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
08f12edc
JG		 439 { RV, RV, RV, RV },
440 },
441};
442
00242ec8 443static const struct piix_map_db ich8_2port_map_db = {
e2d352af
JG		 444 .mask = 0x3,
445 .port_enable = 0x3,
446 .map = {
447 /* PM PS SM SS MAP */
448 { P0, NA, P1, NA }, /* 00b */
449 { RV, RV, RV, RV }, /* 01b */
450 { RV, RV, RV, RV }, /* 10b */
451 { RV, RV, RV, RV },
452 },
c5cf0ffa
JG		 453};
454
8d8ef2fb
TR		 455static const struct piix_map_db ich8m_apple_map_db = {
456 .mask = 0x3,
457 .port_enable = 0x1,
458 .map = {
459 /* PM PS SM SS MAP */
460 { P0, NA, NA, NA }, /* 00b */
461 { RV, RV, RV, RV },
462 { P0, P2, IDE, IDE }, /* 10b */
463 { RV, RV, RV, RV },
464 },
465};
466
00242ec8 467static const struct piix_map_db tolapai_map_db = {
8f73a688
JG		 468 .mask = 0x3,
469 .port_enable = 0x3,
470 .map = {
471 /* PM PS SM SS MAP */
472 { P0, NA, P1, NA }, /* 00b */
473 { RV, RV, RV, RV }, /* 01b */
474 { RV, RV, RV, RV }, /* 10b */
475 { RV, RV, RV, RV },
476 },
477};
478
d96715c1
TH		 479static const struct piix_map_db *piix_map_db_table[] = {
480 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 481 [ich6_sata] = &ich6_map_db,
482 [ich6_sata_ahci] = &ich6_map_db,
483 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 484 [ich8_sata_ahci] = &ich8_map_db,
00242ec8 485 [ich8_2port_sata] = &ich8_2port_map_db,
8d8ef2fb 486 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
c5cf0ffa 487 [tolapai_sata_ahci] = &tolapai_map_db,
d96715c1
TH		 488};
489
1da177e4 490static struct ata_port_info piix_port_info[] = {
00242ec8
TH		 491 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
492 {
493 .sht = &piix_sht,
494 .flags = PIIX_PATA_FLAGS,
495 .pio_mask = 0x1f, /* pio0-4 */
496 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
497 .port_ops = &piix_pata_ops,
498 },
499
ec300d99 500 [piix_pata_33] = /* PIIX4 at 33MHz */
1d076e5b
TH		 501 {
502 .sht = &piix_sht,
b3362f88 503 .flags = PIIX_PATA_FLAGS,
1d076e5b 504 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 505 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 506 .udma_mask = ATA_UDMA_MASK_40C,
507 .port_ops = &piix_pata_ops,
508 },
509
ec300d99 510 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
669a5db4
JG		 511 {
512 .sht = &piix_sht,
b3362f88 513 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 514 .pio_mask = 0x1f, /* pio 0-4 */
515 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
516 .udma_mask = ATA_UDMA2, /* UDMA33 */
517 .port_ops = &ich_pata_ops,
518 },
ec300d99
JG		 519
520 [ich_pata_66] = /* ICH controllers up to 66MHz */
1da177e4
LT		 521 {
522 .sht = &piix_sht,
b3362f88 523 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 524 .pio_mask = 0x1f, /* pio 0-4 */
525 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
526 .udma_mask = ATA_UDMA4,
527 .port_ops = &ich_pata_ops,
528 },
85cd7251 529
ec300d99 530 [ich_pata_100] =
669a5db4
JG		 531 {
532 .sht = &piix_sht,
b3362f88 533 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 534 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 535 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 536 .udma_mask = ATA_UDMA5, /* udma0-5 */
537 .port_ops = &ich_pata_ops,
1da177e4
LT		 538 },
539
ec300d99 540 [ich5_sata] =
1da177e4
LT		 541 {
542 .sht = &piix_sht,
228c1590 543 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 544 .pio_mask = 0x1f, /* pio0-4 */
545 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 546 .udma_mask = ATA_UDMA6,
1da177e4
LT		 547 .port_ops = &piix_sata_ops,
548 },
549
ec300d99 550 [ich6_sata] =
1da177e4
LT		 551 {
552 .sht = &piix_sht,
b3362f88 553 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 554 .pio_mask = 0x1f, /* pio0-4 */
555 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 556 .udma_mask = ATA_UDMA6,
1da177e4
LT		 557 .port_ops = &piix_sata_ops,
558 },
559
ec300d99 560 [ich6_sata_ahci] =
c368ca4e
JG		 561 {
562 .sht = &piix_sht,
b3362f88 563 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 564 PIIX_FLAG_AHCI,
c368ca4e
JG		 565 .pio_mask = 0x1f, /* pio0-4 */
566 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 567 .udma_mask = ATA_UDMA6,
c368ca4e
JG		 568 .port_ops = &piix_sata_ops,
569 },
1d076e5b 570
ec300d99 571 [ich6m_sata_ahci] =
1d076e5b
TH		 572 {
573 .sht = &piix_sht,
b3362f88 574 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 575 PIIX_FLAG_AHCI,
1d076e5b
TH		 576 .pio_mask = 0x1f, /* pio0-4 */
577 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 578 .udma_mask = ATA_UDMA6,
1d076e5b
TH		 579 .port_ops = &piix_sata_ops,
580 },
08f12edc 581
ec300d99 582 [ich8_sata_ahci] =
08f12edc
JG		 583 {
584 .sht = &piix_sht,
b3362f88 585 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 586 PIIX_FLAG_AHCI,
587 .pio_mask = 0x1f, /* pio0-4 */
588 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 589 .udma_mask = ATA_UDMA6,
08f12edc
JG		 590 .port_ops = &piix_sata_ops,
591 },
669a5db4 592
00242ec8 593 [ich8_2port_sata] =
c5cf0ffa
JG		 594 {
595 .sht = &piix_sht,
596 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
597 PIIX_FLAG_AHCI,
598 .pio_mask = 0x1f, /* pio0-4 */
599 .mwdma_mask = 0x07, /* mwdma0-2 */
600 .udma_mask = ATA_UDMA6,
601 .port_ops = &piix_sata_ops,
602 },
8f73a688 603
00242ec8 604 [tolapai_sata_ahci] =
8f73a688
JG		 605 {
606 .sht = &piix_sht,
607 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
608 PIIX_FLAG_AHCI,
609 .pio_mask = 0x1f, /* pio0-4 */
610 .mwdma_mask = 0x07, /* mwdma0-2 */
611 .udma_mask = ATA_UDMA6,
612 .port_ops = &piix_sata_ops,
613 },
8d8ef2fb
TR		 614
615 [ich8m_apple_sata_ahci] =
616 {
617 .sht = &piix_sht,
618 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
619 PIIX_FLAG_AHCI,
620 .pio_mask = 0x1f, /* pio0-4 */
621 .mwdma_mask = 0x07, /* mwdma0-2 */
622 .udma_mask = ATA_UDMA6,
623 .port_ops = &piix_sata_ops,
624 },
625
1da177e4
LT		 626};
627
628static struct pci_bits piix_enable_bits[] = {
629 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
630 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
631};
632
633MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
634MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
635MODULE_LICENSE("GPL");
636MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
637MODULE_VERSION(DRV_VERSION);
638
fc085150
AC		 639struct ich_laptop {
640 u16 device;
641 u16 subvendor;
642 u16 subdevice;
643};
644
645/*
646 * List of laptops that use short cables rather than 80 wire
647 */
648
649static const struct ich_laptop ich_laptop[] = {
650 /* devid, subvendor, subdev */
651 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
2655e2ce 652 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
babfb682 653 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
12340106 654 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
54174db3 655 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
b33620f9 656 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
fc085150
AC		 657 /* end marker */
658 { 0, }
659};
660
1da177e4 661/**
eb4a2c7f 662 * ich_pata_cable_detect - Probe host controller cable detect info
1da177e4
LT		 663 * @ap: Port for which cable detect info is desired
664 *
665 * Read 80c cable indicator from ATA PCI device's PCI config
666 * register. This register is normally set by firmware (BIOS).
667 *
668 * LOCKING:
669 * None (inherited from caller).
670 */
669a5db4 671
eb4a2c7f 672static int ich_pata_cable_detect(struct ata_port *ap)
1da177e4 673{
cca3974e 674 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 675 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 676 u8 tmp, mask;
677
fc085150
AC		 678 /* Check for specials - Acer Aspire 5602WLMi */
679 while (lap->device) {
680 if (lap->device == pdev->device &&
681 lap->subvendor == pdev->subsystem_vendor &&
2dcb407e 682 lap->subdevice == pdev->subsystem_device)
eb4a2c7f 683 return ATA_CBL_PATA40_SHORT;
2dcb407e 684
fc085150
AC		 685 lap++;
686 }
687
1da177e4 688 /* check BIOS cable detect results */
2a88d1ac 689 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 690 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
691 if ((tmp & mask) == 0)
eb4a2c7f
AC		 692 return ATA_CBL_PATA40;
693 return ATA_CBL_PATA80;
1da177e4
LT		 694}
695
696/**
ccc4672a 697 * piix_pata_prereset - prereset for PATA host controller
cc0680a5 698 * @link: Target link
d4b2bab4 699 * @deadline: deadline jiffies for the operation
1da177e4 700 *
573db6b8
TH		 701 * LOCKING:
702 * None (inherited from caller).
703 */
cc0680a5 704static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
1da177e4 705{
cc0680a5 706 struct ata_port *ap = link->ap;
cca3974e 707 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 708
c961922b
AC		 709 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
710 return -ENOENT;
cc0680a5 711 return ata_std_prereset(link, deadline);
ccc4672a
TH		 712}
713
714static void piix_pata_error_handler(struct ata_port *ap)
715{
716 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
717 ata_std_postreset);
1da177e4
LT		 718}
719
1da177e4
LT		 720/**
721 * piix_set_piomode - Initialize host controller PATA PIO timings
722 * @ap: Port whose timings we are configuring
723 * @adev: um
1da177e4
LT		 724 *
725 * Set PIO mode for device, in host controller PCI config space.
726 *
727 * LOCKING:
728 * None (inherited from caller).
729 */
730
2dcb407e 731static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
1da177e4
LT		 732{
733 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 734 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 735 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 736 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 737 unsigned int slave_port = 0x44;
738 u16 master_data;
739 u8 slave_data;
669a5db4
JG		 740 u8 udma_enable;
741 int control = 0;
85cd7251 742
669a5db4
JG		 743 /*
744 * See Intel Document 298600-004 for the timing programing rules
745 * for ICH controllers.
746 */
1da177e4
LT		 747
748 static const /* ISP RTC */
749 u8 timings[][2] = { { 0, 0 },
750 { 0, 0 },
751 { 1, 0 },
752 { 2, 1 },
753 { 2, 3 }, };
754
669a5db4
JG		 755 if (pio >= 2)
756 control |= 1; /* TIME1 enable */
757 if (ata_pio_need_iordy(adev))
758 control |= 2; /* IE enable */
759
85cd7251 760 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 761 if (adev->class == ATA_DEV_ATA)
762 control |= 4; /* PPE enable */
763
a5bf5f5a
TH		 764 /* PIO configuration clears DTE unconditionally. It will be
765 * programmed in set_dmamode which is guaranteed to be called
766 * after set_piomode if any DMA mode is available.
767 */
1da177e4
LT		 768 pci_read_config_word(dev, master_port, &master_data);
769 if (is_slave) {
a5bf5f5a
TH		 770 /* clear TIME1|IE1|PPE1|DTE1 */
771 master_data &= 0xff0f;
669a5db4 772 /* Enable SITRE (seperate slave timing register) */
1da177e4 773 master_data |= 0x4000;
669a5db4
JG		 774 /* enable PPE1, IE1 and TIME1 as needed */
775 master_data |= (control << 4);
1da177e4 776 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 777 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4 778 /* Load the timing nibble for this slave */
a5bf5f5a
TH		 779 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
780 << (ap->port_no ? 4 : 0);
1da177e4 781 } else {
a5bf5f5a
TH		 782 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
783 master_data &= 0xccf0;
669a5db4
JG		 784 /* Enable PPE, IE and TIME as appropriate */
785 master_data |= control;
a5bf5f5a 786 /* load ISP and RCT */
1da177e4
LT		 787 master_data |=
788 (timings[pio][0] << 12) |
789 (timings[pio][1] << 8);
790 }
791 pci_write_config_word(dev, master_port, master_data);
792 if (is_slave)
793 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 794
795 /* Ensure the UDMA bit is off - it will be turned back on if
796 UDMA is selected */
85cd7251 797
669a5db4
JG		 798 if (ap->udma_mask) {
799 pci_read_config_byte(dev, 0x48, &udma_enable);
800 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
801 pci_write_config_byte(dev, 0x48, udma_enable);
802 }
1da177e4
LT		 803}
804
805/**
669a5db4 806 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 807 * @ap: Port whose timings we are configuring
669a5db4 808 * @adev: Drive in question
1da177e4 809 * @udma: udma mode, 0 - 6
c32a8fd7 810 * @isich: set if the chip is an ICH device
1da177e4
LT		 811 *
812 * Set UDMA mode for device, in host controller PCI config space.
813 *
814 * LOCKING:
815 * None (inherited from caller).
816 */
817
2dcb407e 818static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 819{
cca3974e 820 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 821 u8 master_port = ap->port_no ? 0x42 : 0x40;
822 u16 master_data;
823 u8 speed = adev->dma_mode;
824 int devid = adev->devno + 2 * ap->port_no;
dedf61db 825 u8 udma_enable = 0;
85cd7251 826
669a5db4
JG		 827 static const /* ISP RTC */
828 u8 timings[][2] = { { 0, 0 },
829 { 0, 0 },
830 { 1, 0 },
831 { 2, 1 },
832 { 2, 3 }, };
833
834 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
AC		 835 if (ap->udma_mask)
836 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 837
838 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 839 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
840 u16 udma_timing;
841 u16 ideconf;
842 int u_clock, u_speed;
85cd7251 843
669a5db4 844 /*
2dcb407e 845 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 846 * selection of dividers
847 *
669a5db4 848 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 849 * except UDMA0 which is 00
669a5db4
JG		 850 */
851 u_speed = min(2 - (udma & 1), udma);
852 if (udma == 5)
853 u_clock = 0x1000; /* 100Mhz */
854 else if (udma > 2)
855 u_clock = 1; /* 66Mhz */
856 else
857 u_clock = 0; /* 33Mhz */
85cd7251 858
669a5db4 859 udma_enable |= (1 << devid);
85cd7251 860
669a5db4
JG		 861 /* Load the CT/RP selection */
862 pci_read_config_word(dev, 0x4A, &udma_timing);
863 udma_timing &= ~(3 << (4 * devid));
864 udma_timing |= u_speed << (4 * devid);
865 pci_write_config_word(dev, 0x4A, udma_timing);
866
85cd7251 867 if (isich) {
669a5db4
JG		 868 /* Select a 33/66/100Mhz clock */
869 pci_read_config_word(dev, 0x54, &ideconf);
870 ideconf &= ~(0x1001 << devid);
871 ideconf |= u_clock << devid;
872 /* For ICH or later we should set bit 10 for better
873 performance (WR_PingPong_En) */
874 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 875 }
1da177e4 876 } else {
669a5db4
JG		 877 /*
878 * MWDMA is driven by the PIO timings. We must also enable
879 * IORDY unconditionally along with TIME1. PPE has already
880 * been set when the PIO timing was set.
881 */
882 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
883 unsigned int control;
884 u8 slave_data;
885 const unsigned int needed_pio[3] = {
886 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
887 };
888 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 889
669a5db4 890 control = 3; /* IORDY|TIME1 */
85cd7251 891
669a5db4
JG		 892 /* If the drive MWDMA is faster than it can do PIO then
893 we must force PIO into PIO0 */
85cd7251 894
669a5db4
JG		 895 if (adev->pio_mode < needed_pio[mwdma])
896 /* Enable DMA timing only */
897 control |= 8; /* PIO cycles in PIO0 */
898
899 if (adev->devno) { /* Slave */
900 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
901 master_data |= control << 4;
902 pci_read_config_byte(dev, 0x44, &slave_data);
a5bf5f5a 903 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 904 /* Load the matching timing */
905 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
906 pci_write_config_byte(dev, 0x44, slave_data);
907 } else { /* Master */
85cd7251 908 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 909 and master timing bits */
910 master_data |= control;
911 master_data |=
912 (timings[pio][0] << 12) |
913 (timings[pio][1] << 8);
914 }
a5bf5f5a
TH		 915
916 if (ap->udma_mask) {
917 udma_enable &= ~(1 << devid);
918 pci_write_config_word(dev, master_port, master_data);
919 }
1da177e4 920 }
669a5db4
JG		 921 /* Don't scribble on 0x48 if the controller does not support UDMA */
922 if (ap->udma_mask)
923 pci_write_config_byte(dev, 0x48, udma_enable);
924}
925
926/**
927 * piix_set_dmamode - Initialize host controller PATA DMA timings
928 * @ap: Port whose timings we are configuring
929 * @adev: um
930 *
931 * Set MW/UDMA mode for device, in host controller PCI config space.
932 *
933 * LOCKING:
934 * None (inherited from caller).
935 */
936
2dcb407e 937static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 938{
939 do_pata_set_dmamode(ap, adev, 0);
940}
941
942/**
943 * ich_set_dmamode - Initialize host controller PATA DMA timings
944 * @ap: Port whose timings we are configuring
945 * @adev: um
946 *
947 * Set MW/UDMA mode for device, in host controller PCI config space.
948 *
949 * LOCKING:
950 * None (inherited from caller).
951 */
952
2dcb407e 953static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 954{
955 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 956}
957
b8b275ef 958#ifdef CONFIG_PM
8c3832eb
TH		 959static int piix_broken_suspend(void)
960{
1855256c 961 static const struct dmi_system_id sysids[] = {
4c74d4ec
TH		 962 {
963 .ident = "TECRA M3",
964 .matches = {
965 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
966 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
967 },
968 },
8c3832eb
TH		 969 {
970 .ident = "TECRA M5",
971 .matches = {
972 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
974 },
b8b275ef 975 },
5c08ea01
TH		 976 {
977 .ident = "TECRA M7",
978 .matches = {
979 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
981 },
982 },
3cc0b9d3
TH		 983 {
984 .ident = "Satellite U200",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
988 },
989 },
62320e23
YC		 990 {
991 .ident = "Satellite Pro U200",
992 .matches = {
993 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
994 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
995 },
996 },
8c3832eb
TH		 997 {
998 .ident = "Satellite U205",
999 .matches = {
1000 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1001 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1002 },
b8b275ef 1003 },
de753e5e
TH		 1004 {
1005 .ident = "SATELLITE U205",
1006 .matches = {
1007 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1008 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1009 },
1010 },
8c3832eb
TH		 1011 {
1012 .ident = "Portege M500",
1013 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1016 },
b8b275ef 1017 },
7d051548
JG		 1018
1019 { } /* terminate list */
8c3832eb 1020 };
7abe79c3
TH		 1021 static const char *oemstrs[] = {
1022 "Tecra M3,",
1023 };
1024 int i;
8c3832eb
TH		 1025
1026 if (dmi_check_system(sysids))
1027 return 1;
1028
7abe79c3
TH		 1029 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1030 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1031 return 1;
1032
8c3832eb
TH		 1033 return 0;
1034}
b8b275ef
TH		 1035
1036static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1037{
1038 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1039 unsigned long flags;
1040 int rc = 0;
1041
1042 rc = ata_host_suspend(host, mesg);
1043 if (rc)
1044 return rc;
1045
1046 /* Some braindamaged ACPI suspend implementations expect the
1047 * controller to be awake on entry; otherwise, it burns cpu
1048 * cycles and power trying to do something to the sleeping
1049 * beauty.
1050 */
8c3832eb 1051 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
b8b275ef
TH		 1052 pci_save_state(pdev);
1053
1054 /* mark its power state as "unknown", since we don't
1055 * know if e.g. the BIOS will change its device state
1056 * when we suspend.
1057 */
1058 if (pdev->current_state == PCI_D0)
1059 pdev->current_state = PCI_UNKNOWN;
1060
1061 /* tell resume that it's waking up from broken suspend */
1062 spin_lock_irqsave(&host->lock, flags);
1063 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1064 spin_unlock_irqrestore(&host->lock, flags);
1065 } else
1066 ata_pci_device_do_suspend(pdev, mesg);
1067
1068 return 0;
1069}
1070
1071static int piix_pci_device_resume(struct pci_dev *pdev)
1072{
1073 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1074 unsigned long flags;
1075 int rc;
1076
1077 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1078 spin_lock_irqsave(&host->lock, flags);
1079 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1080 spin_unlock_irqrestore(&host->lock, flags);
1081
1082 pci_set_power_state(pdev, PCI_D0);
1083 pci_restore_state(pdev);
1084
1085 /* PCI device wasn't disabled during suspend. Use
0b62e13b
TH		 1086 * pci_reenable_device() to avoid affecting the enable
1087 * count.
b8b275ef 1088 */
0b62e13b 1089 rc = pci_reenable_device(pdev);
b8b275ef
TH		 1090 if (rc)
1091 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1092 "device after resume (%d)\n", rc);
1093 } else
1094 rc = ata_pci_device_do_resume(pdev);
1095
1096 if (rc == 0)
1097 ata_host_resume(host);
1098
1099 return rc;
1100}
1101#endif
1102
1da177e4
LT		 1103#define AHCI_PCI_BAR 5
1104#define AHCI_GLOBAL_CTL 0x04
1105#define AHCI_ENABLE (1 << 31)
1106static int piix_disable_ahci(struct pci_dev *pdev)
1107{
ea6ba10b 1108 void __iomem *mmio;
1da177e4
LT		 1109 u32 tmp;
1110 int rc = 0;
1111
1112 /* BUG: pci_enable_device has not yet been called. This
1113 * works because this device is usually set up by BIOS.
1114 */
1115
374b1873
JG		 1116 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1117 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 1118 return 0;
7b6dbd68 1119
374b1873 1120 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 1121 if (!mmio)
1122 return -ENOMEM;
7b6dbd68 1123
c47a631f 1124 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1da177e4
LT		 1125 if (tmp & AHCI_ENABLE) {
1126 tmp &= ~AHCI_ENABLE;
c47a631f 1127 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1da177e4 1128
c47a631f 1129 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1da177e4
LT		 1130 if (tmp & AHCI_ENABLE)
1131 rc = -EIO;
1132 }
7b6dbd68 1133
374b1873 1134 pci_iounmap(pdev, mmio);
1da177e4
LT		 1135 return rc;
1136}
1137
c621b140
AC		 1138/**
1139 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 1140 * @ata_dev: the PCI device to check
2e9edbf8 1141 *
c621b140
AC		 1142 * Check for the present of 450NX errata #19 and errata #25. If
1143 * they are found return an error code so we can turn off DMA
1144 */
1145
1146static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1147{
1148 struct pci_dev *pdev = NULL;
1149 u16 cfg;
c621b140 1150 int no_piix_dma = 0;
2e9edbf8 1151
2dcb407e 1152 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
c621b140
AC		 1153 /* Look for 450NX PXB. Check for problem configurations
1154 A PCI quirk checks bit 6 already */
c621b140
AC		 1155 pci_read_config_word(pdev, 0x41, &cfg);
1156 /* Only on the original revision: IDE DMA can hang */
44c10138 1157 if (pdev->revision == 0x00)
c621b140
AC		 1158 no_piix_dma = 1;
1159 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138 1160 else if (cfg & (1<<14) && pdev->revision < 5)
c621b140
AC		 1161 no_piix_dma = 2;
1162 }
31a34fe7 1163 if (no_piix_dma)
c621b140 1164 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 1165 if (no_piix_dma == 2)
c621b140
AC		 1166 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1167 return no_piix_dma;
2e9edbf8 1168}
c621b140 1169
ea35d29e 1170static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 1171 struct ata_port_info *pinfo,
ea35d29e
JG		 1172 const struct piix_map_db *map_db)
1173{
1174 u16 pcs, new_pcs;
1175
1176 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1177
1178 new_pcs = pcs | map_db->port_enable;
1179
1180 if (new_pcs != pcs) {
1181 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1182 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1183 msleep(150);
1184 }
1185}
1186
d33f58b8 1187static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 1188 struct ata_port_info *pinfo,
1189 const struct piix_map_db *map_db)
d33f58b8 1190{
d96715c1 1191 struct piix_host_priv *hpriv = pinfo[0].private_data;
b4482a4b 1192 const int *map;
d33f58b8
TH		 1193 int i, invalid_map = 0;
1194 u8 map_value;
1195
1196 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1197
1198 map = map_db->map[map_value & map_db->mask];
1199
1200 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1201 for (i = 0; i < 4; i++) {
1202 switch (map[i]) {
1203 case RV:
1204 invalid_map = 1;
1205 printk(" XX");
1206 break;
1207
1208 case NA:
1209 printk(" --");
1210 break;
1211
1212 case IDE:
1213 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1214 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1215 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1216 i++;
1217 printk(" IDE IDE");
1218 break;
1219
1220 default:
1221 printk(" P%d", map[i]);
1222 if (i & 1)
cca3974e 1223 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1224 break;
1225 }
1226 }
1227 printk(" ]\n");
1228
1229 if (invalid_map)
1230 dev_printk(KERN_ERR, &pdev->dev,
1231 "invalid MAP value %u\n", map_value);
1232
d96715c1 1233 hpriv->map = map;
d33f58b8
TH		 1234}
1235
43a98f05
TH		 1236static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1237{
1855256c 1238 static const struct dmi_system_id sysids[] = {
43a98f05
TH		 1239 {
1240 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1241 * isn't used to boot the system which
1242 * disables the channel.
1243 */
1244 .ident = "M570U",
1245 .matches = {
1246 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1247 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1248 },
1249 },
7d051548
JG		 1250
1251 { } /* terminate list */
43a98f05
TH		 1252 };
1253 u32 iocfg;
1254
1255 if (!dmi_check_system(sysids))
1256 return;
1257
1258 /* The datasheet says that bit 18 is NOOP but certain systems
1259 * seem to use it to disable a channel. Clear the bit on the
1260 * affected systems.
1261 */
1262 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1263 if (iocfg & (1 << 18)) {
1264 dev_printk(KERN_INFO, &pdev->dev,
1265 "applying IOCFG bit18 quirk\n");
1266 iocfg &= ~(1 << 18);
1267 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1268 }
1269}
1270
1da177e4
LT		 1271/**
1272 * piix_init_one - Register PIIX ATA PCI device with kernel services
1273 * @pdev: PCI device to register
1274 * @ent: Entry in piix_pci_tbl matching with @pdev
1275 *
1276 * Called from kernel PCI layer. We probe for combined mode (sigh),
1277 * and then hand over control to libata, for it to do the rest.
1278 *
1279 * LOCKING:
1280 * Inherited from PCI layer (may sleep).
1281 *
1282 * RETURNS:
1283 * Zero on success, or -ERRNO value.
1284 */
1285
2dcb407e 1286static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1287{
1288 static int printed_version;
24dc5f33 1289 struct device *dev = &pdev->dev;
d33f58b8 1290 struct ata_port_info port_info[2];
1626aeb8 1291 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
d96715c1 1292 struct piix_host_priv *hpriv;
cca3974e 1293 unsigned long port_flags;
1da177e4
LT		 1294
1295 if (!printed_version++)
6248e647
JG		 1296 dev_printk(KERN_DEBUG, &pdev->dev,
1297 "version " DRV_VERSION "\n");
1da177e4
LT		 1298
1299 /* no hotplugging support (FIXME) */
1300 if (!in_module_init)
1301 return -ENODEV;
1302
24dc5f33 1303 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1304 if (!hpriv)
1305 return -ENOMEM;
1306
d33f58b8
TH		 1307 port_info[0] = piix_port_info[ent->driver_data];
1308 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1309 port_info[0].private_data = hpriv;
1310 port_info[1].private_data = hpriv;
1da177e4 1311
cca3974e 1312 port_flags = port_info[0].flags;
ff0fc146 1313
cca3974e 1314 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1315 u8 tmp;
1316 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1317 if (tmp == PIIX_AHCI_DEVICE) {
1318 int rc = piix_disable_ahci(pdev);
1319 if (rc)
1320 return rc;
1321 }
1da177e4
LT		 1322 }
1323
d33f58b8 1324 /* Initialize SATA map */
cca3974e 1325 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1326 piix_init_sata_map(pdev, port_info,
1327 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1328 piix_init_pcs(pdev, port_info,
1329 piix_map_db_table[ent->driver_data]);
ea35d29e 1330 }
1da177e4 1331
43a98f05
TH		 1332 /* apply IOCFG bit18 quirk */
1333 piix_iocfg_bit18_quirk(pdev);
1334
1da177e4
LT		 1335 /* On ICH5, some BIOSen disable the interrupt using the
1336 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1337 * On ICH6, this bit has the same effect, but only when
1338 * MSI is disabled (and it is disabled, as we don't use
1339 * message-signalled interrupts currently).
1340 */
cca3974e 1341 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1342 pci_intx(pdev, 1);
1da177e4 1343
c621b140
AC		 1344 if (piix_check_450nx_errata(pdev)) {
1345 /* This writes into the master table but it does not
1346 really matter for this errata as we will apply it to
1347 all the PIIX devices on the board */
d33f58b8
TH		 1348 port_info[0].mwdma_mask = 0;
1349 port_info[0].udma_mask = 0;
1350 port_info[1].mwdma_mask = 0;
1351 port_info[1].udma_mask = 0;
c621b140 1352 }
1626aeb8 1353 return ata_pci_init_one(pdev, ppi);
1da177e4
LT		 1354}
1355
1da177e4
LT		 1356static int __init piix_init(void)
1357{
1358 int rc;
1359
b7887196
PR		 1360 DPRINTK("pci_register_driver\n");
1361 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1362 if (rc)
1363 return rc;
1364
1365 in_module_init = 0;
1366
1367 DPRINTK("done\n");
1368 return 0;
1369}
1370
1da177e4
LT		 1371static void __exit piix_exit(void)
1372{
1373 pci_unregister_driver(&piix_pci_driver);
1374}
1375
1376module_init(piix_init);
1377module_exit(piix_exit);
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