]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/ata/ata_piix.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
libata: factor out ata_pci_activate_sff_host() from ata_pci_one()
[net-next-2.6.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
b8b275ef 94#include <linux/dmi.h>
1da177e4
LT		 95
96#define DRV_NAME "ata_piix"
2a3103ce 97#define DRV_VERSION "2.12"
1da177e4
LT		 98
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 103 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 104
ff0fc146
TH		 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 107
800b3996
TH		 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 110
1da177e4
LT		 111 PIIX_80C_PRI = (1 << 5) | (1 << 4),
112 PIIX_80C_SEC = (1 << 7) | (1 << 6),
113
d33f58b8
TH		 114 /* constants for mapping table */
115 P0 = 0, /* port 0 */
116 P1 = 1, /* port 1 */
117 P2 = 2, /* port 2 */
118 P3 = 3, /* port 3 */
119 IDE = -1, /* IDE */
120 NA = -2, /* not avaliable */
121 RV = -3, /* reserved */
122
7b6dbd68 123 PIIX_AHCI_DEVICE = 6,
b8b275ef
TH		 124
125 /* host->flags bits */
126 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
1da177e4
LT		 127};
128
9cde9ed1
TH		 129enum piix_controller_ids {
130 /* controller IDs */
131 piix_pata_mwdma, /* PIIX3 MWDMA only */
132 piix_pata_33, /* PIIX4 at 33Mhz */
133 ich_pata_33, /* ICH up to UDMA 33 only */
134 ich_pata_66, /* ICH up to 66 Mhz */
135 ich_pata_100, /* ICH up to UDMA 100 */
136 ich5_sata,
137 ich6_sata,
138 ich6_sata_ahci,
139 ich6m_sata_ahci,
140 ich8_sata_ahci,
141 ich8_2port_sata,
142 ich8m_apple_sata_ahci, /* locks up on second port enable */
143 tolapai_sata_ahci,
144 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
145};
146
d33f58b8
TH		 147struct piix_map_db {
148 const u32 mask;
73291a1c 149 const u16 port_enable;
d33f58b8
TH		 150 const int map[][4];
151};
152
d96715c1
TH		 153struct piix_host_priv {
154 const int *map;
155};
156
2dcb407e
JG		 157static int piix_init_one(struct pci_dev *pdev,
158 const struct pci_device_id *ent);
ccc4672a 159static void piix_pata_error_handler(struct ata_port *ap);
2dcb407e
JG		 160static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
161static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
162static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
eb4a2c7f 163static int ich_pata_cable_detect(struct ata_port *ap);
25f98131 164static u8 piix_vmw_bmdma_status(struct ata_port *ap);
b8b275ef
TH		 165#ifdef CONFIG_PM
166static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
167static int piix_pci_device_resume(struct pci_dev *pdev);
168#endif
1da177e4
LT		 169
170static unsigned int in_module_init = 1;
171
3b7d697d 172static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
AC		 173 /* Intel PIIX3 for the 430HX etc */
174 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
25f98131
TH		 175 /* VMware ICH4 */
176 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
669a5db4
JG		 177 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
178 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
179 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 180 /* Intel PIIX4 */
181 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel PIIX4 */
183 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
184 /* Intel PIIX */
185 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
186 /* Intel ICH (i810, i815, i840) UDMA 66*/
187 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
188 /* Intel ICH0 : UDMA 33*/
189 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
190 /* Intel ICH2M */
191 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
193 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH3M */
195 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* Intel ICH3 (E7500/1) UDMA 100 */
197 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH5 */
2eb829e9 202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4
JG		 203 /* C-ICH (i810E2) */
204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* ICH6 (and 6) (i915) UDMA 100 */
208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* ICH7/7-R (i945, i975) UDMA 100*/
2eb829e9 210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4 211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
c1e6f28c
CL		 212 /* ICH8 Mobile PATA Controller */
213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 214
215 /* NOTE: The following PCI ids must be kept in sync with the
216 * list in drivers/pci/quirks.c.
217 */
218
1d076e5b 219 /* 82801EB (ICH5) */
1da177e4 220 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 221 /* 82801EB (ICH5) */
1da177e4 222 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 223 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 224 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 225 /* 6300ESB pretending RAID */
5e56a37c 226 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 227 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 228 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 229 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 230 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 231 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 237 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 239 /* SATA Controller 1 IDE (ICH8) */
08f12edc 240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 241 /* SATA Controller 2 IDE (ICH8) */
00242ec8 242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 243 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 244 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
8d8ef2fb
TR		 245 /* Mobile SATA Controller IDE (ICH8M), Apple */
246 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
f98b6573
JG		 247 /* SATA Controller IDE (ICH9) */
248 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
249 /* SATA Controller IDE (ICH9) */
00242ec8 250 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 251 /* SATA Controller IDE (ICH9) */
00242ec8 252 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 253 /* SATA Controller IDE (ICH9M) */
00242ec8 254 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 255 /* SATA Controller IDE (ICH9M) */
00242ec8 256 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573
JG		 257 /* SATA Controller IDE (ICH9M) */
258 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
c5cf0ffa
JG		 259 /* SATA Controller IDE (Tolapai) */
260 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
1da177e4
LT		 261
262 { } /* terminate list */
263};
264
265static struct pci_driver piix_pci_driver = {
266 .name = DRV_NAME,
267 .id_table = piix_pci_tbl,
268 .probe = piix_init_one,
269 .remove = ata_pci_remove_one,
438ac6d5 270#ifdef CONFIG_PM
b8b275ef
TH		 271 .suspend = piix_pci_device_suspend,
272 .resume = piix_pci_device_resume,
438ac6d5 273#endif
1da177e4
LT		 274};
275
193515d5 276static struct scsi_host_template piix_sht = {
1da177e4
LT		 277 .module = THIS_MODULE,
278 .name = DRV_NAME,
279 .ioctl = ata_scsi_ioctl,
280 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 281 .can_queue = ATA_DEF_QUEUE,
282 .this_id = ATA_SHT_THIS_ID,
283 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 284 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
285 .emulated = ATA_SHT_EMULATED,
286 .use_clustering = ATA_SHT_USE_CLUSTERING,
287 .proc_name = DRV_NAME,
288 .dma_boundary = ATA_DMA_BOUNDARY,
289 .slave_configure = ata_scsi_slave_config,
ccf68c34 290 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 291 .bios_param = ata_std_bios_param,
1da177e4
LT		 292};
293
057ace5e 294static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 295 .set_piomode = piix_set_piomode,
296 .set_dmamode = piix_set_dmamode,
89bad589 297 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 298
299 .tf_load = ata_tf_load,
300 .tf_read = ata_tf_read,
301 .check_status = ata_check_status,
302 .exec_command = ata_exec_command,
303 .dev_select = ata_std_dev_select,
304
1da177e4
LT		 305 .bmdma_setup = ata_bmdma_setup,
306 .bmdma_start = ata_bmdma_start,
307 .bmdma_stop = ata_bmdma_stop,
308 .bmdma_status = ata_bmdma_status,
309 .qc_prep = ata_qc_prep,
310 .qc_issue = ata_qc_issue_prot,
0d5ff566 311 .data_xfer = ata_data_xfer,
1da177e4 312
3f037db0
TH		 313 .freeze = ata_bmdma_freeze,
314 .thaw = ata_bmdma_thaw,
ccc4672a 315 .error_handler = piix_pata_error_handler,
3f037db0 316 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 317 .cable_detect = ata_cable_40wire,
1da177e4
LT		 318
319 .irq_handler = ata_interrupt,
320 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 321 .irq_on = ata_irq_on,
1da177e4
LT		 322
323 .port_start = ata_port_start,
1da177e4
LT		 324};
325
669a5db4 326static const struct ata_port_operations ich_pata_ops = {
669a5db4
JG		 327 .set_piomode = piix_set_piomode,
328 .set_dmamode = ich_set_dmamode,
329 .mode_filter = ata_pci_default_filter,
330
331 .tf_load = ata_tf_load,
332 .tf_read = ata_tf_read,
333 .check_status = ata_check_status,
334 .exec_command = ata_exec_command,
335 .dev_select = ata_std_dev_select,
336
337 .bmdma_setup = ata_bmdma_setup,
338 .bmdma_start = ata_bmdma_start,
339 .bmdma_stop = ata_bmdma_stop,
340 .bmdma_status = ata_bmdma_status,
341 .qc_prep = ata_qc_prep,
342 .qc_issue = ata_qc_issue_prot,
0d5ff566 343 .data_xfer = ata_data_xfer,
669a5db4
JG		 344
345 .freeze = ata_bmdma_freeze,
346 .thaw = ata_bmdma_thaw,
eb4a2c7f 347 .error_handler = piix_pata_error_handler,
669a5db4 348 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 349 .cable_detect = ich_pata_cable_detect,
669a5db4
JG		 350
351 .irq_handler = ata_interrupt,
352 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 353 .irq_on = ata_irq_on,
669a5db4
JG		 354
355 .port_start = ata_port_start,
669a5db4
JG		 356};
357
057ace5e 358static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 359 .tf_load = ata_tf_load,
360 .tf_read = ata_tf_read,
361 .check_status = ata_check_status,
362 .exec_command = ata_exec_command,
363 .dev_select = ata_std_dev_select,
364
1da177e4
LT		 365 .bmdma_setup = ata_bmdma_setup,
366 .bmdma_start = ata_bmdma_start,
367 .bmdma_stop = ata_bmdma_stop,
368 .bmdma_status = ata_bmdma_status,
369 .qc_prep = ata_qc_prep,
370 .qc_issue = ata_qc_issue_prot,
0d5ff566 371 .data_xfer = ata_data_xfer,
1da177e4 372
3f037db0
TH		 373 .freeze = ata_bmdma_freeze,
374 .thaw = ata_bmdma_thaw,
2f91d81d 375 .error_handler = ata_bmdma_error_handler,
3f037db0 376 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 377
378 .irq_handler = ata_interrupt,
379 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 380 .irq_on = ata_irq_on,
1da177e4
LT		 381
382 .port_start = ata_port_start,
1da177e4
LT		 383};
384
25f98131
TH		 385static const struct ata_port_operations piix_vmw_ops = {
386 .set_piomode = piix_set_piomode,
387 .set_dmamode = piix_set_dmamode,
388 .mode_filter = ata_pci_default_filter,
389
390 .tf_load = ata_tf_load,
391 .tf_read = ata_tf_read,
392 .check_status = ata_check_status,
393 .exec_command = ata_exec_command,
394 .dev_select = ata_std_dev_select,
395
396 .bmdma_setup = ata_bmdma_setup,
397 .bmdma_start = ata_bmdma_start,
398 .bmdma_stop = ata_bmdma_stop,
399 .bmdma_status = piix_vmw_bmdma_status,
400 .qc_prep = ata_qc_prep,
401 .qc_issue = ata_qc_issue_prot,
402 .data_xfer = ata_data_xfer,
403
404 .freeze = ata_bmdma_freeze,
405 .thaw = ata_bmdma_thaw,
406 .error_handler = piix_pata_error_handler,
407 .post_internal_cmd = ata_bmdma_post_internal_cmd,
408 .cable_detect = ata_cable_40wire,
409
410 .irq_handler = ata_interrupt,
411 .irq_clear = ata_bmdma_irq_clear,
412 .irq_on = ata_irq_on,
413
414 .port_start = ata_port_start,
415};
416
d96715c1 417static const struct piix_map_db ich5_map_db = {
d33f58b8 418 .mask = 0x7,
ea35d29e 419 .port_enable = 0x3,
d33f58b8
TH		 420 .map = {
421 /* PM PS SM SS MAP */
422 { P0, NA, P1, NA }, /* 000b */
423 { P1, NA, P0, NA }, /* 001b */
424 { RV, RV, RV, RV },
425 { RV, RV, RV, RV },
426 { P0, P1, IDE, IDE }, /* 100b */
427 { P1, P0, IDE, IDE }, /* 101b */
428 { IDE, IDE, P0, P1 }, /* 110b */
429 { IDE, IDE, P1, P0 }, /* 111b */
430 },
431};
432
d96715c1 433static const struct piix_map_db ich6_map_db = {
d33f58b8 434 .mask = 0x3,
ea35d29e 435 .port_enable = 0xf,
d33f58b8
TH		 436 .map = {
437 /* PM PS SM SS MAP */
79ea24e7 438 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 439 { IDE, IDE, P1, P3 }, /* 01b */
440 { P0, P2, IDE, IDE }, /* 10b */
441 { RV, RV, RV, RV },
442 },
443};
444
d96715c1 445static const struct piix_map_db ich6m_map_db = {
d33f58b8 446 .mask = 0x3,
ea35d29e 447 .port_enable = 0x5,
67083741
TH		 448
449 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 450 * it anyway. MAP 01b have been spotted on both ICH6M and
451 * ICH7M.
67083741
TH		 452 */
453 .map = {
454 /* PM PS SM SS MAP */
e04b3b9d 455 { P0, P2, NA, NA }, /* 00b */
67083741
TH		 456 { IDE, IDE, P1, P3 }, /* 01b */
457 { P0, P2, IDE, IDE }, /* 10b */
458 { RV, RV, RV, RV },
459 },
460};
461
08f12edc
JG		 462static const struct piix_map_db ich8_map_db = {
463 .mask = 0x3,
a0ce9aca 464 .port_enable = 0xf,
08f12edc
JG		 465 .map = {
466 /* PM PS SM SS MAP */
158f30c8 467 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 468 { RV, RV, RV, RV },
ac2b0437 469 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
08f12edc
JG		 470 { RV, RV, RV, RV },
471 },
472};
473
00242ec8 474static const struct piix_map_db ich8_2port_map_db = {
e2d352af
JG		 475 .mask = 0x3,
476 .port_enable = 0x3,
477 .map = {
478 /* PM PS SM SS MAP */
479 { P0, NA, P1, NA }, /* 00b */
480 { RV, RV, RV, RV }, /* 01b */
481 { RV, RV, RV, RV }, /* 10b */
482 { RV, RV, RV, RV },
483 },
c5cf0ffa
JG		 484};
485
8d8ef2fb
TR		 486static const struct piix_map_db ich8m_apple_map_db = {
487 .mask = 0x3,
488 .port_enable = 0x1,
489 .map = {
490 /* PM PS SM SS MAP */
491 { P0, NA, NA, NA }, /* 00b */
492 { RV, RV, RV, RV },
493 { P0, P2, IDE, IDE }, /* 10b */
494 { RV, RV, RV, RV },
495 },
496};
497
00242ec8 498static const struct piix_map_db tolapai_map_db = {
8f73a688
JG		 499 .mask = 0x3,
500 .port_enable = 0x3,
501 .map = {
502 /* PM PS SM SS MAP */
503 { P0, NA, P1, NA }, /* 00b */
504 { RV, RV, RV, RV }, /* 01b */
505 { RV, RV, RV, RV }, /* 10b */
506 { RV, RV, RV, RV },
507 },
508};
509
d96715c1
TH		 510static const struct piix_map_db *piix_map_db_table[] = {
511 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 512 [ich6_sata] = &ich6_map_db,
513 [ich6_sata_ahci] = &ich6_map_db,
514 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 515 [ich8_sata_ahci] = &ich8_map_db,
00242ec8 516 [ich8_2port_sata] = &ich8_2port_map_db,
8d8ef2fb 517 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
c5cf0ffa 518 [tolapai_sata_ahci] = &tolapai_map_db,
d96715c1
TH		 519};
520
1da177e4 521static struct ata_port_info piix_port_info[] = {
00242ec8
TH		 522 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
523 {
524 .sht = &piix_sht,
525 .flags = PIIX_PATA_FLAGS,
526 .pio_mask = 0x1f, /* pio0-4 */
527 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
528 .port_ops = &piix_pata_ops,
529 },
530
ec300d99 531 [piix_pata_33] = /* PIIX4 at 33MHz */
1d076e5b
TH		 532 {
533 .sht = &piix_sht,
b3362f88 534 .flags = PIIX_PATA_FLAGS,
1d076e5b 535 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 536 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 537 .udma_mask = ATA_UDMA_MASK_40C,
538 .port_ops = &piix_pata_ops,
539 },
540
ec300d99 541 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
669a5db4
JG		 542 {
543 .sht = &piix_sht,
b3362f88 544 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 545 .pio_mask = 0x1f, /* pio 0-4 */
546 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
547 .udma_mask = ATA_UDMA2, /* UDMA33 */
548 .port_ops = &ich_pata_ops,
549 },
ec300d99
JG		 550
551 [ich_pata_66] = /* ICH controllers up to 66MHz */
1da177e4
LT		 552 {
553 .sht = &piix_sht,
b3362f88 554 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 555 .pio_mask = 0x1f, /* pio 0-4 */
556 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
557 .udma_mask = ATA_UDMA4,
558 .port_ops = &ich_pata_ops,
559 },
85cd7251 560
ec300d99 561 [ich_pata_100] =
669a5db4
JG		 562 {
563 .sht = &piix_sht,
b3362f88 564 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 565 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 566 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 567 .udma_mask = ATA_UDMA5, /* udma0-5 */
568 .port_ops = &ich_pata_ops,
1da177e4
LT		 569 },
570
ec300d99 571 [ich5_sata] =
1da177e4
LT		 572 {
573 .sht = &piix_sht,
228c1590 574 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 575 .pio_mask = 0x1f, /* pio0-4 */
576 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 577 .udma_mask = ATA_UDMA6,
1da177e4
LT		 578 .port_ops = &piix_sata_ops,
579 },
580
ec300d99 581 [ich6_sata] =
1da177e4
LT		 582 {
583 .sht = &piix_sht,
723159c5 584 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 585 .pio_mask = 0x1f, /* pio0-4 */
586 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 587 .udma_mask = ATA_UDMA6,
1da177e4
LT		 588 .port_ops = &piix_sata_ops,
589 },
590
ec300d99 591 [ich6_sata_ahci] =
c368ca4e
JG		 592 {
593 .sht = &piix_sht,
723159c5 594 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
c368ca4e
JG		 595 .pio_mask = 0x1f, /* pio0-4 */
596 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 597 .udma_mask = ATA_UDMA6,
c368ca4e
JG		 598 .port_ops = &piix_sata_ops,
599 },
1d076e5b 600
ec300d99 601 [ich6m_sata_ahci] =
1d076e5b
TH		 602 {
603 .sht = &piix_sht,
723159c5 604 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
1d076e5b
TH		 605 .pio_mask = 0x1f, /* pio0-4 */
606 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 607 .udma_mask = ATA_UDMA6,
1d076e5b
TH		 608 .port_ops = &piix_sata_ops,
609 },
08f12edc 610
ec300d99 611 [ich8_sata_ahci] =
08f12edc
JG		 612 {
613 .sht = &piix_sht,
723159c5 614 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
08f12edc
JG		 615 .pio_mask = 0x1f, /* pio0-4 */
616 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 617 .udma_mask = ATA_UDMA6,
08f12edc
JG		 618 .port_ops = &piix_sata_ops,
619 },
669a5db4 620
00242ec8 621 [ich8_2port_sata] =
c5cf0ffa
JG		 622 {
623 .sht = &piix_sht,
723159c5 624 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
c5cf0ffa
JG		 625 .pio_mask = 0x1f, /* pio0-4 */
626 .mwdma_mask = 0x07, /* mwdma0-2 */
627 .udma_mask = ATA_UDMA6,
628 .port_ops = &piix_sata_ops,
629 },
8f73a688 630
00242ec8 631 [tolapai_sata_ahci] =
8f73a688
JG		 632 {
633 .sht = &piix_sht,
723159c5 634 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
8f73a688
JG		 635 .pio_mask = 0x1f, /* pio0-4 */
636 .mwdma_mask = 0x07, /* mwdma0-2 */
637 .udma_mask = ATA_UDMA6,
638 .port_ops = &piix_sata_ops,
639 },
8d8ef2fb
TR		 640
641 [ich8m_apple_sata_ahci] =
642 {
643 .sht = &piix_sht,
723159c5 644 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
8d8ef2fb
TR		 645 .pio_mask = 0x1f, /* pio0-4 */
646 .mwdma_mask = 0x07, /* mwdma0-2 */
647 .udma_mask = ATA_UDMA6,
648 .port_ops = &piix_sata_ops,
649 },
650
25f98131
TH		 651 [piix_pata_vmw] =
652 {
653 .sht = &piix_sht,
654 .flags = PIIX_PATA_FLAGS,
655 .pio_mask = 0x1f, /* pio0-4 */
656 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
657 .udma_mask = ATA_UDMA_MASK_40C,
658 .port_ops = &piix_vmw_ops,
659 },
660
1da177e4
LT		 661};
662
663static struct pci_bits piix_enable_bits[] = {
664 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
665 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
666};
667
668MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
669MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
670MODULE_LICENSE("GPL");
671MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
672MODULE_VERSION(DRV_VERSION);
673
fc085150
AC		 674struct ich_laptop {
675 u16 device;
676 u16 subvendor;
677 u16 subdevice;
678};
679
680/*
681 * List of laptops that use short cables rather than 80 wire
682 */
683
684static const struct ich_laptop ich_laptop[] = {
685 /* devid, subvendor, subdev */
686 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
2655e2ce 687 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
babfb682 688 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
12340106 689 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
54174db3 690 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
b33620f9 691 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
fc085150
AC		 692 /* end marker */
693 { 0, }
694};
695
1da177e4 696/**
eb4a2c7f 697 * ich_pata_cable_detect - Probe host controller cable detect info
1da177e4
LT		 698 * @ap: Port for which cable detect info is desired
699 *
700 * Read 80c cable indicator from ATA PCI device's PCI config
701 * register. This register is normally set by firmware (BIOS).
702 *
703 * LOCKING:
704 * None (inherited from caller).
705 */
669a5db4 706
eb4a2c7f 707static int ich_pata_cable_detect(struct ata_port *ap)
1da177e4 708{
cca3974e 709 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 710 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 711 u8 tmp, mask;
712
fc085150
AC		 713 /* Check for specials - Acer Aspire 5602WLMi */
714 while (lap->device) {
715 if (lap->device == pdev->device &&
716 lap->subvendor == pdev->subsystem_vendor &&
2dcb407e 717 lap->subdevice == pdev->subsystem_device)
eb4a2c7f 718 return ATA_CBL_PATA40_SHORT;
2dcb407e 719
fc085150
AC		 720 lap++;
721 }
722
1da177e4 723 /* check BIOS cable detect results */
2a88d1ac 724 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 725 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
726 if ((tmp & mask) == 0)
eb4a2c7f
AC		 727 return ATA_CBL_PATA40;
728 return ATA_CBL_PATA80;
1da177e4
LT		 729}
730
731/**
ccc4672a 732 * piix_pata_prereset - prereset for PATA host controller
cc0680a5 733 * @link: Target link
d4b2bab4 734 * @deadline: deadline jiffies for the operation
1da177e4 735 *
573db6b8
TH		 736 * LOCKING:
737 * None (inherited from caller).
738 */
cc0680a5 739static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
1da177e4 740{
cc0680a5 741 struct ata_port *ap = link->ap;
cca3974e 742 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 743
c961922b
AC		 744 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
745 return -ENOENT;
cc0680a5 746 return ata_std_prereset(link, deadline);
ccc4672a
TH		 747}
748
749static void piix_pata_error_handler(struct ata_port *ap)
750{
751 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
752 ata_std_postreset);
1da177e4
LT		 753}
754
1da177e4
LT		 755/**
756 * piix_set_piomode - Initialize host controller PATA PIO timings
757 * @ap: Port whose timings we are configuring
758 * @adev: um
1da177e4
LT		 759 *
760 * Set PIO mode for device, in host controller PCI config space.
761 *
762 * LOCKING:
763 * None (inherited from caller).
764 */
765
2dcb407e 766static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
1da177e4
LT		 767{
768 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 769 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 770 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 771 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 772 unsigned int slave_port = 0x44;
773 u16 master_data;
774 u8 slave_data;
669a5db4
JG		 775 u8 udma_enable;
776 int control = 0;
85cd7251 777
669a5db4
JG		 778 /*
779 * See Intel Document 298600-004 for the timing programing rules
780 * for ICH controllers.
781 */
1da177e4
LT		 782
783 static const /* ISP RTC */
784 u8 timings[][2] = { { 0, 0 },
785 { 0, 0 },
786 { 1, 0 },
787 { 2, 1 },
788 { 2, 3 }, };
789
669a5db4
JG		 790 if (pio >= 2)
791 control |= 1; /* TIME1 enable */
792 if (ata_pio_need_iordy(adev))
793 control |= 2; /* IE enable */
794
85cd7251 795 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 796 if (adev->class == ATA_DEV_ATA)
797 control |= 4; /* PPE enable */
798
a5bf5f5a
TH		 799 /* PIO configuration clears DTE unconditionally. It will be
800 * programmed in set_dmamode which is guaranteed to be called
801 * after set_piomode if any DMA mode is available.
802 */
1da177e4
LT		 803 pci_read_config_word(dev, master_port, &master_data);
804 if (is_slave) {
a5bf5f5a
TH		 805 /* clear TIME1|IE1|PPE1|DTE1 */
806 master_data &= 0xff0f;
669a5db4 807 /* Enable SITRE (seperate slave timing register) */
1da177e4 808 master_data |= 0x4000;
669a5db4
JG		 809 /* enable PPE1, IE1 and TIME1 as needed */
810 master_data |= (control << 4);
1da177e4 811 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 812 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4 813 /* Load the timing nibble for this slave */
a5bf5f5a
TH		 814 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
815 << (ap->port_no ? 4 : 0);
1da177e4 816 } else {
a5bf5f5a
TH		 817 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
818 master_data &= 0xccf0;
669a5db4
JG		 819 /* Enable PPE, IE and TIME as appropriate */
820 master_data |= control;
a5bf5f5a 821 /* load ISP and RCT */
1da177e4
LT		 822 master_data |=
823 (timings[pio][0] << 12) |
824 (timings[pio][1] << 8);
825 }
826 pci_write_config_word(dev, master_port, master_data);
827 if (is_slave)
828 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 829
830 /* Ensure the UDMA bit is off - it will be turned back on if
831 UDMA is selected */
85cd7251 832
669a5db4
JG		 833 if (ap->udma_mask) {
834 pci_read_config_byte(dev, 0x48, &udma_enable);
835 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
836 pci_write_config_byte(dev, 0x48, udma_enable);
837 }
1da177e4
LT		 838}
839
840/**
669a5db4 841 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 842 * @ap: Port whose timings we are configuring
669a5db4 843 * @adev: Drive in question
1da177e4 844 * @udma: udma mode, 0 - 6
c32a8fd7 845 * @isich: set if the chip is an ICH device
1da177e4
LT		 846 *
847 * Set UDMA mode for device, in host controller PCI config space.
848 *
849 * LOCKING:
850 * None (inherited from caller).
851 */
852
2dcb407e 853static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 854{
cca3974e 855 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 856 u8 master_port = ap->port_no ? 0x42 : 0x40;
857 u16 master_data;
858 u8 speed = adev->dma_mode;
859 int devid = adev->devno + 2 * ap->port_no;
dedf61db 860 u8 udma_enable = 0;
85cd7251 861
669a5db4
JG		 862 static const /* ISP RTC */
863 u8 timings[][2] = { { 0, 0 },
864 { 0, 0 },
865 { 1, 0 },
866 { 2, 1 },
867 { 2, 3 }, };
868
869 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
AC		 870 if (ap->udma_mask)
871 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 872
873 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 874 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
875 u16 udma_timing;
876 u16 ideconf;
877 int u_clock, u_speed;
85cd7251 878
669a5db4 879 /*
2dcb407e 880 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 881 * selection of dividers
882 *
669a5db4 883 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 884 * except UDMA0 which is 00
669a5db4
JG		 885 */
886 u_speed = min(2 - (udma & 1), udma);
887 if (udma == 5)
888 u_clock = 0x1000; /* 100Mhz */
889 else if (udma > 2)
890 u_clock = 1; /* 66Mhz */
891 else
892 u_clock = 0; /* 33Mhz */
85cd7251 893
669a5db4 894 udma_enable |= (1 << devid);
85cd7251 895
669a5db4
JG		 896 /* Load the CT/RP selection */
897 pci_read_config_word(dev, 0x4A, &udma_timing);
898 udma_timing &= ~(3 << (4 * devid));
899 udma_timing |= u_speed << (4 * devid);
900 pci_write_config_word(dev, 0x4A, udma_timing);
901
85cd7251 902 if (isich) {
669a5db4
JG		 903 /* Select a 33/66/100Mhz clock */
904 pci_read_config_word(dev, 0x54, &ideconf);
905 ideconf &= ~(0x1001 << devid);
906 ideconf |= u_clock << devid;
907 /* For ICH or later we should set bit 10 for better
908 performance (WR_PingPong_En) */
909 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 910 }
1da177e4 911 } else {
669a5db4
JG		 912 /*
913 * MWDMA is driven by the PIO timings. We must also enable
914 * IORDY unconditionally along with TIME1. PPE has already
915 * been set when the PIO timing was set.
916 */
917 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
918 unsigned int control;
919 u8 slave_data;
920 const unsigned int needed_pio[3] = {
921 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
922 };
923 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 924
669a5db4 925 control = 3; /* IORDY|TIME1 */
85cd7251 926
669a5db4
JG		 927 /* If the drive MWDMA is faster than it can do PIO then
928 we must force PIO into PIO0 */
85cd7251 929
669a5db4
JG		 930 if (adev->pio_mode < needed_pio[mwdma])
931 /* Enable DMA timing only */
932 control |= 8; /* PIO cycles in PIO0 */
933
934 if (adev->devno) { /* Slave */
935 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
936 master_data |= control << 4;
937 pci_read_config_byte(dev, 0x44, &slave_data);
a5bf5f5a 938 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 939 /* Load the matching timing */
940 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
941 pci_write_config_byte(dev, 0x44, slave_data);
942 } else { /* Master */
85cd7251 943 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 944 and master timing bits */
945 master_data |= control;
946 master_data |=
947 (timings[pio][0] << 12) |
948 (timings[pio][1] << 8);
949 }
a5bf5f5a
TH		 950
951 if (ap->udma_mask) {
952 udma_enable &= ~(1 << devid);
953 pci_write_config_word(dev, master_port, master_data);
954 }
1da177e4 955 }
669a5db4
JG		 956 /* Don't scribble on 0x48 if the controller does not support UDMA */
957 if (ap->udma_mask)
958 pci_write_config_byte(dev, 0x48, udma_enable);
959}
960
961/**
962 * piix_set_dmamode - Initialize host controller PATA DMA timings
963 * @ap: Port whose timings we are configuring
964 * @adev: um
965 *
966 * Set MW/UDMA mode for device, in host controller PCI config space.
967 *
968 * LOCKING:
969 * None (inherited from caller).
970 */
971
2dcb407e 972static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 973{
974 do_pata_set_dmamode(ap, adev, 0);
975}
976
977/**
978 * ich_set_dmamode - Initialize host controller PATA DMA timings
979 * @ap: Port whose timings we are configuring
980 * @adev: um
981 *
982 * Set MW/UDMA mode for device, in host controller PCI config space.
983 *
984 * LOCKING:
985 * None (inherited from caller).
986 */
987
2dcb407e 988static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 989{
990 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 991}
992
b8b275ef 993#ifdef CONFIG_PM
8c3832eb
TH		 994static int piix_broken_suspend(void)
995{
1855256c 996 static const struct dmi_system_id sysids[] = {
4c74d4ec
TH		 997 {
998 .ident = "TECRA M3",
999 .matches = {
1000 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1001 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1002 },
1003 },
04d86d6f
PS		 1004 {
1005 .ident = "TECRA M3",
1006 .matches = {
1007 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1008 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1009 },
1010 },
d1aa690a
PS		 1011 {
1012 .ident = "TECRA M4",
1013 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1016 },
1017 },
8c3832eb
TH		 1018 {
1019 .ident = "TECRA M5",
1020 .matches = {
1021 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1022 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1023 },
b8b275ef 1024 },
ffe188dd
PS		 1025 {
1026 .ident = "TECRA M6",
1027 .matches = {
1028 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1029 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1030 },
1031 },
5c08ea01
TH		 1032 {
1033 .ident = "TECRA M7",
1034 .matches = {
1035 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1036 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1037 },
1038 },
04d86d6f
PS		 1039 {
1040 .ident = "TECRA A8",
1041 .matches = {
1042 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1043 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1044 },
1045 },
ffe188dd
PS		 1046 {
1047 .ident = "Satellite R20",
1048 .matches = {
1049 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1050 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1051 },
1052 },
04d86d6f
PS		 1053 {
1054 .ident = "Satellite R25",
1055 .matches = {
1056 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1057 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1058 },
1059 },
3cc0b9d3
TH		 1060 {
1061 .ident = "Satellite U200",
1062 .matches = {
1063 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1064 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1065 },
1066 },
04d86d6f
PS		 1067 {
1068 .ident = "Satellite U200",
1069 .matches = {
1070 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1071 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1072 },
1073 },
62320e23
YC		 1074 {
1075 .ident = "Satellite Pro U200",
1076 .matches = {
1077 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1078 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1079 },
1080 },
8c3832eb
TH		 1081 {
1082 .ident = "Satellite U205",
1083 .matches = {
1084 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1085 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1086 },
b8b275ef 1087 },
de753e5e
TH		 1088 {
1089 .ident = "SATELLITE U205",
1090 .matches = {
1091 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1092 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1093 },
1094 },
8c3832eb
TH		 1095 {
1096 .ident = "Portege M500",
1097 .matches = {
1098 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1099 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1100 },
b8b275ef 1101 },
7d051548
JG		 1102
1103 { } /* terminate list */
8c3832eb 1104 };
7abe79c3
TH		 1105 static const char *oemstrs[] = {
1106 "Tecra M3,",
1107 };
1108 int i;
8c3832eb
TH		 1109
1110 if (dmi_check_system(sysids))
1111 return 1;
1112
7abe79c3
TH		 1113 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1114 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1115 return 1;
1116
8c3832eb
TH		 1117 return 0;
1118}
b8b275ef
TH		 1119
1120static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1121{
1122 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1123 unsigned long flags;
1124 int rc = 0;
1125
1126 rc = ata_host_suspend(host, mesg);
1127 if (rc)
1128 return rc;
1129
1130 /* Some braindamaged ACPI suspend implementations expect the
1131 * controller to be awake on entry; otherwise, it burns cpu
1132 * cycles and power trying to do something to the sleeping
1133 * beauty.
1134 */
8c3832eb 1135 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
b8b275ef
TH		 1136 pci_save_state(pdev);
1137
1138 /* mark its power state as "unknown", since we don't
1139 * know if e.g. the BIOS will change its device state
1140 * when we suspend.
1141 */
1142 if (pdev->current_state == PCI_D0)
1143 pdev->current_state = PCI_UNKNOWN;
1144
1145 /* tell resume that it's waking up from broken suspend */
1146 spin_lock_irqsave(&host->lock, flags);
1147 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1148 spin_unlock_irqrestore(&host->lock, flags);
1149 } else
1150 ata_pci_device_do_suspend(pdev, mesg);
1151
1152 return 0;
1153}
1154
1155static int piix_pci_device_resume(struct pci_dev *pdev)
1156{
1157 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1158 unsigned long flags;
1159 int rc;
1160
1161 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1162 spin_lock_irqsave(&host->lock, flags);
1163 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1164 spin_unlock_irqrestore(&host->lock, flags);
1165
1166 pci_set_power_state(pdev, PCI_D0);
1167 pci_restore_state(pdev);
1168
1169 /* PCI device wasn't disabled during suspend. Use
0b62e13b
TH		 1170 * pci_reenable_device() to avoid affecting the enable
1171 * count.
b8b275ef 1172 */
0b62e13b 1173 rc = pci_reenable_device(pdev);
b8b275ef
TH		 1174 if (rc)
1175 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1176 "device after resume (%d)\n", rc);
1177 } else
1178 rc = ata_pci_device_do_resume(pdev);
1179
1180 if (rc == 0)
1181 ata_host_resume(host);
1182
1183 return rc;
1184}
1185#endif
1186
25f98131
TH		 1187static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1188{
1189 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1190}
1191
1da177e4
LT		 1192#define AHCI_PCI_BAR 5
1193#define AHCI_GLOBAL_CTL 0x04
1194#define AHCI_ENABLE (1 << 31)
1195static int piix_disable_ahci(struct pci_dev *pdev)
1196{
ea6ba10b 1197 void __iomem *mmio;
1da177e4
LT		 1198 u32 tmp;
1199 int rc = 0;
1200
1201 /* BUG: pci_enable_device has not yet been called. This
1202 * works because this device is usually set up by BIOS.
1203 */
1204
374b1873
JG		 1205 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1206 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 1207 return 0;
7b6dbd68 1208
374b1873 1209 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 1210 if (!mmio)
1211 return -ENOMEM;
7b6dbd68 1212
c47a631f 1213 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1da177e4
LT		 1214 if (tmp & AHCI_ENABLE) {
1215 tmp &= ~AHCI_ENABLE;
c47a631f 1216 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1da177e4 1217
c47a631f 1218 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1da177e4
LT		 1219 if (tmp & AHCI_ENABLE)
1220 rc = -EIO;
1221 }
7b6dbd68 1222
374b1873 1223 pci_iounmap(pdev, mmio);
1da177e4
LT		 1224 return rc;
1225}
1226
c621b140
AC		 1227/**
1228 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 1229 * @ata_dev: the PCI device to check
2e9edbf8 1230 *
c621b140
AC		 1231 * Check for the present of 450NX errata #19 and errata #25. If
1232 * they are found return an error code so we can turn off DMA
1233 */
1234
1235static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1236{
1237 struct pci_dev *pdev = NULL;
1238 u16 cfg;
c621b140 1239 int no_piix_dma = 0;
2e9edbf8 1240
2dcb407e 1241 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
c621b140
AC		 1242 /* Look for 450NX PXB. Check for problem configurations
1243 A PCI quirk checks bit 6 already */
c621b140
AC		 1244 pci_read_config_word(pdev, 0x41, &cfg);
1245 /* Only on the original revision: IDE DMA can hang */
44c10138 1246 if (pdev->revision == 0x00)
c621b140
AC		 1247 no_piix_dma = 1;
1248 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138 1249 else if (cfg & (1<<14) && pdev->revision < 5)
c621b140
AC		 1250 no_piix_dma = 2;
1251 }
31a34fe7 1252 if (no_piix_dma)
c621b140 1253 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 1254 if (no_piix_dma == 2)
c621b140
AC		 1255 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1256 return no_piix_dma;
2e9edbf8 1257}
c621b140 1258
ea35d29e 1259static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 1260 struct ata_port_info *pinfo,
ea35d29e
JG		 1261 const struct piix_map_db *map_db)
1262{
1263 u16 pcs, new_pcs;
1264
1265 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1266
1267 new_pcs = pcs | map_db->port_enable;
1268
1269 if (new_pcs != pcs) {
1270 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1271 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1272 msleep(150);
1273 }
1274}
1275
d33f58b8 1276static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 1277 struct ata_port_info *pinfo,
1278 const struct piix_map_db *map_db)
d33f58b8 1279{
d96715c1 1280 struct piix_host_priv *hpriv = pinfo[0].private_data;
b4482a4b 1281 const int *map;
d33f58b8
TH		 1282 int i, invalid_map = 0;
1283 u8 map_value;
1284
1285 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1286
1287 map = map_db->map[map_value & map_db->mask];
1288
1289 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1290 for (i = 0; i < 4; i++) {
1291 switch (map[i]) {
1292 case RV:
1293 invalid_map = 1;
1294 printk(" XX");
1295 break;
1296
1297 case NA:
1298 printk(" --");
1299 break;
1300
1301 case IDE:
1302 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1303 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1304 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1305 i++;
1306 printk(" IDE IDE");
1307 break;
1308
1309 default:
1310 printk(" P%d", map[i]);
1311 if (i & 1)
cca3974e 1312 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1313 break;
1314 }
1315 }
1316 printk(" ]\n");
1317
1318 if (invalid_map)
1319 dev_printk(KERN_ERR, &pdev->dev,
1320 "invalid MAP value %u\n", map_value);
1321
d96715c1 1322 hpriv->map = map;
d33f58b8
TH		 1323}
1324
43a98f05
TH		 1325static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1326{
1855256c 1327 static const struct dmi_system_id sysids[] = {
43a98f05
TH		 1328 {
1329 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1330 * isn't used to boot the system which
1331 * disables the channel.
1332 */
1333 .ident = "M570U",
1334 .matches = {
1335 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1336 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1337 },
1338 },
7d051548
JG		 1339
1340 { } /* terminate list */
43a98f05
TH		 1341 };
1342 u32 iocfg;
1343
1344 if (!dmi_check_system(sysids))
1345 return;
1346
1347 /* The datasheet says that bit 18 is NOOP but certain systems
1348 * seem to use it to disable a channel. Clear the bit on the
1349 * affected systems.
1350 */
1351 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1352 if (iocfg & (1 << 18)) {
1353 dev_printk(KERN_INFO, &pdev->dev,
1354 "applying IOCFG bit18 quirk\n");
1355 iocfg &= ~(1 << 18);
1356 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1357 }
1358}
1359
1da177e4
LT		 1360/**
1361 * piix_init_one - Register PIIX ATA PCI device with kernel services
1362 * @pdev: PCI device to register
1363 * @ent: Entry in piix_pci_tbl matching with @pdev
1364 *
1365 * Called from kernel PCI layer. We probe for combined mode (sigh),
1366 * and then hand over control to libata, for it to do the rest.
1367 *
1368 * LOCKING:
1369 * Inherited from PCI layer (may sleep).
1370 *
1371 * RETURNS:
1372 * Zero on success, or -ERRNO value.
1373 */
1374
2dcb407e 1375static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1376{
1377 static int printed_version;
24dc5f33 1378 struct device *dev = &pdev->dev;
d33f58b8 1379 struct ata_port_info port_info[2];
1626aeb8 1380 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
d96715c1 1381 struct piix_host_priv *hpriv;
cca3974e 1382 unsigned long port_flags;
1da177e4
LT		 1383
1384 if (!printed_version++)
6248e647
JG		 1385 dev_printk(KERN_DEBUG, &pdev->dev,
1386 "version " DRV_VERSION "\n");
1da177e4
LT		 1387
1388 /* no hotplugging support (FIXME) */
1389 if (!in_module_init)
1390 return -ENODEV;
1391
24dc5f33 1392 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1393 if (!hpriv)
1394 return -ENOMEM;
1395
d33f58b8
TH		 1396 port_info[0] = piix_port_info[ent->driver_data];
1397 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1398 port_info[0].private_data = hpriv;
1399 port_info[1].private_data = hpriv;
1da177e4 1400
cca3974e 1401 port_flags = port_info[0].flags;
ff0fc146 1402
cca3974e 1403 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1404 u8 tmp;
1405 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1406 if (tmp == PIIX_AHCI_DEVICE) {
1407 int rc = piix_disable_ahci(pdev);
1408 if (rc)
1409 return rc;
1410 }
1da177e4
LT		 1411 }
1412
d33f58b8 1413 /* Initialize SATA map */
cca3974e 1414 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1415 piix_init_sata_map(pdev, port_info,
1416 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1417 piix_init_pcs(pdev, port_info,
1418 piix_map_db_table[ent->driver_data]);
ea35d29e 1419 }
1da177e4 1420
43a98f05
TH		 1421 /* apply IOCFG bit18 quirk */
1422 piix_iocfg_bit18_quirk(pdev);
1423
1da177e4
LT		 1424 /* On ICH5, some BIOSen disable the interrupt using the
1425 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1426 * On ICH6, this bit has the same effect, but only when
1427 * MSI is disabled (and it is disabled, as we don't use
1428 * message-signalled interrupts currently).
1429 */
cca3974e 1430 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1431 pci_intx(pdev, 1);
1da177e4 1432
c621b140
AC		 1433 if (piix_check_450nx_errata(pdev)) {
1434 /* This writes into the master table but it does not
1435 really matter for this errata as we will apply it to
1436 all the PIIX devices on the board */
d33f58b8
TH		 1437 port_info[0].mwdma_mask = 0;
1438 port_info[0].udma_mask = 0;
1439 port_info[1].mwdma_mask = 0;
1440 port_info[1].udma_mask = 0;
c621b140 1441 }
1626aeb8 1442 return ata_pci_init_one(pdev, ppi);
1da177e4
LT		 1443}
1444
1da177e4
LT		 1445static int __init piix_init(void)
1446{
1447 int rc;
1448
b7887196
PR		 1449 DPRINTK("pci_register_driver\n");
1450 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1451 if (rc)
1452 return rc;
1453
1454 in_module_init = 0;
1455
1456 DPRINTK("done\n");
1457 return 0;
1458}
1459
1da177e4
LT		 1460static void __exit piix_exit(void)
1461{
1462 pci_unregister_driver(&piix_pci_driver);
1463}
1464
1465module_init(piix_init);
1466module_exit(piix_exit);
Clone of davem's net-next-2.6 tree