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1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
669a5db4 96#define DRV_VERSION "2.00ac6"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
219e6214 104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4
LT		 108
109 /* combined mode. if set, PATA is channel 0.
110 * if clear, PATA is channel 1.
111 */
6a690df5
HR		 112 PIIX_PORT_ENABLED = (1 << 0),
113 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
1d076e5b 118 /* controller IDs */
669a5db4
JG		 119 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
120 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
121 ich_pata_66 = 2, /* ICH up to 66 Mhz */
122 ich_pata_100 = 3, /* ICH up to UDMA 100 */
123 ich_pata_133 = 4, /* ICH up to UDMA 133 */
124 ich5_sata = 5,
125 esb_sata = 6,
126 ich6_sata = 7,
127 ich6_sata_ahci = 8,
128 ich6m_sata_ahci = 9,
129 ich8_sata_ahci = 10,
130
d33f58b8
TH		 131 /* constants for mapping table */
132 P0 = 0, /* port 0 */
133 P1 = 1, /* port 1 */
134 P2 = 2, /* port 2 */
135 P3 = 3, /* port 3 */
136 IDE = -1, /* IDE */
137 NA = -2, /* not avaliable */
138 RV = -3, /* reserved */
139
7b6dbd68 140 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 141};
142
d33f58b8
TH		 143struct piix_map_db {
144 const u32 mask;
73291a1c 145 const u16 port_enable;
08f12edc 146 const int present_shift;
d33f58b8
TH		 147 const int map[][4];
148};
149
d96715c1
TH		 150struct piix_host_priv {
151 const int *map;
08f12edc 152 const struct piix_map_db *map_db;
d96715c1
TH		 153};
154
1da177e4
LT		 155static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
cca3974e 157static void piix_host_stop(struct ata_host *host);
ccc4672a 158static void piix_pata_error_handler(struct ata_port *ap);
669a5db4 159static void ich_pata_error_handler(struct ata_port *ap);
ccc4672a 160static void piix_sata_error_handler(struct ata_port *ap);
669a5db4
JG		 161static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
162static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
163static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
1da177e4
LT		 164
165static unsigned int in_module_init = 1;
166
3b7d697d 167static const struct pci_device_id piix_pci_tbl[] = {
1da177e4 168#ifdef ATA_ENABLE_PATA
669a5db4
JG		 169 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
170 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
171 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
172 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
173 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
174 /* Intel PIIX4 */
175 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
176 /* Intel PIIX4 */
177 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178 /* Intel PIIX */
179 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 /* Intel ICH (i810, i815, i840) UDMA 66*/
181 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
182 /* Intel ICH0 : UDMA 33*/
183 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
184 /* Intel ICH2M */
185 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
186 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
187 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* Intel ICH3M */
189 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190 /* Intel ICH3 (E7500/1) UDMA 100 */
191 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
193 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH5 */
196 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
197 /* C-ICH (i810E2) */
198 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
200 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* ICH6 (and 6) (i915) UDMA 100 */
202 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* ICH7/7-R (i945, i975) UDMA 100*/
204 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
205 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 206#endif
207
208 /* NOTE: The following PCI ids must be kept in sync with the
209 * list in drivers/pci/quirks.c.
210 */
211
1d076e5b 212 /* 82801EB (ICH5) */
1da177e4 213 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 214 /* 82801EB (ICH5) */
1da177e4 215 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b
TH		 216 /* 6300ESB (ICH5 variant with broken PCS present bits) */
217 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
218 /* 6300ESB pretending RAID */
219 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
220 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 221 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 222 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 223 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 224 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
225 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
226 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 227 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 228 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
229 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
230 /* Enterprise Southbridge 2 (where's the datasheet?) */
1c24a412 231 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 232 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
08f12edc 233 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1d076e5b 234 /* SATA Controller 2 IDE (ICH8, ditto) */
08f12edc 235 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1d076e5b 236 /* Mobile SATA Controller IDE (ICH8M, ditto) */
08f12edc 237 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1da177e4
LT		 238
239 { } /* terminate list */
240};
241
242static struct pci_driver piix_pci_driver = {
243 .name = DRV_NAME,
244 .id_table = piix_pci_tbl,
245 .probe = piix_init_one,
246 .remove = ata_pci_remove_one,
9b847548
JA		 247 .suspend = ata_pci_device_suspend,
248 .resume = ata_pci_device_resume,
1da177e4
LT		 249};
250
193515d5 251static struct scsi_host_template piix_sht = {
1da177e4
LT		 252 .module = THIS_MODULE,
253 .name = DRV_NAME,
254 .ioctl = ata_scsi_ioctl,
255 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 256 .can_queue = ATA_DEF_QUEUE,
257 .this_id = ATA_SHT_THIS_ID,
258 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 259 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
260 .emulated = ATA_SHT_EMULATED,
261 .use_clustering = ATA_SHT_USE_CLUSTERING,
262 .proc_name = DRV_NAME,
263 .dma_boundary = ATA_DMA_BOUNDARY,
264 .slave_configure = ata_scsi_slave_config,
ccf68c34 265 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 266 .bios_param = ata_std_bios_param,
9b847548
JA		 267 .resume = ata_scsi_device_resume,
268 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 269};
270
057ace5e 271static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 272 .port_disable = ata_port_disable,
273 .set_piomode = piix_set_piomode,
274 .set_dmamode = piix_set_dmamode,
89bad589 275 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 276
277 .tf_load = ata_tf_load,
278 .tf_read = ata_tf_read,
279 .check_status = ata_check_status,
280 .exec_command = ata_exec_command,
281 .dev_select = ata_std_dev_select,
282
1da177e4
LT		 283 .bmdma_setup = ata_bmdma_setup,
284 .bmdma_start = ata_bmdma_start,
285 .bmdma_stop = ata_bmdma_stop,
286 .bmdma_status = ata_bmdma_status,
287 .qc_prep = ata_qc_prep,
288 .qc_issue = ata_qc_issue_prot,
89bad589 289 .data_xfer = ata_pio_data_xfer,
1da177e4 290
3f037db0
TH		 291 .freeze = ata_bmdma_freeze,
292 .thaw = ata_bmdma_thaw,
ccc4672a 293 .error_handler = piix_pata_error_handler,
3f037db0 294 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 295
296 .irq_handler = ata_interrupt,
297 .irq_clear = ata_bmdma_irq_clear,
298
299 .port_start = ata_port_start,
300 .port_stop = ata_port_stop,
d96715c1 301 .host_stop = piix_host_stop,
1da177e4
LT		 302};
303
669a5db4
JG		 304static const struct ata_port_operations ich_pata_ops = {
305 .port_disable = ata_port_disable,
306 .set_piomode = piix_set_piomode,
307 .set_dmamode = ich_set_dmamode,
308 .mode_filter = ata_pci_default_filter,
309
310 .tf_load = ata_tf_load,
311 .tf_read = ata_tf_read,
312 .check_status = ata_check_status,
313 .exec_command = ata_exec_command,
314 .dev_select = ata_std_dev_select,
315
316 .bmdma_setup = ata_bmdma_setup,
317 .bmdma_start = ata_bmdma_start,
318 .bmdma_stop = ata_bmdma_stop,
319 .bmdma_status = ata_bmdma_status,
320 .qc_prep = ata_qc_prep,
321 .qc_issue = ata_qc_issue_prot,
322 .data_xfer = ata_pio_data_xfer,
323
324 .freeze = ata_bmdma_freeze,
325 .thaw = ata_bmdma_thaw,
326 .error_handler = ich_pata_error_handler,
327 .post_internal_cmd = ata_bmdma_post_internal_cmd,
328
329 .irq_handler = ata_interrupt,
330 .irq_clear = ata_bmdma_irq_clear,
331
332 .port_start = ata_port_start,
333 .port_stop = ata_port_stop,
334 .host_stop = ata_host_stop,
335};
336
057ace5e 337static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 338 .port_disable = ata_port_disable,
339
340 .tf_load = ata_tf_load,
341 .tf_read = ata_tf_read,
342 .check_status = ata_check_status,
343 .exec_command = ata_exec_command,
344 .dev_select = ata_std_dev_select,
345
1da177e4
LT		 346 .bmdma_setup = ata_bmdma_setup,
347 .bmdma_start = ata_bmdma_start,
348 .bmdma_stop = ata_bmdma_stop,
349 .bmdma_status = ata_bmdma_status,
350 .qc_prep = ata_qc_prep,
351 .qc_issue = ata_qc_issue_prot,
89bad589 352 .data_xfer = ata_pio_data_xfer,
1da177e4 353
3f037db0
TH		 354 .freeze = ata_bmdma_freeze,
355 .thaw = ata_bmdma_thaw,
ccc4672a 356 .error_handler = piix_sata_error_handler,
3f037db0 357 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 358
359 .irq_handler = ata_interrupt,
360 .irq_clear = ata_bmdma_irq_clear,
361
362 .port_start = ata_port_start,
363 .port_stop = ata_port_stop,
d96715c1 364 .host_stop = piix_host_stop,
1da177e4
LT		 365};
366
d96715c1 367static const struct piix_map_db ich5_map_db = {
d33f58b8 368 .mask = 0x7,
ea35d29e 369 .port_enable = 0x3,
08f12edc 370 .present_shift = 4,
d33f58b8
TH		 371 .map = {
372 /* PM PS SM SS MAP */
373 { P0, NA, P1, NA }, /* 000b */
374 { P1, NA, P0, NA }, /* 001b */
375 { RV, RV, RV, RV },
376 { RV, RV, RV, RV },
377 { P0, P1, IDE, IDE }, /* 100b */
378 { P1, P0, IDE, IDE }, /* 101b */
379 { IDE, IDE, P0, P1 }, /* 110b */
380 { IDE, IDE, P1, P0 }, /* 111b */
381 },
382};
383
d96715c1 384static const struct piix_map_db ich6_map_db = {
d33f58b8 385 .mask = 0x3,
ea35d29e 386 .port_enable = 0xf,
08f12edc 387 .present_shift = 4,
d33f58b8
TH		 388 .map = {
389 /* PM PS SM SS MAP */
79ea24e7 390 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 391 { IDE, IDE, P1, P3 }, /* 01b */
392 { P0, P2, IDE, IDE }, /* 10b */
393 { RV, RV, RV, RV },
394 },
395};
396
d96715c1 397static const struct piix_map_db ich6m_map_db = {
d33f58b8 398 .mask = 0x3,
ea35d29e 399 .port_enable = 0x5,
08f12edc 400 .present_shift = 4,
d33f58b8
TH		 401 .map = {
402 /* PM PS SM SS MAP */
79ea24e7 403 { P0, P2, RV, RV }, /* 00b */
d33f58b8
TH		 404 { RV, RV, RV, RV },
405 { P0, P2, IDE, IDE }, /* 10b */
406 { RV, RV, RV, RV },
407 },
408};
409
08f12edc
JG		 410static const struct piix_map_db ich8_map_db = {
411 .mask = 0x3,
412 .port_enable = 0x3,
413 .present_shift = 8,
414 .map = {
415 /* PM PS SM SS MAP */
f5beec49 416 { P0, NA, P1, NA }, /* 00b (hardwired) */
08f12edc
JG		 417 { RV, RV, RV, RV },
418 { RV, RV, RV, RV }, /* 10b (never) */
419 { RV, RV, RV, RV },
420 },
421};
422
d96715c1
TH		 423static const struct piix_map_db *piix_map_db_table[] = {
424 [ich5_sata] = &ich5_map_db,
425 [esb_sata] = &ich5_map_db,
426 [ich6_sata] = &ich6_map_db,
427 [ich6_sata_ahci] = &ich6_map_db,
428 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 429 [ich8_sata_ahci] = &ich8_map_db,
d96715c1
TH		 430};
431
1da177e4 432static struct ata_port_info piix_port_info[] = {
669a5db4 433 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
1d076e5b
TH		 434 {
435 .sht = &piix_sht,
669a5db4 436 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
1d076e5b 437 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 438 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 439 .udma_mask = ATA_UDMA_MASK_40C,
440 .port_ops = &piix_pata_ops,
441 },
442
669a5db4
JG		 443 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
444 {
445 .sht = &piix_sht,
446 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
447 .pio_mask = 0x1f, /* pio 0-4 */
448 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
449 .udma_mask = ATA_UDMA2, /* UDMA33 */
450 .port_ops = &ich_pata_ops,
451 },
452 /* ich_pata_66: 2 ICH controllers up to 66MHz */
1da177e4
LT		 453 {
454 .sht = &piix_sht,
669a5db4
JG		 455 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
456 .pio_mask = 0x1f, /* pio 0-4 */
457 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
458 .udma_mask = ATA_UDMA4,
459 .port_ops = &ich_pata_ops,
460 },
461
462 /* ich_pata_100: 3 */
463 {
464 .sht = &piix_sht,
465 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
1da177e4 466 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 467 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 468 .udma_mask = ATA_UDMA5, /* udma0-5 */
469 .port_ops = &ich_pata_ops,
1da177e4
LT		 470 },
471
669a5db4
JG		 472 /* ich_pata_133: 4 ICH with full UDMA6 */
473 {
474 .sht = &piix_sht,
475 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
476 .pio_mask = 0x1f, /* pio 0-4 */
477 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
478 .udma_mask = ATA_UDMA6, /* UDMA133 */
479 .port_ops = &ich_pata_ops,
480 },
481
482 /* ich5_sata: 5 */
1da177e4
LT		 483 {
484 .sht = &piix_sht,
cca3974e 485 .flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR |
f3745a3f 486 PIIX_FLAG_IGNORE_PCS,
1da177e4
LT		 487 .pio_mask = 0x1f, /* pio0-4 */
488 .mwdma_mask = 0x07, /* mwdma0-2 */
489 .udma_mask = 0x7f, /* udma0-6 */
490 .port_ops = &piix_sata_ops,
491 },
492
669a5db4 493 /* i6300esb_sata: 6 */
1da177e4
LT		 494 {
495 .sht = &piix_sht,
cca3974e 496 .flags = ATA_FLAG_SATA |
219e6214 497 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
1da177e4 498 .pio_mask = 0x1f, /* pio0-4 */
1d076e5b
TH		 499 .mwdma_mask = 0x07, /* mwdma0-2 */
500 .udma_mask = 0x7f, /* udma0-6 */
501 .port_ops = &piix_sata_ops,
1da177e4
LT		 502 },
503
669a5db4 504 /* ich6_sata: 7 */
1da177e4
LT		 505 {
506 .sht = &piix_sht,
cca3974e 507 .flags = ATA_FLAG_SATA |
d33f58b8 508 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
1da177e4
LT		 509 .pio_mask = 0x1f, /* pio0-4 */
510 .mwdma_mask = 0x07, /* mwdma0-2 */
511 .udma_mask = 0x7f, /* udma0-6 */
512 .port_ops = &piix_sata_ops,
513 },
514
669a5db4 515 /* ich6_sata_ahci:8 */
c368ca4e
JG		 516 {
517 .sht = &piix_sht,
cca3974e 518 .flags = ATA_FLAG_SATA |
d33f58b8
TH		 519 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
520 PIIX_FLAG_AHCI,
c368ca4e
JG		 521 .pio_mask = 0x1f, /* pio0-4 */
522 .mwdma_mask = 0x07, /* mwdma0-2 */
523 .udma_mask = 0x7f, /* udma0-6 */
524 .port_ops = &piix_sata_ops,
525 },
1d076e5b 526
669a5db4 527 /* ich6m_sata_ahci: 9 */
1d076e5b
TH		 528 {
529 .sht = &piix_sht,
cca3974e 530 .flags = ATA_FLAG_SATA |
d33f58b8
TH		 531 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
532 PIIX_FLAG_AHCI,
1d076e5b
TH		 533 .pio_mask = 0x1f, /* pio0-4 */
534 .mwdma_mask = 0x07, /* mwdma0-2 */
535 .udma_mask = 0x7f, /* udma0-6 */
536 .port_ops = &piix_sata_ops,
537 },
08f12edc
JG		 538
539 /* ich8_sata_ahci */
540 {
541 .sht = &piix_sht,
cca3974e 542 .flags = ATA_FLAG_SATA |
08f12edc
JG		 543 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
544 PIIX_FLAG_AHCI,
545 .pio_mask = 0x1f, /* pio0-4 */
546 .mwdma_mask = 0x07, /* mwdma0-2 */
547 .udma_mask = 0x7f, /* udma0-6 */
548 .port_ops = &piix_sata_ops,
549 },
669a5db4 550
1da177e4
LT		 551};
552
553static struct pci_bits piix_enable_bits[] = {
554 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
555 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
556};
557
558MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
559MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
560MODULE_LICENSE("GPL");
561MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
562MODULE_VERSION(DRV_VERSION);
563
9dd9c164
TH		 564static int force_pcs = 0;
565module_param(force_pcs, int, 0444);
566MODULE_PARM_DESC(force_pcs, "force honoring or ignoring PCS to work around "
567 "device mis-detection (0=default, 1=ignore PCS, 2=honor PCS)");
568
1da177e4
LT		 569/**
570 * piix_pata_cbl_detect - Probe host controller cable detect info
571 * @ap: Port for which cable detect info is desired
572 *
573 * Read 80c cable indicator from ATA PCI device's PCI config
574 * register. This register is normally set by firmware (BIOS).
575 *
576 * LOCKING:
577 * None (inherited from caller).
578 */
669a5db4
JG		 579
580static void ich_pata_cbl_detect(struct ata_port *ap)
1da177e4 581{
cca3974e 582 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4
LT		 583 u8 tmp, mask;
584
585 /* no 80c support in host controller? */
586 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
587 goto cbl40;
588
589 /* check BIOS cable detect results */
2a88d1ac 590 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 591 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
592 if ((tmp & mask) == 0)
593 goto cbl40;
594
595 ap->cbl = ATA_CBL_PATA80;
596 return;
597
598cbl40:
599 ap->cbl = ATA_CBL_PATA40;
1da177e4
LT		 600}
601
602/**
ccc4672a 603 * piix_pata_prereset - prereset for PATA host controller
573db6b8 604 * @ap: Target port
1da177e4 605 *
573db6b8
TH		 606 *
607 * LOCKING:
608 * None (inherited from caller).
609 */
ccc4672a 610static int piix_pata_prereset(struct ata_port *ap)
1da177e4 611{
cca3974e 612 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 613
2a88d1ac 614 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
f15a1daf 615 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
ccc4672a 616 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
573db6b8 617 return 0;
1da177e4 618 }
669a5db4 619 ap->cbl = ATA_CBL_PATA40;
ccc4672a
TH		 620 return ata_std_prereset(ap);
621}
622
623static void piix_pata_error_handler(struct ata_port *ap)
624{
625 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
626 ata_std_postreset);
1da177e4
LT		 627}
628
669a5db4
JG		 629
630/**
631 * ich_pata_prereset - prereset for PATA host controller
632 * @ap: Target port
633 *
634 *
635 * LOCKING:
636 * None (inherited from caller).
637 */
638static int ich_pata_prereset(struct ata_port *ap)
639{
640 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
641
642 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
643 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
644 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
645 return 0;
646 }
647
648 ich_pata_cbl_detect(ap);
649
650 return ata_std_prereset(ap);
651}
652
653static void ich_pata_error_handler(struct ata_port *ap)
654{
655 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
656 ata_std_postreset);
657}
658
1da177e4 659/**
f1a58eca 660 * piix_sata_present_mask - determine present mask for SATA host controller
ccc4672a 661 * @ap: Target port
1da177e4 662 *
f1a58eca
TH		 663 * Reads SATA PCI device's PCI config register Port Configuration
664 * and Status (PCS) to determine port and device availability.
1da177e4
LT		 665 *
666 * LOCKING:
667 * None (inherited from caller).
668 *
669 * RETURNS:
f1a58eca 670 * determined present_mask
1da177e4 671 */
f1a58eca 672static unsigned int piix_sata_present_mask(struct ata_port *ap)
1da177e4 673{
cca3974e
JG		 674 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
675 struct piix_host_priv *hpriv = ap->host->private_data;
d96715c1 676 const unsigned int *map = hpriv->map;
2a88d1ac 677 int base = 2 * ap->port_no;
f1a58eca 678 unsigned int present_mask = 0;
d133ecab 679 int port, i;
ea35d29e 680 u16 pcs;
1da177e4 681
ea35d29e 682 pci_read_config_word(pdev, ICH5_PCS, &pcs);
d133ecab
TH		 683 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
684
d133ecab
TH		 685 for (i = 0; i < 2; i++) {
686 port = map[base + i];
687 if (port < 0)
688 continue;
08f12edc
JG		 689 if ((ap->flags & PIIX_FLAG_IGNORE_PCS) ||
690 (pcs & 1 << (hpriv->map_db->present_shift + port)))
f1a58eca 691 present_mask |= 1 << i;
1da177e4
LT		 692 }
693
f1a58eca
TH		 694 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
695 ap->id, pcs, present_mask);
d133ecab 696
f1a58eca
TH		 697 return present_mask;
698}
699
700/**
701 * piix_sata_softreset - reset SATA host port via ATA SRST
702 * @ap: port to reset
703 * @classes: resulting classes of attached devices
704 *
705 * Reset SATA host port via ATA SRST. On controllers with
706 * reliable PCS present bits, the bits are used to determine
707 * device presence.
708 *
709 * LOCKING:
710 * Kernel thread context (may sleep)
711 *
712 * RETURNS:
713 * 0 on success, -errno otherwise.
714 */
715static int piix_sata_softreset(struct ata_port *ap, unsigned int *classes)
716{
717 unsigned int present_mask;
718 int i, rc;
719
720 present_mask = piix_sata_present_mask(ap);
721
722 rc = ata_std_softreset(ap, classes);
723 if (rc)
724 return rc;
725
726 for (i = 0; i < ATA_MAX_DEVICES; i++) {
727 if (!(present_mask & (1 << i)))
728 classes[i] = ATA_DEV_NONE;
1da177e4
LT		 729 }
730
f1a58eca 731 return 0;
ccc4672a
TH		 732}
733
734static void piix_sata_error_handler(struct ata_port *ap)
735{
f1a58eca 736 ata_bmdma_drive_eh(ap, ata_std_prereset, piix_sata_softreset, NULL,
ccc4672a 737 ata_std_postreset);
1da177e4
LT		 738}
739
740/**
741 * piix_set_piomode - Initialize host controller PATA PIO timings
742 * @ap: Port whose timings we are configuring
743 * @adev: um
1da177e4
LT		 744 *
745 * Set PIO mode for device, in host controller PCI config space.
746 *
747 * LOCKING:
748 * None (inherited from caller).
749 */
750
751static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
752{
753 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 754 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 755 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 756 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 757 unsigned int slave_port = 0x44;
758 u16 master_data;
759 u8 slave_data;
669a5db4
JG		 760 u8 udma_enable;
761 int control = 0;
762
763 /*
764 * See Intel Document 298600-004 for the timing programing rules
765 * for ICH controllers.
766 */
1da177e4
LT		 767
768 static const /* ISP RTC */
769 u8 timings[][2] = { { 0, 0 },
770 { 0, 0 },
771 { 1, 0 },
772 { 2, 1 },
773 { 2, 3 }, };
774
669a5db4
JG		 775 if (pio >= 2)
776 control |= 1; /* TIME1 enable */
777 if (ata_pio_need_iordy(adev))
778 control |= 2; /* IE enable */
779
780 /* Intel specifies that the PPE functionality is for disk only */
781 if (adev->class == ATA_DEV_ATA)
782 control |= 4; /* PPE enable */
783
1da177e4
LT		 784 pci_read_config_word(dev, master_port, &master_data);
785 if (is_slave) {
669a5db4 786 /* Enable SITRE (seperate slave timing register) */
1da177e4 787 master_data |= 0x4000;
669a5db4
JG		 788 /* enable PPE1, IE1 and TIME1 as needed */
789 master_data |= (control << 4);
1da177e4 790 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 791 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 792 /* Load the timing nibble for this slave */
793 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
1da177e4 794 } else {
669a5db4 795 /* Master keeps the bits in a different format */
1da177e4 796 master_data &= 0xccf8;
669a5db4
JG		 797 /* Enable PPE, IE and TIME as appropriate */
798 master_data |= control;
1da177e4
LT		 799 master_data |=
800 (timings[pio][0] << 12) |
801 (timings[pio][1] << 8);
802 }
803 pci_write_config_word(dev, master_port, master_data);
804 if (is_slave)
805 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 806
807 /* Ensure the UDMA bit is off - it will be turned back on if
808 UDMA is selected */
809
810 if (ap->udma_mask) {
811 pci_read_config_byte(dev, 0x48, &udma_enable);
812 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
813 pci_write_config_byte(dev, 0x48, udma_enable);
814 }
1da177e4
LT		 815}
816
817/**
669a5db4 818 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 819 * @ap: Port whose timings we are configuring
669a5db4 820 * @adev: Drive in question
1da177e4 821 * @udma: udma mode, 0 - 6
669a5db4 822 * @is_ich: set if the chip is an ICH device
1da177e4
LT		 823 *
824 * Set UDMA mode for device, in host controller PCI config space.
825 *
826 * LOCKING:
827 * None (inherited from caller).
828 */
829
669a5db4 830static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 831{
cca3974e 832 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 833 u8 master_port = ap->port_no ? 0x42 : 0x40;
834 u16 master_data;
835 u8 speed = adev->dma_mode;
836 int devid = adev->devno + 2 * ap->port_no;
837 u8 udma_enable;
838
839 static const /* ISP RTC */
840 u8 timings[][2] = { { 0, 0 },
841 { 0, 0 },
842 { 1, 0 },
843 { 2, 1 },
844 { 2, 3 }, };
845
846 pci_read_config_word(dev, master_port, &master_data);
847 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 848
849 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 850 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
851 u16 udma_timing;
852 u16 ideconf;
853 int u_clock, u_speed;
854
855 /*
856 * UDMA is handled by a combination of clock switching and
857 * selection of dividers
858 *
859 * Handy rule: Odd modes are UDMATIMx 01, even are 02
860 * except UDMA0 which is 00
861 */
862 u_speed = min(2 - (udma & 1), udma);
863 if (udma == 5)
864 u_clock = 0x1000; /* 100Mhz */
865 else if (udma > 2)
866 u_clock = 1; /* 66Mhz */
867 else
868 u_clock = 0; /* 33Mhz */
869
870 udma_enable |= (1 << devid);
871
872 /* Load the CT/RP selection */
873 pci_read_config_word(dev, 0x4A, &udma_timing);
874 udma_timing &= ~(3 << (4 * devid));
875 udma_timing |= u_speed << (4 * devid);
876 pci_write_config_word(dev, 0x4A, udma_timing);
877
878 if (isich) {
879 /* Select a 33/66/100Mhz clock */
880 pci_read_config_word(dev, 0x54, &ideconf);
881 ideconf &= ~(0x1001 << devid);
882 ideconf |= u_clock << devid;
883 /* For ICH or later we should set bit 10 for better
884 performance (WR_PingPong_En) */
885 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 886 }
1da177e4 887 } else {
669a5db4
JG		 888 /*
889 * MWDMA is driven by the PIO timings. We must also enable
890 * IORDY unconditionally along with TIME1. PPE has already
891 * been set when the PIO timing was set.
892 */
893 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
894 unsigned int control;
895 u8 slave_data;
896 const unsigned int needed_pio[3] = {
897 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
898 };
899 int pio = needed_pio[mwdma] - XFER_PIO_0;
900
901 control = 3; /* IORDY|TIME1 */
902
903 /* If the drive MWDMA is faster than it can do PIO then
904 we must force PIO into PIO0 */
905
906 if (adev->pio_mode < needed_pio[mwdma])
907 /* Enable DMA timing only */
908 control |= 8; /* PIO cycles in PIO0 */
909
910 if (adev->devno) { /* Slave */
911 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
912 master_data |= control << 4;
913 pci_read_config_byte(dev, 0x44, &slave_data);
914 slave_data &= (0x0F + 0xE1 * ap->port_no);
915 /* Load the matching timing */
916 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
917 pci_write_config_byte(dev, 0x44, slave_data);
918 } else { /* Master */
919 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
920 and master timing bits */
921 master_data |= control;
922 master_data |=
923 (timings[pio][0] << 12) |
924 (timings[pio][1] << 8);
925 }
926 udma_enable &= ~(1 << devid);
927 pci_write_config_word(dev, master_port, master_data);
1da177e4 928 }
669a5db4
JG		 929 /* Don't scribble on 0x48 if the controller does not support UDMA */
930 if (ap->udma_mask)
931 pci_write_config_byte(dev, 0x48, udma_enable);
932}
933
934/**
935 * piix_set_dmamode - Initialize host controller PATA DMA timings
936 * @ap: Port whose timings we are configuring
937 * @adev: um
938 *
939 * Set MW/UDMA mode for device, in host controller PCI config space.
940 *
941 * LOCKING:
942 * None (inherited from caller).
943 */
944
945static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
946{
947 do_pata_set_dmamode(ap, adev, 0);
948}
949
950/**
951 * ich_set_dmamode - Initialize host controller PATA DMA timings
952 * @ap: Port whose timings we are configuring
953 * @adev: um
954 *
955 * Set MW/UDMA mode for device, in host controller PCI config space.
956 *
957 * LOCKING:
958 * None (inherited from caller).
959 */
960
961static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
962{
963 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 964}
965
1da177e4
LT		 966#define AHCI_PCI_BAR 5
967#define AHCI_GLOBAL_CTL 0x04
968#define AHCI_ENABLE (1 << 31)
969static int piix_disable_ahci(struct pci_dev *pdev)
970{
ea6ba10b 971 void __iomem *mmio;
1da177e4
LT		 972 u32 tmp;
973 int rc = 0;
974
975 /* BUG: pci_enable_device has not yet been called. This
976 * works because this device is usually set up by BIOS.
977 */
978
374b1873
JG		 979 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
980 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 981 return 0;
7b6dbd68 982
374b1873 983 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 984 if (!mmio)
985 return -ENOMEM;
7b6dbd68 986
1da177e4
LT		 987 tmp = readl(mmio + AHCI_GLOBAL_CTL);
988 if (tmp & AHCI_ENABLE) {
989 tmp &= ~AHCI_ENABLE;
990 writel(tmp, mmio + AHCI_GLOBAL_CTL);
991
992 tmp = readl(mmio + AHCI_GLOBAL_CTL);
993 if (tmp & AHCI_ENABLE)
994 rc = -EIO;
995 }
7b6dbd68 996
374b1873 997 pci_iounmap(pdev, mmio);
1da177e4
LT		 998 return rc;
999}
1000
c621b140
AC		 1001/**
1002 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 1003 * @ata_dev: the PCI device to check
2e9edbf8 1004 *
c621b140
AC		 1005 * Check for the present of 450NX errata #19 and errata #25. If
1006 * they are found return an error code so we can turn off DMA
1007 */
1008
1009static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1010{
1011 struct pci_dev *pdev = NULL;
1012 u16 cfg;
1013 u8 rev;
1014 int no_piix_dma = 0;
2e9edbf8 1015
c621b140
AC		 1016 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1017 {
1018 /* Look for 450NX PXB. Check for problem configurations
1019 A PCI quirk checks bit 6 already */
1020 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
1021 pci_read_config_word(pdev, 0x41, &cfg);
1022 /* Only on the original revision: IDE DMA can hang */
31a34fe7 1023 if (rev == 0x00)
c621b140
AC		 1024 no_piix_dma = 1;
1025 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
31a34fe7 1026 else if (cfg & (1<<14) && rev < 5)
c621b140
AC		 1027 no_piix_dma = 2;
1028 }
31a34fe7 1029 if (no_piix_dma)
c621b140 1030 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 1031 if (no_piix_dma == 2)
c621b140
AC		 1032 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1033 return no_piix_dma;
2e9edbf8 1034}
c621b140 1035
ea35d29e 1036static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 1037 struct ata_port_info *pinfo,
ea35d29e
JG		 1038 const struct piix_map_db *map_db)
1039{
1040 u16 pcs, new_pcs;
1041
1042 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1043
1044 new_pcs = pcs | map_db->port_enable;
1045
1046 if (new_pcs != pcs) {
1047 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1048 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1049 msleep(150);
1050 }
9dd9c164
TH		 1051
1052 if (force_pcs == 1) {
1053 dev_printk(KERN_INFO, &pdev->dev,
1054 "force ignoring PCS (0x%x)\n", new_pcs);
cca3974e
JG		 1055 pinfo[0].flags |= PIIX_FLAG_IGNORE_PCS;
1056 pinfo[1].flags |= PIIX_FLAG_IGNORE_PCS;
9dd9c164
TH		 1057 } else if (force_pcs == 2) {
1058 dev_printk(KERN_INFO, &pdev->dev,
1059 "force honoring PCS (0x%x)\n", new_pcs);
cca3974e
JG		 1060 pinfo[0].flags &= ~PIIX_FLAG_IGNORE_PCS;
1061 pinfo[1].flags &= ~PIIX_FLAG_IGNORE_PCS;
9dd9c164 1062 }
ea35d29e
JG		 1063}
1064
d33f58b8 1065static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 1066 struct ata_port_info *pinfo,
1067 const struct piix_map_db *map_db)
d33f58b8 1068{
d96715c1 1069 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 1070 const unsigned int *map;
1071 int i, invalid_map = 0;
1072 u8 map_value;
1073
1074 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1075
1076 map = map_db->map[map_value & map_db->mask];
1077
1078 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1079 for (i = 0; i < 4; i++) {
1080 switch (map[i]) {
1081 case RV:
1082 invalid_map = 1;
1083 printk(" XX");
1084 break;
1085
1086 case NA:
1087 printk(" --");
1088 break;
1089
1090 case IDE:
1091 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1092 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1093 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1094 i++;
1095 printk(" IDE IDE");
1096 break;
1097
1098 default:
1099 printk(" P%d", map[i]);
1100 if (i & 1)
cca3974e 1101 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1102 break;
1103 }
1104 }
1105 printk(" ]\n");
1106
1107 if (invalid_map)
1108 dev_printk(KERN_ERR, &pdev->dev,
1109 "invalid MAP value %u\n", map_value);
1110
d96715c1 1111 hpriv->map = map;
08f12edc 1112 hpriv->map_db = map_db;
d33f58b8
TH		 1113}
1114
1da177e4
LT		 1115/**
1116 * piix_init_one - Register PIIX ATA PCI device with kernel services
1117 * @pdev: PCI device to register
1118 * @ent: Entry in piix_pci_tbl matching with @pdev
1119 *
1120 * Called from kernel PCI layer. We probe for combined mode (sigh),
1121 * and then hand over control to libata, for it to do the rest.
1122 *
1123 * LOCKING:
1124 * Inherited from PCI layer (may sleep).
1125 *
1126 * RETURNS:
1127 * Zero on success, or -ERRNO value.
1128 */
1129
1130static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1131{
1132 static int printed_version;
d33f58b8
TH		 1133 struct ata_port_info port_info[2];
1134 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
d96715c1 1135 struct piix_host_priv *hpriv;
cca3974e 1136 unsigned long port_flags;
1da177e4
LT		 1137
1138 if (!printed_version++)
6248e647
JG		 1139 dev_printk(KERN_DEBUG, &pdev->dev,
1140 "version " DRV_VERSION "\n");
1da177e4
LT		 1141
1142 /* no hotplugging support (FIXME) */
1143 if (!in_module_init)
1144 return -ENODEV;
1145
d96715c1
TH		 1146 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1147 if (!hpriv)
1148 return -ENOMEM;
1149
d33f58b8
TH		 1150 port_info[0] = piix_port_info[ent->driver_data];
1151 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1152 port_info[0].private_data = hpriv;
1153 port_info[1].private_data = hpriv;
1da177e4 1154
cca3974e 1155 port_flags = port_info[0].flags;
ff0fc146 1156
cca3974e 1157 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1158 u8 tmp;
1159 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1160 if (tmp == PIIX_AHCI_DEVICE) {
1161 int rc = piix_disable_ahci(pdev);
1162 if (rc)
1163 return rc;
1164 }
1da177e4
LT		 1165 }
1166
d33f58b8 1167 /* Initialize SATA map */
cca3974e 1168 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1169 piix_init_sata_map(pdev, port_info,
1170 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1171 piix_init_pcs(pdev, port_info,
1172 piix_map_db_table[ent->driver_data]);
ea35d29e 1173 }
1da177e4
LT		 1174
1175 /* On ICH5, some BIOSen disable the interrupt using the
1176 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1177 * On ICH6, this bit has the same effect, but only when
1178 * MSI is disabled (and it is disabled, as we don't use
1179 * message-signalled interrupts currently).
1180 */
cca3974e 1181 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1182 pci_intx(pdev, 1);
1da177e4 1183
c621b140
AC		 1184 if (piix_check_450nx_errata(pdev)) {
1185 /* This writes into the master table but it does not
1186 really matter for this errata as we will apply it to
1187 all the PIIX devices on the board */
d33f58b8
TH		 1188 port_info[0].mwdma_mask = 0;
1189 port_info[0].udma_mask = 0;
1190 port_info[1].mwdma_mask = 0;
1191 port_info[1].udma_mask = 0;
c621b140 1192 }
d33f58b8 1193 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 1194}
1195
cca3974e 1196static void piix_host_stop(struct ata_host *host)
d96715c1 1197{
cca3974e 1198 struct piix_host_priv *hpriv = host->private_data;
24dd01bf 1199
cca3974e 1200 ata_host_stop(host);
24dd01bf
JG		 1201
1202 kfree(hpriv);
d96715c1
TH		 1203}
1204
1da177e4
LT		 1205static int __init piix_init(void)
1206{
1207 int rc;
1208
b7887196
PR		 1209 DPRINTK("pci_register_driver\n");
1210 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1211 if (rc)
1212 return rc;
1213
1214 in_module_init = 0;
1215
1216 DPRINTK("done\n");
1217 return 0;
1218}
1219
1da177e4
LT		 1220static void __exit piix_exit(void)
1221{
1222 pci_unregister_driver(&piix_pci_driver);
1223}
1224
1225module_init(piix_init);
1226module_exit(piix_exit);
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