]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/ata/ata_piix.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
libata: make ata_port_queue_task() an internal function
[net-next-2.6.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
b8b275ef 94#include <linux/dmi.h>
1da177e4
LT		 95
96#define DRV_NAME "ata_piix"
2a3103ce 97#define DRV_VERSION "2.12"
1da177e4
LT		 98
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 103 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 104
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 108
800b3996
TH		 109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 111
1da177e4
LT		 112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
d33f58b8
TH		 121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
127 NA = -2, /* not avaliable */
128 RV = -3, /* reserved */
129
7b6dbd68 130 PIIX_AHCI_DEVICE = 6,
b8b275ef
TH		 131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
1da177e4
LT		 134};
135
9cde9ed1
TH		 136enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich5_sata,
144 ich6_sata,
145 ich6_sata_ahci,
146 ich6m_sata_ahci,
147 ich8_sata_ahci,
148 ich8_2port_sata,
149 ich8m_apple_sata_ahci, /* locks up on second port enable */
150 tolapai_sata_ahci,
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
152};
153
d33f58b8
TH		 154struct piix_map_db {
155 const u32 mask;
73291a1c 156 const u16 port_enable;
d33f58b8
TH		 157 const int map[][4];
158};
159
d96715c1
TH		 160struct piix_host_priv {
161 const int *map;
162};
163
2dcb407e
JG		 164static int piix_init_one(struct pci_dev *pdev,
165 const struct pci_device_id *ent);
ccc4672a 166static void piix_pata_error_handler(struct ata_port *ap);
2dcb407e
JG		 167static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
168static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
169static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
eb4a2c7f 170static int ich_pata_cable_detect(struct ata_port *ap);
25f98131 171static u8 piix_vmw_bmdma_status(struct ata_port *ap);
b8b275ef
TH		 172#ifdef CONFIG_PM
173static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
174static int piix_pci_device_resume(struct pci_dev *pdev);
175#endif
1da177e4
LT		 176
177static unsigned int in_module_init = 1;
178
3b7d697d 179static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
AC		 180 /* Intel PIIX3 for the 430HX etc */
181 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
25f98131
TH		 182 /* VMware ICH4 */
183 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
669a5db4
JG		 184 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
185 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
186 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 187 /* Intel PIIX4 */
188 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
189 /* Intel PIIX4 */
190 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX */
192 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel ICH (i810, i815, i840) UDMA 66*/
194 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
195 /* Intel ICH0 : UDMA 33*/
196 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
197 /* Intel ICH2M */
198 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
200 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH3M */
202 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH3 (E7500/1) UDMA 100 */
204 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
206 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* Intel ICH5 */
2eb829e9 209 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4
JG		 210 /* C-ICH (i810E2) */
211 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 212 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 213 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* ICH6 (and 6) (i915) UDMA 100 */
215 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH7/7-R (i945, i975) UDMA 100*/
2eb829e9 217 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4 218 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
c1e6f28c
CL		 219 /* ICH8 Mobile PATA Controller */
220 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 221
222 /* NOTE: The following PCI ids must be kept in sync with the
223 * list in drivers/pci/quirks.c.
224 */
225
1d076e5b 226 /* 82801EB (ICH5) */
1da177e4 227 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 228 /* 82801EB (ICH5) */
1da177e4 229 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 230 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 231 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 232 /* 6300ESB pretending RAID */
5e56a37c 233 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 234 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 235 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 236 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 237 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 238 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
239 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
240 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 241 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 242 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 243 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 244 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 245 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 246 /* SATA Controller 1 IDE (ICH8) */
08f12edc 247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 248 /* SATA Controller 2 IDE (ICH8) */
00242ec8 249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 250 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 251 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
8d8ef2fb
TR		 252 /* Mobile SATA Controller IDE (ICH8M), Apple */
253 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
f98b6573
JG		 254 /* SATA Controller IDE (ICH9) */
255 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
256 /* SATA Controller IDE (ICH9) */
00242ec8 257 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 258 /* SATA Controller IDE (ICH9) */
00242ec8 259 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 260 /* SATA Controller IDE (ICH9M) */
00242ec8 261 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 262 /* SATA Controller IDE (ICH9M) */
00242ec8 263 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573
JG		 264 /* SATA Controller IDE (ICH9M) */
265 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
c5cf0ffa
JG		 266 /* SATA Controller IDE (Tolapai) */
267 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
1da177e4
LT		 268
269 { } /* terminate list */
270};
271
272static struct pci_driver piix_pci_driver = {
273 .name = DRV_NAME,
274 .id_table = piix_pci_tbl,
275 .probe = piix_init_one,
276 .remove = ata_pci_remove_one,
438ac6d5 277#ifdef CONFIG_PM
b8b275ef
TH		 278 .suspend = piix_pci_device_suspend,
279 .resume = piix_pci_device_resume,
438ac6d5 280#endif
1da177e4
LT		 281};
282
193515d5 283static struct scsi_host_template piix_sht = {
1da177e4
LT		 284 .module = THIS_MODULE,
285 .name = DRV_NAME,
286 .ioctl = ata_scsi_ioctl,
287 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 288 .can_queue = ATA_DEF_QUEUE,
289 .this_id = ATA_SHT_THIS_ID,
290 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 291 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
292 .emulated = ATA_SHT_EMULATED,
293 .use_clustering = ATA_SHT_USE_CLUSTERING,
294 .proc_name = DRV_NAME,
295 .dma_boundary = ATA_DMA_BOUNDARY,
296 .slave_configure = ata_scsi_slave_config,
ccf68c34 297 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 298 .bios_param = ata_std_bios_param,
1da177e4
LT		 299};
300
057ace5e 301static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 302 .set_piomode = piix_set_piomode,
303 .set_dmamode = piix_set_dmamode,
89bad589 304 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 305
306 .tf_load = ata_tf_load,
307 .tf_read = ata_tf_read,
308 .check_status = ata_check_status,
309 .exec_command = ata_exec_command,
310 .dev_select = ata_std_dev_select,
311
1da177e4
LT		 312 .bmdma_setup = ata_bmdma_setup,
313 .bmdma_start = ata_bmdma_start,
314 .bmdma_stop = ata_bmdma_stop,
315 .bmdma_status = ata_bmdma_status,
316 .qc_prep = ata_qc_prep,
317 .qc_issue = ata_qc_issue_prot,
0d5ff566 318 .data_xfer = ata_data_xfer,
1da177e4 319
3f037db0
TH		 320 .freeze = ata_bmdma_freeze,
321 .thaw = ata_bmdma_thaw,
ccc4672a 322 .error_handler = piix_pata_error_handler,
3f037db0 323 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 324 .cable_detect = ata_cable_40wire,
1da177e4
LT		 325
326 .irq_handler = ata_interrupt,
327 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 328 .irq_on = ata_irq_on,
1da177e4
LT		 329
330 .port_start = ata_port_start,
1da177e4
LT		 331};
332
669a5db4 333static const struct ata_port_operations ich_pata_ops = {
669a5db4
JG		 334 .set_piomode = piix_set_piomode,
335 .set_dmamode = ich_set_dmamode,
336 .mode_filter = ata_pci_default_filter,
337
338 .tf_load = ata_tf_load,
339 .tf_read = ata_tf_read,
340 .check_status = ata_check_status,
341 .exec_command = ata_exec_command,
342 .dev_select = ata_std_dev_select,
343
344 .bmdma_setup = ata_bmdma_setup,
345 .bmdma_start = ata_bmdma_start,
346 .bmdma_stop = ata_bmdma_stop,
347 .bmdma_status = ata_bmdma_status,
348 .qc_prep = ata_qc_prep,
349 .qc_issue = ata_qc_issue_prot,
0d5ff566 350 .data_xfer = ata_data_xfer,
669a5db4
JG		 351
352 .freeze = ata_bmdma_freeze,
353 .thaw = ata_bmdma_thaw,
eb4a2c7f 354 .error_handler = piix_pata_error_handler,
669a5db4 355 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 356 .cable_detect = ich_pata_cable_detect,
669a5db4
JG		 357
358 .irq_handler = ata_interrupt,
359 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 360 .irq_on = ata_irq_on,
669a5db4
JG		 361
362 .port_start = ata_port_start,
669a5db4
JG		 363};
364
057ace5e 365static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 366 .tf_load = ata_tf_load,
367 .tf_read = ata_tf_read,
368 .check_status = ata_check_status,
369 .exec_command = ata_exec_command,
370 .dev_select = ata_std_dev_select,
371
1da177e4
LT		 372 .bmdma_setup = ata_bmdma_setup,
373 .bmdma_start = ata_bmdma_start,
374 .bmdma_stop = ata_bmdma_stop,
375 .bmdma_status = ata_bmdma_status,
376 .qc_prep = ata_qc_prep,
377 .qc_issue = ata_qc_issue_prot,
0d5ff566 378 .data_xfer = ata_data_xfer,
1da177e4 379
3f037db0
TH		 380 .freeze = ata_bmdma_freeze,
381 .thaw = ata_bmdma_thaw,
2f91d81d 382 .error_handler = ata_bmdma_error_handler,
3f037db0 383 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 384
385 .irq_handler = ata_interrupt,
386 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 387 .irq_on = ata_irq_on,
1da177e4
LT		 388
389 .port_start = ata_port_start,
1da177e4
LT		 390};
391
25f98131
TH		 392static const struct ata_port_operations piix_vmw_ops = {
393 .set_piomode = piix_set_piomode,
394 .set_dmamode = piix_set_dmamode,
395 .mode_filter = ata_pci_default_filter,
396
397 .tf_load = ata_tf_load,
398 .tf_read = ata_tf_read,
399 .check_status = ata_check_status,
400 .exec_command = ata_exec_command,
401 .dev_select = ata_std_dev_select,
402
403 .bmdma_setup = ata_bmdma_setup,
404 .bmdma_start = ata_bmdma_start,
405 .bmdma_stop = ata_bmdma_stop,
406 .bmdma_status = piix_vmw_bmdma_status,
407 .qc_prep = ata_qc_prep,
408 .qc_issue = ata_qc_issue_prot,
409 .data_xfer = ata_data_xfer,
410
411 .freeze = ata_bmdma_freeze,
412 .thaw = ata_bmdma_thaw,
413 .error_handler = piix_pata_error_handler,
414 .post_internal_cmd = ata_bmdma_post_internal_cmd,
415 .cable_detect = ata_cable_40wire,
416
417 .irq_handler = ata_interrupt,
418 .irq_clear = ata_bmdma_irq_clear,
419 .irq_on = ata_irq_on,
420
421 .port_start = ata_port_start,
422};
423
d96715c1 424static const struct piix_map_db ich5_map_db = {
d33f58b8 425 .mask = 0x7,
ea35d29e 426 .port_enable = 0x3,
d33f58b8
TH		 427 .map = {
428 /* PM PS SM SS MAP */
429 { P0, NA, P1, NA }, /* 000b */
430 { P1, NA, P0, NA }, /* 001b */
431 { RV, RV, RV, RV },
432 { RV, RV, RV, RV },
433 { P0, P1, IDE, IDE }, /* 100b */
434 { P1, P0, IDE, IDE }, /* 101b */
435 { IDE, IDE, P0, P1 }, /* 110b */
436 { IDE, IDE, P1, P0 }, /* 111b */
437 },
438};
439
d96715c1 440static const struct piix_map_db ich6_map_db = {
d33f58b8 441 .mask = 0x3,
ea35d29e 442 .port_enable = 0xf,
d33f58b8
TH		 443 .map = {
444 /* PM PS SM SS MAP */
79ea24e7 445 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 446 { IDE, IDE, P1, P3 }, /* 01b */
447 { P0, P2, IDE, IDE }, /* 10b */
448 { RV, RV, RV, RV },
449 },
450};
451
d96715c1 452static const struct piix_map_db ich6m_map_db = {
d33f58b8 453 .mask = 0x3,
ea35d29e 454 .port_enable = 0x5,
67083741
TH		 455
456 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 457 * it anyway. MAP 01b have been spotted on both ICH6M and
458 * ICH7M.
67083741
TH		 459 */
460 .map = {
461 /* PM PS SM SS MAP */
e04b3b9d 462 { P0, P2, NA, NA }, /* 00b */
67083741
TH		 463 { IDE, IDE, P1, P3 }, /* 01b */
464 { P0, P2, IDE, IDE }, /* 10b */
465 { RV, RV, RV, RV },
466 },
467};
468
08f12edc
JG		 469static const struct piix_map_db ich8_map_db = {
470 .mask = 0x3,
a0ce9aca 471 .port_enable = 0xf,
08f12edc
JG		 472 .map = {
473 /* PM PS SM SS MAP */
158f30c8 474 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 475 { RV, RV, RV, RV },
ac2b0437 476 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
08f12edc
JG		 477 { RV, RV, RV, RV },
478 },
479};
480
00242ec8 481static const struct piix_map_db ich8_2port_map_db = {
e2d352af
JG		 482 .mask = 0x3,
483 .port_enable = 0x3,
484 .map = {
485 /* PM PS SM SS MAP */
486 { P0, NA, P1, NA }, /* 00b */
487 { RV, RV, RV, RV }, /* 01b */
488 { RV, RV, RV, RV }, /* 10b */
489 { RV, RV, RV, RV },
490 },
c5cf0ffa
JG		 491};
492
8d8ef2fb
TR		 493static const struct piix_map_db ich8m_apple_map_db = {
494 .mask = 0x3,
495 .port_enable = 0x1,
496 .map = {
497 /* PM PS SM SS MAP */
498 { P0, NA, NA, NA }, /* 00b */
499 { RV, RV, RV, RV },
500 { P0, P2, IDE, IDE }, /* 10b */
501 { RV, RV, RV, RV },
502 },
503};
504
00242ec8 505static const struct piix_map_db tolapai_map_db = {
8f73a688
JG		 506 .mask = 0x3,
507 .port_enable = 0x3,
508 .map = {
509 /* PM PS SM SS MAP */
510 { P0, NA, P1, NA }, /* 00b */
511 { RV, RV, RV, RV }, /* 01b */
512 { RV, RV, RV, RV }, /* 10b */
513 { RV, RV, RV, RV },
514 },
515};
516
d96715c1
TH		 517static const struct piix_map_db *piix_map_db_table[] = {
518 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 519 [ich6_sata] = &ich6_map_db,
520 [ich6_sata_ahci] = &ich6_map_db,
521 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 522 [ich8_sata_ahci] = &ich8_map_db,
00242ec8 523 [ich8_2port_sata] = &ich8_2port_map_db,
8d8ef2fb 524 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
c5cf0ffa 525 [tolapai_sata_ahci] = &tolapai_map_db,
d96715c1
TH		 526};
527
1da177e4 528static struct ata_port_info piix_port_info[] = {
00242ec8
TH		 529 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
530 {
531 .sht = &piix_sht,
532 .flags = PIIX_PATA_FLAGS,
533 .pio_mask = 0x1f, /* pio0-4 */
534 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
535 .port_ops = &piix_pata_ops,
536 },
537
ec300d99 538 [piix_pata_33] = /* PIIX4 at 33MHz */
1d076e5b
TH		 539 {
540 .sht = &piix_sht,
b3362f88 541 .flags = PIIX_PATA_FLAGS,
1d076e5b 542 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 543 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 544 .udma_mask = ATA_UDMA_MASK_40C,
545 .port_ops = &piix_pata_ops,
546 },
547
ec300d99 548 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
669a5db4
JG		 549 {
550 .sht = &piix_sht,
b3362f88 551 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 552 .pio_mask = 0x1f, /* pio 0-4 */
553 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
554 .udma_mask = ATA_UDMA2, /* UDMA33 */
555 .port_ops = &ich_pata_ops,
556 },
ec300d99
JG		 557
558 [ich_pata_66] = /* ICH controllers up to 66MHz */
1da177e4
LT		 559 {
560 .sht = &piix_sht,
b3362f88 561 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 562 .pio_mask = 0x1f, /* pio 0-4 */
563 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
564 .udma_mask = ATA_UDMA4,
565 .port_ops = &ich_pata_ops,
566 },
85cd7251 567
ec300d99 568 [ich_pata_100] =
669a5db4
JG		 569 {
570 .sht = &piix_sht,
b3362f88 571 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 572 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 573 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 574 .udma_mask = ATA_UDMA5, /* udma0-5 */
575 .port_ops = &ich_pata_ops,
1da177e4
LT		 576 },
577
ec300d99 578 [ich5_sata] =
1da177e4
LT		 579 {
580 .sht = &piix_sht,
228c1590 581 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 582 .pio_mask = 0x1f, /* pio0-4 */
583 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 584 .udma_mask = ATA_UDMA6,
1da177e4
LT		 585 .port_ops = &piix_sata_ops,
586 },
587
ec300d99 588 [ich6_sata] =
1da177e4
LT		 589 {
590 .sht = &piix_sht,
b3362f88 591 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 592 .pio_mask = 0x1f, /* pio0-4 */
593 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 594 .udma_mask = ATA_UDMA6,
1da177e4
LT		 595 .port_ops = &piix_sata_ops,
596 },
597
ec300d99 598 [ich6_sata_ahci] =
c368ca4e
JG		 599 {
600 .sht = &piix_sht,
b3362f88 601 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 602 PIIX_FLAG_AHCI,
c368ca4e
JG		 603 .pio_mask = 0x1f, /* pio0-4 */
604 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 605 .udma_mask = ATA_UDMA6,
c368ca4e
JG		 606 .port_ops = &piix_sata_ops,
607 },
1d076e5b 608
ec300d99 609 [ich6m_sata_ahci] =
1d076e5b
TH		 610 {
611 .sht = &piix_sht,
b3362f88 612 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 613 PIIX_FLAG_AHCI,
1d076e5b
TH		 614 .pio_mask = 0x1f, /* pio0-4 */
615 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
1d076e5b
TH		 617 .port_ops = &piix_sata_ops,
618 },
08f12edc 619
ec300d99 620 [ich8_sata_ahci] =
08f12edc
JG		 621 {
622 .sht = &piix_sht,
b3362f88 623 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 624 PIIX_FLAG_AHCI,
625 .pio_mask = 0x1f, /* pio0-4 */
626 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 627 .udma_mask = ATA_UDMA6,
08f12edc
JG		 628 .port_ops = &piix_sata_ops,
629 },
669a5db4 630
00242ec8 631 [ich8_2port_sata] =
c5cf0ffa
JG		 632 {
633 .sht = &piix_sht,
634 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
635 PIIX_FLAG_AHCI,
636 .pio_mask = 0x1f, /* pio0-4 */
637 .mwdma_mask = 0x07, /* mwdma0-2 */
638 .udma_mask = ATA_UDMA6,
639 .port_ops = &piix_sata_ops,
640 },
8f73a688 641
00242ec8 642 [tolapai_sata_ahci] =
8f73a688
JG		 643 {
644 .sht = &piix_sht,
645 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
646 PIIX_FLAG_AHCI,
647 .pio_mask = 0x1f, /* pio0-4 */
648 .mwdma_mask = 0x07, /* mwdma0-2 */
649 .udma_mask = ATA_UDMA6,
650 .port_ops = &piix_sata_ops,
651 },
8d8ef2fb
TR		 652
653 [ich8m_apple_sata_ahci] =
654 {
655 .sht = &piix_sht,
656 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
657 PIIX_FLAG_AHCI,
658 .pio_mask = 0x1f, /* pio0-4 */
659 .mwdma_mask = 0x07, /* mwdma0-2 */
660 .udma_mask = ATA_UDMA6,
661 .port_ops = &piix_sata_ops,
662 },
663
25f98131
TH		 664 [piix_pata_vmw] =
665 {
666 .sht = &piix_sht,
667 .flags = PIIX_PATA_FLAGS,
668 .pio_mask = 0x1f, /* pio0-4 */
669 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
670 .udma_mask = ATA_UDMA_MASK_40C,
671 .port_ops = &piix_vmw_ops,
672 },
673
1da177e4
LT		 674};
675
676static struct pci_bits piix_enable_bits[] = {
677 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
678 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
679};
680
681MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
682MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
683MODULE_LICENSE("GPL");
684MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
685MODULE_VERSION(DRV_VERSION);
686
fc085150
AC		 687struct ich_laptop {
688 u16 device;
689 u16 subvendor;
690 u16 subdevice;
691};
692
693/*
694 * List of laptops that use short cables rather than 80 wire
695 */
696
697static const struct ich_laptop ich_laptop[] = {
698 /* devid, subvendor, subdev */
699 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
2655e2ce 700 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
babfb682 701 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
12340106 702 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
54174db3 703 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
b33620f9 704 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
fc085150
AC		 705 /* end marker */
706 { 0, }
707};
708
1da177e4 709/**
eb4a2c7f 710 * ich_pata_cable_detect - Probe host controller cable detect info
1da177e4
LT		 711 * @ap: Port for which cable detect info is desired
712 *
713 * Read 80c cable indicator from ATA PCI device's PCI config
714 * register. This register is normally set by firmware (BIOS).
715 *
716 * LOCKING:
717 * None (inherited from caller).
718 */
669a5db4 719
eb4a2c7f 720static int ich_pata_cable_detect(struct ata_port *ap)
1da177e4 721{
cca3974e 722 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 723 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 724 u8 tmp, mask;
725
fc085150
AC		 726 /* Check for specials - Acer Aspire 5602WLMi */
727 while (lap->device) {
728 if (lap->device == pdev->device &&
729 lap->subvendor == pdev->subsystem_vendor &&
2dcb407e 730 lap->subdevice == pdev->subsystem_device)
eb4a2c7f 731 return ATA_CBL_PATA40_SHORT;
2dcb407e 732
fc085150
AC		 733 lap++;
734 }
735
1da177e4 736 /* check BIOS cable detect results */
2a88d1ac 737 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 738 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
739 if ((tmp & mask) == 0)
eb4a2c7f
AC		 740 return ATA_CBL_PATA40;
741 return ATA_CBL_PATA80;
1da177e4
LT		 742}
743
744/**
ccc4672a 745 * piix_pata_prereset - prereset for PATA host controller
cc0680a5 746 * @link: Target link
d4b2bab4 747 * @deadline: deadline jiffies for the operation
1da177e4 748 *
573db6b8
TH		 749 * LOCKING:
750 * None (inherited from caller).
751 */
cc0680a5 752static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
1da177e4 753{
cc0680a5 754 struct ata_port *ap = link->ap;
cca3974e 755 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 756
c961922b
AC		 757 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
758 return -ENOENT;
cc0680a5 759 return ata_std_prereset(link, deadline);
ccc4672a
TH		 760}
761
762static void piix_pata_error_handler(struct ata_port *ap)
763{
764 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
765 ata_std_postreset);
1da177e4
LT		 766}
767
1da177e4
LT		 768/**
769 * piix_set_piomode - Initialize host controller PATA PIO timings
770 * @ap: Port whose timings we are configuring
771 * @adev: um
1da177e4
LT		 772 *
773 * Set PIO mode for device, in host controller PCI config space.
774 *
775 * LOCKING:
776 * None (inherited from caller).
777 */
778
2dcb407e 779static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
1da177e4
LT		 780{
781 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 782 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 783 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 784 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 785 unsigned int slave_port = 0x44;
786 u16 master_data;
787 u8 slave_data;
669a5db4
JG		 788 u8 udma_enable;
789 int control = 0;
85cd7251 790
669a5db4
JG		 791 /*
792 * See Intel Document 298600-004 for the timing programing rules
793 * for ICH controllers.
794 */
1da177e4
LT		 795
796 static const /* ISP RTC */
797 u8 timings[][2] = { { 0, 0 },
798 { 0, 0 },
799 { 1, 0 },
800 { 2, 1 },
801 { 2, 3 }, };
802
669a5db4
JG		 803 if (pio >= 2)
804 control |= 1; /* TIME1 enable */
805 if (ata_pio_need_iordy(adev))
806 control |= 2; /* IE enable */
807
85cd7251 808 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 809 if (adev->class == ATA_DEV_ATA)
810 control |= 4; /* PPE enable */
811
a5bf5f5a
TH		 812 /* PIO configuration clears DTE unconditionally. It will be
813 * programmed in set_dmamode which is guaranteed to be called
814 * after set_piomode if any DMA mode is available.
815 */
1da177e4
LT		 816 pci_read_config_word(dev, master_port, &master_data);
817 if (is_slave) {
a5bf5f5a
TH		 818 /* clear TIME1|IE1|PPE1|DTE1 */
819 master_data &= 0xff0f;
669a5db4 820 /* Enable SITRE (seperate slave timing register) */
1da177e4 821 master_data |= 0x4000;
669a5db4
JG		 822 /* enable PPE1, IE1 and TIME1 as needed */
823 master_data |= (control << 4);
1da177e4 824 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 825 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4 826 /* Load the timing nibble for this slave */
a5bf5f5a
TH		 827 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
828 << (ap->port_no ? 4 : 0);
1da177e4 829 } else {
a5bf5f5a
TH		 830 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
831 master_data &= 0xccf0;
669a5db4
JG		 832 /* Enable PPE, IE and TIME as appropriate */
833 master_data |= control;
a5bf5f5a 834 /* load ISP and RCT */
1da177e4
LT		 835 master_data |=
836 (timings[pio][0] << 12) |
837 (timings[pio][1] << 8);
838 }
839 pci_write_config_word(dev, master_port, master_data);
840 if (is_slave)
841 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 842
843 /* Ensure the UDMA bit is off - it will be turned back on if
844 UDMA is selected */
85cd7251 845
669a5db4
JG		 846 if (ap->udma_mask) {
847 pci_read_config_byte(dev, 0x48, &udma_enable);
848 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
849 pci_write_config_byte(dev, 0x48, udma_enable);
850 }
1da177e4
LT		 851}
852
853/**
669a5db4 854 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 855 * @ap: Port whose timings we are configuring
669a5db4 856 * @adev: Drive in question
1da177e4 857 * @udma: udma mode, 0 - 6
c32a8fd7 858 * @isich: set if the chip is an ICH device
1da177e4
LT		 859 *
860 * Set UDMA mode for device, in host controller PCI config space.
861 *
862 * LOCKING:
863 * None (inherited from caller).
864 */
865
2dcb407e 866static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 867{
cca3974e 868 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 869 u8 master_port = ap->port_no ? 0x42 : 0x40;
870 u16 master_data;
871 u8 speed = adev->dma_mode;
872 int devid = adev->devno + 2 * ap->port_no;
dedf61db 873 u8 udma_enable = 0;
85cd7251 874
669a5db4
JG		 875 static const /* ISP RTC */
876 u8 timings[][2] = { { 0, 0 },
877 { 0, 0 },
878 { 1, 0 },
879 { 2, 1 },
880 { 2, 3 }, };
881
882 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
AC		 883 if (ap->udma_mask)
884 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 885
886 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 887 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
888 u16 udma_timing;
889 u16 ideconf;
890 int u_clock, u_speed;
85cd7251 891
669a5db4 892 /*
2dcb407e 893 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 894 * selection of dividers
895 *
669a5db4 896 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 897 * except UDMA0 which is 00
669a5db4
JG		 898 */
899 u_speed = min(2 - (udma & 1), udma);
900 if (udma == 5)
901 u_clock = 0x1000; /* 100Mhz */
902 else if (udma > 2)
903 u_clock = 1; /* 66Mhz */
904 else
905 u_clock = 0; /* 33Mhz */
85cd7251 906
669a5db4 907 udma_enable |= (1 << devid);
85cd7251 908
669a5db4
JG		 909 /* Load the CT/RP selection */
910 pci_read_config_word(dev, 0x4A, &udma_timing);
911 udma_timing &= ~(3 << (4 * devid));
912 udma_timing |= u_speed << (4 * devid);
913 pci_write_config_word(dev, 0x4A, udma_timing);
914
85cd7251 915 if (isich) {
669a5db4
JG		 916 /* Select a 33/66/100Mhz clock */
917 pci_read_config_word(dev, 0x54, &ideconf);
918 ideconf &= ~(0x1001 << devid);
919 ideconf |= u_clock << devid;
920 /* For ICH or later we should set bit 10 for better
921 performance (WR_PingPong_En) */
922 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 923 }
1da177e4 924 } else {
669a5db4
JG		 925 /*
926 * MWDMA is driven by the PIO timings. We must also enable
927 * IORDY unconditionally along with TIME1. PPE has already
928 * been set when the PIO timing was set.
929 */
930 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
931 unsigned int control;
932 u8 slave_data;
933 const unsigned int needed_pio[3] = {
934 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
935 };
936 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 937
669a5db4 938 control = 3; /* IORDY|TIME1 */
85cd7251 939
669a5db4
JG		 940 /* If the drive MWDMA is faster than it can do PIO then
941 we must force PIO into PIO0 */
85cd7251 942
669a5db4
JG		 943 if (adev->pio_mode < needed_pio[mwdma])
944 /* Enable DMA timing only */
945 control |= 8; /* PIO cycles in PIO0 */
946
947 if (adev->devno) { /* Slave */
948 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
949 master_data |= control << 4;
950 pci_read_config_byte(dev, 0x44, &slave_data);
a5bf5f5a 951 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 952 /* Load the matching timing */
953 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
954 pci_write_config_byte(dev, 0x44, slave_data);
955 } else { /* Master */
85cd7251 956 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 957 and master timing bits */
958 master_data |= control;
959 master_data |=
960 (timings[pio][0] << 12) |
961 (timings[pio][1] << 8);
962 }
a5bf5f5a
TH		 963
964 if (ap->udma_mask) {
965 udma_enable &= ~(1 << devid);
966 pci_write_config_word(dev, master_port, master_data);
967 }
1da177e4 968 }
669a5db4
JG		 969 /* Don't scribble on 0x48 if the controller does not support UDMA */
970 if (ap->udma_mask)
971 pci_write_config_byte(dev, 0x48, udma_enable);
972}
973
974/**
975 * piix_set_dmamode - Initialize host controller PATA DMA timings
976 * @ap: Port whose timings we are configuring
977 * @adev: um
978 *
979 * Set MW/UDMA mode for device, in host controller PCI config space.
980 *
981 * LOCKING:
982 * None (inherited from caller).
983 */
984
2dcb407e 985static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 986{
987 do_pata_set_dmamode(ap, adev, 0);
988}
989
990/**
991 * ich_set_dmamode - Initialize host controller PATA DMA timings
992 * @ap: Port whose timings we are configuring
993 * @adev: um
994 *
995 * Set MW/UDMA mode for device, in host controller PCI config space.
996 *
997 * LOCKING:
998 * None (inherited from caller).
999 */
1000
2dcb407e 1001static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 1002{
1003 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 1004}
1005
b8b275ef 1006#ifdef CONFIG_PM
8c3832eb
TH		 1007static int piix_broken_suspend(void)
1008{
1855256c 1009 static const struct dmi_system_id sysids[] = {
4c74d4ec
TH		 1010 {
1011 .ident = "TECRA M3",
1012 .matches = {
1013 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1014 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1015 },
1016 },
04d86d6f
PS		 1017 {
1018 .ident = "TECRA M3",
1019 .matches = {
1020 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1021 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1022 },
1023 },
d1aa690a
PS		 1024 {
1025 .ident = "TECRA M4",
1026 .matches = {
1027 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1028 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1029 },
1030 },
8c3832eb
TH		 1031 {
1032 .ident = "TECRA M5",
1033 .matches = {
1034 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1035 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1036 },
b8b275ef 1037 },
ffe188dd
PS		 1038 {
1039 .ident = "TECRA M6",
1040 .matches = {
1041 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1042 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1043 },
1044 },
5c08ea01
TH		 1045 {
1046 .ident = "TECRA M7",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1050 },
1051 },
04d86d6f
PS		 1052 {
1053 .ident = "TECRA A8",
1054 .matches = {
1055 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1056 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1057 },
1058 },
ffe188dd
PS		 1059 {
1060 .ident = "Satellite R20",
1061 .matches = {
1062 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1063 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1064 },
1065 },
04d86d6f
PS		 1066 {
1067 .ident = "Satellite R25",
1068 .matches = {
1069 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1070 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1071 },
1072 },
3cc0b9d3
TH		 1073 {
1074 .ident = "Satellite U200",
1075 .matches = {
1076 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1077 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1078 },
1079 },
04d86d6f
PS		 1080 {
1081 .ident = "Satellite U200",
1082 .matches = {
1083 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1084 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1085 },
1086 },
62320e23
YC		 1087 {
1088 .ident = "Satellite Pro U200",
1089 .matches = {
1090 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1091 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1092 },
1093 },
8c3832eb
TH		 1094 {
1095 .ident = "Satellite U205",
1096 .matches = {
1097 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1098 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1099 },
b8b275ef 1100 },
de753e5e
TH		 1101 {
1102 .ident = "SATELLITE U205",
1103 .matches = {
1104 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1105 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1106 },
1107 },
8c3832eb
TH		 1108 {
1109 .ident = "Portege M500",
1110 .matches = {
1111 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1112 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1113 },
b8b275ef 1114 },
7d051548
JG		 1115
1116 { } /* terminate list */
8c3832eb 1117 };
7abe79c3
TH		 1118 static const char *oemstrs[] = {
1119 "Tecra M3,",
1120 };
1121 int i;
8c3832eb
TH		 1122
1123 if (dmi_check_system(sysids))
1124 return 1;
1125
7abe79c3
TH		 1126 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1127 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1128 return 1;
1129
8c3832eb
TH		 1130 return 0;
1131}
b8b275ef
TH		 1132
1133static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1134{
1135 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1136 unsigned long flags;
1137 int rc = 0;
1138
1139 rc = ata_host_suspend(host, mesg);
1140 if (rc)
1141 return rc;
1142
1143 /* Some braindamaged ACPI suspend implementations expect the
1144 * controller to be awake on entry; otherwise, it burns cpu
1145 * cycles and power trying to do something to the sleeping
1146 * beauty.
1147 */
8c3832eb 1148 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
b8b275ef
TH		 1149 pci_save_state(pdev);
1150
1151 /* mark its power state as "unknown", since we don't
1152 * know if e.g. the BIOS will change its device state
1153 * when we suspend.
1154 */
1155 if (pdev->current_state == PCI_D0)
1156 pdev->current_state = PCI_UNKNOWN;
1157
1158 /* tell resume that it's waking up from broken suspend */
1159 spin_lock_irqsave(&host->lock, flags);
1160 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1161 spin_unlock_irqrestore(&host->lock, flags);
1162 } else
1163 ata_pci_device_do_suspend(pdev, mesg);
1164
1165 return 0;
1166}
1167
1168static int piix_pci_device_resume(struct pci_dev *pdev)
1169{
1170 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1171 unsigned long flags;
1172 int rc;
1173
1174 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1175 spin_lock_irqsave(&host->lock, flags);
1176 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1177 spin_unlock_irqrestore(&host->lock, flags);
1178
1179 pci_set_power_state(pdev, PCI_D0);
1180 pci_restore_state(pdev);
1181
1182 /* PCI device wasn't disabled during suspend. Use
0b62e13b
TH		 1183 * pci_reenable_device() to avoid affecting the enable
1184 * count.
b8b275ef 1185 */
0b62e13b 1186 rc = pci_reenable_device(pdev);
b8b275ef
TH		 1187 if (rc)
1188 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1189 "device after resume (%d)\n", rc);
1190 } else
1191 rc = ata_pci_device_do_resume(pdev);
1192
1193 if (rc == 0)
1194 ata_host_resume(host);
1195
1196 return rc;
1197}
1198#endif
1199
25f98131
TH		 1200static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1201{
1202 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1203}
1204
1da177e4
LT		 1205#define AHCI_PCI_BAR 5
1206#define AHCI_GLOBAL_CTL 0x04
1207#define AHCI_ENABLE (1 << 31)
1208static int piix_disable_ahci(struct pci_dev *pdev)
1209{
ea6ba10b 1210 void __iomem *mmio;
1da177e4
LT		 1211 u32 tmp;
1212 int rc = 0;
1213
1214 /* BUG: pci_enable_device has not yet been called. This
1215 * works because this device is usually set up by BIOS.
1216 */
1217
374b1873
JG		 1218 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1219 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 1220 return 0;
7b6dbd68 1221
374b1873 1222 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 1223 if (!mmio)
1224 return -ENOMEM;
7b6dbd68 1225
c47a631f 1226 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1da177e4
LT		 1227 if (tmp & AHCI_ENABLE) {
1228 tmp &= ~AHCI_ENABLE;
c47a631f 1229 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1da177e4 1230
c47a631f 1231 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1da177e4
LT		 1232 if (tmp & AHCI_ENABLE)
1233 rc = -EIO;
1234 }
7b6dbd68 1235
374b1873 1236 pci_iounmap(pdev, mmio);
1da177e4
LT		 1237 return rc;
1238}
1239
c621b140
AC		 1240/**
1241 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 1242 * @ata_dev: the PCI device to check
2e9edbf8 1243 *
c621b140
AC		 1244 * Check for the present of 450NX errata #19 and errata #25. If
1245 * they are found return an error code so we can turn off DMA
1246 */
1247
1248static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1249{
1250 struct pci_dev *pdev = NULL;
1251 u16 cfg;
c621b140 1252 int no_piix_dma = 0;
2e9edbf8 1253
2dcb407e 1254 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
c621b140
AC		 1255 /* Look for 450NX PXB. Check for problem configurations
1256 A PCI quirk checks bit 6 already */
c621b140
AC		 1257 pci_read_config_word(pdev, 0x41, &cfg);
1258 /* Only on the original revision: IDE DMA can hang */
44c10138 1259 if (pdev->revision == 0x00)
c621b140
AC		 1260 no_piix_dma = 1;
1261 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138 1262 else if (cfg & (1<<14) && pdev->revision < 5)
c621b140
AC		 1263 no_piix_dma = 2;
1264 }
31a34fe7 1265 if (no_piix_dma)
c621b140 1266 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 1267 if (no_piix_dma == 2)
c621b140
AC		 1268 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1269 return no_piix_dma;
2e9edbf8 1270}
c621b140 1271
ea35d29e 1272static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 1273 struct ata_port_info *pinfo,
ea35d29e
JG		 1274 const struct piix_map_db *map_db)
1275{
1276 u16 pcs, new_pcs;
1277
1278 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1279
1280 new_pcs = pcs | map_db->port_enable;
1281
1282 if (new_pcs != pcs) {
1283 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1284 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1285 msleep(150);
1286 }
1287}
1288
d33f58b8 1289static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 1290 struct ata_port_info *pinfo,
1291 const struct piix_map_db *map_db)
d33f58b8 1292{
d96715c1 1293 struct piix_host_priv *hpriv = pinfo[0].private_data;
b4482a4b 1294 const int *map;
d33f58b8
TH		 1295 int i, invalid_map = 0;
1296 u8 map_value;
1297
1298 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1299
1300 map = map_db->map[map_value & map_db->mask];
1301
1302 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1303 for (i = 0; i < 4; i++) {
1304 switch (map[i]) {
1305 case RV:
1306 invalid_map = 1;
1307 printk(" XX");
1308 break;
1309
1310 case NA:
1311 printk(" --");
1312 break;
1313
1314 case IDE:
1315 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1316 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1317 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1318 i++;
1319 printk(" IDE IDE");
1320 break;
1321
1322 default:
1323 printk(" P%d", map[i]);
1324 if (i & 1)
cca3974e 1325 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1326 break;
1327 }
1328 }
1329 printk(" ]\n");
1330
1331 if (invalid_map)
1332 dev_printk(KERN_ERR, &pdev->dev,
1333 "invalid MAP value %u\n", map_value);
1334
d96715c1 1335 hpriv->map = map;
d33f58b8
TH		 1336}
1337
43a98f05
TH		 1338static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1339{
1855256c 1340 static const struct dmi_system_id sysids[] = {
43a98f05
TH		 1341 {
1342 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1343 * isn't used to boot the system which
1344 * disables the channel.
1345 */
1346 .ident = "M570U",
1347 .matches = {
1348 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1349 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1350 },
1351 },
7d051548
JG		 1352
1353 { } /* terminate list */
43a98f05
TH		 1354 };
1355 u32 iocfg;
1356
1357 if (!dmi_check_system(sysids))
1358 return;
1359
1360 /* The datasheet says that bit 18 is NOOP but certain systems
1361 * seem to use it to disable a channel. Clear the bit on the
1362 * affected systems.
1363 */
1364 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1365 if (iocfg & (1 << 18)) {
1366 dev_printk(KERN_INFO, &pdev->dev,
1367 "applying IOCFG bit18 quirk\n");
1368 iocfg &= ~(1 << 18);
1369 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1370 }
1371}
1372
1da177e4
LT		 1373/**
1374 * piix_init_one - Register PIIX ATA PCI device with kernel services
1375 * @pdev: PCI device to register
1376 * @ent: Entry in piix_pci_tbl matching with @pdev
1377 *
1378 * Called from kernel PCI layer. We probe for combined mode (sigh),
1379 * and then hand over control to libata, for it to do the rest.
1380 *
1381 * LOCKING:
1382 * Inherited from PCI layer (may sleep).
1383 *
1384 * RETURNS:
1385 * Zero on success, or -ERRNO value.
1386 */
1387
2dcb407e 1388static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1389{
1390 static int printed_version;
24dc5f33 1391 struct device *dev = &pdev->dev;
d33f58b8 1392 struct ata_port_info port_info[2];
1626aeb8 1393 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
d96715c1 1394 struct piix_host_priv *hpriv;
cca3974e 1395 unsigned long port_flags;
1da177e4
LT		 1396
1397 if (!printed_version++)
6248e647
JG		 1398 dev_printk(KERN_DEBUG, &pdev->dev,
1399 "version " DRV_VERSION "\n");
1da177e4
LT		 1400
1401 /* no hotplugging support (FIXME) */
1402 if (!in_module_init)
1403 return -ENODEV;
1404
24dc5f33 1405 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1406 if (!hpriv)
1407 return -ENOMEM;
1408
d33f58b8
TH		 1409 port_info[0] = piix_port_info[ent->driver_data];
1410 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1411 port_info[0].private_data = hpriv;
1412 port_info[1].private_data = hpriv;
1da177e4 1413
cca3974e 1414 port_flags = port_info[0].flags;
ff0fc146 1415
cca3974e 1416 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1417 u8 tmp;
1418 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1419 if (tmp == PIIX_AHCI_DEVICE) {
1420 int rc = piix_disable_ahci(pdev);
1421 if (rc)
1422 return rc;
1423 }
1da177e4
LT		 1424 }
1425
d33f58b8 1426 /* Initialize SATA map */
cca3974e 1427 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1428 piix_init_sata_map(pdev, port_info,
1429 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1430 piix_init_pcs(pdev, port_info,
1431 piix_map_db_table[ent->driver_data]);
ea35d29e 1432 }
1da177e4 1433
43a98f05
TH		 1434 /* apply IOCFG bit18 quirk */
1435 piix_iocfg_bit18_quirk(pdev);
1436
1da177e4
LT		 1437 /* On ICH5, some BIOSen disable the interrupt using the
1438 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1439 * On ICH6, this bit has the same effect, but only when
1440 * MSI is disabled (and it is disabled, as we don't use
1441 * message-signalled interrupts currently).
1442 */
cca3974e 1443 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1444 pci_intx(pdev, 1);
1da177e4 1445
c621b140
AC		 1446 if (piix_check_450nx_errata(pdev)) {
1447 /* This writes into the master table but it does not
1448 really matter for this errata as we will apply it to
1449 all the PIIX devices on the board */
d33f58b8
TH		 1450 port_info[0].mwdma_mask = 0;
1451 port_info[0].udma_mask = 0;
1452 port_info[1].mwdma_mask = 0;
1453 port_info[1].udma_mask = 0;
c621b140 1454 }
1626aeb8 1455 return ata_pci_init_one(pdev, ppi);
1da177e4
LT		 1456}
1457
1da177e4
LT		 1458static int __init piix_init(void)
1459{
1460 int rc;
1461
b7887196
PR		 1462 DPRINTK("pci_register_driver\n");
1463 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1464 if (rc)
1465 return rc;
1466
1467 in_module_init = 0;
1468
1469 DPRINTK("done\n");
1470 return 0;
1471}
1472
1da177e4
LT		 1473static void __exit piix_exit(void)
1474{
1475 pci_unregister_driver(&piix_pci_driver);
1476}
1477
1478module_init(piix_init);
1479module_exit(piix_exit);
Clone of davem's net-next-2.6 tree