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ata_timing: ensure t->cycle is always correct
[net-next-2.6.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
1da177e4 44#include <scsi/scsi_host.h>
193515d5 45#include <scsi/scsi_cmnd.h>
1da177e4 46#include <linux/libata.h>
1da177e4
LT		 47
48#define DRV_NAME "ahci"
cb48cab7 49#define DRV_VERSION "2.1"
1da177e4
LT		 50
51
52enum {
53 AHCI_PCI_BAR = 5,
648a88be 54 AHCI_MAX_PORTS = 32,
1da177e4
LT		 55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
12fad3f9 58 AHCI_MAX_CMDS = 32,
dd410ff1 59 AHCI_CMD_SZ = 32,
12fad3f9 60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 61 AHCI_RX_FIS_SZ = 256,
a0ea7328 62 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
4b10e559 71 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
648a88be
TH		 80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
55a61604 83 board_ahci_sb600 = 4,
1da177e4
LT		 84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
0be0aa98 98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
22b49985 99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
979db803 101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 103
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140
78cd52d0
TH		 141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
142 PORT_IRQ_IF_ERR |
143 PORT_IRQ_CONNECT |
4296971d 144 PORT_IRQ_PHYRDY |
78cd52d0
TH		 145 PORT_IRQ_UNK_FIS,
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_TF_ERR |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 152
153 /* PORT_CMD bits */
02eaa666 154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 158 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162
0be0aa98 163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 167
bf2af2a2 168 /* ap->flags bits */
4aeb0e32
TH		 169 AHCI_FLAG_NO_NCQ = (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
648a88be 171 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
55a61604 172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
1da177e4
LT		 173};
174
175struct ahci_cmd_hdr {
176 u32 opts;
177 u32 status;
178 u32 tbl_addr;
179 u32 tbl_addr_hi;
180 u32 reserved[4];
181};
182
183struct ahci_sg {
184 u32 addr;
185 u32 addr_hi;
186 u32 reserved;
187 u32 flags_size;
188};
189
190struct ahci_host_priv {
d447df14
TH		 191 u32 cap; /* cap to use */
192 u32 port_map; /* port map to use */
193 u32 saved_cap; /* saved initial cap */
194 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 195};
196
197struct ahci_port_priv {
198 struct ahci_cmd_hdr *cmd_slot;
199 dma_addr_t cmd_slot_dma;
200 void *cmd_tbl;
201 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 202 void *rx_fis;
203 dma_addr_t rx_fis_dma;
0291f95f 204 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 205 unsigned int ncq_saw_d2h:1;
206 unsigned int ncq_saw_dmas:1;
afb2d552 207 unsigned int ncq_saw_sdb:1;
1da177e4
LT		 208};
209
210static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
211static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
212static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 213static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 214static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 215static int ahci_port_start(struct ata_port *ap);
216static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 217static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
218static void ahci_qc_prep(struct ata_queued_cmd *qc);
219static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 220static void ahci_freeze(struct ata_port *ap);
221static void ahci_thaw(struct ata_port *ap);
222static void ahci_error_handler(struct ata_port *ap);
ad616ffb 223static void ahci_vt8251_error_handler(struct ata_port *ap);
78cd52d0 224static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
438ac6d5 225#ifdef CONFIG_PM
c1332875
TH		 226static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
227static int ahci_port_resume(struct ata_port *ap);
228static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
229static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 230#endif
1da177e4 231
193515d5 232static struct scsi_host_template ahci_sht = {
1da177e4
LT		 233 .module = THIS_MODULE,
234 .name = DRV_NAME,
235 .ioctl = ata_scsi_ioctl,
236 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 237 .change_queue_depth = ata_scsi_change_queue_depth,
238 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 239 .this_id = ATA_SHT_THIS_ID,
240 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 241 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
242 .emulated = ATA_SHT_EMULATED,
243 .use_clustering = AHCI_USE_CLUSTERING,
244 .proc_name = DRV_NAME,
245 .dma_boundary = AHCI_DMA_BOUNDARY,
246 .slave_configure = ata_scsi_slave_config,
ccf68c34 247 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 248 .bios_param = ata_std_bios_param,
438ac6d5 249#ifdef CONFIG_PM
c1332875
TH		 250 .suspend = ata_scsi_device_suspend,
251 .resume = ata_scsi_device_resume,
438ac6d5 252#endif
1da177e4
LT		 253};
254
057ace5e 255static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 256 .port_disable = ata_port_disable,
257
258 .check_status = ahci_check_status,
259 .check_altstatus = ahci_check_status,
1da177e4
LT		 260 .dev_select = ata_noop_dev_select,
261
262 .tf_read = ahci_tf_read,
263
1da177e4
LT		 264 .qc_prep = ahci_qc_prep,
265 .qc_issue = ahci_qc_issue,
266
1da177e4 267 .irq_clear = ahci_irq_clear,
246ce3b6
AI		 268 .irq_on = ata_dummy_irq_on,
269 .irq_ack = ata_dummy_irq_ack,
1da177e4
LT		 270
271 .scr_read = ahci_scr_read,
272 .scr_write = ahci_scr_write,
273
78cd52d0
TH		 274 .freeze = ahci_freeze,
275 .thaw = ahci_thaw,
276
277 .error_handler = ahci_error_handler,
278 .post_internal_cmd = ahci_post_internal_cmd,
279
438ac6d5 280#ifdef CONFIG_PM
c1332875
TH		 281 .port_suspend = ahci_port_suspend,
282 .port_resume = ahci_port_resume,
438ac6d5 283#endif
c1332875 284
1da177e4
LT		 285 .port_start = ahci_port_start,
286 .port_stop = ahci_port_stop,
1da177e4
LT		 287};
288
ad616ffb
TH		 289static const struct ata_port_operations ahci_vt8251_ops = {
290 .port_disable = ata_port_disable,
291
292 .check_status = ahci_check_status,
293 .check_altstatus = ahci_check_status,
294 .dev_select = ata_noop_dev_select,
295
296 .tf_read = ahci_tf_read,
297
298 .qc_prep = ahci_qc_prep,
299 .qc_issue = ahci_qc_issue,
300
ad616ffb 301 .irq_clear = ahci_irq_clear,
246ce3b6
AI		 302 .irq_on = ata_dummy_irq_on,
303 .irq_ack = ata_dummy_irq_ack,
ad616ffb
TH		 304
305 .scr_read = ahci_scr_read,
306 .scr_write = ahci_scr_write,
307
308 .freeze = ahci_freeze,
309 .thaw = ahci_thaw,
310
311 .error_handler = ahci_vt8251_error_handler,
312 .post_internal_cmd = ahci_post_internal_cmd,
313
438ac6d5 314#ifdef CONFIG_PM
ad616ffb
TH		 315 .port_suspend = ahci_port_suspend,
316 .port_resume = ahci_port_resume,
438ac6d5 317#endif
ad616ffb
TH		 318
319 .port_start = ahci_port_start,
320 .port_stop = ahci_port_stop,
321};
322
98ac62de 323static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 324 /* board_ahci */
325 {
cca3974e 326 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4296971d
TH		 327 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
328 ATA_FLAG_SKIP_D2H_BSY,
7da79312 329 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
331 .port_ops = &ahci_ops,
332 },
648a88be
TH		 333 /* board_ahci_pi */
334 {
648a88be
TH		 335 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
336 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
337 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
338 .pio_mask = 0x1f, /* pio0-4 */
339 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
340 .port_ops = &ahci_ops,
341 },
bf2af2a2
BJ		 342 /* board_ahci_vt8251 */
343 {
cca3974e 344 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bf2af2a2 345 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
ad616ffb
TH		 346 ATA_FLAG_SKIP_D2H_BSY |
347 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
bf2af2a2
BJ		 348 .pio_mask = 0x1f, /* pio0-4 */
349 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
ad616ffb 350 .port_ops = &ahci_vt8251_ops,
bf2af2a2 351 },
41669553
TH		 352 /* board_ahci_ign_iferr */
353 {
41669553
TH		 354 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
355 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
356 ATA_FLAG_SKIP_D2H_BSY |
357 AHCI_FLAG_IGN_IRQ_IF_ERR,
358 .pio_mask = 0x1f, /* pio0-4 */
359 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
360 .port_ops = &ahci_ops,
361 },
55a61604
CH		 362 /* board_ahci_sb600 */
363 {
364 .sht = &ahci_sht,
365 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
366 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
367 ATA_FLAG_SKIP_D2H_BSY |
368 AHCI_FLAG_IGN_SERR_INTERNAL,
369 .pio_mask = 0x1f, /* pio0-4 */
370 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
371 .port_ops = &ahci_ops,
372 },
373
1da177e4
LT		 374};
375
3b7d697d 376static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 377 /* Intel */
54bb3a94
JG		 378 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
379 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
380 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
381 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
382 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 383 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 384 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
385 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
386 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
387 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
648a88be
TH		 388 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
389 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
390 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
391 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
392 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
393 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
394 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
395 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
396 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
397 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
398 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
399 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
400 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
8af12cdb 401 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
648a88be
TH		 402 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
403 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
404 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
fe7fa31a 405
e34bb370
TH		 406 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
407 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
408 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 409
410 /* ATI */
c65ec1c2 411 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
fe7fa31a
JG		 412
413 /* VIA */
54bb3a94 414 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 415 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 416
417 /* NVIDIA */
54bb3a94
JG		 418 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 422 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 430 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
fe7fa31a 438
95916edd 439 /* SiS */
54bb3a94
JG		 440 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
441 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
442 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 443
415ae2b5
JG		 444 /* Generic, PCI class code for AHCI */
445 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 446 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 447
1da177e4
LT		 448 { } /* terminate list */
449};
450
451
452static struct pci_driver ahci_pci_driver = {
453 .name = DRV_NAME,
454 .id_table = ahci_pci_tbl,
455 .probe = ahci_init_one,
24dc5f33 456 .remove = ata_pci_remove_one,
438ac6d5 457#ifdef CONFIG_PM
c1332875
TH		 458 .suspend = ahci_pci_device_suspend,
459 .resume = ahci_pci_device_resume,
438ac6d5 460#endif
1da177e4
LT		 461};
462
463
98fa4b60
TH		 464static inline int ahci_nr_ports(u32 cap)
465{
466 return (cap & 0x1f) + 1;
467}
468
4447d351 469static inline void __iomem *ahci_port_base(struct ata_port *ap)
1da177e4 470{
4447d351
TH		 471 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
472
473 return mmio + 0x100 + (ap->port_no * 0x80);
1da177e4
LT		 474}
475
d447df14
TH		 476/**
477 * ahci_save_initial_config - Save and fixup initial config values
4447d351
TH		 478 * @pdev: target PCI device
479 * @pi: associated ATA port info
480 * @hpriv: host private area to store config values
d447df14
TH		 481 *
482 * Some registers containing configuration info might be setup by
483 * BIOS and might be cleared on reset. This function saves the
484 * initial values of those registers into @hpriv such that they
485 * can be restored after controller reset.
486 *
487 * If inconsistent, config values are fixed up by this function.
488 *
489 * LOCKING:
490 * None.
491 */
4447d351
TH		 492static void ahci_save_initial_config(struct pci_dev *pdev,
493 const struct ata_port_info *pi,
494 struct ahci_host_priv *hpriv)
d447df14 495{
4447d351 496 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 497 u32 cap, port_map;
17199b18 498 int i;
d447df14
TH		 499
500 /* Values prefixed with saved_ are written back to host after
501 * reset. Values without are used for driver operation.
502 */
503 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
504 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
505
506 /* fixup zero port_map */
507 if (!port_map) {
508 port_map = (1 << ahci_nr_ports(hpriv->cap)) - 1;
4447d351 509 dev_printk(KERN_WARNING, &pdev->dev,
d447df14
TH		 510 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
511
512 /* write the fixed up value to the PI register */
513 hpriv->saved_port_map = port_map;
514 }
515
17199b18 516 /* cross check port_map and cap.n_ports */
4447d351 517 if (pi->flags & AHCI_FLAG_HONOR_PI) {
17199b18
TH		 518 u32 tmp_port_map = port_map;
519 int n_ports = ahci_nr_ports(cap);
520
521 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
522 if (tmp_port_map & (1 << i)) {
523 n_ports--;
524 tmp_port_map &= ~(1 << i);
525 }
526 }
527
528 /* Whine if inconsistent. No need to update cap.
529 * port_map is used to determine number of ports.
530 */
531 if (n_ports || tmp_port_map)
4447d351 532 dev_printk(KERN_WARNING, &pdev->dev,
17199b18
TH		 533 "nr_ports (%u) and implemented port map "
534 "(0x%x) don't match\n",
535 ahci_nr_ports(cap), port_map);
536 } else {
537 /* fabricate port_map from cap.nr_ports */
538 port_map = (1 << ahci_nr_ports(cap)) - 1;
539 }
540
d447df14
TH		 541 /* record values to use during operation */
542 hpriv->cap = cap;
543 hpriv->port_map = port_map;
544}
545
546/**
547 * ahci_restore_initial_config - Restore initial config
4447d351 548 * @host: target ATA host
d447df14
TH		 549 *
550 * Restore initial config stored by ahci_save_initial_config().
551 *
552 * LOCKING:
553 * None.
554 */
4447d351 555static void ahci_restore_initial_config(struct ata_host *host)
d447df14 556{
4447d351
TH		 557 struct ahci_host_priv *hpriv = host->private_data;
558 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
559
d447df14
TH		 560 writel(hpriv->saved_cap, mmio + HOST_CAP);
561 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
562 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
563}
564
1da177e4
LT		 565static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
566{
567 unsigned int sc_reg;
568
569 switch (sc_reg_in) {
570 case SCR_STATUS: sc_reg = 0; break;
571 case SCR_CONTROL: sc_reg = 1; break;
572 case SCR_ERROR: sc_reg = 2; break;
573 case SCR_ACTIVE: sc_reg = 3; break;
574 default:
575 return 0xffffffffU;
576 }
577
0d5ff566 578 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 579}
580
581
582static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
583 u32 val)
584{
585 unsigned int sc_reg;
586
587 switch (sc_reg_in) {
588 case SCR_STATUS: sc_reg = 0; break;
589 case SCR_CONTROL: sc_reg = 1; break;
590 case SCR_ERROR: sc_reg = 2; break;
591 case SCR_ACTIVE: sc_reg = 3; break;
592 default:
593 return;
594 }
595
0d5ff566 596 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 597}
598
4447d351 599static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 600{
4447d351 601 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 602 u32 tmp;
603
d8fcd116 604 /* start DMA */
9f592056 605 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 606 tmp |= PORT_CMD_START;
607 writel(tmp, port_mmio + PORT_CMD);
608 readl(port_mmio + PORT_CMD); /* flush */
609}
610
4447d351 611static int ahci_stop_engine(struct ata_port *ap)
254950cd 612{
4447d351 613 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 614 u32 tmp;
615
616 tmp = readl(port_mmio + PORT_CMD);
617
d8fcd116 618 /* check if the HBA is idle */
254950cd
TH		 619 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
620 return 0;
621
d8fcd116 622 /* setting HBA to idle */
254950cd
TH		 623 tmp &= ~PORT_CMD_START;
624 writel(tmp, port_mmio + PORT_CMD);
625
d8fcd116 626 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 627 tmp = ata_wait_register(port_mmio + PORT_CMD,
628 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 629 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 630 return -EIO;
631
632 return 0;
633}
634
4447d351 635static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 636{
4447d351
TH		 637 void __iomem *port_mmio = ahci_port_base(ap);
638 struct ahci_host_priv *hpriv = ap->host->private_data;
639 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 640 u32 tmp;
641
642 /* set FIS registers */
4447d351
TH		 643 if (hpriv->cap & HOST_CAP_64)
644 writel((pp->cmd_slot_dma >> 16) >> 16,
645 port_mmio + PORT_LST_ADDR_HI);
646 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 647
4447d351
TH		 648 if (hpriv->cap & HOST_CAP_64)
649 writel((pp->rx_fis_dma >> 16) >> 16,
650 port_mmio + PORT_FIS_ADDR_HI);
651 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 652
653 /* enable FIS reception */
654 tmp = readl(port_mmio + PORT_CMD);
655 tmp |= PORT_CMD_FIS_RX;
656 writel(tmp, port_mmio + PORT_CMD);
657
658 /* flush */
659 readl(port_mmio + PORT_CMD);
660}
661
4447d351 662static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 663{
4447d351 664 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 665 u32 tmp;
666
667 /* disable FIS reception */
668 tmp = readl(port_mmio + PORT_CMD);
669 tmp &= ~PORT_CMD_FIS_RX;
670 writel(tmp, port_mmio + PORT_CMD);
671
672 /* wait for completion, spec says 500ms, give it 1000 */
673 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
674 PORT_CMD_FIS_ON, 10, 1000);
675 if (tmp & PORT_CMD_FIS_ON)
676 return -EBUSY;
677
678 return 0;
679}
680
4447d351 681static void ahci_power_up(struct ata_port *ap)
0be0aa98 682{
4447d351
TH		 683 struct ahci_host_priv *hpriv = ap->host->private_data;
684 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 685 u32 cmd;
686
687 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
688
689 /* spin up device */
4447d351 690 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 691 cmd |= PORT_CMD_SPIN_UP;
692 writel(cmd, port_mmio + PORT_CMD);
693 }
694
695 /* wake up link */
696 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
697}
698
438ac6d5 699#ifdef CONFIG_PM
4447d351 700static void ahci_power_down(struct ata_port *ap)
0be0aa98 701{
4447d351
TH		 702 struct ahci_host_priv *hpriv = ap->host->private_data;
703 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 704 u32 cmd, scontrol;
705
4447d351 706 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 707 return;
0be0aa98 708
07c53dac
TH		 709 /* put device into listen mode, first set PxSCTL.DET to 0 */
710 scontrol = readl(port_mmio + PORT_SCR_CTL);
711 scontrol &= ~0xf;
712 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 713
07c53dac
TH		 714 /* then set PxCMD.SUD to 0 */
715 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
716 cmd &= ~PORT_CMD_SPIN_UP;
717 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 718}
438ac6d5 719#endif
0be0aa98 720
4447d351 721static void ahci_init_port(struct ata_port *ap)
0be0aa98 722{
0be0aa98 723 /* enable FIS reception */
4447d351 724 ahci_start_fis_rx(ap);
0be0aa98
TH		 725
726 /* enable DMA */
4447d351 727 ahci_start_engine(ap);
0be0aa98
TH		 728}
729
4447d351 730static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 731{
732 int rc;
733
734 /* disable DMA */
4447d351 735 rc = ahci_stop_engine(ap);
0be0aa98
TH		 736 if (rc) {
737 *emsg = "failed to stop engine";
738 return rc;
739 }
740
741 /* disable FIS reception */
4447d351 742 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 743 if (rc) {
744 *emsg = "failed stop FIS RX";
745 return rc;
746 }
747
0be0aa98
TH		 748 return 0;
749}
750
4447d351 751static int ahci_reset_controller(struct ata_host *host)
d91542c1 752{
4447d351
TH		 753 struct pci_dev *pdev = to_pci_dev(host->dev);
754 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 755 u32 tmp;
d91542c1
TH		 756
757 /* global controller reset */
758 tmp = readl(mmio + HOST_CTL);
759 if ((tmp & HOST_RESET) == 0) {
760 writel(tmp | HOST_RESET, mmio + HOST_CTL);
761 readl(mmio + HOST_CTL); /* flush */
762 }
763
764 /* reset must complete within 1 second, or
765 * the hardware should be considered fried.
766 */
767 ssleep(1);
768
769 tmp = readl(mmio + HOST_CTL);
770 if (tmp & HOST_RESET) {
4447d351 771 dev_printk(KERN_ERR, host->dev,
d91542c1
TH		 772 "controller reset failed (0x%x)\n", tmp);
773 return -EIO;
774 }
775
98fa4b60 776 /* turn on AHCI mode */
d91542c1
TH		 777 writel(HOST_AHCI_EN, mmio + HOST_CTL);
778 (void) readl(mmio + HOST_CTL); /* flush */
98fa4b60 779
d447df14 780 /* some registers might be cleared on reset. restore initial values */
4447d351 781 ahci_restore_initial_config(host);
d91542c1
TH		 782
783 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
784 u16 tmp16;
785
786 /* configure PCS */
787 pci_read_config_word(pdev, 0x92, &tmp16);
788 tmp16 |= 0xf;
789 pci_write_config_word(pdev, 0x92, tmp16);
790 }
791
792 return 0;
793}
794
4447d351 795static void ahci_init_controller(struct ata_host *host)
d91542c1 796{
4447d351
TH		 797 struct pci_dev *pdev = to_pci_dev(host->dev);
798 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d91542c1
TH		 799 int i, rc;
800 u32 tmp;
801
4447d351
TH		 802 for (i = 0; i < host->n_ports; i++) {
803 struct ata_port *ap = host->ports[i];
804 void __iomem *port_mmio = ahci_port_base(ap);
d91542c1
TH		 805 const char *emsg = NULL;
806
4447d351 807 if (ata_port_is_dummy(ap))
d91542c1 808 continue;
d91542c1
TH		 809
810 /* make sure port is not active */
4447d351 811 rc = ahci_deinit_port(ap, &emsg);
d91542c1
TH		 812 if (rc)
813 dev_printk(KERN_WARNING, &pdev->dev,
814 "%s (%d)\n", emsg, rc);
815
816 /* clear SError */
817 tmp = readl(port_mmio + PORT_SCR_ERR);
818 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
819 writel(tmp, port_mmio + PORT_SCR_ERR);
820
f4b5cc87 821 /* clear port IRQ */
d91542c1
TH		 822 tmp = readl(port_mmio + PORT_IRQ_STAT);
823 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
824 if (tmp)
825 writel(tmp, port_mmio + PORT_IRQ_STAT);
826
827 writel(1 << i, mmio + HOST_IRQ_STAT);
d91542c1
TH		 828 }
829
830 tmp = readl(mmio + HOST_CTL);
831 VPRINTK("HOST_CTL 0x%x\n", tmp);
832 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
833 tmp = readl(mmio + HOST_CTL);
834 VPRINTK("HOST_CTL 0x%x\n", tmp);
835}
836
422b7595 837static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 838{
4447d351 839 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 840 struct ata_taskfile tf;
422b7595
TH		 841 u32 tmp;
842
843 tmp = readl(port_mmio + PORT_SIG);
844 tf.lbah = (tmp >> 24) & 0xff;
845 tf.lbam = (tmp >> 16) & 0xff;
846 tf.lbal = (tmp >> 8) & 0xff;
847 tf.nsect = (tmp) & 0xff;
848
849 return ata_dev_classify(&tf);
850}
851
12fad3f9
TH		 852static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
853 u32 opts)
cc9278ed 854{
12fad3f9
TH		 855 dma_addr_t cmd_tbl_dma;
856
857 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
858
859 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
860 pp->cmd_slot[tag].status = 0;
861 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
862 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 863}
864
bf2af2a2 865static int ahci_clo(struct ata_port *ap)
4658f79b 866{
0d5ff566 867 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 868 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2
BJ		 869 u32 tmp;
870
871 if (!(hpriv->cap & HOST_CAP_CLO))
872 return -EOPNOTSUPP;
873
874 tmp = readl(port_mmio + PORT_CMD);
875 tmp |= PORT_CMD_CLO;
876 writel(tmp, port_mmio + PORT_CMD);
877
878 tmp = ata_wait_register(port_mmio + PORT_CMD,
879 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
880 if (tmp & PORT_CMD_CLO)
881 return -EIO;
882
883 return 0;
884}
885
886static int ahci_softreset(struct ata_port *ap, unsigned int *class)
887{
4658f79b 888 struct ahci_port_priv *pp = ap->private_data;
4447d351 889 void __iomem *port_mmio = ahci_port_base(ap);
4658f79b
TH		 890 const u32 cmd_fis_len = 5; /* five dwords */
891 const char *reason = NULL;
892 struct ata_taskfile tf;
75fe1806 893 u32 tmp;
4658f79b
TH		 894 u8 *fis;
895 int rc;
896
897 DPRINTK("ENTER\n");
898
81952c54 899 if (ata_port_offline(ap)) {
c2a65852
TH		 900 DPRINTK("PHY reports no device\n");
901 *class = ATA_DEV_NONE;
902 return 0;
903 }
904
4658f79b 905 /* prepare for SRST (AHCI-1.1 10.4.1) */
4447d351 906 rc = ahci_stop_engine(ap);
4658f79b
TH		 907 if (rc) {
908 reason = "failed to stop engine";
909 goto fail_restart;
910 }
911
912 /* check BUSY/DRQ, perform Command List Override if necessary */
1244a19c 913 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 914 rc = ahci_clo(ap);
4658f79b 915
bf2af2a2
BJ		 916 if (rc == -EOPNOTSUPP) {
917 reason = "port busy but CLO unavailable";
918 goto fail_restart;
919 } else if (rc) {
920 reason = "port busy but CLO failed";
4658f79b
TH		 921 goto fail_restart;
922 }
923 }
924
925 /* restart engine */
4447d351 926 ahci_start_engine(ap);
4658f79b 927
3373efd8 928 ata_tf_init(ap->device, &tf);
4658f79b
TH		 929 fis = pp->cmd_tbl;
930
931 /* issue the first D2H Register FIS */
12fad3f9
TH		 932 ahci_fill_cmd_slot(pp, 0,
933 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 934
935 tf.ctl |= ATA_SRST;
936 ata_tf_to_fis(&tf, fis, 0);
937 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
938
939 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 940
75fe1806
TH		 941 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
942 if (tmp & 0x1) {
4658f79b
TH		 943 rc = -EIO;
944 reason = "1st FIS failed";
945 goto fail;
946 }
947
948 /* spec says at least 5us, but be generous and sleep for 1ms */
949 msleep(1);
950
951 /* issue the second D2H Register FIS */
12fad3f9 952 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 953
954 tf.ctl &= ~ATA_SRST;
955 ata_tf_to_fis(&tf, fis, 0);
956 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
957
958 writel(1, port_mmio + PORT_CMD_ISSUE);
959 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
960
961 /* spec mandates ">= 2ms" before checking status.
962 * We wait 150ms, because that was the magic delay used for
963 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
964 * between when the ATA command register is written, and then
965 * status is checked. Because waiting for "a while" before
966 * checking status is fine, post SRST, we perform this magic
967 * delay here as well.
968 */
969 msleep(150);
970
971 *class = ATA_DEV_NONE;
81952c54 972 if (ata_port_online(ap)) {
4658f79b
TH		 973 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
974 rc = -EIO;
975 reason = "device not ready";
976 goto fail;
977 }
978 *class = ahci_dev_classify(ap);
979 }
980
981 DPRINTK("EXIT, class=%u\n", *class);
982 return 0;
983
984 fail_restart:
4447d351 985 ahci_start_engine(ap);
4658f79b 986 fail:
f15a1daf 987 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 988 return rc;
989}
990
2bf2cb26 991static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 992{
4296971d
TH		 993 struct ahci_port_priv *pp = ap->private_data;
994 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
995 struct ata_taskfile tf;
4bd00f6a
TH		 996 int rc;
997
998 DPRINTK("ENTER\n");
1da177e4 999
4447d351 1000 ahci_stop_engine(ap);
4296971d
TH		 1001
1002 /* clear D2H reception area to properly wait for D2H FIS */
1003 ata_tf_init(ap->device, &tf);
dfd7a3db 1004 tf.command = 0x80;
4296971d
TH		 1005 ata_tf_to_fis(&tf, d2h_fis, 0);
1006
2bf2cb26 1007 rc = sata_std_hardreset(ap, class);
4296971d 1008
4447d351 1009 ahci_start_engine(ap);
1da177e4 1010
81952c54 1011 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 1012 *class = ahci_dev_classify(ap);
1013 if (*class == ATA_DEV_UNKNOWN)
1014 *class = ATA_DEV_NONE;
1da177e4 1015
4bd00f6a
TH		 1016 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1017 return rc;
1018}
1019
ad616ffb
TH		 1020static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
1021{
ad616ffb
TH		 1022 int rc;
1023
1024 DPRINTK("ENTER\n");
1025
4447d351 1026 ahci_stop_engine(ap);
ad616ffb
TH		 1027
1028 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
1029
1030 /* vt8251 needs SError cleared for the port to operate */
1031 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
1032
4447d351 1033 ahci_start_engine(ap);
ad616ffb
TH		 1034
1035 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1036
1037 /* vt8251 doesn't clear BSY on signature FIS reception,
1038 * request follow-up softreset.
1039 */
1040 return rc ?: -EAGAIN;
1041}
1042
4bd00f6a
TH		 1043static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1044{
4447d351 1045 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1046 u32 new_tmp, tmp;
1047
1048 ata_std_postreset(ap, class);
02eaa666
JG		 1049
1050 /* Make sure port's ATAPI bit is set appropriately */
1051 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1052 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1053 new_tmp |= PORT_CMD_ATAPI;
1054 else
1055 new_tmp &= ~PORT_CMD_ATAPI;
1056 if (new_tmp != tmp) {
1057 writel(new_tmp, port_mmio + PORT_CMD);
1058 readl(port_mmio + PORT_CMD); /* flush */
1059 }
1da177e4
LT		 1060}
1061
1062static u8 ahci_check_status(struct ata_port *ap)
1063{
0d5ff566 1064 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1065
1066 return readl(mmio + PORT_TFDATA) & 0xFF;
1067}
1068
1da177e4
LT		 1069static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1070{
1071 struct ahci_port_priv *pp = ap->private_data;
1072 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1073
1074 ata_tf_from_fis(d2h_fis, tf);
1075}
1076
12fad3f9 1077static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1078{
cedc9a47
JG		 1079 struct scatterlist *sg;
1080 struct ahci_sg *ahci_sg;
828d09de 1081 unsigned int n_sg = 0;
1da177e4
LT		 1082
1083 VPRINTK("ENTER\n");
1084
1085 /*
1086 * Next, the S/G list.
1087 */
12fad3f9 1088 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 1089 ata_for_each_sg(sg, qc) {
1090 dma_addr_t addr = sg_dma_address(sg);
1091 u32 sg_len = sg_dma_len(sg);
1092
1093 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1094 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1095 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 1096
cedc9a47 1097 ahci_sg++;
828d09de 1098 n_sg++;
1da177e4 1099 }
828d09de
JG		 1100
1101 return n_sg;
1da177e4
LT		 1102}
1103
1104static void ahci_qc_prep(struct ata_queued_cmd *qc)
1105{
a0ea7328
JG		 1106 struct ata_port *ap = qc->ap;
1107 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 1108 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 1109 void *cmd_tbl;
1da177e4
LT		 1110 u32 opts;
1111 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1112 unsigned int n_elem;
1da177e4 1113
1da177e4
LT		 1114 /*
1115 * Fill in command table information. First, the header,
1116 * a SATA Register - Host to Device command FIS.
1117 */
12fad3f9
TH		 1118 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1119
1120 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 1121 if (is_atapi) {
12fad3f9
TH		 1122 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1123 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1124 }
1da177e4 1125
cc9278ed
TH		 1126 n_elem = 0;
1127 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1128 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1129
cc9278ed
TH		 1130 /*
1131 * Fill in command slot information.
1132 */
1133 opts = cmd_fis_len | n_elem << 16;
1134 if (qc->tf.flags & ATA_TFLAG_WRITE)
1135 opts |= AHCI_CMD_WRITE;
1136 if (is_atapi)
4b10e559 1137 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1138
12fad3f9 1139 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1140}
1141
78cd52d0 1142static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1143{
78cd52d0
TH		 1144 struct ahci_port_priv *pp = ap->private_data;
1145 struct ata_eh_info *ehi = &ap->eh_info;
1146 unsigned int err_mask = 0, action = 0;
1147 struct ata_queued_cmd *qc;
1148 u32 serror;
1da177e4 1149
78cd52d0 1150 ata_ehi_clear_desc(ehi);
1da177e4 1151
78cd52d0
TH		 1152 /* AHCI needs SError cleared; otherwise, it might lock up */
1153 serror = ahci_scr_read(ap, SCR_ERROR);
1154 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 1155
78cd52d0
TH		 1156 /* analyze @irq_stat */
1157 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1158
41669553
TH		 1159 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1160 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1161 irq_stat &= ~PORT_IRQ_IF_ERR;
1162
55a61604 1163 if (irq_stat & PORT_IRQ_TF_ERR) {
78cd52d0 1164 err_mask |= AC_ERR_DEV;
55a61604
CH		 1165 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1166 serror &= ~SERR_INTERNAL;
1167 }
78cd52d0
TH		 1168
1169 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1170 err_mask |= AC_ERR_HOST_BUS;
1171 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 1172 }
1173
78cd52d0
TH		 1174 if (irq_stat & PORT_IRQ_IF_ERR) {
1175 err_mask |= AC_ERR_ATA_BUS;
1176 action |= ATA_EH_SOFTRESET;
1177 ata_ehi_push_desc(ehi, ", interface fatal error");
1178 }
1da177e4 1179
78cd52d0 1180 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 1181 ata_ehi_hotplugged(ehi);
78cd52d0
TH		 1182 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1183 "connection status changed" : "PHY RDY changed");
1184 }
1185
1186 if (irq_stat & PORT_IRQ_UNK_FIS) {
1187 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 1188
78cd52d0
TH		 1189 err_mask |= AC_ERR_HSM;
1190 action |= ATA_EH_SOFTRESET;
1191 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1192 unk[0], unk[1], unk[2], unk[3]);
1193 }
1da177e4 1194
78cd52d0
TH		 1195 /* okay, let's hand over to EH */
1196 ehi->serror |= serror;
1197 ehi->action |= action;
b8f6153e 1198
1da177e4 1199 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 1200 if (qc)
1201 qc->err_mask |= err_mask;
1202 else
1203 ehi->err_mask |= err_mask;
a72ec4ce 1204
78cd52d0
TH		 1205 if (irq_stat & PORT_IRQ_FREEZE)
1206 ata_port_freeze(ap);
1207 else
1208 ata_port_abort(ap);
1da177e4
LT		 1209}
1210
78cd52d0 1211static void ahci_host_intr(struct ata_port *ap)
1da177e4 1212{
4447d351 1213 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
12fad3f9 1214 struct ata_eh_info *ehi = &ap->eh_info;
0291f95f 1215 struct ahci_port_priv *pp = ap->private_data;
12fad3f9 1216 u32 status, qc_active;
0291f95f 1217 int rc, known_irq = 0;
1da177e4
LT		 1218
1219 status = readl(port_mmio + PORT_IRQ_STAT);
1220 writel(status, port_mmio + PORT_IRQ_STAT);
1221
78cd52d0
TH		 1222 if (unlikely(status & PORT_IRQ_ERROR)) {
1223 ahci_error_intr(ap, status);
1224 return;
1da177e4
LT		 1225 }
1226
12fad3f9
TH		 1227 if (ap->sactive)
1228 qc_active = readl(port_mmio + PORT_SCR_ACT);
1229 else
1230 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1231
1232 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1233 if (rc > 0)
1234 return;
1235 if (rc < 0) {
1236 ehi->err_mask |= AC_ERR_HSM;
1237 ehi->action |= ATA_EH_SOFTRESET;
1238 ata_port_freeze(ap);
1239 return;
1da177e4
LT		 1240 }
1241
2a3917a8
TH		 1242 /* hmmm... a spurious interupt */
1243
0291f95f
TH		 1244 /* if !NCQ, ignore. No modern ATA device has broken HSM
1245 * implementation for non-NCQ commands.
1246 */
1247 if (!ap->sactive)
12fad3f9
TH		 1248 return;
1249
0291f95f
TH		 1250 if (status & PORT_IRQ_D2H_REG_FIS) {
1251 if (!pp->ncq_saw_d2h)
1252 ata_port_printk(ap, KERN_INFO,
1253 "D2H reg with I during NCQ, "
1254 "this message won't be printed again\n");
1255 pp->ncq_saw_d2h = 1;
1256 known_irq = 1;
1257 }
1258
1259 if (status & PORT_IRQ_DMAS_FIS) {
1260 if (!pp->ncq_saw_dmas)
1261 ata_port_printk(ap, KERN_INFO,
1262 "DMAS FIS during NCQ, "
1263 "this message won't be printed again\n");
1264 pp->ncq_saw_dmas = 1;
1265 known_irq = 1;
1266 }
1267
a2bbd0c9 1268 if (status & PORT_IRQ_SDB_FIS) {
04d4f7a1 1269 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
0291f95f 1270
afb2d552
TH		 1271 if (le32_to_cpu(f[1])) {
1272 /* SDB FIS containing spurious completions
1273 * might be dangerous, whine and fail commands
1274 * with HSM violation. EH will turn off NCQ
1275 * after several such failures.
1276 */
1277 ata_ehi_push_desc(ehi,
1278 "spurious completions during NCQ "
1279 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1280 readl(port_mmio + PORT_CMD_ISSUE),
1281 readl(port_mmio + PORT_SCR_ACT),
1282 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1283 ehi->err_mask |= AC_ERR_HSM;
1284 ehi->action |= ATA_EH_SOFTRESET;
1285 ata_port_freeze(ap);
1286 } else {
1287 if (!pp->ncq_saw_sdb)
1288 ata_port_printk(ap, KERN_INFO,
1289 "spurious SDB FIS %08x:%08x during NCQ, "
1290 "this message won't be printed again\n",
1291 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1292 pp->ncq_saw_sdb = 1;
1293 }
0291f95f
TH		 1294 known_irq = 1;
1295 }
2a3917a8 1296
0291f95f 1297 if (!known_irq)
78cd52d0 1298 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
0291f95f 1299 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
12fad3f9 1300 status, ap->active_tag, ap->sactive);
1da177e4
LT		 1301}
1302
1303static void ahci_irq_clear(struct ata_port *ap)
1304{
1305 /* TODO */
1306}
1307
7d12e780 1308static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1309{
cca3974e 1310 struct ata_host *host = dev_instance;
1da177e4
LT		 1311 struct ahci_host_priv *hpriv;
1312 unsigned int i, handled = 0;
ea6ba10b 1313 void __iomem *mmio;
1da177e4
LT		 1314 u32 irq_stat, irq_ack = 0;
1315
1316 VPRINTK("ENTER\n");
1317
cca3974e 1318 hpriv = host->private_data;
0d5ff566 1319 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1320
1321 /* sigh. 0xffffffff is a valid return from h/w */
1322 irq_stat = readl(mmio + HOST_IRQ_STAT);
1323 irq_stat &= hpriv->port_map;
1324 if (!irq_stat)
1325 return IRQ_NONE;
1326
cca3974e 1327 spin_lock(&host->lock);
1da177e4 1328
cca3974e 1329 for (i = 0; i < host->n_ports; i++) {
1da177e4 1330 struct ata_port *ap;
1da177e4 1331
67846b30
JG		 1332 if (!(irq_stat & (1 << i)))
1333 continue;
1334
cca3974e 1335 ap = host->ports[i];
67846b30 1336 if (ap) {
78cd52d0 1337 ahci_host_intr(ap);
67846b30
JG		 1338 VPRINTK("port %u\n", i);
1339 } else {
1340 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1341 if (ata_ratelimit())
cca3974e 1342 dev_printk(KERN_WARNING, host->dev,
a9524a76 1343 "interrupt on disabled port %u\n", i);
1da177e4 1344 }
67846b30
JG		 1345
1346 irq_ack |= (1 << i);
1da177e4
LT		 1347 }
1348
1349 if (irq_ack) {
1350 writel(irq_ack, mmio + HOST_IRQ_STAT);
1351 handled = 1;
1352 }
1353
cca3974e 1354 spin_unlock(&host->lock);
1da177e4
LT		 1355
1356 VPRINTK("EXIT\n");
1357
1358 return IRQ_RETVAL(handled);
1359}
1360
9a3d9eb0 1361static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1362{
1363 struct ata_port *ap = qc->ap;
4447d351 1364 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1365
12fad3f9
TH		 1366 if (qc->tf.protocol == ATA_PROT_NCQ)
1367 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1368 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1369 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1370
1371 return 0;
1372}
1373
78cd52d0
TH		 1374static void ahci_freeze(struct ata_port *ap)
1375{
4447d351 1376 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1377
1378 /* turn IRQ off */
1379 writel(0, port_mmio + PORT_IRQ_MASK);
1380}
1381
1382static void ahci_thaw(struct ata_port *ap)
1383{
0d5ff566 1384 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 1385 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1386 u32 tmp;
1387
1388 /* clear IRQ */
1389 tmp = readl(port_mmio + PORT_IRQ_STAT);
1390 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1391 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0
TH		 1392
1393 /* turn IRQ back on */
1394 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1395}
1396
1397static void ahci_error_handler(struct ata_port *ap)
1398{
b51e9e5d 1399 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1400 /* restart engine */
4447d351
TH		 1401 ahci_stop_engine(ap);
1402 ahci_start_engine(ap);
78cd52d0
TH		 1403 }
1404
1405 /* perform recovery */
4aeb0e32 1406 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1407 ahci_postreset);
78cd52d0
TH		 1408}
1409
ad616ffb
TH		 1410static void ahci_vt8251_error_handler(struct ata_port *ap)
1411{
ad616ffb
TH		 1412 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1413 /* restart engine */
4447d351
TH		 1414 ahci_stop_engine(ap);
1415 ahci_start_engine(ap);
ad616ffb
TH		 1416 }
1417
1418 /* perform recovery */
1419 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1420 ahci_postreset);
1421}
1422
78cd52d0
TH		 1423static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1424{
1425 struct ata_port *ap = qc->ap;
1426
a51d644a 1427 if (qc->flags & ATA_QCFLAG_FAILED) {
78cd52d0 1428 /* make DMA engine forget about the failed command */
4447d351
TH		 1429 ahci_stop_engine(ap);
1430 ahci_start_engine(ap);
78cd52d0
TH		 1431 }
1432}
1433
438ac6d5 1434#ifdef CONFIG_PM
c1332875
TH		 1435static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1436{
c1332875
TH		 1437 const char *emsg = NULL;
1438 int rc;
1439
4447d351 1440 rc = ahci_deinit_port(ap, &emsg);
8e16f941 1441 if (rc == 0)
4447d351 1442 ahci_power_down(ap);
8e16f941 1443 else {
c1332875 1444 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
4447d351 1445 ahci_init_port(ap);
c1332875
TH		 1446 }
1447
1448 return rc;
1449}
1450
1451static int ahci_port_resume(struct ata_port *ap)
1452{
4447d351
TH		 1453 ahci_power_up(ap);
1454 ahci_init_port(ap);
c1332875
TH		 1455
1456 return 0;
1457}
1458
1459static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1460{
cca3974e 1461 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1462 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1463 u32 ctl;
1464
1465 if (mesg.event == PM_EVENT_SUSPEND) {
1466 /* AHCI spec rev1.1 section 8.3.3:
1467 * Software must disable interrupts prior to requesting a
1468 * transition of the HBA to D3 state.
1469 */
1470 ctl = readl(mmio + HOST_CTL);
1471 ctl &= ~HOST_IRQ_EN;
1472 writel(ctl, mmio + HOST_CTL);
1473 readl(mmio + HOST_CTL); /* flush */
1474 }
1475
1476 return ata_pci_device_suspend(pdev, mesg);
1477}
1478
1479static int ahci_pci_device_resume(struct pci_dev *pdev)
1480{
cca3974e 1481 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 1482 int rc;
1483
553c4aa6
TH		 1484 rc = ata_pci_device_do_resume(pdev);
1485 if (rc)
1486 return rc;
c1332875
TH		 1487
1488 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 1489 rc = ahci_reset_controller(host);
c1332875
TH		 1490 if (rc)
1491 return rc;
1492
4447d351 1493 ahci_init_controller(host);
c1332875
TH		 1494 }
1495
cca3974e 1496 ata_host_resume(host);
c1332875
TH		 1497
1498 return 0;
1499}
438ac6d5 1500#endif
c1332875 1501
254950cd
TH		 1502static int ahci_port_start(struct ata_port *ap)
1503{
cca3974e 1504 struct device *dev = ap->host->dev;
254950cd 1505 struct ahci_port_priv *pp;
254950cd
TH		 1506 void *mem;
1507 dma_addr_t mem_dma;
1508 int rc;
1509
24dc5f33 1510 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 1511 if (!pp)
1512 return -ENOMEM;
254950cd
TH		 1513
1514 rc = ata_pad_alloc(ap, dev);
24dc5f33 1515 if (rc)
254950cd 1516 return rc;
254950cd 1517
24dc5f33
TH		 1518 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1519 GFP_KERNEL);
1520 if (!mem)
254950cd 1521 return -ENOMEM;
254950cd
TH		 1522 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1523
1524 /*
1525 * First item in chunk of DMA memory: 32-slot command table,
1526 * 32 bytes each in size
1527 */
1528 pp->cmd_slot = mem;
1529 pp->cmd_slot_dma = mem_dma;
1530
1531 mem += AHCI_CMD_SLOT_SZ;
1532 mem_dma += AHCI_CMD_SLOT_SZ;
1533
1534 /*
1535 * Second item: Received-FIS area
1536 */
1537 pp->rx_fis = mem;
1538 pp->rx_fis_dma = mem_dma;
1539
1540 mem += AHCI_RX_FIS_SZ;
1541 mem_dma += AHCI_RX_FIS_SZ;
1542
1543 /*
1544 * Third item: data area for storing a single command
1545 * and its scatter-gather table
1546 */
1547 pp->cmd_tbl = mem;
1548 pp->cmd_tbl_dma = mem_dma;
1549
1550 ap->private_data = pp;
1551
8e16f941 1552 /* power up port */
4447d351 1553 ahci_power_up(ap);
8e16f941 1554
0be0aa98 1555 /* initialize port */
4447d351 1556 ahci_init_port(ap);
254950cd
TH		 1557
1558 return 0;
1559}
1560
1561static void ahci_port_stop(struct ata_port *ap)
1562{
0be0aa98
TH		 1563 const char *emsg = NULL;
1564 int rc;
254950cd 1565
0be0aa98 1566 /* de-initialize port */
4447d351 1567 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 1568 if (rc)
1569 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1570}
1571
4447d351 1572static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 1573{
1da177e4 1574 int rc;
1da177e4 1575
1da177e4
LT		 1576 if (using_dac &&
1577 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1578 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1579 if (rc) {
1580 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1581 if (rc) {
a9524a76
JG		 1582 dev_printk(KERN_ERR, &pdev->dev,
1583 "64-bit DMA enable failed\n");
1da177e4
LT		 1584 return rc;
1585 }
1586 }
1da177e4
LT		 1587 } else {
1588 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1589 if (rc) {
a9524a76
JG		 1590 dev_printk(KERN_ERR, &pdev->dev,
1591 "32-bit DMA enable failed\n");
1da177e4
LT		 1592 return rc;
1593 }
1594 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1595 if (rc) {
a9524a76
JG		 1596 dev_printk(KERN_ERR, &pdev->dev,
1597 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1598 return rc;
1599 }
1600 }
1da177e4
LT		 1601 return 0;
1602}
1603
4447d351 1604static void ahci_print_info(struct ata_host *host)
1da177e4 1605{
4447d351
TH		 1606 struct ahci_host_priv *hpriv = host->private_data;
1607 struct pci_dev *pdev = to_pci_dev(host->dev);
1608 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1609 u32 vers, cap, impl, speed;
1610 const char *speed_s;
1611 u16 cc;
1612 const char *scc_s;
1613
1614 vers = readl(mmio + HOST_VERSION);
1615 cap = hpriv->cap;
1616 impl = hpriv->port_map;
1617
1618 speed = (cap >> 20) & 0xf;
1619 if (speed == 1)
1620 speed_s = "1.5";
1621 else if (speed == 2)
1622 speed_s = "3";
1623 else
1624 speed_s = "?";
1625
1626 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 1627 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 1628 scc_s = "IDE";
c9f89475 1629 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 1630 scc_s = "SATA";
c9f89475 1631 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 1632 scc_s = "RAID";
1633 else
1634 scc_s = "unknown";
1635
a9524a76
JG		 1636 dev_printk(KERN_INFO, &pdev->dev,
1637 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1638 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1639 ,
1da177e4
LT		 1640
1641 (vers >> 24) & 0xff,
1642 (vers >> 16) & 0xff,
1643 (vers >> 8) & 0xff,
1644 vers & 0xff,
1645
1646 ((cap >> 8) & 0x1f) + 1,
1647 (cap & 0x1f) + 1,
1648 speed_s,
1649 impl,
1650 scc_s);
1651
a9524a76
JG		 1652 dev_printk(KERN_INFO, &pdev->dev,
1653 "flags: "
1da177e4
LT		 1654 "%s%s%s%s%s%s"
1655 "%s%s%s%s%s%s%s\n"
1656 ,
1da177e4
LT		 1657
1658 cap & (1 << 31) ? "64bit " : "",
1659 cap & (1 << 30) ? "ncq " : "",
1660 cap & (1 << 28) ? "ilck " : "",
1661 cap & (1 << 27) ? "stag " : "",
1662 cap & (1 << 26) ? "pm " : "",
1663 cap & (1 << 25) ? "led " : "",
1664
1665 cap & (1 << 24) ? "clo " : "",
1666 cap & (1 << 19) ? "nz " : "",
1667 cap & (1 << 18) ? "only " : "",
1668 cap & (1 << 17) ? "pmp " : "",
1669 cap & (1 << 15) ? "pio " : "",
1670 cap & (1 << 14) ? "slum " : "",
1671 cap & (1 << 13) ? "part " : ""
1672 );
1673}
1674
24dc5f33 1675static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1676{
1677 static int printed_version;
4447d351
TH		 1678 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1679 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1680 struct device *dev = &pdev->dev;
1da177e4 1681 struct ahci_host_priv *hpriv;
4447d351
TH		 1682 struct ata_host *host;
1683 int i, rc;
1da177e4
LT		 1684
1685 VPRINTK("ENTER\n");
1686
12fad3f9
TH		 1687 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1688
1da177e4 1689 if (!printed_version++)
a9524a76 1690 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1691
4447d351 1692 /* acquire resources */
24dc5f33 1693 rc = pcim_enable_device(pdev);
1da177e4
LT		 1694 if (rc)
1695 return rc;
1696
0d5ff566
TH		 1697 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1698 if (rc == -EBUSY)
24dc5f33 1699 pcim_pin_device(pdev);
0d5ff566 1700 if (rc)
24dc5f33 1701 return rc;
1da177e4 1702
24dc5f33 1703 if (pci_enable_msi(pdev))
907f4678 1704 pci_intx(pdev, 1);
1da177e4 1705
24dc5f33
TH		 1706 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1707 if (!hpriv)
1708 return -ENOMEM;
1da177e4 1709
4447d351
TH		 1710 /* save initial config */
1711 ahci_save_initial_config(pdev, &pi, hpriv);
1da177e4 1712
4447d351
TH		 1713 /* prepare host */
1714 if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
1715 pi.flags |= ATA_FLAG_NCQ;
1da177e4 1716
4447d351
TH		 1717 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1718 if (!host)
1719 return -ENOMEM;
1720 host->iomap = pcim_iomap_table(pdev);
1721 host->private_data = hpriv;
1722
1723 for (i = 0; i < host->n_ports; i++) {
1724 if (hpriv->port_map & (1 << i)) {
1725 struct ata_port *ap = host->ports[i];
1726 void __iomem *port_mmio = ahci_port_base(ap);
1727
1728 ap->ioaddr.cmd_addr = port_mmio;
1729 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
1730 } else
1731 host->ports[i]->ops = &ata_dummy_port_ops;
1732 }
d447df14 1733
4447d351
TH		 1734 /* initialize adapter */
1735 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1736 if (rc)
24dc5f33 1737 return rc;
1da177e4 1738
4447d351
TH		 1739 rc = ahci_reset_controller(host);
1740 if (rc)
1741 return rc;
1da177e4 1742
4447d351
TH		 1743 ahci_init_controller(host);
1744 ahci_print_info(host);
1da177e4 1745
4447d351
TH		 1746 pci_set_master(pdev);
1747 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1748 &ahci_sht);
907f4678 1749}
1da177e4
LT		 1750
1751static int __init ahci_init(void)
1752{
b7887196 1753 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1754}
1755
1da177e4
LT		 1756static void __exit ahci_exit(void)
1757{
1758 pci_unregister_driver(&ahci_pci_driver);
1759}
1760
1761
1762MODULE_AUTHOR("Jeff Garzik");
1763MODULE_DESCRIPTION("AHCI SATA low-level driver");
1764MODULE_LICENSE("GPL");
1765MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1766MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1767
1768module_init(ahci_init);
1769module_exit(ahci_exit);
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