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sata_mv: add RocketRaid 1720 PCI ID to driver
[net-next-2.6.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
a22e6444
TH		 52static int ahci_skip_host_reset;
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
31556594
KCA		 56static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58static void ahci_disable_alpm(struct ata_port *ap);
18f7ba4c
KCA		 59static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
60static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
61 size_t size);
62static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
63 ssize_t size);
64#define MAX_SLOTS 8
1da177e4
LT		 65
66enum {
67 AHCI_PCI_BAR = 5,
648a88be 68 AHCI_MAX_PORTS = 32,
1da177e4
LT		 69 AHCI_MAX_SG = 168, /* hardware max is 64K */
70 AHCI_DMA_BOUNDARY = 0xffffffff,
12fad3f9 71 AHCI_MAX_CMDS = 32,
dd410ff1 72 AHCI_CMD_SZ = 32,
12fad3f9 73 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 74 AHCI_RX_FIS_SZ = 256,
a0ea7328 75 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 76 AHCI_CMD_TBL_HDR_SZ = 0x80,
77 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
78 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
79 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 80 AHCI_RX_FIS_SZ,
81 AHCI_IRQ_ON_SG = (1 << 31),
82 AHCI_CMD_ATAPI = (1 << 5),
83 AHCI_CMD_WRITE = (1 << 6),
4b10e559 84 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 85 AHCI_CMD_RESET = (1 << 8),
86 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 87
88 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 89 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 90 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 91
92 board_ahci = 0,
7a234aff
TH		 93 board_ahci_vt8251 = 1,
94 board_ahci_ign_iferr = 2,
95 board_ahci_sb600 = 3,
96 board_ahci_mv = 4,
e39fc8c9 97 board_ahci_sb700 = 5,
e297d99e 98 board_ahci_mcp65 = 6,
9a3b103c 99 board_ahci_nopmp = 7,
1da177e4
LT		 100
101 /* global controller registers */
102 HOST_CAP = 0x00, /* host capabilities */
103 HOST_CTL = 0x04, /* global host control */
104 HOST_IRQ_STAT = 0x08, /* interrupt status */
105 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
106 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
18f7ba4c
KCA		 107 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
108 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
1da177e4
LT		 109
110 /* HOST_CTL bits */
111 HOST_RESET = (1 << 0), /* reset controller; self-clear */
112 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
113 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
114
115 /* HOST_CAP bits */
18f7ba4c 116 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
0be0aa98 117 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 118 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 119 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 120 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 121 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 122 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 123 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 124 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 125
126 /* registers for each SATA port */
127 PORT_LST_ADDR = 0x00, /* command list DMA addr */
128 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
129 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
130 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
131 PORT_IRQ_STAT = 0x10, /* interrupt status */
132 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
133 PORT_CMD = 0x18, /* port command */
134 PORT_TFDATA = 0x20, /* taskfile data */
135 PORT_SIG = 0x24, /* device TF signature */
136 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 137 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
138 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
139 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
140 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 141 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 142
143 /* PORT_IRQ_{STAT,MASK} bits */
144 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
145 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
146 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
147 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
148 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
149 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
150 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
151 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
152
153 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
154 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
155 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
156 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
157 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
158 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
159 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
160 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
161 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
162
78cd52d0
TH		 163 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
164 PORT_IRQ_IF_ERR |
165 PORT_IRQ_CONNECT |
4296971d 166 PORT_IRQ_PHYRDY |
7d50b60b
TH		 167 PORT_IRQ_UNK_FIS |
168 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 169 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
170 PORT_IRQ_TF_ERR |
171 PORT_IRQ_HBUS_DATA_ERR,
172 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
173 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
174 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 175
176 /* PORT_CMD bits */
31556594
KCA		 177 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
178 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 179 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 180 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 184 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
188
0be0aa98 189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 193
417a1a6d
TH		 194 /* hpriv->flags bits */
195 AHCI_HFLAG_NO_NCQ = (1 << 0),
196 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
197 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
198 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
199 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
200 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 201 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 202 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 203 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
e297d99e 204 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
417a1a6d 205
bf2af2a2 206 /* ap->flags bits */
1188c0d8
TH		 207
208 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
209 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 210 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
211 ATA_FLAG_IPM,
c4f7792c
TH		 212
213 ICH_MAP = 0x90, /* ICH MAP register */
18f7ba4c
KCA		 214
215 /* em_ctl bits */
216 EM_CTL_RST = (1 << 9), /* Reset */
217 EM_CTL_TM = (1 << 8), /* Transmit Message */
218 EM_CTL_ALHD = (1 << 26), /* Activity LED */
1da177e4
LT		 219};
220
221struct ahci_cmd_hdr {
4ca4e439
AV		 222 __le32 opts;
223 __le32 status;
224 __le32 tbl_addr;
225 __le32 tbl_addr_hi;
226 __le32 reserved[4];
1da177e4
LT		 227};
228
229struct ahci_sg {
4ca4e439
AV		 230 __le32 addr;
231 __le32 addr_hi;
232 __le32 reserved;
233 __le32 flags_size;
1da177e4
LT		 234};
235
18f7ba4c
KCA		 236struct ahci_em_priv {
237 enum sw_activity blink_policy;
238 struct timer_list timer;
239 unsigned long saved_activity;
240 unsigned long activity;
241 unsigned long led_state;
242};
243
1da177e4 244struct ahci_host_priv {
417a1a6d 245 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 246 u32 cap; /* cap to use */
247 u32 port_map; /* port map to use */
248 u32 saved_cap; /* saved initial cap */
249 u32 saved_port_map; /* saved initial port_map */
18f7ba4c 250 u32 em_loc; /* enclosure management location */
1da177e4
LT		 251};
252
253struct ahci_port_priv {
7d50b60b 254 struct ata_link *active_link;
1da177e4
LT		 255 struct ahci_cmd_hdr *cmd_slot;
256 dma_addr_t cmd_slot_dma;
257 void *cmd_tbl;
258 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 259 void *rx_fis;
260 dma_addr_t rx_fis_dma;
0291f95f 261 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 262 unsigned int ncq_saw_d2h:1;
263 unsigned int ncq_saw_dmas:1;
afb2d552 264 unsigned int ncq_saw_sdb:1;
a7384925 265 u32 intr_mask; /* interrupts to enable */
18f7ba4c
KCA		 266 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
267 * per PM slot */
1da177e4
LT		 268};
269
da3dbb17
TH		 270static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
271static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
2dcb407e 272static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 273static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
4c9bf4e7 274static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
1da177e4
LT		 275static int ahci_port_start(struct ata_port *ap);
276static void ahci_port_stop(struct ata_port *ap);
1da177e4 277static void ahci_qc_prep(struct ata_queued_cmd *qc);
78cd52d0
TH		 278static void ahci_freeze(struct ata_port *ap);
279static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 280static void ahci_pmp_attach(struct ata_port *ap);
281static void ahci_pmp_detach(struct ata_port *ap);
a1efdaba
TH		 282static int ahci_softreset(struct ata_link *link, unsigned int *class,
283 unsigned long deadline);
bd17243a
SH		 284static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
285 unsigned long deadline);
a1efdaba
TH		 286static int ahci_hardreset(struct ata_link *link, unsigned int *class,
287 unsigned long deadline);
288static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
289 unsigned long deadline);
290static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
291 unsigned long deadline);
292static void ahci_postreset(struct ata_link *link, unsigned int *class);
78cd52d0
TH		 293static void ahci_error_handler(struct ata_port *ap);
294static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 295static int ahci_port_resume(struct ata_port *ap);
a878539e 296static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 297static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
298static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
299 u32 opts);
438ac6d5 300#ifdef CONFIG_PM
c1332875 301static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 302static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
303static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 304#endif
18f7ba4c
KCA		 305static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
306static ssize_t ahci_activity_store(struct ata_device *dev,
307 enum sw_activity val);
308static void ahci_init_sw_activity(struct ata_link *link);
1da177e4 309
ee959b00
TJ		 310static struct device_attribute *ahci_shost_attrs[] = {
311 &dev_attr_link_power_management_policy,
18f7ba4c
KCA		 312 &dev_attr_em_message_type,
313 &dev_attr_em_message,
314 NULL
315};
316
317static struct device_attribute *ahci_sdev_attrs[] = {
318 &dev_attr_sw_activity,
31556594
KCA		 319 NULL
320};
321
193515d5 322static struct scsi_host_template ahci_sht = {
68d1d07b 323 ATA_NCQ_SHT(DRV_NAME),
12fad3f9 324 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4 325 .sg_tablesize = AHCI_MAX_SG,
1da177e4 326 .dma_boundary = AHCI_DMA_BOUNDARY,
31556594 327 .shost_attrs = ahci_shost_attrs,
18f7ba4c 328 .sdev_attrs = ahci_sdev_attrs,
1da177e4
LT		 329};
330
029cfd6b
TH		 331static struct ata_port_operations ahci_ops = {
332 .inherits = &sata_pmp_port_ops,
333
7d50b60b 334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
4c9bf4e7 337 .qc_fill_rtf = ahci_qc_fill_rtf,
1da177e4 338
78cd52d0
TH		 339 .freeze = ahci_freeze,
340 .thaw = ahci_thaw,
a1efdaba
TH		 341 .softreset = ahci_softreset,
342 .hardreset = ahci_hardreset,
343 .postreset = ahci_postreset,
071f44b1 344 .pmp_softreset = ahci_softreset,
78cd52d0
TH		 345 .error_handler = ahci_error_handler,
346 .post_internal_cmd = ahci_post_internal_cmd,
6bd99b4e
TH		 347 .dev_config = ahci_dev_config,
348
ad616ffb
TH		 349 .scr_read = ahci_scr_read,
350 .scr_write = ahci_scr_write,
7d50b60b
TH		 351 .pmp_attach = ahci_pmp_attach,
352 .pmp_detach = ahci_pmp_detach,
7d50b60b 353
029cfd6b
TH		 354 .enable_pm = ahci_enable_alpm,
355 .disable_pm = ahci_disable_alpm,
18f7ba4c
KCA		 356 .em_show = ahci_led_show,
357 .em_store = ahci_led_store,
358 .sw_activity_show = ahci_activity_show,
359 .sw_activity_store = ahci_activity_store,
438ac6d5 360#ifdef CONFIG_PM
ad616ffb
TH		 361 .port_suspend = ahci_port_suspend,
362 .port_resume = ahci_port_resume,
438ac6d5 363#endif
ad616ffb
TH		 364 .port_start = ahci_port_start,
365 .port_stop = ahci_port_stop,
366};
367
029cfd6b
TH		 368static struct ata_port_operations ahci_vt8251_ops = {
369 .inherits = &ahci_ops,
a1efdaba 370 .hardreset = ahci_vt8251_hardreset,
029cfd6b 371};
edc93052 372
029cfd6b
TH		 373static struct ata_port_operations ahci_p5wdh_ops = {
374 .inherits = &ahci_ops,
a1efdaba 375 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 376};
377
bd17243a
SH		 378static struct ata_port_operations ahci_sb600_ops = {
379 .inherits = &ahci_ops,
380 .softreset = ahci_sb600_softreset,
381 .pmp_softreset = ahci_sb600_softreset,
382};
383
417a1a6d
TH		 384#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
385
98ac62de 386static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 387 /* board_ahci */
388 {
1188c0d8 389 .flags = AHCI_FLAG_COMMON,
7da79312 390 .pio_mask = 0x1f, /* pio0-4 */
469248ab 391 .udma_mask = ATA_UDMA6,
1da177e4
LT		 392 .port_ops = &ahci_ops,
393 },
bf2af2a2
BJ		 394 /* board_ahci_vt8251 */
395 {
6949b914 396 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 397 .flags = AHCI_FLAG_COMMON,
bf2af2a2 398 .pio_mask = 0x1f, /* pio0-4 */
469248ab 399 .udma_mask = ATA_UDMA6,
ad616ffb 400 .port_ops = &ahci_vt8251_ops,
bf2af2a2 401 },
41669553
TH		 402 /* board_ahci_ign_iferr */
403 {
417a1a6d
TH		 404 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
405 .flags = AHCI_FLAG_COMMON,
41669553 406 .pio_mask = 0x1f, /* pio0-4 */
469248ab 407 .udma_mask = ATA_UDMA6,
41669553
TH		 408 .port_ops = &ahci_ops,
409 },
55a61604
CH		 410 /* board_ahci_sb600 */
411 {
417a1a6d 412 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
22b5e7a7 413 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
bd17243a 414 AHCI_HFLAG_SECT255),
417a1a6d 415 .flags = AHCI_FLAG_COMMON,
55a61604 416 .pio_mask = 0x1f, /* pio0-4 */
469248ab 417 .udma_mask = ATA_UDMA6,
bd17243a 418 .port_ops = &ahci_sb600_ops,
55a61604 419 },
cd70c266
JG		 420 /* board_ahci_mv */
421 {
417a1a6d
TH		 422 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
423 AHCI_HFLAG_MV_PATA),
cd70c266 424 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 425 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
cd70c266
JG		 426 .pio_mask = 0x1f, /* pio0-4 */
427 .udma_mask = ATA_UDMA6,
428 .port_ops = &ahci_ops,
429 },
e39fc8c9
SH		 430 /* board_ahci_sb700 */
431 {
bd17243a 432 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
e39fc8c9 433 .flags = AHCI_FLAG_COMMON,
e39fc8c9
SH		 434 .pio_mask = 0x1f, /* pio0-4 */
435 .udma_mask = ATA_UDMA6,
bd17243a 436 .port_ops = &ahci_sb600_ops,
e39fc8c9 437 },
e297d99e
TH		 438 /* board_ahci_mcp65 */
439 {
440 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
441 .flags = AHCI_FLAG_COMMON,
442 .pio_mask = 0x1f, /* pio0-4 */
443 .udma_mask = ATA_UDMA6,
444 .port_ops = &ahci_ops,
445 },
9a3b103c
TH		 446 /* board_ahci_nopmp */
447 {
448 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
449 .flags = AHCI_FLAG_COMMON,
450 .pio_mask = 0x1f, /* pio0-4 */
451 .udma_mask = ATA_UDMA6,
452 .port_ops = &ahci_ops,
453 },
1da177e4
LT		 454};
455
3b7d697d 456static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 457 /* Intel */
54bb3a94
JG		 458 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
459 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
460 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
461 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
462 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 463 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 464 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
465 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
466 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 468 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
469 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
470 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
472 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
473 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
474 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
479 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 485 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
486 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9
JG		 487 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
488 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
adcb5308
SH		 489 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
490 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
fe7fa31a 491
e34bb370
TH		 492 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
493 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
494 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 495
496 /* ATI */
c65ec1c2 497 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 498 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
499 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
500 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
501 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a
JG		 504
505 /* VIA */
54bb3a94 506 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 507 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 508
509 /* NVIDIA */
e297d99e
TH		 510 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
511 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
512 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
6fbf5ba4
PC		 518 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
520 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 522 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 530 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
532 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
544 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 554 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
555 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
556 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 558 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
70d562cf 566 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
567 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
568 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
569 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
3072c379 574 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
fe7fa31a 578
95916edd 579 /* SiS */
20e2de4a
TH		 580 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
581 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
582 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 583
cd70c266
JG		 584 /* Marvell */
585 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 586 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 587
415ae2b5
JG		 588 /* Generic, PCI class code for AHCI */
589 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 590 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 591
1da177e4
LT		 592 { } /* terminate list */
593};
594
595
596static struct pci_driver ahci_pci_driver = {
597 .name = DRV_NAME,
598 .id_table = ahci_pci_tbl,
599 .probe = ahci_init_one,
24dc5f33 600 .remove = ata_pci_remove_one,
438ac6d5 601#ifdef CONFIG_PM
c1332875
TH		 602 .suspend = ahci_pci_device_suspend,
603 .resume = ahci_pci_device_resume,
438ac6d5 604#endif
1da177e4
LT		 605};
606
18f7ba4c
KCA		 607static int ahci_em_messages = 1;
608module_param(ahci_em_messages, int, 0444);
609/* add other LED protocol types when they become supported */
610MODULE_PARM_DESC(ahci_em_messages,
611 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
1da177e4 612
5b66c829
AC		 613#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
614static int marvell_enable;
615#else
616static int marvell_enable = 1;
617#endif
618module_param(marvell_enable, int, 0644);
619MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
620
621
98fa4b60
TH		 622static inline int ahci_nr_ports(u32 cap)
623{
624 return (cap & 0x1f) + 1;
625}
626
dab632e8
JG		 627static inline void __iomem *__ahci_port_base(struct ata_host *host,
628 unsigned int port_no)
1da177e4 629{
dab632e8 630 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 631
dab632e8
JG		 632 return mmio + 0x100 + (port_no * 0x80);
633}
634
635static inline void __iomem *ahci_port_base(struct ata_port *ap)
636{
637 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 638}
639
b710a1f4
TH		 640static void ahci_enable_ahci(void __iomem *mmio)
641{
15fe982e 642 int i;
b710a1f4
TH		 643 u32 tmp;
644
645 /* turn on AHCI_EN */
646 tmp = readl(mmio + HOST_CTL);
15fe982e
TH		 647 if (tmp & HOST_AHCI_EN)
648 return;
649
650 /* Some controllers need AHCI_EN to be written multiple times.
651 * Try a few times before giving up.
652 */
653 for (i = 0; i < 5; i++) {
b710a1f4
TH		 654 tmp |= HOST_AHCI_EN;
655 writel(tmp, mmio + HOST_CTL);
656 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
15fe982e
TH		 657 if (tmp & HOST_AHCI_EN)
658 return;
659 msleep(10);
b710a1f4 660 }
15fe982e
TH		 661
662 WARN_ON(1);
b710a1f4
TH		 663}
664
d447df14
TH		 665/**
666 * ahci_save_initial_config - Save and fixup initial config values
4447d351 667 * @pdev: target PCI device
4447d351 668 * @hpriv: host private area to store config values
d447df14
TH		 669 *
670 * Some registers containing configuration info might be setup by
671 * BIOS and might be cleared on reset. This function saves the
672 * initial values of those registers into @hpriv such that they
673 * can be restored after controller reset.
674 *
675 * If inconsistent, config values are fixed up by this function.
676 *
677 * LOCKING:
678 * None.
679 */
4447d351 680static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 681 struct ahci_host_priv *hpriv)
d447df14 682{
4447d351 683 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 684 u32 cap, port_map;
17199b18 685 int i;
c40e7cb8 686 int mv;
d447df14 687
b710a1f4
TH		 688 /* make sure AHCI mode is enabled before accessing CAP */
689 ahci_enable_ahci(mmio);
690
d447df14
TH		 691 /* Values prefixed with saved_ are written back to host after
692 * reset. Values without are used for driver operation.
693 */
694 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
695 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
696
274c1fde 697 /* some chips have errata preventing 64bit use */
417a1a6d 698 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 699 dev_printk(KERN_INFO, &pdev->dev,
700 "controller can't do 64bit DMA, forcing 32bit\n");
701 cap &= ~HOST_CAP_64;
702 }
703
417a1a6d 704 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 705 dev_printk(KERN_INFO, &pdev->dev,
706 "controller can't do NCQ, turning off CAP_NCQ\n");
707 cap &= ~HOST_CAP_NCQ;
708 }
709
e297d99e
TH		 710 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
711 dev_printk(KERN_INFO, &pdev->dev,
712 "controller can do NCQ, turning on CAP_NCQ\n");
713 cap |= HOST_CAP_NCQ;
714 }
715
258cd846 716 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 717 dev_printk(KERN_INFO, &pdev->dev,
718 "controller can't do PMP, turning off CAP_PMP\n");
719 cap &= ~HOST_CAP_PMP;
720 }
721
d799e083
TH		 722 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
723 port_map != 1) {
724 dev_printk(KERN_INFO, &pdev->dev,
725 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
726 port_map, 1);
727 port_map = 1;
728 }
729
cd70c266
JG		 730 /*
731 * Temporary Marvell 6145 hack: PATA port presence
732 * is asserted through the standard AHCI port
733 * presence register, as bit 4 (counting from 0)
734 */
417a1a6d 735 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 736 if (pdev->device == 0x6121)
737 mv = 0x3;
738 else
739 mv = 0xf;
cd70c266
JG		 740 dev_printk(KERN_ERR, &pdev->dev,
741 "MV_AHCI HACK: port_map %x -> %x\n",
c40e7cb8
JAR		 742 port_map,
743 port_map & mv);
5b66c829
AC		 744 dev_printk(KERN_ERR, &pdev->dev,
745 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
cd70c266 746
c40e7cb8 747 port_map &= mv;
cd70c266
JG		 748 }
749
17199b18 750 /* cross check port_map and cap.n_ports */
7a234aff 751 if (port_map) {
837f5f8f 752 int map_ports = 0;
17199b18 753
837f5f8f
TH		 754 for (i = 0; i < AHCI_MAX_PORTS; i++)
755 if (port_map & (1 << i))
756 map_ports++;
17199b18 757
837f5f8f
TH		 758 /* If PI has more ports than n_ports, whine, clear
759 * port_map and let it be generated from n_ports.
17199b18 760 */
837f5f8f 761 if (map_ports > ahci_nr_ports(cap)) {
4447d351 762 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 763 "implemented port map (0x%x) contains more "
764 "ports than nr_ports (%u), using nr_ports\n",
765 port_map, ahci_nr_ports(cap));
7a234aff
TH		 766 port_map = 0;
767 }
768 }
769
770 /* fabricate port_map from cap.nr_ports */
771 if (!port_map) {
17199b18 772 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 773 dev_printk(KERN_WARNING, &pdev->dev,
774 "forcing PORTS_IMPL to 0x%x\n", port_map);
775
776 /* write the fixed up value to the PI register */
777 hpriv->saved_port_map = port_map;
17199b18
TH		 778 }
779
d447df14
TH		 780 /* record values to use during operation */
781 hpriv->cap = cap;
782 hpriv->port_map = port_map;
783}
784
785/**
786 * ahci_restore_initial_config - Restore initial config
4447d351 787 * @host: target ATA host
d447df14
TH		 788 *
789 * Restore initial config stored by ahci_save_initial_config().
790 *
791 * LOCKING:
792 * None.
793 */
4447d351 794static void ahci_restore_initial_config(struct ata_host *host)
d447df14 795{
4447d351
TH		 796 struct ahci_host_priv *hpriv = host->private_data;
797 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
798
d447df14
TH		 799 writel(hpriv->saved_cap, mmio + HOST_CAP);
800 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
801 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
802}
803
203ef6c4 804static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 805{
203ef6c4
TH		 806 static const int offset[] = {
807 [SCR_STATUS] = PORT_SCR_STAT,
808 [SCR_CONTROL] = PORT_SCR_CTL,
809 [SCR_ERROR] = PORT_SCR_ERR,
810 [SCR_ACTIVE] = PORT_SCR_ACT,
811 [SCR_NOTIFICATION] = PORT_SCR_NTF,
812 };
813 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 814
203ef6c4
TH		 815 if (sc_reg < ARRAY_SIZE(offset) &&
816 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
817 return offset[sc_reg];
da3dbb17 818 return 0;
1da177e4
LT		 819}
820
203ef6c4 821static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 822{
203ef6c4
TH		 823 void __iomem *port_mmio = ahci_port_base(ap);
824 int offset = ahci_scr_offset(ap, sc_reg);
825
826 if (offset) {
827 *val = readl(port_mmio + offset);
828 return 0;
1da177e4 829 }
203ef6c4
TH		 830 return -EINVAL;
831}
1da177e4 832
203ef6c4
TH		 833static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
834{
835 void __iomem *port_mmio = ahci_port_base(ap);
836 int offset = ahci_scr_offset(ap, sc_reg);
837
838 if (offset) {
839 writel(val, port_mmio + offset);
840 return 0;
841 }
842 return -EINVAL;
1da177e4
LT		 843}
844
4447d351 845static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 846{
4447d351 847 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 848 u32 tmp;
849
d8fcd116 850 /* start DMA */
9f592056 851 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 852 tmp |= PORT_CMD_START;
853 writel(tmp, port_mmio + PORT_CMD);
854 readl(port_mmio + PORT_CMD); /* flush */
855}
856
4447d351 857static int ahci_stop_engine(struct ata_port *ap)
254950cd 858{
4447d351 859 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 860 u32 tmp;
861
862 tmp = readl(port_mmio + PORT_CMD);
863
d8fcd116 864 /* check if the HBA is idle */
254950cd
TH		 865 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
866 return 0;
867
d8fcd116 868 /* setting HBA to idle */
254950cd
TH		 869 tmp &= ~PORT_CMD_START;
870 writel(tmp, port_mmio + PORT_CMD);
871
d8fcd116 872 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 873 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 874 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 875 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 876 return -EIO;
877
878 return 0;
879}
880
4447d351 881static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 882{
4447d351
TH		 883 void __iomem *port_mmio = ahci_port_base(ap);
884 struct ahci_host_priv *hpriv = ap->host->private_data;
885 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 886 u32 tmp;
887
888 /* set FIS registers */
4447d351
TH		 889 if (hpriv->cap & HOST_CAP_64)
890 writel((pp->cmd_slot_dma >> 16) >> 16,
891 port_mmio + PORT_LST_ADDR_HI);
892 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 893
4447d351
TH		 894 if (hpriv->cap & HOST_CAP_64)
895 writel((pp->rx_fis_dma >> 16) >> 16,
896 port_mmio + PORT_FIS_ADDR_HI);
897 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 898
899 /* enable FIS reception */
900 tmp = readl(port_mmio + PORT_CMD);
901 tmp |= PORT_CMD_FIS_RX;
902 writel(tmp, port_mmio + PORT_CMD);
903
904 /* flush */
905 readl(port_mmio + PORT_CMD);
906}
907
4447d351 908static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 909{
4447d351 910 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 911 u32 tmp;
912
913 /* disable FIS reception */
914 tmp = readl(port_mmio + PORT_CMD);
915 tmp &= ~PORT_CMD_FIS_RX;
916 writel(tmp, port_mmio + PORT_CMD);
917
918 /* wait for completion, spec says 500ms, give it 1000 */
919 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
920 PORT_CMD_FIS_ON, 10, 1000);
921 if (tmp & PORT_CMD_FIS_ON)
922 return -EBUSY;
923
924 return 0;
925}
926
4447d351 927static void ahci_power_up(struct ata_port *ap)
0be0aa98 928{
4447d351
TH		 929 struct ahci_host_priv *hpriv = ap->host->private_data;
930 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 931 u32 cmd;
932
933 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
934
935 /* spin up device */
4447d351 936 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 937 cmd |= PORT_CMD_SPIN_UP;
938 writel(cmd, port_mmio + PORT_CMD);
939 }
940
941 /* wake up link */
942 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
943}
944
31556594
KCA		 945static void ahci_disable_alpm(struct ata_port *ap)
946{
947 struct ahci_host_priv *hpriv = ap->host->private_data;
948 void __iomem *port_mmio = ahci_port_base(ap);
949 u32 cmd;
950 struct ahci_port_priv *pp = ap->private_data;
951
952 /* IPM bits should be disabled by libata-core */
953 /* get the existing command bits */
954 cmd = readl(port_mmio + PORT_CMD);
955
956 /* disable ALPM and ASP */
957 cmd &= ~PORT_CMD_ASP;
958 cmd &= ~PORT_CMD_ALPE;
959
960 /* force the interface back to active */
961 cmd |= PORT_CMD_ICC_ACTIVE;
962
963 /* write out new cmd value */
964 writel(cmd, port_mmio + PORT_CMD);
965 cmd = readl(port_mmio + PORT_CMD);
966
967 /* wait 10ms to be sure we've come out of any low power state */
968 msleep(10);
969
970 /* clear out any PhyRdy stuff from interrupt status */
971 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
972
973 /* go ahead and clean out PhyRdy Change from Serror too */
974 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
975
976 /*
977 * Clear flag to indicate that we should ignore all PhyRdy
978 * state changes
979 */
980 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
981
982 /*
983 * Enable interrupts on Phy Ready.
984 */
985 pp->intr_mask |= PORT_IRQ_PHYRDY;
986 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
987
988 /*
989 * don't change the link pm policy - we can be called
990 * just to turn of link pm temporarily
991 */
992}
993
994static int ahci_enable_alpm(struct ata_port *ap,
995 enum link_pm policy)
996{
997 struct ahci_host_priv *hpriv = ap->host->private_data;
998 void __iomem *port_mmio = ahci_port_base(ap);
999 u32 cmd;
1000 struct ahci_port_priv *pp = ap->private_data;
1001 u32 asp;
1002
1003 /* Make sure the host is capable of link power management */
1004 if (!(hpriv->cap & HOST_CAP_ALPM))
1005 return -EINVAL;
1006
1007 switch (policy) {
1008 case MAX_PERFORMANCE:
1009 case NOT_AVAILABLE:
1010 /*
1011 * if we came here with NOT_AVAILABLE,
1012 * it just means this is the first time we
1013 * have tried to enable - default to max performance,
1014 * and let the user go to lower power modes on request.
1015 */
1016 ahci_disable_alpm(ap);
1017 return 0;
1018 case MIN_POWER:
1019 /* configure HBA to enter SLUMBER */
1020 asp = PORT_CMD_ASP;
1021 break;
1022 case MEDIUM_POWER:
1023 /* configure HBA to enter PARTIAL */
1024 asp = 0;
1025 break;
1026 default:
1027 return -EINVAL;
1028 }
1029
1030 /*
1031 * Disable interrupts on Phy Ready. This keeps us from
1032 * getting woken up due to spurious phy ready interrupts
1033 * TBD - Hot plug should be done via polling now, is
1034 * that even supported?
1035 */
1036 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1037 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1038
1039 /*
1040 * Set a flag to indicate that we should ignore all PhyRdy
1041 * state changes since these can happen now whenever we
1042 * change link state
1043 */
1044 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1045
1046 /* get the existing command bits */
1047 cmd = readl(port_mmio + PORT_CMD);
1048
1049 /*
1050 * Set ASP based on Policy
1051 */
1052 cmd |= asp;
1053
1054 /*
1055 * Setting this bit will instruct the HBA to aggressively
1056 * enter a lower power link state when it's appropriate and
1057 * based on the value set above for ASP
1058 */
1059 cmd |= PORT_CMD_ALPE;
1060
1061 /* write out new cmd value */
1062 writel(cmd, port_mmio + PORT_CMD);
1063 cmd = readl(port_mmio + PORT_CMD);
1064
1065 /* IPM bits should be set by libata-core */
1066 return 0;
1067}
1068
438ac6d5 1069#ifdef CONFIG_PM
4447d351 1070static void ahci_power_down(struct ata_port *ap)
0be0aa98 1071{
4447d351
TH		 1072 struct ahci_host_priv *hpriv = ap->host->private_data;
1073 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1074 u32 cmd, scontrol;
1075
4447d351 1076 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1077 return;
0be0aa98 1078
07c53dac
TH		 1079 /* put device into listen mode, first set PxSCTL.DET to 0 */
1080 scontrol = readl(port_mmio + PORT_SCR_CTL);
1081 scontrol &= ~0xf;
1082 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1083
07c53dac
TH		 1084 /* then set PxCMD.SUD to 0 */
1085 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1086 cmd &= ~PORT_CMD_SPIN_UP;
1087 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1088}
438ac6d5 1089#endif
0be0aa98 1090
df69c9c5 1091static void ahci_start_port(struct ata_port *ap)
0be0aa98 1092{
18f7ba4c
KCA		 1093 struct ahci_port_priv *pp = ap->private_data;
1094 struct ata_link *link;
1095 struct ahci_em_priv *emp;
1096
0be0aa98 1097 /* enable FIS reception */
4447d351 1098 ahci_start_fis_rx(ap);
0be0aa98
TH		 1099
1100 /* enable DMA */
4447d351 1101 ahci_start_engine(ap);
18f7ba4c
KCA		 1102
1103 /* turn on LEDs */
1104 if (ap->flags & ATA_FLAG_EM) {
1105 ata_port_for_each_link(link, ap) {
1106 emp = &pp->em_priv[link->pmp];
1107 ahci_transmit_led_message(ap, emp->led_state, 4);
1108 }
1109 }
1110
1111 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1112 ata_port_for_each_link(link, ap)
1113 ahci_init_sw_activity(link);
1114
0be0aa98
TH		 1115}
1116
4447d351 1117static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1118{
1119 int rc;
1120
1121 /* disable DMA */
4447d351 1122 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1123 if (rc) {
1124 *emsg = "failed to stop engine";
1125 return rc;
1126 }
1127
1128 /* disable FIS reception */
4447d351 1129 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1130 if (rc) {
1131 *emsg = "failed stop FIS RX";
1132 return rc;
1133 }
1134
0be0aa98
TH		 1135 return 0;
1136}
1137
4447d351 1138static int ahci_reset_controller(struct ata_host *host)
d91542c1 1139{
4447d351 1140 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1141 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1142 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1143 u32 tmp;
d91542c1 1144
3cc3eb11
JG		 1145 /* we must be in AHCI mode, before using anything
1146 * AHCI-specific, such as HOST_RESET.
1147 */
b710a1f4 1148 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1149
1150 /* global controller reset */
a22e6444
TH		 1151 if (!ahci_skip_host_reset) {
1152 tmp = readl(mmio + HOST_CTL);
1153 if ((tmp & HOST_RESET) == 0) {
1154 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1155 readl(mmio + HOST_CTL); /* flush */
1156 }
d91542c1 1157
24920c8a
ZR		 1158 /*
1159 * to perform host reset, OS should set HOST_RESET
1160 * and poll until this bit is read to be "0".
1161 * reset must complete within 1 second, or
a22e6444
TH		 1162 * the hardware should be considered fried.
1163 */
24920c8a
ZR		 1164 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1165 HOST_RESET, 10, 1000);
d91542c1 1166
a22e6444
TH		 1167 if (tmp & HOST_RESET) {
1168 dev_printk(KERN_ERR, host->dev,
1169 "controller reset failed (0x%x)\n", tmp);
1170 return -EIO;
1171 }
d91542c1 1172
a22e6444
TH		 1173 /* turn on AHCI mode */
1174 ahci_enable_ahci(mmio);
98fa4b60 1175
a22e6444
TH		 1176 /* Some registers might be cleared on reset. Restore
1177 * initial values.
1178 */
1179 ahci_restore_initial_config(host);
1180 } else
1181 dev_printk(KERN_INFO, host->dev,
1182 "skipping global host reset\n");
d91542c1
TH		 1183
1184 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1185 u16 tmp16;
1186
1187 /* configure PCS */
1188 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1189 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1190 tmp16 |= hpriv->port_map;
1191 pci_write_config_word(pdev, 0x92, tmp16);
1192 }
d91542c1
TH		 1193 }
1194
1195 return 0;
1196}
1197
18f7ba4c
KCA		 1198static void ahci_sw_activity(struct ata_link *link)
1199{
1200 struct ata_port *ap = link->ap;
1201 struct ahci_port_priv *pp = ap->private_data;
1202 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1203
1204 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1205 return;
1206
1207 emp->activity++;
1208 if (!timer_pending(&emp->timer))
1209 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1210}
1211
1212static void ahci_sw_activity_blink(unsigned long arg)
1213{
1214 struct ata_link *link = (struct ata_link *)arg;
1215 struct ata_port *ap = link->ap;
1216 struct ahci_port_priv *pp = ap->private_data;
1217 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1218 unsigned long led_message = emp->led_state;
1219 u32 activity_led_state;
1220
1221 led_message &= 0xffff0000;
1222 led_message |= ap->port_no | (link->pmp << 8);
1223
1224 /* check to see if we've had activity. If so,
1225 * toggle state of LED and reset timer. If not,
1226 * turn LED to desired idle state.
1227 */
1228 if (emp->saved_activity != emp->activity) {
1229 emp->saved_activity = emp->activity;
1230 /* get the current LED state */
1231 activity_led_state = led_message & 0x00010000;
1232
1233 if (activity_led_state)
1234 activity_led_state = 0;
1235 else
1236 activity_led_state = 1;
1237
1238 /* clear old state */
1239 led_message &= 0xfff8ffff;
1240
1241 /* toggle state */
1242 led_message |= (activity_led_state << 16);
1243 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1244 } else {
1245 /* switch to idle */
1246 led_message &= 0xfff8ffff;
1247 if (emp->blink_policy == BLINK_OFF)
1248 led_message |= (1 << 16);
1249 }
1250 ahci_transmit_led_message(ap, led_message, 4);
1251}
1252
1253static void ahci_init_sw_activity(struct ata_link *link)
1254{
1255 struct ata_port *ap = link->ap;
1256 struct ahci_port_priv *pp = ap->private_data;
1257 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1258
1259 /* init activity stats, setup timer */
1260 emp->saved_activity = emp->activity = 0;
1261 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1262
1263 /* check our blink policy and set flag for link if it's enabled */
1264 if (emp->blink_policy)
1265 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1266}
1267
1268static int ahci_reset_em(struct ata_host *host)
1269{
1270 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1271 u32 em_ctl;
1272
1273 em_ctl = readl(mmio + HOST_EM_CTL);
1274 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1275 return -EINVAL;
1276
1277 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1278 return 0;
1279}
1280
1281static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1282 ssize_t size)
1283{
1284 struct ahci_host_priv *hpriv = ap->host->private_data;
1285 struct ahci_port_priv *pp = ap->private_data;
1286 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1287 u32 em_ctl;
1288 u32 message[] = {0, 0};
93082f0b 1289 unsigned long flags;
18f7ba4c
KCA		 1290 int pmp;
1291 struct ahci_em_priv *emp;
1292
1293 /* get the slot number from the message */
1294 pmp = (state & 0x0000ff00) >> 8;
1295 if (pmp < MAX_SLOTS)
1296 emp = &pp->em_priv[pmp];
1297 else
1298 return -EINVAL;
1299
1300 spin_lock_irqsave(ap->lock, flags);
1301
1302 /*
1303 * if we are still busy transmitting a previous message,
1304 * do not allow
1305 */
1306 em_ctl = readl(mmio + HOST_EM_CTL);
1307 if (em_ctl & EM_CTL_TM) {
1308 spin_unlock_irqrestore(ap->lock, flags);
1309 return -EINVAL;
1310 }
1311
1312 /*
1313 * create message header - this is all zero except for
1314 * the message size, which is 4 bytes.
1315 */
1316 message[0] |= (4 << 8);
1317
1318 /* ignore 0:4 of byte zero, fill in port info yourself */
1319 message[1] = ((state & 0xfffffff0) | ap->port_no);
1320
1321 /* write message to EM_LOC */
1322 writel(message[0], mmio + hpriv->em_loc);
1323 writel(message[1], mmio + hpriv->em_loc+4);
1324
1325 /* save off new led state for port/slot */
1326 emp->led_state = message[1];
1327
1328 /*
1329 * tell hardware to transmit the message
1330 */
1331 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1332
1333 spin_unlock_irqrestore(ap->lock, flags);
1334 return size;
1335}
1336
1337static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1338{
1339 struct ahci_port_priv *pp = ap->private_data;
1340 struct ata_link *link;
1341 struct ahci_em_priv *emp;
1342 int rc = 0;
1343
1344 ata_port_for_each_link(link, ap) {
1345 emp = &pp->em_priv[link->pmp];
1346 rc += sprintf(buf, "%lx\n", emp->led_state);
1347 }
1348 return rc;
1349}
1350
1351static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1352 size_t size)
1353{
1354 int state;
1355 int pmp;
1356 struct ahci_port_priv *pp = ap->private_data;
1357 struct ahci_em_priv *emp;
1358
1359 state = simple_strtoul(buf, NULL, 0);
1360
1361 /* get the slot number from the message */
1362 pmp = (state & 0x0000ff00) >> 8;
1363 if (pmp < MAX_SLOTS)
1364 emp = &pp->em_priv[pmp];
1365 else
1366 return -EINVAL;
1367
1368 /* mask off the activity bits if we are in sw_activity
1369 * mode, user should turn off sw_activity before setting
1370 * activity led through em_message
1371 */
1372 if (emp->blink_policy)
1373 state &= 0xfff8ffff;
1374
1375 return ahci_transmit_led_message(ap, state, size);
1376}
1377
1378static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1379{
1380 struct ata_link *link = dev->link;
1381 struct ata_port *ap = link->ap;
1382 struct ahci_port_priv *pp = ap->private_data;
1383 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1384 u32 port_led_state = emp->led_state;
1385
1386 /* save the desired Activity LED behavior */
1387 if (val == OFF) {
1388 /* clear LFLAG */
1389 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1390
1391 /* set the LED to OFF */
1392 port_led_state &= 0xfff80000;
1393 port_led_state |= (ap->port_no | (link->pmp << 8));
1394 ahci_transmit_led_message(ap, port_led_state, 4);
1395 } else {
1396 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1397 if (val == BLINK_OFF) {
1398 /* set LED to ON for idle */
1399 port_led_state &= 0xfff80000;
1400 port_led_state |= (ap->port_no | (link->pmp << 8));
1401 port_led_state |= 0x00010000; /* check this */
1402 ahci_transmit_led_message(ap, port_led_state, 4);
1403 }
1404 }
1405 emp->blink_policy = val;
1406 return 0;
1407}
1408
1409static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1410{
1411 struct ata_link *link = dev->link;
1412 struct ata_port *ap = link->ap;
1413 struct ahci_port_priv *pp = ap->private_data;
1414 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1415
1416 /* display the saved value of activity behavior for this
1417 * disk.
1418 */
1419 return sprintf(buf, "%d\n", emp->blink_policy);
1420}
1421
2bcd866b
JG		 1422static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1423 int port_no, void __iomem *mmio,
1424 void __iomem *port_mmio)
1425{
1426 const char *emsg = NULL;
1427 int rc;
1428 u32 tmp;
1429
1430 /* make sure port is not active */
1431 rc = ahci_deinit_port(ap, &emsg);
1432 if (rc)
1433 dev_printk(KERN_WARNING, &pdev->dev,
1434 "%s (%d)\n", emsg, rc);
1435
1436 /* clear SError */
1437 tmp = readl(port_mmio + PORT_SCR_ERR);
1438 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1439 writel(tmp, port_mmio + PORT_SCR_ERR);
1440
1441 /* clear port IRQ */
1442 tmp = readl(port_mmio + PORT_IRQ_STAT);
1443 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1444 if (tmp)
1445 writel(tmp, port_mmio + PORT_IRQ_STAT);
1446
1447 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1448}
1449
4447d351 1450static void ahci_init_controller(struct ata_host *host)
d91542c1 1451{
417a1a6d 1452 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1453 struct pci_dev *pdev = to_pci_dev(host->dev);
1454 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1455 int i;
cd70c266 1456 void __iomem *port_mmio;
d91542c1 1457 u32 tmp;
c40e7cb8 1458 int mv;
d91542c1 1459
417a1a6d 1460 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 1461 if (pdev->device == 0x6121)
1462 mv = 2;
1463 else
1464 mv = 4;
1465 port_mmio = __ahci_port_base(host, mv);
cd70c266
JG		 1466
1467 writel(0, port_mmio + PORT_IRQ_MASK);
1468
1469 /* clear port IRQ */
1470 tmp = readl(port_mmio + PORT_IRQ_STAT);
1471 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1472 if (tmp)
1473 writel(tmp, port_mmio + PORT_IRQ_STAT);
1474 }
1475
4447d351
TH		 1476 for (i = 0; i < host->n_ports; i++) {
1477 struct ata_port *ap = host->ports[i];
d91542c1 1478
cd70c266 1479 port_mmio = ahci_port_base(ap);
4447d351 1480 if (ata_port_is_dummy(ap))
d91542c1 1481 continue;
d91542c1 1482
2bcd866b 1483 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1484 }
1485
1486 tmp = readl(mmio + HOST_CTL);
1487 VPRINTK("HOST_CTL 0x%x\n", tmp);
1488 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1489 tmp = readl(mmio + HOST_CTL);
1490 VPRINTK("HOST_CTL 0x%x\n", tmp);
1491}
1492
a878539e
JG		 1493static void ahci_dev_config(struct ata_device *dev)
1494{
1495 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1496
4cde32fc 1497 if (hpriv->flags & AHCI_HFLAG_SECT255) {
a878539e 1498 dev->max_sectors = 255;
4cde32fc
JG		 1499 ata_dev_printk(dev, KERN_INFO,
1500 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1501 }
a878539e
JG		 1502}
1503
422b7595 1504static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1505{
4447d351 1506 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1507 struct ata_taskfile tf;
422b7595
TH		 1508 u32 tmp;
1509
1510 tmp = readl(port_mmio + PORT_SIG);
1511 tf.lbah = (tmp >> 24) & 0xff;
1512 tf.lbam = (tmp >> 16) & 0xff;
1513 tf.lbal = (tmp >> 8) & 0xff;
1514 tf.nsect = (tmp) & 0xff;
1515
1516 return ata_dev_classify(&tf);
1517}
1518
12fad3f9
TH		 1519static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1520 u32 opts)
cc9278ed 1521{
12fad3f9
TH		 1522 dma_addr_t cmd_tbl_dma;
1523
1524 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1525
1526 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1527 pp->cmd_slot[tag].status = 0;
1528 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1529 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1530}
1531
d2e75dff 1532static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1533{
350756f6 1534 void __iomem *port_mmio = ahci_port_base(ap);
cca3974e 1535 struct ahci_host_priv *hpriv = ap->host->private_data;
520d06f9 1536 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
bf2af2a2 1537 u32 tmp;
d2e75dff 1538 int busy, rc;
bf2af2a2 1539
d2e75dff 1540 /* do we need to kick the port? */
520d06f9 1541 busy = status & (ATA_BUSY | ATA_DRQ);
d2e75dff
TH		 1542 if (!busy && !force_restart)
1543 return 0;
1544
1545 /* stop engine */
1546 rc = ahci_stop_engine(ap);
1547 if (rc)
1548 goto out_restart;
1549
1550 /* need to do CLO? */
1551 if (!busy) {
1552 rc = 0;
1553 goto out_restart;
1554 }
1555
1556 if (!(hpriv->cap & HOST_CAP_CLO)) {
1557 rc = -EOPNOTSUPP;
1558 goto out_restart;
1559 }
bf2af2a2 1560
d2e75dff 1561 /* perform CLO */
bf2af2a2
BJ		 1562 tmp = readl(port_mmio + PORT_CMD);
1563 tmp |= PORT_CMD_CLO;
1564 writel(tmp, port_mmio + PORT_CMD);
1565
d2e75dff 1566 rc = 0;
bf2af2a2
BJ		 1567 tmp = ata_wait_register(port_mmio + PORT_CMD,
1568 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1569 if (tmp & PORT_CMD_CLO)
d2e75dff 1570 rc = -EIO;
bf2af2a2 1571
d2e75dff
TH		 1572 /* restart engine */
1573 out_restart:
1574 ahci_start_engine(ap);
1575 return rc;
bf2af2a2
BJ		 1576}
1577
91c4a2e0
TH		 1578static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1579 struct ata_taskfile *tf, int is_cmd, u16 flags,
1580 unsigned long timeout_msec)
bf2af2a2 1581{
91c4a2e0 1582 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1583 struct ahci_port_priv *pp = ap->private_data;
4447d351 1584 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1585 u8 *fis = pp->cmd_tbl;
1586 u32 tmp;
1587
1588 /* prep the command */
1589 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1590 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1591
1592 /* issue & wait */
1593 writel(1, port_mmio + PORT_CMD_ISSUE);
1594
1595 if (timeout_msec) {
1596 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1597 1, timeout_msec);
1598 if (tmp & 0x1) {
1599 ahci_kick_engine(ap, 1);
1600 return -EBUSY;
1601 }
1602 } else
1603 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1604
1605 return 0;
1606}
1607
bd17243a
SH		 1608static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1609 int pmp, unsigned long deadline,
1610 int (*check_ready)(struct ata_link *link))
91c4a2e0 1611{
cc0680a5 1612 struct ata_port *ap = link->ap;
4658f79b 1613 const char *reason = NULL;
2cbb79eb 1614 unsigned long now, msecs;
4658f79b 1615 struct ata_taskfile tf;
4658f79b
TH		 1616 int rc;
1617
1618 DPRINTK("ENTER\n");
1619
1620 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1621 rc = ahci_kick_engine(ap, 1);
994056d7 1622 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1623 ata_link_printk(link, KERN_WARNING,
994056d7 1624 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1625
cc0680a5 1626 ata_tf_init(link->device, &tf);
4658f79b
TH		 1627
1628 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1629 msecs = 0;
1630 now = jiffies;
1631 if (time_after(now, deadline))
1632 msecs = jiffies_to_msecs(deadline - now);
1633
4658f79b 1634 tf.ctl |= ATA_SRST;
a9cf5e85 1635 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1636 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1637 rc = -EIO;
1638 reason = "1st FIS failed";
1639 goto fail;
1640 }
1641
1642 /* spec says at least 5us, but be generous and sleep for 1ms */
1643 msleep(1);
1644
1645 /* issue the second D2H Register FIS */
4658f79b 1646 tf.ctl &= ~ATA_SRST;
a9cf5e85 1647 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1648
705e76be 1649 /* wait for link to become ready */
bd17243a 1650 rc = ata_wait_after_reset(link, deadline, check_ready);
9b89391c
TH		 1651 /* link occupied, -ENODEV too is an error */
1652 if (rc) {
1653 reason = "device not ready";
1654 goto fail;
4658f79b 1655 }
9b89391c 1656 *class = ahci_dev_classify(ap);
4658f79b
TH		 1657
1658 DPRINTK("EXIT, class=%u\n", *class);
1659 return 0;
1660
4658f79b 1661 fail:
cc0680a5 1662 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1663 return rc;
1664}
1665
bd17243a
SH		 1666static int ahci_check_ready(struct ata_link *link)
1667{
1668 void __iomem *port_mmio = ahci_port_base(link->ap);
1669 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1670
1671 return ata_check_ready(status);
1672}
1673
1674static int ahci_softreset(struct ata_link *link, unsigned int *class,
1675 unsigned long deadline)
1676{
1677 int pmp = sata_srst_pmp(link);
1678
1679 DPRINTK("ENTER\n");
1680
1681 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1682}
1683
1684static int ahci_sb600_check_ready(struct ata_link *link)
1685{
1686 void __iomem *port_mmio = ahci_port_base(link->ap);
1687 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1688 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1689
1690 /*
1691 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1692 * which can save timeout delay.
1693 */
1694 if (irq_status & PORT_IRQ_BAD_PMP)
1695 return -EIO;
1696
1697 return ata_check_ready(status);
1698}
1699
1700static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1701 unsigned long deadline)
1702{
1703 struct ata_port *ap = link->ap;
1704 void __iomem *port_mmio = ahci_port_base(ap);
1705 int pmp = sata_srst_pmp(link);
1706 int rc;
1707 u32 irq_sts;
1708
1709 DPRINTK("ENTER\n");
1710
1711 rc = ahci_do_softreset(link, class, pmp, deadline,
1712 ahci_sb600_check_ready);
1713
1714 /*
1715 * Soft reset fails on some ATI chips with IPMS set when PMP
1716 * is enabled but SATA HDD/ODD is connected to SATA port,
1717 * do soft reset again to port 0.
1718 */
1719 if (rc == -EIO) {
1720 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1721 if (irq_sts & PORT_IRQ_BAD_PMP) {
1722 ata_link_printk(link, KERN_WARNING,
1723 "failed due to HW bug, retry pmp=0\n");
1724 rc = ahci_do_softreset(link, class, 0, deadline,
1725 ahci_check_ready);
1726 }
1727 }
1728
1729 return rc;
1730}
1731
cc0680a5 1732static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1733 unsigned long deadline)
422b7595 1734{
9dadd45b 1735 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
cc0680a5 1736 struct ata_port *ap = link->ap;
4296971d
TH		 1737 struct ahci_port_priv *pp = ap->private_data;
1738 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1739 struct ata_taskfile tf;
9dadd45b 1740 bool online;
4bd00f6a
TH		 1741 int rc;
1742
1743 DPRINTK("ENTER\n");
1da177e4 1744
4447d351 1745 ahci_stop_engine(ap);
4296971d
TH		 1746
1747 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1748 ata_tf_init(link->device, &tf);
dfd7a3db 1749 tf.command = 0x80;
9977126c 1750 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1751
9dadd45b
TH		 1752 rc = sata_link_hardreset(link, timing, deadline, &online,
1753 ahci_check_ready);
4296971d 1754
4447d351 1755 ahci_start_engine(ap);
1da177e4 1756
9dadd45b 1757 if (online)
4bd00f6a 1758 *class = ahci_dev_classify(ap);
1da177e4 1759
4bd00f6a
TH		 1760 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1761 return rc;
1762}
1763
cc0680a5 1764static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1765 unsigned long deadline)
ad616ffb 1766{
cc0680a5 1767 struct ata_port *ap = link->ap;
9dadd45b 1768 bool online;
ad616ffb
TH		 1769 int rc;
1770
1771 DPRINTK("ENTER\n");
1772
4447d351 1773 ahci_stop_engine(ap);
ad616ffb 1774
cc0680a5 1775 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1776 deadline, &online, NULL);
ad616ffb 1777
4447d351 1778 ahci_start_engine(ap);
ad616ffb
TH		 1779
1780 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1781
1782 /* vt8251 doesn't clear BSY on signature FIS reception,
1783 * request follow-up softreset.
1784 */
9dadd45b 1785 return online ? -EAGAIN : rc;
ad616ffb
TH		 1786}
1787
edc93052
TH		 1788static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1789 unsigned long deadline)
1790{
1791 struct ata_port *ap = link->ap;
1792 struct ahci_port_priv *pp = ap->private_data;
1793 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1794 struct ata_taskfile tf;
9dadd45b 1795 bool online;
edc93052
TH		 1796 int rc;
1797
1798 ahci_stop_engine(ap);
1799
1800 /* clear D2H reception area to properly wait for D2H FIS */
1801 ata_tf_init(link->device, &tf);
1802 tf.command = 0x80;
1803 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1804
1805 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1806 deadline, &online, NULL);
edc93052
TH		 1807
1808 ahci_start_engine(ap);
1809
edc93052
TH		 1810 /* The pseudo configuration device on SIMG4726 attached to
1811 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1812 * hardreset if no device is attached to the first downstream
1813 * port && the pseudo device locks up on SRST w/ PMP==0. To
1814 * work around this, wait for !BSY only briefly. If BSY isn't
1815 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1816 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1817 *
1818 * Wait for two seconds. Devices attached to downstream port
1819 * which can't process the following IDENTIFY after this will
1820 * have to be reset again. For most cases, this should
1821 * suffice while making probing snappish enough.
1822 */
9dadd45b
TH		 1823 if (online) {
1824 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1825 ahci_check_ready);
1826 if (rc)
1827 ahci_kick_engine(ap, 0);
1828 }
9dadd45b 1829 return rc;
edc93052
TH		 1830}
1831
cc0680a5 1832static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1833{
cc0680a5 1834 struct ata_port *ap = link->ap;
4447d351 1835 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1836 u32 new_tmp, tmp;
1837
203c75b8 1838 ata_std_postreset(link, class);
02eaa666
JG		 1839
1840 /* Make sure port's ATAPI bit is set appropriately */
1841 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1842 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1843 new_tmp |= PORT_CMD_ATAPI;
1844 else
1845 new_tmp &= ~PORT_CMD_ATAPI;
1846 if (new_tmp != tmp) {
1847 writel(new_tmp, port_mmio + PORT_CMD);
1848 readl(port_mmio + PORT_CMD); /* flush */
1849 }
1da177e4
LT		 1850}
1851
12fad3f9 1852static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1853{
cedc9a47 1854 struct scatterlist *sg;
ff2aeb1e
TH		 1855 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1856 unsigned int si;
1da177e4
LT		 1857
1858 VPRINTK("ENTER\n");
1859
1860 /*
1861 * Next, the S/G list.
1862 */
ff2aeb1e 1863 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1864 dma_addr_t addr = sg_dma_address(sg);
1865 u32 sg_len = sg_dma_len(sg);
1866
ff2aeb1e
TH		 1867 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1868 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1869 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1870 }
828d09de 1871
ff2aeb1e 1872 return si;
1da177e4
LT		 1873}
1874
1875static void ahci_qc_prep(struct ata_queued_cmd *qc)
1876{
a0ea7328
JG		 1877 struct ata_port *ap = qc->ap;
1878 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1879 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1880 void *cmd_tbl;
1da177e4
LT		 1881 u32 opts;
1882 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1883 unsigned int n_elem;
1da177e4 1884
1da177e4
LT		 1885 /*
1886 * Fill in command table information. First, the header,
1887 * a SATA Register - Host to Device command FIS.
1888 */
12fad3f9
TH		 1889 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1890
7d50b60b 1891 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1892 if (is_atapi) {
12fad3f9
TH		 1893 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1894 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1895 }
1da177e4 1896
cc9278ed
TH		 1897 n_elem = 0;
1898 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1899 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1900
cc9278ed
TH		 1901 /*
1902 * Fill in command slot information.
1903 */
7d50b60b 1904 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1905 if (qc->tf.flags & ATA_TFLAG_WRITE)
1906 opts |= AHCI_CMD_WRITE;
1907 if (is_atapi)
4b10e559 1908 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1909
12fad3f9 1910 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1911}
1912
78cd52d0 1913static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1914{
417a1a6d 1915 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1916 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1917 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1918 struct ata_link *link = NULL;
1919 struct ata_queued_cmd *active_qc;
1920 struct ata_eh_info *active_ehi;
78cd52d0 1921 u32 serror;
1da177e4 1922
7d50b60b
TH		 1923 /* determine active link */
1924 ata_port_for_each_link(link, ap)
1925 if (ata_link_active(link))
1926 break;
1927 if (!link)
1928 link = &ap->link;
1929
1930 active_qc = ata_qc_from_tag(ap, link->active_tag);
1931 active_ehi = &link->eh_info;
1932
1933 /* record irq stat */
1934 ata_ehi_clear_desc(host_ehi);
1935 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1936
78cd52d0 1937 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1938 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1939 ahci_scr_write(ap, SCR_ERROR, serror);
7d50b60b 1940 host_ehi->serror |= serror;
78cd52d0 1941
41669553 1942 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1943 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1944 irq_stat &= ~PORT_IRQ_IF_ERR;
1945
55a61604 1946 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1947 /* If qc is active, charge it; otherwise, the active
1948 * link. There's no active qc on NCQ errors. It will
1949 * be determined by EH by reading log page 10h.
1950 */
1951 if (active_qc)
1952 active_qc->err_mask |= AC_ERR_DEV;
1953 else
1954 active_ehi->err_mask |= AC_ERR_DEV;
1955
417a1a6d 1956 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1957 host_ehi->serror &= ~SERR_INTERNAL;
1958 }
1959
1960 if (irq_stat & PORT_IRQ_UNK_FIS) {
1961 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1962
1963 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1964 active_ehi->action |= ATA_EH_RESET;
7d50b60b
TH		 1965 ata_ehi_push_desc(active_ehi,
1966 "unknown FIS %08x %08x %08x %08x" ,
1967 unk[0], unk[1], unk[2], unk[3]);
1968 }
1969
071f44b1 1970 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
7d50b60b 1971 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1972 active_ehi->action |= ATA_EH_RESET;
7d50b60b 1973 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1974 }
78cd52d0
TH		 1975
1976 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b 1977 host_ehi->err_mask |= AC_ERR_HOST_BUS;
cf480626 1978 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1979 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1980 }
1981
78cd52d0 1982 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b 1983 host_ehi->err_mask |= AC_ERR_ATA_BUS;
cf480626 1984 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1985 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1986 }
1da177e4 1987
78cd52d0 1988 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1989 ata_ehi_hotplugged(host_ehi);
1990 ata_ehi_push_desc(host_ehi, "%s",
1991 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1992 "connection status changed" : "PHY RDY changed");
1993 }
1994
78cd52d0 1995 /* okay, let's hand over to EH */
a72ec4ce 1996
78cd52d0
TH		 1997 if (irq_stat & PORT_IRQ_FREEZE)
1998 ata_port_freeze(ap);
1999 else
2000 ata_port_abort(ap);
1da177e4
LT		 2001}
2002
df69c9c5 2003static void ahci_port_intr(struct ata_port *ap)
1da177e4 2004{
350756f6 2005 void __iomem *port_mmio = ahci_port_base(ap);
9af5c9c9 2006 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 2007 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 2008 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 2009 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 2010 u32 status, qc_active;
459ad688 2011 int rc;
1da177e4
LT		 2012
2013 status = readl(port_mmio + PORT_IRQ_STAT);
2014 writel(status, port_mmio + PORT_IRQ_STAT);
2015
b06ce3e5
TH		 2016 /* ignore BAD_PMP while resetting */
2017 if (unlikely(resetting))
2018 status &= ~PORT_IRQ_BAD_PMP;
2019
31556594
KCA		 2020 /* If we are getting PhyRdy, this is
2021 * just a power state change, we should
2022 * clear out this, plus the PhyRdy/Comm
2023 * Wake bits from Serror
2024 */
2025 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2026 (status & PORT_IRQ_PHYRDY)) {
2027 status &= ~PORT_IRQ_PHYRDY;
2028 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
2029 }
2030
78cd52d0
TH		 2031 if (unlikely(status & PORT_IRQ_ERROR)) {
2032 ahci_error_intr(ap, status);
2033 return;
1da177e4
LT		 2034 }
2035
2f294968 2036 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 2037 /* If SNotification is available, leave notification
2038 * handling to sata_async_notification(). If not,
2039 * emulate it by snooping SDB FIS RX area.
2040 *
2041 * Snooping FIS RX area is probably cheaper than
2042 * poking SNotification but some constrollers which
2043 * implement SNotification, ICH9 for example, don't
2044 * store AN SDB FIS into receive area.
2f294968 2045 */
5f226c6b 2046 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 2047 sata_async_notification(ap);
5f226c6b
TH		 2048 else {
2049 /* If the 'N' bit in word 0 of the FIS is set,
2050 * we just received asynchronous notification.
2051 * Tell libata about it.
2052 */
2053 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2054 u32 f0 = le32_to_cpu(f[0]);
2055
2056 if (f0 & (1 << 15))
2057 sata_async_notification(ap);
2058 }
2f294968
KCA		 2059 }
2060
7d50b60b
TH		 2061 /* pp->active_link is valid iff any command is in flight */
2062 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 2063 qc_active = readl(port_mmio + PORT_SCR_ACT);
2064 else
2065 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2066
79f97dad 2067 rc = ata_qc_complete_multiple(ap, qc_active);
b06ce3e5 2068
459ad688
TH		 2069 /* while resetting, invalid completions are expected */
2070 if (unlikely(rc < 0 && !resetting)) {
12fad3f9 2071 ehi->err_mask |= AC_ERR_HSM;
cf480626 2072 ehi->action |= ATA_EH_RESET;
12fad3f9 2073 ata_port_freeze(ap);
1da177e4 2074 }
1da177e4
LT		 2075}
2076
7d12e780 2077static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 2078{
cca3974e 2079 struct ata_host *host = dev_instance;
1da177e4
LT		 2080 struct ahci_host_priv *hpriv;
2081 unsigned int i, handled = 0;
ea6ba10b 2082 void __iomem *mmio;
d28f87aa 2083 u32 irq_stat, irq_masked;
1da177e4
LT		 2084
2085 VPRINTK("ENTER\n");
2086
cca3974e 2087 hpriv = host->private_data;
0d5ff566 2088 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2089
2090 /* sigh. 0xffffffff is a valid return from h/w */
2091 irq_stat = readl(mmio + HOST_IRQ_STAT);
1da177e4
LT		 2092 if (!irq_stat)
2093 return IRQ_NONE;
2094
d28f87aa
TH		 2095 irq_masked = irq_stat & hpriv->port_map;
2096
2dcb407e 2097 spin_lock(&host->lock);
1da177e4 2098
2dcb407e 2099 for (i = 0; i < host->n_ports; i++) {
1da177e4 2100 struct ata_port *ap;
1da177e4 2101
d28f87aa 2102 if (!(irq_masked & (1 << i)))
67846b30
JG		 2103 continue;
2104
cca3974e 2105 ap = host->ports[i];
67846b30 2106 if (ap) {
df69c9c5 2107 ahci_port_intr(ap);
67846b30
JG		 2108 VPRINTK("port %u\n", i);
2109 } else {
2110 VPRINTK("port %u (no irq)\n", i);
6971ed1f 2111 if (ata_ratelimit())
cca3974e 2112 dev_printk(KERN_WARNING, host->dev,
a9524a76 2113 "interrupt on disabled port %u\n", i);
1da177e4 2114 }
67846b30 2115
1da177e4
LT		 2116 handled = 1;
2117 }
2118
d28f87aa
TH		 2119 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2120 * it should be cleared after all the port events are cleared;
2121 * otherwise, it will raise a spurious interrupt after each
2122 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2123 * information.
2124 *
2125 * Also, use the unmasked value to clear interrupt as spurious
2126 * pending event on a dummy port might cause screaming IRQ.
2127 */
ea0c62f7
TH		 2128 writel(irq_stat, mmio + HOST_IRQ_STAT);
2129
cca3974e 2130 spin_unlock(&host->lock);
1da177e4
LT		 2131
2132 VPRINTK("EXIT\n");
2133
2134 return IRQ_RETVAL(handled);
2135}
2136
9a3d9eb0 2137static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 2138{
2139 struct ata_port *ap = qc->ap;
4447d351 2140 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 2141 struct ahci_port_priv *pp = ap->private_data;
2142
2143 /* Keep track of the currently active link. It will be used
2144 * in completion path to determine whether NCQ phase is in
2145 * progress.
2146 */
2147 pp->active_link = qc->dev->link;
1da177e4 2148
12fad3f9
TH		 2149 if (qc->tf.protocol == ATA_PROT_NCQ)
2150 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2151 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4 2152
18f7ba4c
KCA		 2153 ahci_sw_activity(qc->dev->link);
2154
1da177e4
LT		 2155 return 0;
2156}
2157
4c9bf4e7
TH		 2158static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2159{
2160 struct ahci_port_priv *pp = qc->ap->private_data;
2161 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2162
2163 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2164 return true;
2165}
2166
78cd52d0
TH		 2167static void ahci_freeze(struct ata_port *ap)
2168{
4447d351 2169 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 2170
2171 /* turn IRQ off */
2172 writel(0, port_mmio + PORT_IRQ_MASK);
2173}
2174
2175static void ahci_thaw(struct ata_port *ap)
2176{
0d5ff566 2177 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 2178 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 2179 u32 tmp;
a7384925 2180 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 2181
2182 /* clear IRQ */
2183 tmp = readl(port_mmio + PORT_IRQ_STAT);
2184 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 2185 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 2186
1c954a4d
TH		 2187 /* turn IRQ back on */
2188 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 2189}
2190
2191static void ahci_error_handler(struct ata_port *ap)
2192{
b51e9e5d 2193 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 2194 /* restart engine */
4447d351
TH		 2195 ahci_stop_engine(ap);
2196 ahci_start_engine(ap);
78cd52d0
TH		 2197 }
2198
a1efdaba 2199 sata_pmp_error_handler(ap);
edc93052
TH		 2200}
2201
78cd52d0
TH		 2202static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2203{
2204 struct ata_port *ap = qc->ap;
2205
d2e75dff
TH		 2206 /* make DMA engine forget about the failed command */
2207 if (qc->flags & ATA_QCFLAG_FAILED)
2208 ahci_kick_engine(ap, 1);
78cd52d0
TH		 2209}
2210
7d50b60b
TH		 2211static void ahci_pmp_attach(struct ata_port *ap)
2212{
2213 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2214 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2215 u32 cmd;
2216
2217 cmd = readl(port_mmio + PORT_CMD);
2218 cmd |= PORT_CMD_PMP;
2219 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2220
2221 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2222 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2223}
2224
2225static void ahci_pmp_detach(struct ata_port *ap)
2226{
2227 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2228 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2229 u32 cmd;
2230
2231 cmd = readl(port_mmio + PORT_CMD);
2232 cmd &= ~PORT_CMD_PMP;
2233 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2234
2235 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2236 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2237}
2238
028a2596
AD		 2239static int ahci_port_resume(struct ata_port *ap)
2240{
2241 ahci_power_up(ap);
2242 ahci_start_port(ap);
2243
071f44b1 2244 if (sata_pmp_attached(ap))
7d50b60b
TH		 2245 ahci_pmp_attach(ap);
2246 else
2247 ahci_pmp_detach(ap);
2248
028a2596
AD		 2249 return 0;
2250}
2251
438ac6d5 2252#ifdef CONFIG_PM
c1332875
TH		 2253static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2254{
c1332875
TH		 2255 const char *emsg = NULL;
2256 int rc;
2257
4447d351 2258 rc = ahci_deinit_port(ap, &emsg);
8e16f941 2259 if (rc == 0)
4447d351 2260 ahci_power_down(ap);
8e16f941 2261 else {
c1332875 2262 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 2263 ahci_start_port(ap);
c1332875
TH		 2264 }
2265
2266 return rc;
2267}
2268
c1332875
TH		 2269static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2270{
cca3974e 2271 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 2272 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 2273 u32 ctl;
2274
3a2d5b70 2275 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 2276 /* AHCI spec rev1.1 section 8.3.3:
2277 * Software must disable interrupts prior to requesting a
2278 * transition of the HBA to D3 state.
2279 */
2280 ctl = readl(mmio + HOST_CTL);
2281 ctl &= ~HOST_IRQ_EN;
2282 writel(ctl, mmio + HOST_CTL);
2283 readl(mmio + HOST_CTL); /* flush */
2284 }
2285
2286 return ata_pci_device_suspend(pdev, mesg);
2287}
2288
2289static int ahci_pci_device_resume(struct pci_dev *pdev)
2290{
cca3974e 2291 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 2292 int rc;
2293
553c4aa6
TH		 2294 rc = ata_pci_device_do_resume(pdev);
2295 if (rc)
2296 return rc;
c1332875
TH		 2297
2298 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2299 rc = ahci_reset_controller(host);
c1332875
TH		 2300 if (rc)
2301 return rc;
2302
4447d351 2303 ahci_init_controller(host);
c1332875
TH		 2304 }
2305
cca3974e 2306 ata_host_resume(host);
c1332875
TH		 2307
2308 return 0;
2309}
438ac6d5 2310#endif
c1332875 2311
254950cd
TH		 2312static int ahci_port_start(struct ata_port *ap)
2313{
cca3974e 2314 struct device *dev = ap->host->dev;
254950cd 2315 struct ahci_port_priv *pp;
254950cd
TH		 2316 void *mem;
2317 dma_addr_t mem_dma;
254950cd 2318
24dc5f33 2319 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2320 if (!pp)
2321 return -ENOMEM;
254950cd 2322
24dc5f33
TH		 2323 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2324 GFP_KERNEL);
2325 if (!mem)
254950cd 2326 return -ENOMEM;
254950cd
TH		 2327 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2328
2329 /*
2330 * First item in chunk of DMA memory: 32-slot command table,
2331 * 32 bytes each in size
2332 */
2333 pp->cmd_slot = mem;
2334 pp->cmd_slot_dma = mem_dma;
2335
2336 mem += AHCI_CMD_SLOT_SZ;
2337 mem_dma += AHCI_CMD_SLOT_SZ;
2338
2339 /*
2340 * Second item: Received-FIS area
2341 */
2342 pp->rx_fis = mem;
2343 pp->rx_fis_dma = mem_dma;
2344
2345 mem += AHCI_RX_FIS_SZ;
2346 mem_dma += AHCI_RX_FIS_SZ;
2347
2348 /*
2349 * Third item: data area for storing a single command
2350 * and its scatter-gather table
2351 */
2352 pp->cmd_tbl = mem;
2353 pp->cmd_tbl_dma = mem_dma;
2354
a7384925 2355 /*
2dcb407e
JG		 2356 * Save off initial list of interrupts to be enabled.
2357 * This could be changed later
2358 */
a7384925
KCA		 2359 pp->intr_mask = DEF_PORT_IRQ;
2360
254950cd
TH		 2361 ap->private_data = pp;
2362
df69c9c5
JG		 2363 /* engage engines, captain */
2364 return ahci_port_resume(ap);
254950cd
TH		 2365}
2366
2367static void ahci_port_stop(struct ata_port *ap)
2368{
0be0aa98
TH		 2369 const char *emsg = NULL;
2370 int rc;
254950cd 2371
0be0aa98 2372 /* de-initialize port */
4447d351 2373 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2374 if (rc)
2375 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2376}
2377
4447d351 2378static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2379{
1da177e4 2380 int rc;
1da177e4 2381
1da177e4
LT		 2382 if (using_dac &&
2383 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2384 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2385 if (rc) {
2386 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2387 if (rc) {
a9524a76
JG		 2388 dev_printk(KERN_ERR, &pdev->dev,
2389 "64-bit DMA enable failed\n");
1da177e4
LT		 2390 return rc;
2391 }
2392 }
1da177e4
LT		 2393 } else {
2394 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2395 if (rc) {
a9524a76
JG		 2396 dev_printk(KERN_ERR, &pdev->dev,
2397 "32-bit DMA enable failed\n");
1da177e4
LT		 2398 return rc;
2399 }
2400 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2401 if (rc) {
a9524a76
JG		 2402 dev_printk(KERN_ERR, &pdev->dev,
2403 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2404 return rc;
2405 }
2406 }
1da177e4
LT		 2407 return 0;
2408}
2409
4447d351 2410static void ahci_print_info(struct ata_host *host)
1da177e4 2411{
4447d351
TH		 2412 struct ahci_host_priv *hpriv = host->private_data;
2413 struct pci_dev *pdev = to_pci_dev(host->dev);
2414 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2415 u32 vers, cap, impl, speed;
2416 const char *speed_s;
2417 u16 cc;
2418 const char *scc_s;
2419
2420 vers = readl(mmio + HOST_VERSION);
2421 cap = hpriv->cap;
2422 impl = hpriv->port_map;
2423
2424 speed = (cap >> 20) & 0xf;
2425 if (speed == 1)
2426 speed_s = "1.5";
2427 else if (speed == 2)
2428 speed_s = "3";
2429 else
2430 speed_s = "?";
2431
2432 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2433 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2434 scc_s = "IDE";
c9f89475 2435 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2436 scc_s = "SATA";
c9f89475 2437 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2438 scc_s = "RAID";
2439 else
2440 scc_s = "unknown";
2441
a9524a76
JG		 2442 dev_printk(KERN_INFO, &pdev->dev,
2443 "AHCI %02x%02x.%02x%02x "
1da177e4 2444 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2445 ,
1da177e4 2446
2dcb407e
JG		 2447 (vers >> 24) & 0xff,
2448 (vers >> 16) & 0xff,
2449 (vers >> 8) & 0xff,
2450 vers & 0xff,
1da177e4
LT		 2451
2452 ((cap >> 8) & 0x1f) + 1,
2453 (cap & 0x1f) + 1,
2454 speed_s,
2455 impl,
2456 scc_s);
2457
a9524a76
JG		 2458 dev_printk(KERN_INFO, &pdev->dev,
2459 "flags: "
203ef6c4 2460 "%s%s%s%s%s%s%s"
18f7ba4c
KCA		 2461 "%s%s%s%s%s%s%s"
2462 "%s\n"
2dcb407e 2463 ,
1da177e4
LT		 2464
2465 cap & (1 << 31) ? "64bit " : "",
2466 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2467 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2468 cap & (1 << 28) ? "ilck " : "",
2469 cap & (1 << 27) ? "stag " : "",
2470 cap & (1 << 26) ? "pm " : "",
2471 cap & (1 << 25) ? "led " : "",
2472
2473 cap & (1 << 24) ? "clo " : "",
2474 cap & (1 << 19) ? "nz " : "",
2475 cap & (1 << 18) ? "only " : "",
2476 cap & (1 << 17) ? "pmp " : "",
2477 cap & (1 << 15) ? "pio " : "",
2478 cap & (1 << 14) ? "slum " : "",
18f7ba4c
KCA		 2479 cap & (1 << 13) ? "part " : "",
2480 cap & (1 << 6) ? "ems ": ""
1da177e4
LT		 2481 );
2482}
2483
edc93052
TH		 2484/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2485 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2486 * support PMP and the 4726 either directly exports the device
2487 * attached to the first downstream port or acts as a hardware storage
2488 * controller and emulate a single ATA device (can be RAID 0/1 or some
2489 * other configuration).
2490 *
2491 * When there's no device attached to the first downstream port of the
2492 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2493 * configure the 4726. However, ATA emulation of the device is very
2494 * lame. It doesn't send signature D2H Reg FIS after the initial
2495 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2496 *
2497 * The following function works around the problem by always using
2498 * hardreset on the port and not depending on receiving signature FIS
2499 * afterward. If signature FIS isn't received soon, ATA class is
2500 * assumed without follow-up softreset.
2501 */
2502static void ahci_p5wdh_workaround(struct ata_host *host)
2503{
2504 static struct dmi_system_id sysids[] = {
2505 {
2506 .ident = "P5W DH Deluxe",
2507 .matches = {
2508 DMI_MATCH(DMI_SYS_VENDOR,
2509 "ASUSTEK COMPUTER INC"),
2510 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2511 },
2512 },
2513 { }
2514 };
2515 struct pci_dev *pdev = to_pci_dev(host->dev);
2516
2517 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2518 dmi_check_system(sysids)) {
2519 struct ata_port *ap = host->ports[1];
2520
2521 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2522 "Deluxe on-board SIMG4726 workaround\n");
2523
2524 ap->ops = &ahci_p5wdh_ops;
2525 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2526 }
2527}
2528
24dc5f33 2529static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2530{
2531 static int printed_version;
e297d99e
TH		 2532 unsigned int board_id = ent->driver_data;
2533 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 2534 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2535 struct device *dev = &pdev->dev;
1da177e4 2536 struct ahci_host_priv *hpriv;
4447d351 2537 struct ata_host *host;
837f5f8f 2538 int n_ports, i, rc;
1da177e4
LT		 2539
2540 VPRINTK("ENTER\n");
2541
12fad3f9
TH		 2542 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2543
1da177e4 2544 if (!printed_version++)
a9524a76 2545 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2546
5b66c829
AC		 2547 /* The AHCI driver can only drive the SATA ports, the PATA driver
2548 can drive them all so if both drivers are selected make sure
2549 AHCI stays out of the way */
2550 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2551 return -ENODEV;
2552
4447d351 2553 /* acquire resources */
24dc5f33 2554 rc = pcim_enable_device(pdev);
1da177e4
LT		 2555 if (rc)
2556 return rc;
2557
dea55137
TH		 2558 /* AHCI controllers often implement SFF compatible interface.
2559 * Grab all PCI BARs just in case.
2560 */
2561 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 2562 if (rc == -EBUSY)
24dc5f33 2563 pcim_pin_device(pdev);
0d5ff566 2564 if (rc)
24dc5f33 2565 return rc;
1da177e4 2566
c4f7792c
TH		 2567 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2568 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2569 u8 map;
2570
2571 /* ICH6s share the same PCI ID for both piix and ahci
2572 * modes. Enabling ahci mode while MAP indicates
2573 * combined mode is a bad idea. Yield to ata_piix.
2574 */
2575 pci_read_config_byte(pdev, ICH_MAP, &map);
2576 if (map & 0x3) {
2577 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2578 "combined mode, can't enable AHCI mode\n");
2579 return -ENODEV;
2580 }
2581 }
2582
24dc5f33
TH		 2583 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2584 if (!hpriv)
2585 return -ENOMEM;
417a1a6d
TH		 2586 hpriv->flags |= (unsigned long)pi.private_data;
2587
e297d99e
TH		 2588 /* MCP65 revision A1 and A2 can't do MSI */
2589 if (board_id == board_ahci_mcp65 &&
2590 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2591 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2592
417a1a6d
TH		 2593 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2594 pci_intx(pdev, 1);
1da177e4 2595
4447d351 2596 /* save initial config */
417a1a6d 2597 ahci_save_initial_config(pdev, hpriv);
1da177e4 2598
4447d351 2599 /* prepare host */
274c1fde 2600 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2601 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2602
7d50b60b
TH		 2603 if (hpriv->cap & HOST_CAP_PMP)
2604 pi.flags |= ATA_FLAG_PMP;
2605
18f7ba4c
KCA		 2606 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2607 u8 messages;
2608 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2609 u32 em_loc = readl(mmio + HOST_EM_LOC);
2610 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2611
2612 messages = (em_ctl & 0x000f0000) >> 16;
2613
2614 /* we only support LED message type right now */
2615 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2616 /* store em_loc */
2617 hpriv->em_loc = ((em_loc >> 16) * 4);
2618 pi.flags |= ATA_FLAG_EM;
2619 if (!(em_ctl & EM_CTL_ALHD))
2620 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2621 }
2622 }
2623
837f5f8f
TH		 2624 /* CAP.NP sometimes indicate the index of the last enabled
2625 * port, at other times, that of the last possible port, so
2626 * determining the maximum port number requires looking at
2627 * both CAP.NP and port_map.
2628 */
2629 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2630
2631 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2632 if (!host)
2633 return -ENOMEM;
2634 host->iomap = pcim_iomap_table(pdev);
2635 host->private_data = hpriv;
2636
18f7ba4c
KCA		 2637 if (pi.flags & ATA_FLAG_EM)
2638 ahci_reset_em(host);
2639
4447d351 2640 for (i = 0; i < host->n_ports; i++) {
dab632e8 2641 struct ata_port *ap = host->ports[i];
4447d351 2642
cbcdd875
TH		 2643 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2644 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2645 0x100 + ap->port_no * 0x80, "port");
2646
31556594
KCA		 2647 /* set initial link pm policy */
2648 ap->pm_policy = NOT_AVAILABLE;
2649
18f7ba4c
KCA		 2650 /* set enclosure management message type */
2651 if (ap->flags & ATA_FLAG_EM)
2652 ap->em_message_type = ahci_em_messages;
2653
2654
dab632e8 2655 /* disabled/not-implemented port */
350756f6 2656 if (!(hpriv->port_map & (1 << i)))
dab632e8 2657 ap->ops = &ata_dummy_port_ops;
4447d351 2658 }
d447df14 2659
edc93052
TH		 2660 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2661 ahci_p5wdh_workaround(host);
2662
4447d351
TH		 2663 /* initialize adapter */
2664 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2665 if (rc)
24dc5f33 2666 return rc;
1da177e4 2667
4447d351
TH		 2668 rc = ahci_reset_controller(host);
2669 if (rc)
2670 return rc;
1da177e4 2671
4447d351
TH		 2672 ahci_init_controller(host);
2673 ahci_print_info(host);
1da177e4 2674
4447d351
TH		 2675 pci_set_master(pdev);
2676 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2677 &ahci_sht);
907f4678 2678}
1da177e4
LT		 2679
2680static int __init ahci_init(void)
2681{
b7887196 2682 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2683}
2684
1da177e4
LT		 2685static void __exit ahci_exit(void)
2686{
2687 pci_unregister_driver(&ahci_pci_driver);
2688}
2689
2690
2691MODULE_AUTHOR("Jeff Garzik");
2692MODULE_DESCRIPTION("AHCI SATA low-level driver");
2693MODULE_LICENSE("GPL");
2694MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2695MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2696
2697module_init(ahci_init);
2698module_exit(ahci_exit);
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