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i915: fix AR register restore.
[net-next-2.6.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
31556594
KCA		 52static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54static void ahci_disable_alpm(struct ata_port *ap);
1da177e4
LT		 55
56enum {
57 AHCI_PCI_BAR = 5,
648a88be 58 AHCI_MAX_PORTS = 32,
1da177e4
LT		 59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
be5d8218 61 AHCI_USE_CLUSTERING = 1,
12fad3f9 62 AHCI_MAX_CMDS = 32,
dd410ff1 63 AHCI_CMD_SZ = 32,
12fad3f9 64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 65 AHCI_RX_FIS_SZ = 256,
a0ea7328 66 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 67 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 71 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
4b10e559 75 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 76 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 78
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 82
83 board_ahci = 0,
7a234aff
TH		 84 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
1da177e4
LT		 88
89 /* global controller registers */
90 HOST_CAP = 0x00, /* host capabilities */
91 HOST_CTL = 0x04, /* global host control */
92 HOST_IRQ_STAT = 0x08, /* interrupt status */
93 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
94 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
95
96 /* HOST_CTL bits */
97 HOST_RESET = (1 << 0), /* reset controller; self-clear */
98 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
99 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
100
101 /* HOST_CAP bits */
0be0aa98 102 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 103 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 104 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 105 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 106 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 107 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 108 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 109 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 110
111 /* registers for each SATA port */
112 PORT_LST_ADDR = 0x00, /* command list DMA addr */
113 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
114 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
115 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
116 PORT_IRQ_STAT = 0x10, /* interrupt status */
117 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
118 PORT_CMD = 0x18, /* port command */
119 PORT_TFDATA = 0x20, /* taskfile data */
120 PORT_SIG = 0x24, /* device TF signature */
121 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 122 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
123 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
124 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
125 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 126 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 127
128 /* PORT_IRQ_{STAT,MASK} bits */
129 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
130 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
131 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
132 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
133 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
134 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
135 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
136 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
137
138 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
139 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
140 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
141 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
142 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
143 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
144 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
145 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
146 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
147
78cd52d0
TH		 148 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
149 PORT_IRQ_IF_ERR |
150 PORT_IRQ_CONNECT |
4296971d 151 PORT_IRQ_PHYRDY |
7d50b60b
TH		 152 PORT_IRQ_UNK_FIS |
153 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 154 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
155 PORT_IRQ_TF_ERR |
156 PORT_IRQ_HBUS_DATA_ERR,
157 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
158 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
159 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 160
161 /* PORT_CMD bits */
31556594
KCA		 162 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
163 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 164 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 165 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 166 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
167 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
168 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 169 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 170 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
171 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
172 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
173
0be0aa98 174 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 175 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
176 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
177 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 178
417a1a6d
TH		 179 /* hpriv->flags bits */
180 AHCI_HFLAG_NO_NCQ = (1 << 0),
181 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
182 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
183 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
184 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
185 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 186 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 187 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
417a1a6d 188
bf2af2a2 189 /* ap->flags bits */
1188c0d8
TH		 190
191 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
192 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 193 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
194 ATA_FLAG_IPM,
0c88758b 195 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
c4f7792c
TH		 196
197 ICH_MAP = 0x90, /* ICH MAP register */
1da177e4
LT		 198};
199
200struct ahci_cmd_hdr {
4ca4e439
AV		 201 __le32 opts;
202 __le32 status;
203 __le32 tbl_addr;
204 __le32 tbl_addr_hi;
205 __le32 reserved[4];
1da177e4
LT		 206};
207
208struct ahci_sg {
4ca4e439
AV		 209 __le32 addr;
210 __le32 addr_hi;
211 __le32 reserved;
212 __le32 flags_size;
1da177e4
LT		 213};
214
215struct ahci_host_priv {
417a1a6d 216 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 217 u32 cap; /* cap to use */
218 u32 port_map; /* port map to use */
219 u32 saved_cap; /* saved initial cap */
220 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 221};
222
223struct ahci_port_priv {
7d50b60b 224 struct ata_link *active_link;
1da177e4
LT		 225 struct ahci_cmd_hdr *cmd_slot;
226 dma_addr_t cmd_slot_dma;
227 void *cmd_tbl;
228 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 229 void *rx_fis;
230 dma_addr_t rx_fis_dma;
0291f95f 231 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 232 unsigned int ncq_saw_d2h:1;
233 unsigned int ncq_saw_dmas:1;
afb2d552 234 unsigned int ncq_saw_sdb:1;
a7384925 235 u32 intr_mask; /* interrupts to enable */
1da177e4
LT		 236};
237
da3dbb17
TH		 238static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
239static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
2dcb407e 240static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 241static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 242static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 243static int ahci_port_start(struct ata_port *ap);
244static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 245static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
246static void ahci_qc_prep(struct ata_queued_cmd *qc);
247static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 248static void ahci_freeze(struct ata_port *ap);
249static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 250static void ahci_pmp_attach(struct ata_port *ap);
251static void ahci_pmp_detach(struct ata_port *ap);
78cd52d0 252static void ahci_error_handler(struct ata_port *ap);
ad616ffb 253static void ahci_vt8251_error_handler(struct ata_port *ap);
edc93052 254static void ahci_p5wdh_error_handler(struct ata_port *ap);
78cd52d0 255static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 256static int ahci_port_resume(struct ata_port *ap);
dab632e8
JG		 257static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
258static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
259 u32 opts);
438ac6d5 260#ifdef CONFIG_PM
c1332875 261static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 262static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
263static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 264#endif
1da177e4 265
31556594
KCA		 266static struct class_device_attribute *ahci_shost_attrs[] = {
267 &class_device_attr_link_power_management_policy,
268 NULL
269};
270
193515d5 271static struct scsi_host_template ahci_sht = {
1da177e4
LT		 272 .module = THIS_MODULE,
273 .name = DRV_NAME,
274 .ioctl = ata_scsi_ioctl,
275 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 276 .change_queue_depth = ata_scsi_change_queue_depth,
277 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 278 .this_id = ATA_SHT_THIS_ID,
279 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 280 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
281 .emulated = ATA_SHT_EMULATED,
282 .use_clustering = AHCI_USE_CLUSTERING,
283 .proc_name = DRV_NAME,
284 .dma_boundary = AHCI_DMA_BOUNDARY,
285 .slave_configure = ata_scsi_slave_config,
ccf68c34 286 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 287 .bios_param = ata_std_bios_param,
31556594 288 .shost_attrs = ahci_shost_attrs,
1da177e4
LT		 289};
290
057ace5e 291static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 292 .check_status = ahci_check_status,
293 .check_altstatus = ahci_check_status,
1da177e4
LT		 294 .dev_select = ata_noop_dev_select,
295
296 .tf_read = ahci_tf_read,
297
7d50b60b 298 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 299 .qc_prep = ahci_qc_prep,
300 .qc_issue = ahci_qc_issue,
301
1da177e4
LT		 302 .irq_clear = ahci_irq_clear,
303
304 .scr_read = ahci_scr_read,
305 .scr_write = ahci_scr_write,
306
78cd52d0
TH		 307 .freeze = ahci_freeze,
308 .thaw = ahci_thaw,
309
310 .error_handler = ahci_error_handler,
311 .post_internal_cmd = ahci_post_internal_cmd,
312
7d50b60b
TH		 313 .pmp_attach = ahci_pmp_attach,
314 .pmp_detach = ahci_pmp_detach,
7d50b60b 315
438ac6d5 316#ifdef CONFIG_PM
c1332875
TH		 317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
438ac6d5 319#endif
31556594
KCA		 320 .enable_pm = ahci_enable_alpm,
321 .disable_pm = ahci_disable_alpm,
c1332875 322
1da177e4
LT		 323 .port_start = ahci_port_start,
324 .port_stop = ahci_port_stop,
1da177e4
LT		 325};
326
ad616ffb 327static const struct ata_port_operations ahci_vt8251_ops = {
ad616ffb
TH		 328 .check_status = ahci_check_status,
329 .check_altstatus = ahci_check_status,
330 .dev_select = ata_noop_dev_select,
331
332 .tf_read = ahci_tf_read,
333
7d50b60b 334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
ad616ffb
TH		 335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
337
ad616ffb
TH		 338 .irq_clear = ahci_irq_clear,
339
340 .scr_read = ahci_scr_read,
341 .scr_write = ahci_scr_write,
342
343 .freeze = ahci_freeze,
344 .thaw = ahci_thaw,
345
346 .error_handler = ahci_vt8251_error_handler,
347 .post_internal_cmd = ahci_post_internal_cmd,
348
7d50b60b
TH		 349 .pmp_attach = ahci_pmp_attach,
350 .pmp_detach = ahci_pmp_detach,
7d50b60b 351
438ac6d5 352#ifdef CONFIG_PM
ad616ffb
TH		 353 .port_suspend = ahci_port_suspend,
354 .port_resume = ahci_port_resume,
438ac6d5 355#endif
ad616ffb
TH		 356
357 .port_start = ahci_port_start,
358 .port_stop = ahci_port_stop,
359};
360
edc93052
TH		 361static const struct ata_port_operations ahci_p5wdh_ops = {
362 .check_status = ahci_check_status,
363 .check_altstatus = ahci_check_status,
364 .dev_select = ata_noop_dev_select,
365
366 .tf_read = ahci_tf_read,
367
368 .qc_defer = sata_pmp_qc_defer_cmd_switch,
369 .qc_prep = ahci_qc_prep,
370 .qc_issue = ahci_qc_issue,
371
372 .irq_clear = ahci_irq_clear,
373
374 .scr_read = ahci_scr_read,
375 .scr_write = ahci_scr_write,
376
377 .freeze = ahci_freeze,
378 .thaw = ahci_thaw,
379
380 .error_handler = ahci_p5wdh_error_handler,
381 .post_internal_cmd = ahci_post_internal_cmd,
382
383 .pmp_attach = ahci_pmp_attach,
384 .pmp_detach = ahci_pmp_detach,
385
386#ifdef CONFIG_PM
387 .port_suspend = ahci_port_suspend,
388 .port_resume = ahci_port_resume,
389#endif
390
391 .port_start = ahci_port_start,
392 .port_stop = ahci_port_stop,
393};
394
417a1a6d
TH		 395#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
396
98ac62de 397static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 398 /* board_ahci */
399 {
1188c0d8 400 .flags = AHCI_FLAG_COMMON,
0c88758b 401 .link_flags = AHCI_LFLAG_COMMON,
7da79312 402 .pio_mask = 0x1f, /* pio0-4 */
469248ab 403 .udma_mask = ATA_UDMA6,
1da177e4
LT		 404 .port_ops = &ahci_ops,
405 },
bf2af2a2
BJ		 406 /* board_ahci_vt8251 */
407 {
6949b914 408 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 409 .flags = AHCI_FLAG_COMMON,
0c88758b 410 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
bf2af2a2 411 .pio_mask = 0x1f, /* pio0-4 */
469248ab 412 .udma_mask = ATA_UDMA6,
ad616ffb 413 .port_ops = &ahci_vt8251_ops,
bf2af2a2 414 },
41669553
TH		 415 /* board_ahci_ign_iferr */
416 {
417a1a6d
TH		 417 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
418 .flags = AHCI_FLAG_COMMON,
0c88758b 419 .link_flags = AHCI_LFLAG_COMMON,
41669553 420 .pio_mask = 0x1f, /* pio0-4 */
469248ab 421 .udma_mask = ATA_UDMA6,
41669553
TH		 422 .port_ops = &ahci_ops,
423 },
55a61604
CH		 424 /* board_ahci_sb600 */
425 {
417a1a6d 426 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
6949b914 427 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
417a1a6d 428 .flags = AHCI_FLAG_COMMON,
0c88758b 429 .link_flags = AHCI_LFLAG_COMMON,
55a61604 430 .pio_mask = 0x1f, /* pio0-4 */
469248ab 431 .udma_mask = ATA_UDMA6,
55a61604
CH		 432 .port_ops = &ahci_ops,
433 },
cd70c266
JG		 434 /* board_ahci_mv */
435 {
417a1a6d
TH		 436 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
437 AHCI_HFLAG_MV_PATA),
cd70c266 438 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 439 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
0c88758b 440 .link_flags = AHCI_LFLAG_COMMON,
cd70c266
JG		 441 .pio_mask = 0x1f, /* pio0-4 */
442 .udma_mask = ATA_UDMA6,
443 .port_ops = &ahci_ops,
444 },
1da177e4
LT		 445};
446
3b7d697d 447static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 448 /* Intel */
54bb3a94
JG		 449 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
450 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
451 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
452 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
453 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 454 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 455 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
456 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
457 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
458 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 459 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
460 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
461 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
462 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
463 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
464 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
465 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
466 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
467 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
468 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
469 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
470 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
471 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
472 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
473 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
474 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 476 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
477 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9
JG		 478 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
479 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
fe7fa31a 480
e34bb370
TH		 481 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
482 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
483 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 484
485 /* ATI */
c65ec1c2 486 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
c69c0892 487 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
488 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
489 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
490 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
491 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
492 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
fe7fa31a
JG		 493
494 /* VIA */
54bb3a94 495 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 496 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 497
498 /* NVIDIA */
54bb3a94
JG		 499 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
500 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
501 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
502 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 503 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
504 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
505 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
506 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
507 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
508 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
509 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
510 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 511 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
512 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
513 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
514 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
515 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
516 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
517 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
518 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 519 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 543 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 547 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
554 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
fe7fa31a 555
95916edd 556 /* SiS */
54bb3a94
JG		 557 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
558 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
559 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 560
cd70c266
JG		 561 /* Marvell */
562 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
563
415ae2b5
JG		 564 /* Generic, PCI class code for AHCI */
565 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 566 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 567
1da177e4
LT		 568 { } /* terminate list */
569};
570
571
572static struct pci_driver ahci_pci_driver = {
573 .name = DRV_NAME,
574 .id_table = ahci_pci_tbl,
575 .probe = ahci_init_one,
24dc5f33 576 .remove = ata_pci_remove_one,
438ac6d5 577#ifdef CONFIG_PM
c1332875
TH		 578 .suspend = ahci_pci_device_suspend,
579 .resume = ahci_pci_device_resume,
438ac6d5 580#endif
1da177e4
LT		 581};
582
583
98fa4b60
TH		 584static inline int ahci_nr_ports(u32 cap)
585{
586 return (cap & 0x1f) + 1;
587}
588
dab632e8
JG		 589static inline void __iomem *__ahci_port_base(struct ata_host *host,
590 unsigned int port_no)
1da177e4 591{
dab632e8 592 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 593
dab632e8
JG		 594 return mmio + 0x100 + (port_no * 0x80);
595}
596
597static inline void __iomem *ahci_port_base(struct ata_port *ap)
598{
599 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 600}
601
b710a1f4
TH		 602static void ahci_enable_ahci(void __iomem *mmio)
603{
604 u32 tmp;
605
606 /* turn on AHCI_EN */
607 tmp = readl(mmio + HOST_CTL);
608 if (!(tmp & HOST_AHCI_EN)) {
609 tmp |= HOST_AHCI_EN;
610 writel(tmp, mmio + HOST_CTL);
611 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
612 WARN_ON(!(tmp & HOST_AHCI_EN));
613 }
614}
615
d447df14
TH		 616/**
617 * ahci_save_initial_config - Save and fixup initial config values
4447d351 618 * @pdev: target PCI device
4447d351 619 * @hpriv: host private area to store config values
d447df14
TH		 620 *
621 * Some registers containing configuration info might be setup by
622 * BIOS and might be cleared on reset. This function saves the
623 * initial values of those registers into @hpriv such that they
624 * can be restored after controller reset.
625 *
626 * If inconsistent, config values are fixed up by this function.
627 *
628 * LOCKING:
629 * None.
630 */
4447d351 631static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 632 struct ahci_host_priv *hpriv)
d447df14 633{
4447d351 634 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 635 u32 cap, port_map;
17199b18 636 int i;
d447df14 637
b710a1f4
TH		 638 /* make sure AHCI mode is enabled before accessing CAP */
639 ahci_enable_ahci(mmio);
640
d447df14
TH		 641 /* Values prefixed with saved_ are written back to host after
642 * reset. Values without are used for driver operation.
643 */
644 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
645 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
646
274c1fde 647 /* some chips have errata preventing 64bit use */
417a1a6d 648 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 649 dev_printk(KERN_INFO, &pdev->dev,
650 "controller can't do 64bit DMA, forcing 32bit\n");
651 cap &= ~HOST_CAP_64;
652 }
653
417a1a6d 654 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 655 dev_printk(KERN_INFO, &pdev->dev,
656 "controller can't do NCQ, turning off CAP_NCQ\n");
657 cap &= ~HOST_CAP_NCQ;
658 }
659
6949b914
TH		 660 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
661 dev_printk(KERN_INFO, &pdev->dev,
662 "controller can't do PMP, turning off CAP_PMP\n");
663 cap &= ~HOST_CAP_PMP;
664 }
665
cd70c266
JG		 666 /*
667 * Temporary Marvell 6145 hack: PATA port presence
668 * is asserted through the standard AHCI port
669 * presence register, as bit 4 (counting from 0)
670 */
417a1a6d 671 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
cd70c266
JG		 672 dev_printk(KERN_ERR, &pdev->dev,
673 "MV_AHCI HACK: port_map %x -> %x\n",
674 hpriv->port_map,
675 hpriv->port_map & 0xf);
676
677 port_map &= 0xf;
678 }
679
17199b18 680 /* cross check port_map and cap.n_ports */
7a234aff 681 if (port_map) {
837f5f8f 682 int map_ports = 0;
17199b18 683
837f5f8f
TH		 684 for (i = 0; i < AHCI_MAX_PORTS; i++)
685 if (port_map & (1 << i))
686 map_ports++;
17199b18 687
837f5f8f
TH		 688 /* If PI has more ports than n_ports, whine, clear
689 * port_map and let it be generated from n_ports.
17199b18 690 */
837f5f8f 691 if (map_ports > ahci_nr_ports(cap)) {
4447d351 692 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 693 "implemented port map (0x%x) contains more "
694 "ports than nr_ports (%u), using nr_ports\n",
695 port_map, ahci_nr_ports(cap));
7a234aff
TH		 696 port_map = 0;
697 }
698 }
699
700 /* fabricate port_map from cap.nr_ports */
701 if (!port_map) {
17199b18 702 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 703 dev_printk(KERN_WARNING, &pdev->dev,
704 "forcing PORTS_IMPL to 0x%x\n", port_map);
705
706 /* write the fixed up value to the PI register */
707 hpriv->saved_port_map = port_map;
17199b18
TH		 708 }
709
d447df14
TH		 710 /* record values to use during operation */
711 hpriv->cap = cap;
712 hpriv->port_map = port_map;
713}
714
715/**
716 * ahci_restore_initial_config - Restore initial config
4447d351 717 * @host: target ATA host
d447df14
TH		 718 *
719 * Restore initial config stored by ahci_save_initial_config().
720 *
721 * LOCKING:
722 * None.
723 */
4447d351 724static void ahci_restore_initial_config(struct ata_host *host)
d447df14 725{
4447d351
TH		 726 struct ahci_host_priv *hpriv = host->private_data;
727 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
728
d447df14
TH		 729 writel(hpriv->saved_cap, mmio + HOST_CAP);
730 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
731 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
732}
733
203ef6c4 734static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 735{
203ef6c4
TH		 736 static const int offset[] = {
737 [SCR_STATUS] = PORT_SCR_STAT,
738 [SCR_CONTROL] = PORT_SCR_CTL,
739 [SCR_ERROR] = PORT_SCR_ERR,
740 [SCR_ACTIVE] = PORT_SCR_ACT,
741 [SCR_NOTIFICATION] = PORT_SCR_NTF,
742 };
743 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 744
203ef6c4
TH		 745 if (sc_reg < ARRAY_SIZE(offset) &&
746 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
747 return offset[sc_reg];
da3dbb17 748 return 0;
1da177e4
LT		 749}
750
203ef6c4 751static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 752{
203ef6c4
TH		 753 void __iomem *port_mmio = ahci_port_base(ap);
754 int offset = ahci_scr_offset(ap, sc_reg);
755
756 if (offset) {
757 *val = readl(port_mmio + offset);
758 return 0;
1da177e4 759 }
203ef6c4
TH		 760 return -EINVAL;
761}
1da177e4 762
203ef6c4
TH		 763static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
764{
765 void __iomem *port_mmio = ahci_port_base(ap);
766 int offset = ahci_scr_offset(ap, sc_reg);
767
768 if (offset) {
769 writel(val, port_mmio + offset);
770 return 0;
771 }
772 return -EINVAL;
1da177e4
LT		 773}
774
4447d351 775static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 776{
4447d351 777 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 778 u32 tmp;
779
d8fcd116 780 /* start DMA */
9f592056 781 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 782 tmp |= PORT_CMD_START;
783 writel(tmp, port_mmio + PORT_CMD);
784 readl(port_mmio + PORT_CMD); /* flush */
785}
786
4447d351 787static int ahci_stop_engine(struct ata_port *ap)
254950cd 788{
4447d351 789 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 790 u32 tmp;
791
792 tmp = readl(port_mmio + PORT_CMD);
793
d8fcd116 794 /* check if the HBA is idle */
254950cd
TH		 795 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
796 return 0;
797
d8fcd116 798 /* setting HBA to idle */
254950cd
TH		 799 tmp &= ~PORT_CMD_START;
800 writel(tmp, port_mmio + PORT_CMD);
801
d8fcd116 802 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 803 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 804 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 805 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 806 return -EIO;
807
808 return 0;
809}
810
4447d351 811static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 812{
4447d351
TH		 813 void __iomem *port_mmio = ahci_port_base(ap);
814 struct ahci_host_priv *hpriv = ap->host->private_data;
815 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 816 u32 tmp;
817
818 /* set FIS registers */
4447d351
TH		 819 if (hpriv->cap & HOST_CAP_64)
820 writel((pp->cmd_slot_dma >> 16) >> 16,
821 port_mmio + PORT_LST_ADDR_HI);
822 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 823
4447d351
TH		 824 if (hpriv->cap & HOST_CAP_64)
825 writel((pp->rx_fis_dma >> 16) >> 16,
826 port_mmio + PORT_FIS_ADDR_HI);
827 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 828
829 /* enable FIS reception */
830 tmp = readl(port_mmio + PORT_CMD);
831 tmp |= PORT_CMD_FIS_RX;
832 writel(tmp, port_mmio + PORT_CMD);
833
834 /* flush */
835 readl(port_mmio + PORT_CMD);
836}
837
4447d351 838static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 839{
4447d351 840 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 841 u32 tmp;
842
843 /* disable FIS reception */
844 tmp = readl(port_mmio + PORT_CMD);
845 tmp &= ~PORT_CMD_FIS_RX;
846 writel(tmp, port_mmio + PORT_CMD);
847
848 /* wait for completion, spec says 500ms, give it 1000 */
849 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
850 PORT_CMD_FIS_ON, 10, 1000);
851 if (tmp & PORT_CMD_FIS_ON)
852 return -EBUSY;
853
854 return 0;
855}
856
4447d351 857static void ahci_power_up(struct ata_port *ap)
0be0aa98 858{
4447d351
TH		 859 struct ahci_host_priv *hpriv = ap->host->private_data;
860 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 861 u32 cmd;
862
863 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
864
865 /* spin up device */
4447d351 866 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 867 cmd |= PORT_CMD_SPIN_UP;
868 writel(cmd, port_mmio + PORT_CMD);
869 }
870
871 /* wake up link */
872 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
873}
874
31556594
KCA		 875static void ahci_disable_alpm(struct ata_port *ap)
876{
877 struct ahci_host_priv *hpriv = ap->host->private_data;
878 void __iomem *port_mmio = ahci_port_base(ap);
879 u32 cmd;
880 struct ahci_port_priv *pp = ap->private_data;
881
882 /* IPM bits should be disabled by libata-core */
883 /* get the existing command bits */
884 cmd = readl(port_mmio + PORT_CMD);
885
886 /* disable ALPM and ASP */
887 cmd &= ~PORT_CMD_ASP;
888 cmd &= ~PORT_CMD_ALPE;
889
890 /* force the interface back to active */
891 cmd |= PORT_CMD_ICC_ACTIVE;
892
893 /* write out new cmd value */
894 writel(cmd, port_mmio + PORT_CMD);
895 cmd = readl(port_mmio + PORT_CMD);
896
897 /* wait 10ms to be sure we've come out of any low power state */
898 msleep(10);
899
900 /* clear out any PhyRdy stuff from interrupt status */
901 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
902
903 /* go ahead and clean out PhyRdy Change from Serror too */
904 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
905
906 /*
907 * Clear flag to indicate that we should ignore all PhyRdy
908 * state changes
909 */
910 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
911
912 /*
913 * Enable interrupts on Phy Ready.
914 */
915 pp->intr_mask |= PORT_IRQ_PHYRDY;
916 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
917
918 /*
919 * don't change the link pm policy - we can be called
920 * just to turn of link pm temporarily
921 */
922}
923
924static int ahci_enable_alpm(struct ata_port *ap,
925 enum link_pm policy)
926{
927 struct ahci_host_priv *hpriv = ap->host->private_data;
928 void __iomem *port_mmio = ahci_port_base(ap);
929 u32 cmd;
930 struct ahci_port_priv *pp = ap->private_data;
931 u32 asp;
932
933 /* Make sure the host is capable of link power management */
934 if (!(hpriv->cap & HOST_CAP_ALPM))
935 return -EINVAL;
936
937 switch (policy) {
938 case MAX_PERFORMANCE:
939 case NOT_AVAILABLE:
940 /*
941 * if we came here with NOT_AVAILABLE,
942 * it just means this is the first time we
943 * have tried to enable - default to max performance,
944 * and let the user go to lower power modes on request.
945 */
946 ahci_disable_alpm(ap);
947 return 0;
948 case MIN_POWER:
949 /* configure HBA to enter SLUMBER */
950 asp = PORT_CMD_ASP;
951 break;
952 case MEDIUM_POWER:
953 /* configure HBA to enter PARTIAL */
954 asp = 0;
955 break;
956 default:
957 return -EINVAL;
958 }
959
960 /*
961 * Disable interrupts on Phy Ready. This keeps us from
962 * getting woken up due to spurious phy ready interrupts
963 * TBD - Hot plug should be done via polling now, is
964 * that even supported?
965 */
966 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
967 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
968
969 /*
970 * Set a flag to indicate that we should ignore all PhyRdy
971 * state changes since these can happen now whenever we
972 * change link state
973 */
974 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
975
976 /* get the existing command bits */
977 cmd = readl(port_mmio + PORT_CMD);
978
979 /*
980 * Set ASP based on Policy
981 */
982 cmd |= asp;
983
984 /*
985 * Setting this bit will instruct the HBA to aggressively
986 * enter a lower power link state when it's appropriate and
987 * based on the value set above for ASP
988 */
989 cmd |= PORT_CMD_ALPE;
990
991 /* write out new cmd value */
992 writel(cmd, port_mmio + PORT_CMD);
993 cmd = readl(port_mmio + PORT_CMD);
994
995 /* IPM bits should be set by libata-core */
996 return 0;
997}
998
438ac6d5 999#ifdef CONFIG_PM
4447d351 1000static void ahci_power_down(struct ata_port *ap)
0be0aa98 1001{
4447d351
TH		 1002 struct ahci_host_priv *hpriv = ap->host->private_data;
1003 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1004 u32 cmd, scontrol;
1005
4447d351 1006 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1007 return;
0be0aa98 1008
07c53dac
TH		 1009 /* put device into listen mode, first set PxSCTL.DET to 0 */
1010 scontrol = readl(port_mmio + PORT_SCR_CTL);
1011 scontrol &= ~0xf;
1012 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1013
07c53dac
TH		 1014 /* then set PxCMD.SUD to 0 */
1015 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1016 cmd &= ~PORT_CMD_SPIN_UP;
1017 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1018}
438ac6d5 1019#endif
0be0aa98 1020
df69c9c5 1021static void ahci_start_port(struct ata_port *ap)
0be0aa98 1022{
0be0aa98 1023 /* enable FIS reception */
4447d351 1024 ahci_start_fis_rx(ap);
0be0aa98
TH		 1025
1026 /* enable DMA */
4447d351 1027 ahci_start_engine(ap);
0be0aa98
TH		 1028}
1029
4447d351 1030static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1031{
1032 int rc;
1033
1034 /* disable DMA */
4447d351 1035 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1036 if (rc) {
1037 *emsg = "failed to stop engine";
1038 return rc;
1039 }
1040
1041 /* disable FIS reception */
4447d351 1042 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1043 if (rc) {
1044 *emsg = "failed stop FIS RX";
1045 return rc;
1046 }
1047
0be0aa98
TH		 1048 return 0;
1049}
1050
4447d351 1051static int ahci_reset_controller(struct ata_host *host)
d91542c1 1052{
4447d351 1053 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1054 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1055 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1056 u32 tmp;
d91542c1 1057
3cc3eb11
JG		 1058 /* we must be in AHCI mode, before using anything
1059 * AHCI-specific, such as HOST_RESET.
1060 */
b710a1f4 1061 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1062
1063 /* global controller reset */
b710a1f4 1064 tmp = readl(mmio + HOST_CTL);
d91542c1
TH		 1065 if ((tmp & HOST_RESET) == 0) {
1066 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1067 readl(mmio + HOST_CTL); /* flush */
1068 }
1069
1070 /* reset must complete within 1 second, or
1071 * the hardware should be considered fried.
1072 */
1073 ssleep(1);
1074
1075 tmp = readl(mmio + HOST_CTL);
1076 if (tmp & HOST_RESET) {
4447d351 1077 dev_printk(KERN_ERR, host->dev,
d91542c1
TH		 1078 "controller reset failed (0x%x)\n", tmp);
1079 return -EIO;
1080 }
1081
98fa4b60 1082 /* turn on AHCI mode */
b710a1f4 1083 ahci_enable_ahci(mmio);
98fa4b60 1084
d447df14 1085 /* some registers might be cleared on reset. restore initial values */
4447d351 1086 ahci_restore_initial_config(host);
d91542c1
TH		 1087
1088 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1089 u16 tmp16;
1090
1091 /* configure PCS */
1092 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1093 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1094 tmp16 |= hpriv->port_map;
1095 pci_write_config_word(pdev, 0x92, tmp16);
1096 }
d91542c1
TH		 1097 }
1098
1099 return 0;
1100}
1101
2bcd866b
JG		 1102static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1103 int port_no, void __iomem *mmio,
1104 void __iomem *port_mmio)
1105{
1106 const char *emsg = NULL;
1107 int rc;
1108 u32 tmp;
1109
1110 /* make sure port is not active */
1111 rc = ahci_deinit_port(ap, &emsg);
1112 if (rc)
1113 dev_printk(KERN_WARNING, &pdev->dev,
1114 "%s (%d)\n", emsg, rc);
1115
1116 /* clear SError */
1117 tmp = readl(port_mmio + PORT_SCR_ERR);
1118 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1119 writel(tmp, port_mmio + PORT_SCR_ERR);
1120
1121 /* clear port IRQ */
1122 tmp = readl(port_mmio + PORT_IRQ_STAT);
1123 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1124 if (tmp)
1125 writel(tmp, port_mmio + PORT_IRQ_STAT);
1126
1127 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1128}
1129
4447d351 1130static void ahci_init_controller(struct ata_host *host)
d91542c1 1131{
417a1a6d 1132 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1133 struct pci_dev *pdev = to_pci_dev(host->dev);
1134 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1135 int i;
cd70c266 1136 void __iomem *port_mmio;
d91542c1
TH		 1137 u32 tmp;
1138
417a1a6d 1139 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
cd70c266
JG		 1140 port_mmio = __ahci_port_base(host, 4);
1141
1142 writel(0, port_mmio + PORT_IRQ_MASK);
1143
1144 /* clear port IRQ */
1145 tmp = readl(port_mmio + PORT_IRQ_STAT);
1146 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1147 if (tmp)
1148 writel(tmp, port_mmio + PORT_IRQ_STAT);
1149 }
1150
4447d351
TH		 1151 for (i = 0; i < host->n_ports; i++) {
1152 struct ata_port *ap = host->ports[i];
d91542c1 1153
cd70c266 1154 port_mmio = ahci_port_base(ap);
4447d351 1155 if (ata_port_is_dummy(ap))
d91542c1 1156 continue;
d91542c1 1157
2bcd866b 1158 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1159 }
1160
1161 tmp = readl(mmio + HOST_CTL);
1162 VPRINTK("HOST_CTL 0x%x\n", tmp);
1163 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1164 tmp = readl(mmio + HOST_CTL);
1165 VPRINTK("HOST_CTL 0x%x\n", tmp);
1166}
1167
422b7595 1168static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1169{
4447d351 1170 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1171 struct ata_taskfile tf;
422b7595
TH		 1172 u32 tmp;
1173
1174 tmp = readl(port_mmio + PORT_SIG);
1175 tf.lbah = (tmp >> 24) & 0xff;
1176 tf.lbam = (tmp >> 16) & 0xff;
1177 tf.lbal = (tmp >> 8) & 0xff;
1178 tf.nsect = (tmp) & 0xff;
1179
1180 return ata_dev_classify(&tf);
1181}
1182
12fad3f9
TH		 1183static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1184 u32 opts)
cc9278ed 1185{
12fad3f9
TH		 1186 dma_addr_t cmd_tbl_dma;
1187
1188 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1189
1190 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1191 pp->cmd_slot[tag].status = 0;
1192 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1193 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1194}
1195
d2e75dff 1196static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1197{
0d5ff566 1198 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 1199 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2 1200 u32 tmp;
d2e75dff 1201 int busy, rc;
bf2af2a2 1202
d2e75dff
TH		 1203 /* do we need to kick the port? */
1204 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1205 if (!busy && !force_restart)
1206 return 0;
1207
1208 /* stop engine */
1209 rc = ahci_stop_engine(ap);
1210 if (rc)
1211 goto out_restart;
1212
1213 /* need to do CLO? */
1214 if (!busy) {
1215 rc = 0;
1216 goto out_restart;
1217 }
1218
1219 if (!(hpriv->cap & HOST_CAP_CLO)) {
1220 rc = -EOPNOTSUPP;
1221 goto out_restart;
1222 }
bf2af2a2 1223
d2e75dff 1224 /* perform CLO */
bf2af2a2
BJ		 1225 tmp = readl(port_mmio + PORT_CMD);
1226 tmp |= PORT_CMD_CLO;
1227 writel(tmp, port_mmio + PORT_CMD);
1228
d2e75dff 1229 rc = 0;
bf2af2a2
BJ		 1230 tmp = ata_wait_register(port_mmio + PORT_CMD,
1231 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1232 if (tmp & PORT_CMD_CLO)
d2e75dff 1233 rc = -EIO;
bf2af2a2 1234
d2e75dff
TH		 1235 /* restart engine */
1236 out_restart:
1237 ahci_start_engine(ap);
1238 return rc;
bf2af2a2
BJ		 1239}
1240
91c4a2e0
TH		 1241static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1242 struct ata_taskfile *tf, int is_cmd, u16 flags,
1243 unsigned long timeout_msec)
bf2af2a2 1244{
91c4a2e0 1245 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1246 struct ahci_port_priv *pp = ap->private_data;
4447d351 1247 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1248 u8 *fis = pp->cmd_tbl;
1249 u32 tmp;
1250
1251 /* prep the command */
1252 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1253 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1254
1255 /* issue & wait */
1256 writel(1, port_mmio + PORT_CMD_ISSUE);
1257
1258 if (timeout_msec) {
1259 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1260 1, timeout_msec);
1261 if (tmp & 0x1) {
1262 ahci_kick_engine(ap, 1);
1263 return -EBUSY;
1264 }
1265 } else
1266 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1267
1268 return 0;
1269}
1270
cc0680a5 1271static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85 1272 int pmp, unsigned long deadline)
91c4a2e0 1273{
cc0680a5 1274 struct ata_port *ap = link->ap;
4658f79b 1275 const char *reason = NULL;
2cbb79eb 1276 unsigned long now, msecs;
4658f79b 1277 struct ata_taskfile tf;
4658f79b
TH		 1278 int rc;
1279
1280 DPRINTK("ENTER\n");
1281
cc0680a5 1282 if (ata_link_offline(link)) {
c2a65852
TH		 1283 DPRINTK("PHY reports no device\n");
1284 *class = ATA_DEV_NONE;
1285 return 0;
1286 }
1287
4658f79b 1288 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1289 rc = ahci_kick_engine(ap, 1);
994056d7 1290 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1291 ata_link_printk(link, KERN_WARNING,
994056d7 1292 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1293
cc0680a5 1294 ata_tf_init(link->device, &tf);
4658f79b
TH		 1295
1296 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1297 msecs = 0;
1298 now = jiffies;
1299 if (time_after(now, deadline))
1300 msecs = jiffies_to_msecs(deadline - now);
1301
4658f79b 1302 tf.ctl |= ATA_SRST;
a9cf5e85 1303 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1304 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1305 rc = -EIO;
1306 reason = "1st FIS failed";
1307 goto fail;
1308 }
1309
1310 /* spec says at least 5us, but be generous and sleep for 1ms */
1311 msleep(1);
1312
1313 /* issue the second D2H Register FIS */
4658f79b 1314 tf.ctl &= ~ATA_SRST;
a9cf5e85 1315 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1316
88ff6eaf
TH		 1317 /* wait a while before checking status */
1318 ata_wait_after_reset(ap, deadline);
4658f79b 1319
9b89391c
TH		 1320 rc = ata_wait_ready(ap, deadline);
1321 /* link occupied, -ENODEV too is an error */
1322 if (rc) {
1323 reason = "device not ready";
1324 goto fail;
4658f79b 1325 }
9b89391c 1326 *class = ahci_dev_classify(ap);
4658f79b
TH		 1327
1328 DPRINTK("EXIT, class=%u\n", *class);
1329 return 0;
1330
4658f79b 1331 fail:
cc0680a5 1332 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1333 return rc;
1334}
1335
cc0680a5 1336static int ahci_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85
TH		 1337 unsigned long deadline)
1338{
7d50b60b
TH		 1339 int pmp = 0;
1340
1341 if (link->ap->flags & ATA_FLAG_PMP)
1342 pmp = SATA_PMP_CTRL_PORT;
1343
1344 return ahci_do_softreset(link, class, pmp, deadline);
a9cf5e85
TH		 1345}
1346
cc0680a5 1347static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1348 unsigned long deadline)
422b7595 1349{
cc0680a5 1350 struct ata_port *ap = link->ap;
4296971d
TH		 1351 struct ahci_port_priv *pp = ap->private_data;
1352 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1353 struct ata_taskfile tf;
4bd00f6a
TH		 1354 int rc;
1355
1356 DPRINTK("ENTER\n");
1da177e4 1357
4447d351 1358 ahci_stop_engine(ap);
4296971d
TH		 1359
1360 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1361 ata_tf_init(link->device, &tf);
dfd7a3db 1362 tf.command = 0x80;
9977126c 1363 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1364
cc0680a5 1365 rc = sata_std_hardreset(link, class, deadline);
4296971d 1366
4447d351 1367 ahci_start_engine(ap);
1da177e4 1368
cc0680a5 1369 if (rc == 0 && ata_link_online(link))
4bd00f6a 1370 *class = ahci_dev_classify(ap);
7d50b60b 1371 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
4bd00f6a 1372 *class = ATA_DEV_NONE;
1da177e4 1373
4bd00f6a
TH		 1374 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1375 return rc;
1376}
1377
cc0680a5 1378static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1379 unsigned long deadline)
ad616ffb 1380{
cc0680a5 1381 struct ata_port *ap = link->ap;
da3dbb17 1382 u32 serror;
ad616ffb
TH		 1383 int rc;
1384
1385 DPRINTK("ENTER\n");
1386
4447d351 1387 ahci_stop_engine(ap);
ad616ffb 1388
cc0680a5 1389 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
d4b2bab4 1390 deadline);
ad616ffb
TH		 1391
1392 /* vt8251 needs SError cleared for the port to operate */
da3dbb17
TH		 1393 ahci_scr_read(ap, SCR_ERROR, &serror);
1394 ahci_scr_write(ap, SCR_ERROR, serror);
ad616ffb 1395
4447d351 1396 ahci_start_engine(ap);
ad616ffb
TH		 1397
1398 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1399
1400 /* vt8251 doesn't clear BSY on signature FIS reception,
1401 * request follow-up softreset.
1402 */
1403 return rc ?: -EAGAIN;
1404}
1405
edc93052
TH		 1406static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1407 unsigned long deadline)
1408{
1409 struct ata_port *ap = link->ap;
1410 struct ahci_port_priv *pp = ap->private_data;
1411 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1412 struct ata_taskfile tf;
1413 int rc;
1414
1415 ahci_stop_engine(ap);
1416
1417 /* clear D2H reception area to properly wait for D2H FIS */
1418 ata_tf_init(link->device, &tf);
1419 tf.command = 0x80;
1420 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1421
1422 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1423 deadline);
1424
1425 ahci_start_engine(ap);
1426
1427 if (rc || ata_link_offline(link))
1428 return rc;
1429
1430 /* spec mandates ">= 2ms" before checking status */
1431 msleep(150);
1432
1433 /* The pseudo configuration device on SIMG4726 attached to
1434 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1435 * hardreset if no device is attached to the first downstream
1436 * port && the pseudo device locks up on SRST w/ PMP==0. To
1437 * work around this, wait for !BSY only briefly. If BSY isn't
1438 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1439 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1440 *
1441 * Wait for two seconds. Devices attached to downstream port
1442 * which can't process the following IDENTIFY after this will
1443 * have to be reset again. For most cases, this should
1444 * suffice while making probing snappish enough.
1445 */
1446 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1447 if (rc)
1448 ahci_kick_engine(ap, 0);
1449
1450 return 0;
1451}
1452
cc0680a5 1453static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1454{
cc0680a5 1455 struct ata_port *ap = link->ap;
4447d351 1456 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1457 u32 new_tmp, tmp;
1458
cc0680a5 1459 ata_std_postreset(link, class);
02eaa666
JG		 1460
1461 /* Make sure port's ATAPI bit is set appropriately */
1462 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1463 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1464 new_tmp |= PORT_CMD_ATAPI;
1465 else
1466 new_tmp &= ~PORT_CMD_ATAPI;
1467 if (new_tmp != tmp) {
1468 writel(new_tmp, port_mmio + PORT_CMD);
1469 readl(port_mmio + PORT_CMD); /* flush */
1470 }
1da177e4
LT		 1471}
1472
7d50b60b
TH		 1473static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1474 unsigned long deadline)
1475{
1476 return ahci_do_softreset(link, class, link->pmp, deadline);
1477}
1478
1da177e4
LT		 1479static u8 ahci_check_status(struct ata_port *ap)
1480{
0d5ff566 1481 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1482
1483 return readl(mmio + PORT_TFDATA) & 0xFF;
1484}
1485
1da177e4
LT		 1486static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1487{
1488 struct ahci_port_priv *pp = ap->private_data;
1489 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1490
1491 ata_tf_from_fis(d2h_fis, tf);
1492}
1493
12fad3f9 1494static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1495{
cedc9a47 1496 struct scatterlist *sg;
ff2aeb1e
TH		 1497 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1498 unsigned int si;
1da177e4
LT		 1499
1500 VPRINTK("ENTER\n");
1501
1502 /*
1503 * Next, the S/G list.
1504 */
ff2aeb1e 1505 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1506 dma_addr_t addr = sg_dma_address(sg);
1507 u32 sg_len = sg_dma_len(sg);
1508
ff2aeb1e
TH		 1509 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1510 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1511 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1512 }
828d09de 1513
ff2aeb1e 1514 return si;
1da177e4
LT		 1515}
1516
1517static void ahci_qc_prep(struct ata_queued_cmd *qc)
1518{
a0ea7328
JG		 1519 struct ata_port *ap = qc->ap;
1520 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1521 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1522 void *cmd_tbl;
1da177e4
LT		 1523 u32 opts;
1524 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1525 unsigned int n_elem;
1da177e4 1526
1da177e4
LT		 1527 /*
1528 * Fill in command table information. First, the header,
1529 * a SATA Register - Host to Device command FIS.
1530 */
12fad3f9
TH		 1531 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1532
7d50b60b 1533 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1534 if (is_atapi) {
12fad3f9
TH		 1535 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1536 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1537 }
1da177e4 1538
cc9278ed
TH		 1539 n_elem = 0;
1540 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1541 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1542
cc9278ed
TH		 1543 /*
1544 * Fill in command slot information.
1545 */
7d50b60b 1546 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1547 if (qc->tf.flags & ATA_TFLAG_WRITE)
1548 opts |= AHCI_CMD_WRITE;
1549 if (is_atapi)
4b10e559 1550 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1551
12fad3f9 1552 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1553}
1554
78cd52d0 1555static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1556{
417a1a6d 1557 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1558 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1559 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1560 struct ata_link *link = NULL;
1561 struct ata_queued_cmd *active_qc;
1562 struct ata_eh_info *active_ehi;
78cd52d0 1563 u32 serror;
1da177e4 1564
7d50b60b
TH		 1565 /* determine active link */
1566 ata_port_for_each_link(link, ap)
1567 if (ata_link_active(link))
1568 break;
1569 if (!link)
1570 link = &ap->link;
1571
1572 active_qc = ata_qc_from_tag(ap, link->active_tag);
1573 active_ehi = &link->eh_info;
1574
1575 /* record irq stat */
1576 ata_ehi_clear_desc(host_ehi);
1577 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1578
78cd52d0 1579 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1580 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1581 ahci_scr_write(ap, SCR_ERROR, serror);
7d50b60b 1582 host_ehi->serror |= serror;
78cd52d0 1583
41669553 1584 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1585 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1586 irq_stat &= ~PORT_IRQ_IF_ERR;
1587
55a61604 1588 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1589 /* If qc is active, charge it; otherwise, the active
1590 * link. There's no active qc on NCQ errors. It will
1591 * be determined by EH by reading log page 10h.
1592 */
1593 if (active_qc)
1594 active_qc->err_mask |= AC_ERR_DEV;
1595 else
1596 active_ehi->err_mask |= AC_ERR_DEV;
1597
417a1a6d 1598 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1599 host_ehi->serror &= ~SERR_INTERNAL;
1600 }
1601
1602 if (irq_stat & PORT_IRQ_UNK_FIS) {
1603 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1604
1605 active_ehi->err_mask |= AC_ERR_HSM;
1606 active_ehi->action |= ATA_EH_SOFTRESET;
1607 ata_ehi_push_desc(active_ehi,
1608 "unknown FIS %08x %08x %08x %08x" ,
1609 unk[0], unk[1], unk[2], unk[3]);
1610 }
1611
1612 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1613 active_ehi->err_mask |= AC_ERR_HSM;
1614 active_ehi->action |= ATA_EH_SOFTRESET;
1615 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1616 }
78cd52d0
TH		 1617
1618 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b
TH		 1619 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1620 host_ehi->action |= ATA_EH_SOFTRESET;
1621 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1622 }
1623
78cd52d0 1624 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b
TH		 1625 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1626 host_ehi->action |= ATA_EH_SOFTRESET;
1627 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1628 }
1da177e4 1629
78cd52d0 1630 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1631 ata_ehi_hotplugged(host_ehi);
1632 ata_ehi_push_desc(host_ehi, "%s",
1633 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1634 "connection status changed" : "PHY RDY changed");
1635 }
1636
78cd52d0 1637 /* okay, let's hand over to EH */
a72ec4ce 1638
78cd52d0
TH		 1639 if (irq_stat & PORT_IRQ_FREEZE)
1640 ata_port_freeze(ap);
1641 else
1642 ata_port_abort(ap);
1da177e4
LT		 1643}
1644
df69c9c5 1645static void ahci_port_intr(struct ata_port *ap)
1da177e4 1646{
4447d351 1647 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
9af5c9c9 1648 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 1649 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 1650 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 1651 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 1652 u32 status, qc_active;
459ad688 1653 int rc;
1da177e4
LT		 1654
1655 status = readl(port_mmio + PORT_IRQ_STAT);
1656 writel(status, port_mmio + PORT_IRQ_STAT);
1657
b06ce3e5
TH		 1658 /* ignore BAD_PMP while resetting */
1659 if (unlikely(resetting))
1660 status &= ~PORT_IRQ_BAD_PMP;
1661
31556594
KCA		 1662 /* If we are getting PhyRdy, this is
1663 * just a power state change, we should
1664 * clear out this, plus the PhyRdy/Comm
1665 * Wake bits from Serror
1666 */
1667 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1668 (status & PORT_IRQ_PHYRDY)) {
1669 status &= ~PORT_IRQ_PHYRDY;
1670 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1671 }
1672
78cd52d0
TH		 1673 if (unlikely(status & PORT_IRQ_ERROR)) {
1674 ahci_error_intr(ap, status);
1675 return;
1da177e4
LT		 1676 }
1677
2f294968 1678 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 1679 /* If SNotification is available, leave notification
1680 * handling to sata_async_notification(). If not,
1681 * emulate it by snooping SDB FIS RX area.
1682 *
1683 * Snooping FIS RX area is probably cheaper than
1684 * poking SNotification but some constrollers which
1685 * implement SNotification, ICH9 for example, don't
1686 * store AN SDB FIS into receive area.
2f294968 1687 */
5f226c6b 1688 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 1689 sata_async_notification(ap);
5f226c6b
TH		 1690 else {
1691 /* If the 'N' bit in word 0 of the FIS is set,
1692 * we just received asynchronous notification.
1693 * Tell libata about it.
1694 */
1695 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1696 u32 f0 = le32_to_cpu(f[0]);
1697
1698 if (f0 & (1 << 15))
1699 sata_async_notification(ap);
1700 }
2f294968
KCA		 1701 }
1702
7d50b60b
TH		 1703 /* pp->active_link is valid iff any command is in flight */
1704 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 1705 qc_active = readl(port_mmio + PORT_SCR_ACT);
1706 else
1707 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1708
1709 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
b06ce3e5 1710
459ad688
TH		 1711 /* while resetting, invalid completions are expected */
1712 if (unlikely(rc < 0 && !resetting)) {
12fad3f9
TH		 1713 ehi->err_mask |= AC_ERR_HSM;
1714 ehi->action |= ATA_EH_SOFTRESET;
1715 ata_port_freeze(ap);
1da177e4 1716 }
1da177e4
LT		 1717}
1718
1719static void ahci_irq_clear(struct ata_port *ap)
1720{
1721 /* TODO */
1722}
1723
7d12e780 1724static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1725{
cca3974e 1726 struct ata_host *host = dev_instance;
1da177e4
LT		 1727 struct ahci_host_priv *hpriv;
1728 unsigned int i, handled = 0;
ea6ba10b 1729 void __iomem *mmio;
1da177e4
LT		 1730 u32 irq_stat, irq_ack = 0;
1731
1732 VPRINTK("ENTER\n");
1733
cca3974e 1734 hpriv = host->private_data;
0d5ff566 1735 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1736
1737 /* sigh. 0xffffffff is a valid return from h/w */
1738 irq_stat = readl(mmio + HOST_IRQ_STAT);
1739 irq_stat &= hpriv->port_map;
1740 if (!irq_stat)
1741 return IRQ_NONE;
1742
2dcb407e 1743 spin_lock(&host->lock);
1da177e4 1744
2dcb407e 1745 for (i = 0; i < host->n_ports; i++) {
1da177e4 1746 struct ata_port *ap;
1da177e4 1747
67846b30
JG		 1748 if (!(irq_stat & (1 << i)))
1749 continue;
1750
cca3974e 1751 ap = host->ports[i];
67846b30 1752 if (ap) {
df69c9c5 1753 ahci_port_intr(ap);
67846b30
JG		 1754 VPRINTK("port %u\n", i);
1755 } else {
1756 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1757 if (ata_ratelimit())
cca3974e 1758 dev_printk(KERN_WARNING, host->dev,
a9524a76 1759 "interrupt on disabled port %u\n", i);
1da177e4 1760 }
67846b30
JG		 1761
1762 irq_ack |= (1 << i);
1da177e4
LT		 1763 }
1764
1765 if (irq_ack) {
1766 writel(irq_ack, mmio + HOST_IRQ_STAT);
1767 handled = 1;
1768 }
1769
cca3974e 1770 spin_unlock(&host->lock);
1da177e4
LT		 1771
1772 VPRINTK("EXIT\n");
1773
1774 return IRQ_RETVAL(handled);
1775}
1776
9a3d9eb0 1777static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1778{
1779 struct ata_port *ap = qc->ap;
4447d351 1780 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 1781 struct ahci_port_priv *pp = ap->private_data;
1782
1783 /* Keep track of the currently active link. It will be used
1784 * in completion path to determine whether NCQ phase is in
1785 * progress.
1786 */
1787 pp->active_link = qc->dev->link;
1da177e4 1788
12fad3f9
TH		 1789 if (qc->tf.protocol == ATA_PROT_NCQ)
1790 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1791 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1792 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1793
1794 return 0;
1795}
1796
78cd52d0
TH		 1797static void ahci_freeze(struct ata_port *ap)
1798{
4447d351 1799 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1800
1801 /* turn IRQ off */
1802 writel(0, port_mmio + PORT_IRQ_MASK);
1803}
1804
1805static void ahci_thaw(struct ata_port *ap)
1806{
0d5ff566 1807 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 1808 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 1809 u32 tmp;
a7384925 1810 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 1811
1812 /* clear IRQ */
1813 tmp = readl(port_mmio + PORT_IRQ_STAT);
1814 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1815 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 1816
1c954a4d
TH		 1817 /* turn IRQ back on */
1818 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 1819}
1820
1821static void ahci_error_handler(struct ata_port *ap)
1822{
b51e9e5d 1823 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1824 /* restart engine */
4447d351
TH		 1825 ahci_stop_engine(ap);
1826 ahci_start_engine(ap);
78cd52d0
TH		 1827 }
1828
1829 /* perform recovery */
7d50b60b
TH		 1830 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1831 ahci_hardreset, ahci_postreset,
1832 sata_pmp_std_prereset, ahci_pmp_softreset,
1833 sata_pmp_std_hardreset, sata_pmp_std_postreset);
78cd52d0
TH		 1834}
1835
ad616ffb
TH		 1836static void ahci_vt8251_error_handler(struct ata_port *ap)
1837{
ad616ffb
TH		 1838 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1839 /* restart engine */
4447d351
TH		 1840 ahci_stop_engine(ap);
1841 ahci_start_engine(ap);
ad616ffb
TH		 1842 }
1843
1844 /* perform recovery */
1845 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1846 ahci_postreset);
1847}
1848
edc93052
TH		 1849static void ahci_p5wdh_error_handler(struct ata_port *ap)
1850{
1851 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1852 /* restart engine */
1853 ahci_stop_engine(ap);
1854 ahci_start_engine(ap);
1855 }
1856
1857 /* perform recovery */
1858 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1859 ahci_postreset);
1860}
1861
78cd52d0
TH		 1862static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1863{
1864 struct ata_port *ap = qc->ap;
1865
d2e75dff
TH		 1866 /* make DMA engine forget about the failed command */
1867 if (qc->flags & ATA_QCFLAG_FAILED)
1868 ahci_kick_engine(ap, 1);
78cd52d0
TH		 1869}
1870
7d50b60b
TH		 1871static void ahci_pmp_attach(struct ata_port *ap)
1872{
1873 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1874 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1875 u32 cmd;
1876
1877 cmd = readl(port_mmio + PORT_CMD);
1878 cmd |= PORT_CMD_PMP;
1879 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1880
1881 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1882 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1883}
1884
1885static void ahci_pmp_detach(struct ata_port *ap)
1886{
1887 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1888 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1889 u32 cmd;
1890
1891 cmd = readl(port_mmio + PORT_CMD);
1892 cmd &= ~PORT_CMD_PMP;
1893 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1894
1895 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1896 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1897}
1898
028a2596
AD		 1899static int ahci_port_resume(struct ata_port *ap)
1900{
1901 ahci_power_up(ap);
1902 ahci_start_port(ap);
1903
7d50b60b
TH		 1904 if (ap->nr_pmp_links)
1905 ahci_pmp_attach(ap);
1906 else
1907 ahci_pmp_detach(ap);
1908
028a2596
AD		 1909 return 0;
1910}
1911
438ac6d5 1912#ifdef CONFIG_PM
c1332875
TH		 1913static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1914{
c1332875
TH		 1915 const char *emsg = NULL;
1916 int rc;
1917
4447d351 1918 rc = ahci_deinit_port(ap, &emsg);
8e16f941 1919 if (rc == 0)
4447d351 1920 ahci_power_down(ap);
8e16f941 1921 else {
c1332875 1922 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 1923 ahci_start_port(ap);
c1332875
TH		 1924 }
1925
1926 return rc;
1927}
1928
c1332875
TH		 1929static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1930{
cca3974e 1931 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1932 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1933 u32 ctl;
1934
1935 if (mesg.event == PM_EVENT_SUSPEND) {
1936 /* AHCI spec rev1.1 section 8.3.3:
1937 * Software must disable interrupts prior to requesting a
1938 * transition of the HBA to D3 state.
1939 */
1940 ctl = readl(mmio + HOST_CTL);
1941 ctl &= ~HOST_IRQ_EN;
1942 writel(ctl, mmio + HOST_CTL);
1943 readl(mmio + HOST_CTL); /* flush */
1944 }
1945
1946 return ata_pci_device_suspend(pdev, mesg);
1947}
1948
1949static int ahci_pci_device_resume(struct pci_dev *pdev)
1950{
cca3974e 1951 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 1952 int rc;
1953
553c4aa6
TH		 1954 rc = ata_pci_device_do_resume(pdev);
1955 if (rc)
1956 return rc;
c1332875
TH		 1957
1958 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 1959 rc = ahci_reset_controller(host);
c1332875
TH		 1960 if (rc)
1961 return rc;
1962
4447d351 1963 ahci_init_controller(host);
c1332875
TH		 1964 }
1965
cca3974e 1966 ata_host_resume(host);
c1332875
TH		 1967
1968 return 0;
1969}
438ac6d5 1970#endif
c1332875 1971
254950cd
TH		 1972static int ahci_port_start(struct ata_port *ap)
1973{
cca3974e 1974 struct device *dev = ap->host->dev;
254950cd 1975 struct ahci_port_priv *pp;
254950cd
TH		 1976 void *mem;
1977 dma_addr_t mem_dma;
254950cd 1978
24dc5f33 1979 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 1980 if (!pp)
1981 return -ENOMEM;
254950cd 1982
24dc5f33
TH		 1983 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1984 GFP_KERNEL);
1985 if (!mem)
254950cd 1986 return -ENOMEM;
254950cd
TH		 1987 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1988
1989 /*
1990 * First item in chunk of DMA memory: 32-slot command table,
1991 * 32 bytes each in size
1992 */
1993 pp->cmd_slot = mem;
1994 pp->cmd_slot_dma = mem_dma;
1995
1996 mem += AHCI_CMD_SLOT_SZ;
1997 mem_dma += AHCI_CMD_SLOT_SZ;
1998
1999 /*
2000 * Second item: Received-FIS area
2001 */
2002 pp->rx_fis = mem;
2003 pp->rx_fis_dma = mem_dma;
2004
2005 mem += AHCI_RX_FIS_SZ;
2006 mem_dma += AHCI_RX_FIS_SZ;
2007
2008 /*
2009 * Third item: data area for storing a single command
2010 * and its scatter-gather table
2011 */
2012 pp->cmd_tbl = mem;
2013 pp->cmd_tbl_dma = mem_dma;
2014
a7384925 2015 /*
2dcb407e
JG		 2016 * Save off initial list of interrupts to be enabled.
2017 * This could be changed later
2018 */
a7384925
KCA		 2019 pp->intr_mask = DEF_PORT_IRQ;
2020
254950cd
TH		 2021 ap->private_data = pp;
2022
df69c9c5
JG		 2023 /* engage engines, captain */
2024 return ahci_port_resume(ap);
254950cd
TH		 2025}
2026
2027static void ahci_port_stop(struct ata_port *ap)
2028{
0be0aa98
TH		 2029 const char *emsg = NULL;
2030 int rc;
254950cd 2031
0be0aa98 2032 /* de-initialize port */
4447d351 2033 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2034 if (rc)
2035 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2036}
2037
4447d351 2038static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2039{
1da177e4 2040 int rc;
1da177e4 2041
1da177e4
LT		 2042 if (using_dac &&
2043 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2044 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2045 if (rc) {
2046 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2047 if (rc) {
a9524a76
JG		 2048 dev_printk(KERN_ERR, &pdev->dev,
2049 "64-bit DMA enable failed\n");
1da177e4
LT		 2050 return rc;
2051 }
2052 }
1da177e4
LT		 2053 } else {
2054 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2055 if (rc) {
a9524a76
JG		 2056 dev_printk(KERN_ERR, &pdev->dev,
2057 "32-bit DMA enable failed\n");
1da177e4
LT		 2058 return rc;
2059 }
2060 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2061 if (rc) {
a9524a76
JG		 2062 dev_printk(KERN_ERR, &pdev->dev,
2063 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2064 return rc;
2065 }
2066 }
1da177e4
LT		 2067 return 0;
2068}
2069
4447d351 2070static void ahci_print_info(struct ata_host *host)
1da177e4 2071{
4447d351
TH		 2072 struct ahci_host_priv *hpriv = host->private_data;
2073 struct pci_dev *pdev = to_pci_dev(host->dev);
2074 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2075 u32 vers, cap, impl, speed;
2076 const char *speed_s;
2077 u16 cc;
2078 const char *scc_s;
2079
2080 vers = readl(mmio + HOST_VERSION);
2081 cap = hpriv->cap;
2082 impl = hpriv->port_map;
2083
2084 speed = (cap >> 20) & 0xf;
2085 if (speed == 1)
2086 speed_s = "1.5";
2087 else if (speed == 2)
2088 speed_s = "3";
2089 else
2090 speed_s = "?";
2091
2092 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2093 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2094 scc_s = "IDE";
c9f89475 2095 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2096 scc_s = "SATA";
c9f89475 2097 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2098 scc_s = "RAID";
2099 else
2100 scc_s = "unknown";
2101
a9524a76
JG		 2102 dev_printk(KERN_INFO, &pdev->dev,
2103 "AHCI %02x%02x.%02x%02x "
1da177e4 2104 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2105 ,
1da177e4 2106
2dcb407e
JG		 2107 (vers >> 24) & 0xff,
2108 (vers >> 16) & 0xff,
2109 (vers >> 8) & 0xff,
2110 vers & 0xff,
1da177e4
LT		 2111
2112 ((cap >> 8) & 0x1f) + 1,
2113 (cap & 0x1f) + 1,
2114 speed_s,
2115 impl,
2116 scc_s);
2117
a9524a76
JG		 2118 dev_printk(KERN_INFO, &pdev->dev,
2119 "flags: "
203ef6c4
TH		 2120 "%s%s%s%s%s%s%s"
2121 "%s%s%s%s%s%s%s\n"
2dcb407e 2122 ,
1da177e4
LT		 2123
2124 cap & (1 << 31) ? "64bit " : "",
2125 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2126 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2127 cap & (1 << 28) ? "ilck " : "",
2128 cap & (1 << 27) ? "stag " : "",
2129 cap & (1 << 26) ? "pm " : "",
2130 cap & (1 << 25) ? "led " : "",
2131
2132 cap & (1 << 24) ? "clo " : "",
2133 cap & (1 << 19) ? "nz " : "",
2134 cap & (1 << 18) ? "only " : "",
2135 cap & (1 << 17) ? "pmp " : "",
2136 cap & (1 << 15) ? "pio " : "",
2137 cap & (1 << 14) ? "slum " : "",
2138 cap & (1 << 13) ? "part " : ""
2139 );
2140}
2141
edc93052
TH		 2142/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2143 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2144 * support PMP and the 4726 either directly exports the device
2145 * attached to the first downstream port or acts as a hardware storage
2146 * controller and emulate a single ATA device (can be RAID 0/1 or some
2147 * other configuration).
2148 *
2149 * When there's no device attached to the first downstream port of the
2150 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2151 * configure the 4726. However, ATA emulation of the device is very
2152 * lame. It doesn't send signature D2H Reg FIS after the initial
2153 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2154 *
2155 * The following function works around the problem by always using
2156 * hardreset on the port and not depending on receiving signature FIS
2157 * afterward. If signature FIS isn't received soon, ATA class is
2158 * assumed without follow-up softreset.
2159 */
2160static void ahci_p5wdh_workaround(struct ata_host *host)
2161{
2162 static struct dmi_system_id sysids[] = {
2163 {
2164 .ident = "P5W DH Deluxe",
2165 .matches = {
2166 DMI_MATCH(DMI_SYS_VENDOR,
2167 "ASUSTEK COMPUTER INC"),
2168 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2169 },
2170 },
2171 { }
2172 };
2173 struct pci_dev *pdev = to_pci_dev(host->dev);
2174
2175 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2176 dmi_check_system(sysids)) {
2177 struct ata_port *ap = host->ports[1];
2178
2179 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2180 "Deluxe on-board SIMG4726 workaround\n");
2181
2182 ap->ops = &ahci_p5wdh_ops;
2183 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2184 }
2185}
2186
24dc5f33 2187static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2188{
2189 static int printed_version;
4447d351
TH		 2190 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2191 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2192 struct device *dev = &pdev->dev;
1da177e4 2193 struct ahci_host_priv *hpriv;
4447d351 2194 struct ata_host *host;
837f5f8f 2195 int n_ports, i, rc;
1da177e4
LT		 2196
2197 VPRINTK("ENTER\n");
2198
12fad3f9
TH		 2199 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2200
1da177e4 2201 if (!printed_version++)
a9524a76 2202 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2203
4447d351 2204 /* acquire resources */
24dc5f33 2205 rc = pcim_enable_device(pdev);
1da177e4
LT		 2206 if (rc)
2207 return rc;
2208
0d5ff566
TH		 2209 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2210 if (rc == -EBUSY)
24dc5f33 2211 pcim_pin_device(pdev);
0d5ff566 2212 if (rc)
24dc5f33 2213 return rc;
1da177e4 2214
c4f7792c
TH		 2215 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2216 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2217 u8 map;
2218
2219 /* ICH6s share the same PCI ID for both piix and ahci
2220 * modes. Enabling ahci mode while MAP indicates
2221 * combined mode is a bad idea. Yield to ata_piix.
2222 */
2223 pci_read_config_byte(pdev, ICH_MAP, &map);
2224 if (map & 0x3) {
2225 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2226 "combined mode, can't enable AHCI mode\n");
2227 return -ENODEV;
2228 }
2229 }
2230
24dc5f33
TH		 2231 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2232 if (!hpriv)
2233 return -ENOMEM;
417a1a6d
TH		 2234 hpriv->flags |= (unsigned long)pi.private_data;
2235
2236 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2237 pci_intx(pdev, 1);
1da177e4 2238
4447d351 2239 /* save initial config */
417a1a6d 2240 ahci_save_initial_config(pdev, hpriv);
1da177e4 2241
4447d351 2242 /* prepare host */
274c1fde 2243 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2244 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2245
7d50b60b
TH		 2246 if (hpriv->cap & HOST_CAP_PMP)
2247 pi.flags |= ATA_FLAG_PMP;
2248
837f5f8f
TH		 2249 /* CAP.NP sometimes indicate the index of the last enabled
2250 * port, at other times, that of the last possible port, so
2251 * determining the maximum port number requires looking at
2252 * both CAP.NP and port_map.
2253 */
2254 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2255
2256 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2257 if (!host)
2258 return -ENOMEM;
2259 host->iomap = pcim_iomap_table(pdev);
2260 host->private_data = hpriv;
2261
2262 for (i = 0; i < host->n_ports; i++) {
dab632e8
JG		 2263 struct ata_port *ap = host->ports[i];
2264 void __iomem *port_mmio = ahci_port_base(ap);
4447d351 2265
cbcdd875
TH		 2266 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2267 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2268 0x100 + ap->port_no * 0x80, "port");
2269
31556594
KCA		 2270 /* set initial link pm policy */
2271 ap->pm_policy = NOT_AVAILABLE;
2272
dab632e8 2273 /* standard SATA port setup */
203ef6c4 2274 if (hpriv->port_map & (1 << i))
4447d351 2275 ap->ioaddr.cmd_addr = port_mmio;
dab632e8
JG		 2276
2277 /* disabled/not-implemented port */
2278 else
2279 ap->ops = &ata_dummy_port_ops;
4447d351 2280 }
d447df14 2281
edc93052
TH		 2282 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2283 ahci_p5wdh_workaround(host);
2284
4447d351
TH		 2285 /* initialize adapter */
2286 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2287 if (rc)
24dc5f33 2288 return rc;
1da177e4 2289
4447d351
TH		 2290 rc = ahci_reset_controller(host);
2291 if (rc)
2292 return rc;
1da177e4 2293
4447d351
TH		 2294 ahci_init_controller(host);
2295 ahci_print_info(host);
1da177e4 2296
4447d351
TH		 2297 pci_set_master(pdev);
2298 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2299 &ahci_sht);
907f4678 2300}
1da177e4
LT		 2301
2302static int __init ahci_init(void)
2303{
b7887196 2304 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2305}
2306
1da177e4
LT		 2307static void __exit ahci_exit(void)
2308{
2309 pci_unregister_driver(&ahci_pci_driver);
2310}
2311
2312
2313MODULE_AUTHOR("Jeff Garzik");
2314MODULE_DESCRIPTION("AHCI SATA low-level driver");
2315MODULE_LICENSE("GPL");
2316MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2317MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2318
2319module_init(ahci_init);
2320module_exit(ahci_exit);
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