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[net-next-2.6.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
1da177e4 44#include <scsi/scsi_host.h>
193515d5 45#include <scsi/scsi_cmnd.h>
1da177e4 46#include <linux/libata.h>
1da177e4
LT		 47
48#define DRV_NAME "ahci"
cb48cab7 49#define DRV_VERSION "2.1"
1da177e4
LT		 50
51
52enum {
53 AHCI_PCI_BAR = 5,
648a88be 54 AHCI_MAX_PORTS = 32,
1da177e4
LT		 55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
12fad3f9 58 AHCI_MAX_CMDS = 32,
dd410ff1 59 AHCI_CMD_SZ = 32,
12fad3f9 60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 61 AHCI_RX_FIS_SZ = 256,
a0ea7328 62 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
4b10e559 71 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
648a88be
TH		 80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
55a61604 83 board_ahci_sb600 = 4,
1da177e4
LT		 84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
0be0aa98 98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
22b49985 99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
979db803 101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 103
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140
78cd52d0
TH		 141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
142 PORT_IRQ_IF_ERR |
143 PORT_IRQ_CONNECT |
4296971d 144 PORT_IRQ_PHYRDY |
78cd52d0
TH		 145 PORT_IRQ_UNK_FIS,
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_TF_ERR |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 152
153 /* PORT_CMD bits */
02eaa666 154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 158 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162
0be0aa98 163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 167
bf2af2a2 168 /* ap->flags bits */
4aeb0e32
TH		 169 AHCI_FLAG_NO_NCQ = (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
648a88be 171 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
55a61604 172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
1da177e4
LT		 173};
174
175struct ahci_cmd_hdr {
176 u32 opts;
177 u32 status;
178 u32 tbl_addr;
179 u32 tbl_addr_hi;
180 u32 reserved[4];
181};
182
183struct ahci_sg {
184 u32 addr;
185 u32 addr_hi;
186 u32 reserved;
187 u32 flags_size;
188};
189
190struct ahci_host_priv {
d447df14
TH		 191 u32 cap; /* cap to use */
192 u32 port_map; /* port map to use */
193 u32 saved_cap; /* saved initial cap */
194 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 195};
196
197struct ahci_port_priv {
198 struct ahci_cmd_hdr *cmd_slot;
199 dma_addr_t cmd_slot_dma;
200 void *cmd_tbl;
201 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 202 void *rx_fis;
203 dma_addr_t rx_fis_dma;
0291f95f 204 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 205 unsigned int ncq_saw_d2h:1;
206 unsigned int ncq_saw_dmas:1;
afb2d552 207 unsigned int ncq_saw_sdb:1;
1da177e4
LT		 208};
209
210static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
211static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
212static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 213static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
7d12e780 214static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
1da177e4 215static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 216static int ahci_port_start(struct ata_port *ap);
217static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 218static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
219static void ahci_qc_prep(struct ata_queued_cmd *qc);
220static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 221static void ahci_freeze(struct ata_port *ap);
222static void ahci_thaw(struct ata_port *ap);
223static void ahci_error_handler(struct ata_port *ap);
ad616ffb 224static void ahci_vt8251_error_handler(struct ata_port *ap);
78cd52d0 225static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
438ac6d5 226#ifdef CONFIG_PM
c1332875
TH		 227static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
228static int ahci_port_resume(struct ata_port *ap);
229static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
230static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 231#endif
1da177e4 232
193515d5 233static struct scsi_host_template ahci_sht = {
1da177e4
LT		 234 .module = THIS_MODULE,
235 .name = DRV_NAME,
236 .ioctl = ata_scsi_ioctl,
237 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 238 .change_queue_depth = ata_scsi_change_queue_depth,
239 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 240 .this_id = ATA_SHT_THIS_ID,
241 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 242 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
243 .emulated = ATA_SHT_EMULATED,
244 .use_clustering = AHCI_USE_CLUSTERING,
245 .proc_name = DRV_NAME,
246 .dma_boundary = AHCI_DMA_BOUNDARY,
247 .slave_configure = ata_scsi_slave_config,
ccf68c34 248 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 249 .bios_param = ata_std_bios_param,
438ac6d5 250#ifdef CONFIG_PM
c1332875
TH		 251 .suspend = ata_scsi_device_suspend,
252 .resume = ata_scsi_device_resume,
438ac6d5 253#endif
1da177e4
LT		 254};
255
057ace5e 256static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 257 .port_disable = ata_port_disable,
258
259 .check_status = ahci_check_status,
260 .check_altstatus = ahci_check_status,
1da177e4
LT		 261 .dev_select = ata_noop_dev_select,
262
263 .tf_read = ahci_tf_read,
264
1da177e4
LT		 265 .qc_prep = ahci_qc_prep,
266 .qc_issue = ahci_qc_issue,
267
1da177e4
LT		 268 .irq_handler = ahci_interrupt,
269 .irq_clear = ahci_irq_clear,
246ce3b6
AI		 270 .irq_on = ata_dummy_irq_on,
271 .irq_ack = ata_dummy_irq_ack,
1da177e4
LT		 272
273 .scr_read = ahci_scr_read,
274 .scr_write = ahci_scr_write,
275
78cd52d0
TH		 276 .freeze = ahci_freeze,
277 .thaw = ahci_thaw,
278
279 .error_handler = ahci_error_handler,
280 .post_internal_cmd = ahci_post_internal_cmd,
281
438ac6d5 282#ifdef CONFIG_PM
c1332875
TH		 283 .port_suspend = ahci_port_suspend,
284 .port_resume = ahci_port_resume,
438ac6d5 285#endif
c1332875 286
1da177e4
LT		 287 .port_start = ahci_port_start,
288 .port_stop = ahci_port_stop,
1da177e4
LT		 289};
290
ad616ffb
TH		 291static const struct ata_port_operations ahci_vt8251_ops = {
292 .port_disable = ata_port_disable,
293
294 .check_status = ahci_check_status,
295 .check_altstatus = ahci_check_status,
296 .dev_select = ata_noop_dev_select,
297
298 .tf_read = ahci_tf_read,
299
300 .qc_prep = ahci_qc_prep,
301 .qc_issue = ahci_qc_issue,
302
303 .irq_handler = ahci_interrupt,
304 .irq_clear = ahci_irq_clear,
246ce3b6
AI		 305 .irq_on = ata_dummy_irq_on,
306 .irq_ack = ata_dummy_irq_ack,
ad616ffb
TH		 307
308 .scr_read = ahci_scr_read,
309 .scr_write = ahci_scr_write,
310
311 .freeze = ahci_freeze,
312 .thaw = ahci_thaw,
313
314 .error_handler = ahci_vt8251_error_handler,
315 .post_internal_cmd = ahci_post_internal_cmd,
316
438ac6d5 317#ifdef CONFIG_PM
ad616ffb
TH		 318 .port_suspend = ahci_port_suspend,
319 .port_resume = ahci_port_resume,
438ac6d5 320#endif
ad616ffb
TH		 321
322 .port_start = ahci_port_start,
323 .port_stop = ahci_port_stop,
324};
325
98ac62de 326static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 327 /* board_ahci */
328 {
329 .sht = &ahci_sht,
cca3974e 330 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4296971d
TH		 331 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
332 ATA_FLAG_SKIP_D2H_BSY,
7da79312 333 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 334 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
335 .port_ops = &ahci_ops,
336 },
648a88be
TH		 337 /* board_ahci_pi */
338 {
339 .sht = &ahci_sht,
340 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
341 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
342 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
343 .pio_mask = 0x1f, /* pio0-4 */
344 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
345 .port_ops = &ahci_ops,
346 },
bf2af2a2
BJ		 347 /* board_ahci_vt8251 */
348 {
349 .sht = &ahci_sht,
cca3974e 350 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bf2af2a2 351 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
ad616ffb
TH		 352 ATA_FLAG_SKIP_D2H_BSY |
353 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
bf2af2a2
BJ		 354 .pio_mask = 0x1f, /* pio0-4 */
355 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
ad616ffb 356 .port_ops = &ahci_vt8251_ops,
bf2af2a2 357 },
41669553
TH		 358 /* board_ahci_ign_iferr */
359 {
360 .sht = &ahci_sht,
361 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
362 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
363 ATA_FLAG_SKIP_D2H_BSY |
364 AHCI_FLAG_IGN_IRQ_IF_ERR,
365 .pio_mask = 0x1f, /* pio0-4 */
366 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
367 .port_ops = &ahci_ops,
368 },
55a61604
CH		 369 /* board_ahci_sb600 */
370 {
371 .sht = &ahci_sht,
372 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
373 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
374 ATA_FLAG_SKIP_D2H_BSY |
375 AHCI_FLAG_IGN_SERR_INTERNAL,
376 .pio_mask = 0x1f, /* pio0-4 */
377 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
378 .port_ops = &ahci_ops,
379 },
380
1da177e4
LT		 381};
382
3b7d697d 383static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 384 /* Intel */
54bb3a94
JG		 385 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
386 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
387 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
388 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
389 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 390 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 391 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
392 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
393 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
394 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
648a88be
TH		 395 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
396 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
397 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
398 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
399 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
400 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
401 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
402 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
404 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
405 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
406 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
407 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
8af12cdb 408 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
648a88be
TH		 409 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
410 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
411 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
fe7fa31a 412
e34bb370
TH		 413 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
414 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
415 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 416
417 /* ATI */
c65ec1c2 418 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
fe7fa31a
JG		 419
420 /* VIA */
54bb3a94 421 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 422
423 /* NVIDIA */
54bb3a94
JG		 424 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 428 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 436 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
fe7fa31a 444
95916edd 445 /* SiS */
54bb3a94
JG		 446 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
447 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
448 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 449
415ae2b5
JG		 450 /* Generic, PCI class code for AHCI */
451 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 452 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 453
1da177e4
LT		 454 { } /* terminate list */
455};
456
457
458static struct pci_driver ahci_pci_driver = {
459 .name = DRV_NAME,
460 .id_table = ahci_pci_tbl,
461 .probe = ahci_init_one,
24dc5f33 462 .remove = ata_pci_remove_one,
438ac6d5 463#ifdef CONFIG_PM
c1332875
TH		 464 .suspend = ahci_pci_device_suspend,
465 .resume = ahci_pci_device_resume,
438ac6d5 466#endif
1da177e4
LT		 467};
468
469
98fa4b60
TH		 470static inline int ahci_nr_ports(u32 cap)
471{
472 return (cap & 0x1f) + 1;
473}
474
0d5ff566
TH		 475static inline void __iomem *ahci_port_base(void __iomem *base,
476 unsigned int port)
1da177e4
LT		 477{
478 return base + 0x100 + (port * 0x80);
479}
480
d447df14
TH		 481/**
482 * ahci_save_initial_config - Save and fixup initial config values
483 * @probe_ent: probe_ent of target device
484 *
485 * Some registers containing configuration info might be setup by
486 * BIOS and might be cleared on reset. This function saves the
487 * initial values of those registers into @hpriv such that they
488 * can be restored after controller reset.
489 *
490 * If inconsistent, config values are fixed up by this function.
491 *
492 * LOCKING:
493 * None.
494 */
495static void ahci_save_initial_config(struct ata_probe_ent *probe_ent)
496{
497 struct ahci_host_priv *hpriv = probe_ent->private_data;
498 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
499 u32 cap, port_map;
17199b18 500 int i;
d447df14
TH		 501
502 /* Values prefixed with saved_ are written back to host after
503 * reset. Values without are used for driver operation.
504 */
505 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
506 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
507
508 /* fixup zero port_map */
509 if (!port_map) {
510 port_map = (1 << ahci_nr_ports(hpriv->cap)) - 1;
511 dev_printk(KERN_WARNING, probe_ent->dev,
512 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
513
514 /* write the fixed up value to the PI register */
515 hpriv->saved_port_map = port_map;
516 }
517
17199b18
TH		 518 /* cross check port_map and cap.n_ports */
519 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
520 u32 tmp_port_map = port_map;
521 int n_ports = ahci_nr_ports(cap);
522
523 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
524 if (tmp_port_map & (1 << i)) {
525 n_ports--;
526 tmp_port_map &= ~(1 << i);
527 }
528 }
529
530 /* Whine if inconsistent. No need to update cap.
531 * port_map is used to determine number of ports.
532 */
533 if (n_ports || tmp_port_map)
534 dev_printk(KERN_WARNING, probe_ent->dev,
535 "nr_ports (%u) and implemented port map "
536 "(0x%x) don't match\n",
537 ahci_nr_ports(cap), port_map);
538 } else {
539 /* fabricate port_map from cap.nr_ports */
540 port_map = (1 << ahci_nr_ports(cap)) - 1;
541 }
542
d447df14
TH		 543 /* record values to use during operation */
544 hpriv->cap = cap;
545 hpriv->port_map = port_map;
546}
547
548/**
549 * ahci_restore_initial_config - Restore initial config
550 * @mmio: MMIO base for the host
551 * @hpriv: host private data
552 *
553 * Restore initial config stored by ahci_save_initial_config().
554 *
555 * LOCKING:
556 * None.
557 */
558static void ahci_restore_initial_config(void __iomem *mmio,
559 struct ahci_host_priv *hpriv)
560{
561 writel(hpriv->saved_cap, mmio + HOST_CAP);
562 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
563 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
564}
565
1da177e4
LT		 566static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
567{
568 unsigned int sc_reg;
569
570 switch (sc_reg_in) {
571 case SCR_STATUS: sc_reg = 0; break;
572 case SCR_CONTROL: sc_reg = 1; break;
573 case SCR_ERROR: sc_reg = 2; break;
574 case SCR_ACTIVE: sc_reg = 3; break;
575 default:
576 return 0xffffffffU;
577 }
578
0d5ff566 579 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 580}
581
582
583static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
584 u32 val)
585{
586 unsigned int sc_reg;
587
588 switch (sc_reg_in) {
589 case SCR_STATUS: sc_reg = 0; break;
590 case SCR_CONTROL: sc_reg = 1; break;
591 case SCR_ERROR: sc_reg = 2; break;
592 case SCR_ACTIVE: sc_reg = 3; break;
593 default:
594 return;
595 }
596
0d5ff566 597 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 598}
599
9f592056 600static void ahci_start_engine(void __iomem *port_mmio)
7c76d1e8 601{
7c76d1e8
TH		 602 u32 tmp;
603
d8fcd116 604 /* start DMA */
9f592056 605 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 606 tmp |= PORT_CMD_START;
607 writel(tmp, port_mmio + PORT_CMD);
608 readl(port_mmio + PORT_CMD); /* flush */
609}
610
254950cd
TH		 611static int ahci_stop_engine(void __iomem *port_mmio)
612{
613 u32 tmp;
614
615 tmp = readl(port_mmio + PORT_CMD);
616
d8fcd116 617 /* check if the HBA is idle */
254950cd
TH		 618 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
619 return 0;
620
d8fcd116 621 /* setting HBA to idle */
254950cd
TH		 622 tmp &= ~PORT_CMD_START;
623 writel(tmp, port_mmio + PORT_CMD);
624
d8fcd116 625 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 626 tmp = ata_wait_register(port_mmio + PORT_CMD,
627 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 628 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 629 return -EIO;
630
631 return 0;
632}
633
0be0aa98
TH		 634static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
635 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
636{
637 u32 tmp;
638
639 /* set FIS registers */
640 if (cap & HOST_CAP_64)
641 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
642 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
643
644 if (cap & HOST_CAP_64)
645 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
646 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
647
648 /* enable FIS reception */
649 tmp = readl(port_mmio + PORT_CMD);
650 tmp |= PORT_CMD_FIS_RX;
651 writel(tmp, port_mmio + PORT_CMD);
652
653 /* flush */
654 readl(port_mmio + PORT_CMD);
655}
656
657static int ahci_stop_fis_rx(void __iomem *port_mmio)
658{
659 u32 tmp;
660
661 /* disable FIS reception */
662 tmp = readl(port_mmio + PORT_CMD);
663 tmp &= ~PORT_CMD_FIS_RX;
664 writel(tmp, port_mmio + PORT_CMD);
665
666 /* wait for completion, spec says 500ms, give it 1000 */
667 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
668 PORT_CMD_FIS_ON, 10, 1000);
669 if (tmp & PORT_CMD_FIS_ON)
670 return -EBUSY;
671
672 return 0;
673}
674
675static void ahci_power_up(void __iomem *port_mmio, u32 cap)
676{
677 u32 cmd;
678
679 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
680
681 /* spin up device */
682 if (cap & HOST_CAP_SSS) {
683 cmd |= PORT_CMD_SPIN_UP;
684 writel(cmd, port_mmio + PORT_CMD);
685 }
686
687 /* wake up link */
688 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
689}
690
438ac6d5 691#ifdef CONFIG_PM
0be0aa98
TH		 692static void ahci_power_down(void __iomem *port_mmio, u32 cap)
693{
694 u32 cmd, scontrol;
695
07c53dac
TH		 696 if (!(cap & HOST_CAP_SSS))
697 return;
0be0aa98 698
07c53dac
TH		 699 /* put device into listen mode, first set PxSCTL.DET to 0 */
700 scontrol = readl(port_mmio + PORT_SCR_CTL);
701 scontrol &= ~0xf;
702 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 703
07c53dac
TH		 704 /* then set PxCMD.SUD to 0 */
705 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
706 cmd &= ~PORT_CMD_SPIN_UP;
707 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 708}
438ac6d5 709#endif
0be0aa98
TH		 710
711static void ahci_init_port(void __iomem *port_mmio, u32 cap,
712 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
713{
0be0aa98
TH		 714 /* enable FIS reception */
715 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
716
717 /* enable DMA */
718 ahci_start_engine(port_mmio);
719}
720
721static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
722{
723 int rc;
724
725 /* disable DMA */
726 rc = ahci_stop_engine(port_mmio);
727 if (rc) {
728 *emsg = "failed to stop engine";
729 return rc;
730 }
731
732 /* disable FIS reception */
733 rc = ahci_stop_fis_rx(port_mmio);
734 if (rc) {
735 *emsg = "failed stop FIS RX";
736 return rc;
737 }
738
0be0aa98
TH		 739 return 0;
740}
741
d447df14
TH		 742static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev,
743 struct ahci_host_priv *hpriv)
d91542c1 744{
d447df14 745 u32 tmp;
d91542c1
TH		 746
747 /* global controller reset */
748 tmp = readl(mmio + HOST_CTL);
749 if ((tmp & HOST_RESET) == 0) {
750 writel(tmp | HOST_RESET, mmio + HOST_CTL);
751 readl(mmio + HOST_CTL); /* flush */
752 }
753
754 /* reset must complete within 1 second, or
755 * the hardware should be considered fried.
756 */
757 ssleep(1);
758
759 tmp = readl(mmio + HOST_CTL);
760 if (tmp & HOST_RESET) {
761 dev_printk(KERN_ERR, &pdev->dev,
762 "controller reset failed (0x%x)\n", tmp);
763 return -EIO;
764 }
765
98fa4b60 766 /* turn on AHCI mode */
d91542c1
TH		 767 writel(HOST_AHCI_EN, mmio + HOST_CTL);
768 (void) readl(mmio + HOST_CTL); /* flush */
98fa4b60 769
d447df14
TH		 770 /* some registers might be cleared on reset. restore initial values */
771 ahci_restore_initial_config(mmio, hpriv);
d91542c1
TH		 772
773 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
774 u16 tmp16;
775
776 /* configure PCS */
777 pci_read_config_word(pdev, 0x92, &tmp16);
778 tmp16 |= 0xf;
779 pci_write_config_word(pdev, 0x92, tmp16);
780 }
781
782 return 0;
783}
784
785static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
648a88be
TH		 786 int n_ports, unsigned int port_flags,
787 struct ahci_host_priv *hpriv)
d91542c1
TH		 788{
789 int i, rc;
790 u32 tmp;
791
792 for (i = 0; i < n_ports; i++) {
793 void __iomem *port_mmio = ahci_port_base(mmio, i);
794 const char *emsg = NULL;
795
648a88be
TH		 796 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
797 !(hpriv->port_map & (1 << i)))
d91542c1 798 continue;
d91542c1
TH		 799
800 /* make sure port is not active */
648a88be 801 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
d91542c1
TH		 802 if (rc)
803 dev_printk(KERN_WARNING, &pdev->dev,
804 "%s (%d)\n", emsg, rc);
805
806 /* clear SError */
807 tmp = readl(port_mmio + PORT_SCR_ERR);
808 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
809 writel(tmp, port_mmio + PORT_SCR_ERR);
810
f4b5cc87 811 /* clear port IRQ */
d91542c1
TH		 812 tmp = readl(port_mmio + PORT_IRQ_STAT);
813 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
814 if (tmp)
815 writel(tmp, port_mmio + PORT_IRQ_STAT);
816
817 writel(1 << i, mmio + HOST_IRQ_STAT);
d91542c1
TH		 818 }
819
820 tmp = readl(mmio + HOST_CTL);
821 VPRINTK("HOST_CTL 0x%x\n", tmp);
822 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
823 tmp = readl(mmio + HOST_CTL);
824 VPRINTK("HOST_CTL 0x%x\n", tmp);
825}
826
422b7595 827static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 828{
0d5ff566 829 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1da177e4 830 struct ata_taskfile tf;
422b7595
TH		 831 u32 tmp;
832
833 tmp = readl(port_mmio + PORT_SIG);
834 tf.lbah = (tmp >> 24) & 0xff;
835 tf.lbam = (tmp >> 16) & 0xff;
836 tf.lbal = (tmp >> 8) & 0xff;
837 tf.nsect = (tmp) & 0xff;
838
839 return ata_dev_classify(&tf);
840}
841
12fad3f9
TH		 842static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
843 u32 opts)
cc9278ed 844{
12fad3f9
TH		 845 dma_addr_t cmd_tbl_dma;
846
847 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
848
849 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
850 pp->cmd_slot[tag].status = 0;
851 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
852 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 853}
854
bf2af2a2 855static int ahci_clo(struct ata_port *ap)
4658f79b 856{
0d5ff566 857 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 858 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2
BJ		 859 u32 tmp;
860
861 if (!(hpriv->cap & HOST_CAP_CLO))
862 return -EOPNOTSUPP;
863
864 tmp = readl(port_mmio + PORT_CMD);
865 tmp |= PORT_CMD_CLO;
866 writel(tmp, port_mmio + PORT_CMD);
867
868 tmp = ata_wait_register(port_mmio + PORT_CMD,
869 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
870 if (tmp & PORT_CMD_CLO)
871 return -EIO;
872
873 return 0;
874}
875
876static int ahci_softreset(struct ata_port *ap, unsigned int *class)
877{
4658f79b 878 struct ahci_port_priv *pp = ap->private_data;
0d5ff566 879 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4658f79b
TH		 880 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
881 const u32 cmd_fis_len = 5; /* five dwords */
882 const char *reason = NULL;
883 struct ata_taskfile tf;
75fe1806 884 u32 tmp;
4658f79b
TH		 885 u8 *fis;
886 int rc;
887
888 DPRINTK("ENTER\n");
889
81952c54 890 if (ata_port_offline(ap)) {
c2a65852
TH		 891 DPRINTK("PHY reports no device\n");
892 *class = ATA_DEV_NONE;
893 return 0;
894 }
895
4658f79b 896 /* prepare for SRST (AHCI-1.1 10.4.1) */
5457f219 897 rc = ahci_stop_engine(port_mmio);
4658f79b
TH		 898 if (rc) {
899 reason = "failed to stop engine";
900 goto fail_restart;
901 }
902
903 /* check BUSY/DRQ, perform Command List Override if necessary */
1244a19c 904 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 905 rc = ahci_clo(ap);
4658f79b 906
bf2af2a2
BJ		 907 if (rc == -EOPNOTSUPP) {
908 reason = "port busy but CLO unavailable";
909 goto fail_restart;
910 } else if (rc) {
911 reason = "port busy but CLO failed";
4658f79b
TH		 912 goto fail_restart;
913 }
914 }
915
916 /* restart engine */
5457f219 917 ahci_start_engine(port_mmio);
4658f79b 918
3373efd8 919 ata_tf_init(ap->device, &tf);
4658f79b
TH		 920 fis = pp->cmd_tbl;
921
922 /* issue the first D2H Register FIS */
12fad3f9
TH		 923 ahci_fill_cmd_slot(pp, 0,
924 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 925
926 tf.ctl |= ATA_SRST;
927 ata_tf_to_fis(&tf, fis, 0);
928 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
929
930 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 931
75fe1806
TH		 932 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
933 if (tmp & 0x1) {
4658f79b
TH		 934 rc = -EIO;
935 reason = "1st FIS failed";
936 goto fail;
937 }
938
939 /* spec says at least 5us, but be generous and sleep for 1ms */
940 msleep(1);
941
942 /* issue the second D2H Register FIS */
12fad3f9 943 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 944
945 tf.ctl &= ~ATA_SRST;
946 ata_tf_to_fis(&tf, fis, 0);
947 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
948
949 writel(1, port_mmio + PORT_CMD_ISSUE);
950 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
951
952 /* spec mandates ">= 2ms" before checking status.
953 * We wait 150ms, because that was the magic delay used for
954 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
955 * between when the ATA command register is written, and then
956 * status is checked. Because waiting for "a while" before
957 * checking status is fine, post SRST, we perform this magic
958 * delay here as well.
959 */
960 msleep(150);
961
962 *class = ATA_DEV_NONE;
81952c54 963 if (ata_port_online(ap)) {
4658f79b
TH		 964 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
965 rc = -EIO;
966 reason = "device not ready";
967 goto fail;
968 }
969 *class = ahci_dev_classify(ap);
970 }
971
972 DPRINTK("EXIT, class=%u\n", *class);
973 return 0;
974
975 fail_restart:
5457f219 976 ahci_start_engine(port_mmio);
4658f79b 977 fail:
f15a1daf 978 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 979 return rc;
980}
981
2bf2cb26 982static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 983{
4296971d
TH		 984 struct ahci_port_priv *pp = ap->private_data;
985 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
986 struct ata_taskfile tf;
0d5ff566 987 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
5457f219 988 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
4bd00f6a
TH		 989 int rc;
990
991 DPRINTK("ENTER\n");
1da177e4 992
5457f219 993 ahci_stop_engine(port_mmio);
4296971d
TH		 994
995 /* clear D2H reception area to properly wait for D2H FIS */
996 ata_tf_init(ap->device, &tf);
dfd7a3db 997 tf.command = 0x80;
4296971d
TH		 998 ata_tf_to_fis(&tf, d2h_fis, 0);
999
2bf2cb26 1000 rc = sata_std_hardreset(ap, class);
4296971d 1001
5457f219 1002 ahci_start_engine(port_mmio);
1da177e4 1003
81952c54 1004 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 1005 *class = ahci_dev_classify(ap);
1006 if (*class == ATA_DEV_UNKNOWN)
1007 *class = ATA_DEV_NONE;
1da177e4 1008
4bd00f6a
TH		 1009 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1010 return rc;
1011}
1012
ad616ffb
TH		 1013static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
1014{
0d5ff566 1015 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
ad616ffb
TH		 1016 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1017 int rc;
1018
1019 DPRINTK("ENTER\n");
1020
1021 ahci_stop_engine(port_mmio);
1022
1023 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
1024
1025 /* vt8251 needs SError cleared for the port to operate */
1026 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
1027
1028 ahci_start_engine(port_mmio);
1029
1030 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1031
1032 /* vt8251 doesn't clear BSY on signature FIS reception,
1033 * request follow-up softreset.
1034 */
1035 return rc ?: -EAGAIN;
1036}
1037
4bd00f6a
TH		 1038static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1039{
0d5ff566 1040 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
4bd00f6a
TH		 1041 u32 new_tmp, tmp;
1042
1043 ata_std_postreset(ap, class);
02eaa666
JG		 1044
1045 /* Make sure port's ATAPI bit is set appropriately */
1046 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1047 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1048 new_tmp |= PORT_CMD_ATAPI;
1049 else
1050 new_tmp &= ~PORT_CMD_ATAPI;
1051 if (new_tmp != tmp) {
1052 writel(new_tmp, port_mmio + PORT_CMD);
1053 readl(port_mmio + PORT_CMD); /* flush */
1054 }
1da177e4
LT		 1055}
1056
1057static u8 ahci_check_status(struct ata_port *ap)
1058{
0d5ff566 1059 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1060
1061 return readl(mmio + PORT_TFDATA) & 0xFF;
1062}
1063
1da177e4
LT		 1064static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1065{
1066 struct ahci_port_priv *pp = ap->private_data;
1067 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1068
1069 ata_tf_from_fis(d2h_fis, tf);
1070}
1071
12fad3f9 1072static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1073{
cedc9a47
JG		 1074 struct scatterlist *sg;
1075 struct ahci_sg *ahci_sg;
828d09de 1076 unsigned int n_sg = 0;
1da177e4
LT		 1077
1078 VPRINTK("ENTER\n");
1079
1080 /*
1081 * Next, the S/G list.
1082 */
12fad3f9 1083 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 1084 ata_for_each_sg(sg, qc) {
1085 dma_addr_t addr = sg_dma_address(sg);
1086 u32 sg_len = sg_dma_len(sg);
1087
1088 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1089 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1090 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 1091
cedc9a47 1092 ahci_sg++;
828d09de 1093 n_sg++;
1da177e4 1094 }
828d09de
JG		 1095
1096 return n_sg;
1da177e4
LT		 1097}
1098
1099static void ahci_qc_prep(struct ata_queued_cmd *qc)
1100{
a0ea7328
JG		 1101 struct ata_port *ap = qc->ap;
1102 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 1103 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 1104 void *cmd_tbl;
1da177e4
LT		 1105 u32 opts;
1106 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1107 unsigned int n_elem;
1da177e4 1108
1da177e4
LT		 1109 /*
1110 * Fill in command table information. First, the header,
1111 * a SATA Register - Host to Device command FIS.
1112 */
12fad3f9
TH		 1113 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1114
1115 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 1116 if (is_atapi) {
12fad3f9
TH		 1117 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1118 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1119 }
1da177e4 1120
cc9278ed
TH		 1121 n_elem = 0;
1122 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1123 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1124
cc9278ed
TH		 1125 /*
1126 * Fill in command slot information.
1127 */
1128 opts = cmd_fis_len | n_elem << 16;
1129 if (qc->tf.flags & ATA_TFLAG_WRITE)
1130 opts |= AHCI_CMD_WRITE;
1131 if (is_atapi)
4b10e559 1132 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1133
12fad3f9 1134 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1135}
1136
78cd52d0 1137static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1138{
78cd52d0
TH		 1139 struct ahci_port_priv *pp = ap->private_data;
1140 struct ata_eh_info *ehi = &ap->eh_info;
1141 unsigned int err_mask = 0, action = 0;
1142 struct ata_queued_cmd *qc;
1143 u32 serror;
1da177e4 1144
78cd52d0 1145 ata_ehi_clear_desc(ehi);
1da177e4 1146
78cd52d0
TH		 1147 /* AHCI needs SError cleared; otherwise, it might lock up */
1148 serror = ahci_scr_read(ap, SCR_ERROR);
1149 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 1150
78cd52d0
TH		 1151 /* analyze @irq_stat */
1152 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1153
41669553
TH		 1154 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1155 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1156 irq_stat &= ~PORT_IRQ_IF_ERR;
1157
55a61604 1158 if (irq_stat & PORT_IRQ_TF_ERR) {
78cd52d0 1159 err_mask |= AC_ERR_DEV;
55a61604
CH		 1160 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1161 serror &= ~SERR_INTERNAL;
1162 }
78cd52d0
TH		 1163
1164 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1165 err_mask |= AC_ERR_HOST_BUS;
1166 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 1167 }
1168
78cd52d0
TH		 1169 if (irq_stat & PORT_IRQ_IF_ERR) {
1170 err_mask |= AC_ERR_ATA_BUS;
1171 action |= ATA_EH_SOFTRESET;
1172 ata_ehi_push_desc(ehi, ", interface fatal error");
1173 }
1da177e4 1174
78cd52d0 1175 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 1176 ata_ehi_hotplugged(ehi);
78cd52d0
TH		 1177 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1178 "connection status changed" : "PHY RDY changed");
1179 }
1180
1181 if (irq_stat & PORT_IRQ_UNK_FIS) {
1182 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 1183
78cd52d0
TH		 1184 err_mask |= AC_ERR_HSM;
1185 action |= ATA_EH_SOFTRESET;
1186 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1187 unk[0], unk[1], unk[2], unk[3]);
1188 }
1da177e4 1189
78cd52d0
TH		 1190 /* okay, let's hand over to EH */
1191 ehi->serror |= serror;
1192 ehi->action |= action;
b8f6153e 1193
1da177e4 1194 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 1195 if (qc)
1196 qc->err_mask |= err_mask;
1197 else
1198 ehi->err_mask |= err_mask;
a72ec4ce 1199
78cd52d0
TH		 1200 if (irq_stat & PORT_IRQ_FREEZE)
1201 ata_port_freeze(ap);
1202 else
1203 ata_port_abort(ap);
1da177e4
LT		 1204}
1205
78cd52d0 1206static void ahci_host_intr(struct ata_port *ap)
1da177e4 1207{
0d5ff566 1208 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
ea6ba10b 1209 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
12fad3f9 1210 struct ata_eh_info *ehi = &ap->eh_info;
0291f95f 1211 struct ahci_port_priv *pp = ap->private_data;
12fad3f9 1212 u32 status, qc_active;
0291f95f 1213 int rc, known_irq = 0;
1da177e4
LT		 1214
1215 status = readl(port_mmio + PORT_IRQ_STAT);
1216 writel(status, port_mmio + PORT_IRQ_STAT);
1217
78cd52d0
TH		 1218 if (unlikely(status & PORT_IRQ_ERROR)) {
1219 ahci_error_intr(ap, status);
1220 return;
1da177e4
LT		 1221 }
1222
12fad3f9
TH		 1223 if (ap->sactive)
1224 qc_active = readl(port_mmio + PORT_SCR_ACT);
1225 else
1226 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1227
1228 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1229 if (rc > 0)
1230 return;
1231 if (rc < 0) {
1232 ehi->err_mask |= AC_ERR_HSM;
1233 ehi->action |= ATA_EH_SOFTRESET;
1234 ata_port_freeze(ap);
1235 return;
1da177e4
LT		 1236 }
1237
2a3917a8
TH		 1238 /* hmmm... a spurious interupt */
1239
0291f95f
TH		 1240 /* if !NCQ, ignore. No modern ATA device has broken HSM
1241 * implementation for non-NCQ commands.
1242 */
1243 if (!ap->sactive)
12fad3f9
TH		 1244 return;
1245
0291f95f
TH		 1246 if (status & PORT_IRQ_D2H_REG_FIS) {
1247 if (!pp->ncq_saw_d2h)
1248 ata_port_printk(ap, KERN_INFO,
1249 "D2H reg with I during NCQ, "
1250 "this message won't be printed again\n");
1251 pp->ncq_saw_d2h = 1;
1252 known_irq = 1;
1253 }
1254
1255 if (status & PORT_IRQ_DMAS_FIS) {
1256 if (!pp->ncq_saw_dmas)
1257 ata_port_printk(ap, KERN_INFO,
1258 "DMAS FIS during NCQ, "
1259 "this message won't be printed again\n");
1260 pp->ncq_saw_dmas = 1;
1261 known_irq = 1;
1262 }
1263
a2bbd0c9 1264 if (status & PORT_IRQ_SDB_FIS) {
04d4f7a1 1265 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
0291f95f 1266
afb2d552
TH		 1267 if (le32_to_cpu(f[1])) {
1268 /* SDB FIS containing spurious completions
1269 * might be dangerous, whine and fail commands
1270 * with HSM violation. EH will turn off NCQ
1271 * after several such failures.
1272 */
1273 ata_ehi_push_desc(ehi,
1274 "spurious completions during NCQ "
1275 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1276 readl(port_mmio + PORT_CMD_ISSUE),
1277 readl(port_mmio + PORT_SCR_ACT),
1278 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1279 ehi->err_mask |= AC_ERR_HSM;
1280 ehi->action |= ATA_EH_SOFTRESET;
1281 ata_port_freeze(ap);
1282 } else {
1283 if (!pp->ncq_saw_sdb)
1284 ata_port_printk(ap, KERN_INFO,
1285 "spurious SDB FIS %08x:%08x during NCQ, "
1286 "this message won't be printed again\n",
1287 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1288 pp->ncq_saw_sdb = 1;
1289 }
0291f95f
TH		 1290 known_irq = 1;
1291 }
2a3917a8 1292
0291f95f 1293 if (!known_irq)
78cd52d0 1294 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
0291f95f 1295 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
12fad3f9 1296 status, ap->active_tag, ap->sactive);
1da177e4
LT		 1297}
1298
1299static void ahci_irq_clear(struct ata_port *ap)
1300{
1301 /* TODO */
1302}
1303
7d12e780 1304static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1305{
cca3974e 1306 struct ata_host *host = dev_instance;
1da177e4
LT		 1307 struct ahci_host_priv *hpriv;
1308 unsigned int i, handled = 0;
ea6ba10b 1309 void __iomem *mmio;
1da177e4
LT		 1310 u32 irq_stat, irq_ack = 0;
1311
1312 VPRINTK("ENTER\n");
1313
cca3974e 1314 hpriv = host->private_data;
0d5ff566 1315 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1316
1317 /* sigh. 0xffffffff is a valid return from h/w */
1318 irq_stat = readl(mmio + HOST_IRQ_STAT);
1319 irq_stat &= hpriv->port_map;
1320 if (!irq_stat)
1321 return IRQ_NONE;
1322
cca3974e 1323 spin_lock(&host->lock);
1da177e4 1324
cca3974e 1325 for (i = 0; i < host->n_ports; i++) {
1da177e4 1326 struct ata_port *ap;
1da177e4 1327
67846b30
JG		 1328 if (!(irq_stat & (1 << i)))
1329 continue;
1330
cca3974e 1331 ap = host->ports[i];
67846b30 1332 if (ap) {
78cd52d0 1333 ahci_host_intr(ap);
67846b30
JG		 1334 VPRINTK("port %u\n", i);
1335 } else {
1336 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1337 if (ata_ratelimit())
cca3974e 1338 dev_printk(KERN_WARNING, host->dev,
a9524a76 1339 "interrupt on disabled port %u\n", i);
1da177e4 1340 }
67846b30
JG		 1341
1342 irq_ack |= (1 << i);
1da177e4
LT		 1343 }
1344
1345 if (irq_ack) {
1346 writel(irq_ack, mmio + HOST_IRQ_STAT);
1347 handled = 1;
1348 }
1349
cca3974e 1350 spin_unlock(&host->lock);
1da177e4
LT		 1351
1352 VPRINTK("EXIT\n");
1353
1354 return IRQ_RETVAL(handled);
1355}
1356
9a3d9eb0 1357static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1358{
1359 struct ata_port *ap = qc->ap;
0d5ff566 1360 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1da177e4 1361
12fad3f9
TH		 1362 if (qc->tf.protocol == ATA_PROT_NCQ)
1363 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1364 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1365 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1366
1367 return 0;
1368}
1369
78cd52d0
TH		 1370static void ahci_freeze(struct ata_port *ap)
1371{
0d5ff566 1372 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
78cd52d0
TH		 1373 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1374
1375 /* turn IRQ off */
1376 writel(0, port_mmio + PORT_IRQ_MASK);
1377}
1378
1379static void ahci_thaw(struct ata_port *ap)
1380{
0d5ff566 1381 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
78cd52d0
TH		 1382 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1383 u32 tmp;
1384
1385 /* clear IRQ */
1386 tmp = readl(port_mmio + PORT_IRQ_STAT);
1387 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1388 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0
TH		 1389
1390 /* turn IRQ back on */
1391 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1392}
1393
1394static void ahci_error_handler(struct ata_port *ap)
1395{
0d5ff566 1396 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
5457f219 1397 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1398
b51e9e5d 1399 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1400 /* restart engine */
5457f219 1401 ahci_stop_engine(port_mmio);
1402 ahci_start_engine(port_mmio);
78cd52d0
TH		 1403 }
1404
1405 /* perform recovery */
4aeb0e32 1406 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1407 ahci_postreset);
78cd52d0
TH		 1408}
1409
ad616ffb
TH		 1410static void ahci_vt8251_error_handler(struct ata_port *ap)
1411{
0d5ff566 1412 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
ad616ffb
TH		 1413 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1414
1415 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1416 /* restart engine */
1417 ahci_stop_engine(port_mmio);
1418 ahci_start_engine(port_mmio);
1419 }
1420
1421 /* perform recovery */
1422 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1423 ahci_postreset);
1424}
1425
78cd52d0
TH		 1426static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1427{
1428 struct ata_port *ap = qc->ap;
0d5ff566 1429 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
5457f219 1430 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
78cd52d0 1431
a51d644a 1432 if (qc->flags & ATA_QCFLAG_FAILED) {
78cd52d0 1433 /* make DMA engine forget about the failed command */
5457f219 1434 ahci_stop_engine(port_mmio);
1435 ahci_start_engine(port_mmio);
78cd52d0
TH		 1436 }
1437}
1438
438ac6d5 1439#ifdef CONFIG_PM
c1332875
TH		 1440static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1441{
cca3974e 1442 struct ahci_host_priv *hpriv = ap->host->private_data;
c1332875 1443 struct ahci_port_priv *pp = ap->private_data;
0d5ff566 1444 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1445 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1446 const char *emsg = NULL;
1447 int rc;
1448
1449 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
8e16f941
TH		 1450 if (rc == 0)
1451 ahci_power_down(port_mmio, hpriv->cap);
1452 else {
c1332875
TH		 1453 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1454 ahci_init_port(port_mmio, hpriv->cap,
1455 pp->cmd_slot_dma, pp->rx_fis_dma);
1456 }
1457
1458 return rc;
1459}
1460
1461static int ahci_port_resume(struct ata_port *ap)
1462{
1463 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1464 struct ahci_host_priv *hpriv = ap->host->private_data;
0d5ff566 1465 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1466 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1467
8e16f941 1468 ahci_power_up(port_mmio, hpriv->cap);
c1332875
TH		 1469 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1470
1471 return 0;
1472}
1473
1474static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1475{
cca3974e 1476 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1477 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1478 u32 ctl;
1479
1480 if (mesg.event == PM_EVENT_SUSPEND) {
1481 /* AHCI spec rev1.1 section 8.3.3:
1482 * Software must disable interrupts prior to requesting a
1483 * transition of the HBA to D3 state.
1484 */
1485 ctl = readl(mmio + HOST_CTL);
1486 ctl &= ~HOST_IRQ_EN;
1487 writel(ctl, mmio + HOST_CTL);
1488 readl(mmio + HOST_CTL); /* flush */
1489 }
1490
1491 return ata_pci_device_suspend(pdev, mesg);
1492}
1493
1494static int ahci_pci_device_resume(struct pci_dev *pdev)
1495{
cca3974e
JG		 1496 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1497 struct ahci_host_priv *hpriv = host->private_data;
0d5ff566 1498 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1499 int rc;
1500
553c4aa6
TH		 1501 rc = ata_pci_device_do_resume(pdev);
1502 if (rc)
1503 return rc;
c1332875
TH		 1504
1505 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
d447df14 1506 rc = ahci_reset_controller(mmio, pdev, hpriv);
c1332875
TH		 1507 if (rc)
1508 return rc;
1509
648a88be
TH		 1510 ahci_init_controller(mmio, pdev, host->n_ports,
1511 host->ports[0]->flags, hpriv);
c1332875
TH		 1512 }
1513
cca3974e 1514 ata_host_resume(host);
c1332875
TH		 1515
1516 return 0;
1517}
438ac6d5 1518#endif
c1332875 1519
254950cd
TH		 1520static int ahci_port_start(struct ata_port *ap)
1521{
cca3974e
JG		 1522 struct device *dev = ap->host->dev;
1523 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1524 struct ahci_port_priv *pp;
0d5ff566 1525 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
254950cd
TH		 1526 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1527 void *mem;
1528 dma_addr_t mem_dma;
1529 int rc;
1530
24dc5f33 1531 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 1532 if (!pp)
1533 return -ENOMEM;
254950cd
TH		 1534
1535 rc = ata_pad_alloc(ap, dev);
24dc5f33 1536 if (rc)
254950cd 1537 return rc;
254950cd 1538
24dc5f33
TH		 1539 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1540 GFP_KERNEL);
1541 if (!mem)
254950cd 1542 return -ENOMEM;
254950cd
TH		 1543 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1544
1545 /*
1546 * First item in chunk of DMA memory: 32-slot command table,
1547 * 32 bytes each in size
1548 */
1549 pp->cmd_slot = mem;
1550 pp->cmd_slot_dma = mem_dma;
1551
1552 mem += AHCI_CMD_SLOT_SZ;
1553 mem_dma += AHCI_CMD_SLOT_SZ;
1554
1555 /*
1556 * Second item: Received-FIS area
1557 */
1558 pp->rx_fis = mem;
1559 pp->rx_fis_dma = mem_dma;
1560
1561 mem += AHCI_RX_FIS_SZ;
1562 mem_dma += AHCI_RX_FIS_SZ;
1563
1564 /*
1565 * Third item: data area for storing a single command
1566 * and its scatter-gather table
1567 */
1568 pp->cmd_tbl = mem;
1569 pp->cmd_tbl_dma = mem_dma;
1570
1571 ap->private_data = pp;
1572
8e16f941
TH		 1573 /* power up port */
1574 ahci_power_up(port_mmio, hpriv->cap);
1575
0be0aa98
TH		 1576 /* initialize port */
1577 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
254950cd
TH		 1578
1579 return 0;
1580}
1581
1582static void ahci_port_stop(struct ata_port *ap)
1583{
cca3974e 1584 struct ahci_host_priv *hpriv = ap->host->private_data;
0d5ff566 1585 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
254950cd 1586 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
0be0aa98
TH		 1587 const char *emsg = NULL;
1588 int rc;
254950cd 1589
0be0aa98
TH		 1590 /* de-initialize port */
1591 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1592 if (rc)
1593 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1594}
1595
0d5ff566 1596static void ahci_setup_port(struct ata_ioports *port, void __iomem *base,
1da177e4
LT		 1597 unsigned int port_idx)
1598{
1599 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
0d5ff566 1600 base = ahci_port_base(base, port_idx);
1da177e4
LT		 1601 VPRINTK("base now==0x%lx\n", base);
1602
1603 port->cmd_addr = base;
1604 port->scr_addr = base + PORT_SCR;
1605
1606 VPRINTK("EXIT\n");
1607}
1608
1609static int ahci_host_init(struct ata_probe_ent *probe_ent)
1610{
1611 struct ahci_host_priv *hpriv = probe_ent->private_data;
1612 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
0d5ff566 1613 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
17199b18 1614 unsigned int i, using_dac;
1da177e4 1615 int rc;
1da177e4 1616
d447df14 1617 rc = ahci_reset_controller(mmio, pdev, hpriv);
d91542c1
TH		 1618 if (rc)
1619 return rc;
1da177e4 1620
17199b18
TH		 1621 probe_ent->n_ports = fls(hpriv->port_map);
1622 probe_ent->dummy_port_mask = ~hpriv->port_map;
1da177e4
LT		 1623
1624 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
17199b18 1625 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1da177e4
LT		 1626
1627 using_dac = hpriv->cap & HOST_CAP_64;
1628 if (using_dac &&
1629 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1630 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1631 if (rc) {
1632 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1633 if (rc) {
a9524a76
JG		 1634 dev_printk(KERN_ERR, &pdev->dev,
1635 "64-bit DMA enable failed\n");
1da177e4
LT		 1636 return rc;
1637 }
1638 }
1da177e4
LT		 1639 } else {
1640 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1641 if (rc) {
a9524a76
JG		 1642 dev_printk(KERN_ERR, &pdev->dev,
1643 "32-bit DMA enable failed\n");
1da177e4
LT		 1644 return rc;
1645 }
1646 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1647 if (rc) {
a9524a76
JG		 1648 dev_printk(KERN_ERR, &pdev->dev,
1649 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1650 return rc;
1651 }
1652 }
1653
d91542c1 1654 for (i = 0; i < probe_ent->n_ports; i++)
0d5ff566 1655 ahci_setup_port(&probe_ent->port[i], mmio, i);
1da177e4 1656
648a88be
TH		 1657 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1658 probe_ent->port_flags, hpriv);
1da177e4
LT		 1659
1660 pci_set_master(pdev);
1661
1662 return 0;
1663}
1664
1da177e4
LT		 1665static void ahci_print_info(struct ata_probe_ent *probe_ent)
1666{
1667 struct ahci_host_priv *hpriv = probe_ent->private_data;
1668 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
0d5ff566 1669 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1670 u32 vers, cap, impl, speed;
1671 const char *speed_s;
1672 u16 cc;
1673 const char *scc_s;
1674
1675 vers = readl(mmio + HOST_VERSION);
1676 cap = hpriv->cap;
1677 impl = hpriv->port_map;
1678
1679 speed = (cap >> 20) & 0xf;
1680 if (speed == 1)
1681 speed_s = "1.5";
1682 else if (speed == 2)
1683 speed_s = "3";
1684 else
1685 speed_s = "?";
1686
1687 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 1688 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 1689 scc_s = "IDE";
c9f89475 1690 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 1691 scc_s = "SATA";
c9f89475 1692 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 1693 scc_s = "RAID";
1694 else
1695 scc_s = "unknown";
1696
a9524a76
JG		 1697 dev_printk(KERN_INFO, &pdev->dev,
1698 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1699 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1700 ,
1da177e4
LT		 1701
1702 (vers >> 24) & 0xff,
1703 (vers >> 16) & 0xff,
1704 (vers >> 8) & 0xff,
1705 vers & 0xff,
1706
1707 ((cap >> 8) & 0x1f) + 1,
1708 (cap & 0x1f) + 1,
1709 speed_s,
1710 impl,
1711 scc_s);
1712
a9524a76
JG		 1713 dev_printk(KERN_INFO, &pdev->dev,
1714 "flags: "
1da177e4
LT		 1715 "%s%s%s%s%s%s"
1716 "%s%s%s%s%s%s%s\n"
1717 ,
1da177e4
LT		 1718
1719 cap & (1 << 31) ? "64bit " : "",
1720 cap & (1 << 30) ? "ncq " : "",
1721 cap & (1 << 28) ? "ilck " : "",
1722 cap & (1 << 27) ? "stag " : "",
1723 cap & (1 << 26) ? "pm " : "",
1724 cap & (1 << 25) ? "led " : "",
1725
1726 cap & (1 << 24) ? "clo " : "",
1727 cap & (1 << 19) ? "nz " : "",
1728 cap & (1 << 18) ? "only " : "",
1729 cap & (1 << 17) ? "pmp " : "",
1730 cap & (1 << 15) ? "pio " : "",
1731 cap & (1 << 14) ? "slum " : "",
1732 cap & (1 << 13) ? "part " : ""
1733 );
1734}
1735
24dc5f33 1736static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1737{
1738 static int printed_version;
24dc5f33
TH		 1739 unsigned int board_idx = (unsigned int) ent->driver_data;
1740 struct device *dev = &pdev->dev;
1741 struct ata_probe_ent *probe_ent;
1da177e4 1742 struct ahci_host_priv *hpriv;
1da177e4
LT		 1743 int rc;
1744
1745 VPRINTK("ENTER\n");
1746
12fad3f9
TH		 1747 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1748
1da177e4 1749 if (!printed_version++)
a9524a76 1750 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1751
24dc5f33 1752 rc = pcim_enable_device(pdev);
1da177e4
LT		 1753 if (rc)
1754 return rc;
1755
0d5ff566
TH		 1756 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1757 if (rc == -EBUSY)
24dc5f33 1758 pcim_pin_device(pdev);
0d5ff566 1759 if (rc)
24dc5f33 1760 return rc;
1da177e4 1761
24dc5f33 1762 if (pci_enable_msi(pdev))
907f4678 1763 pci_intx(pdev, 1);
1da177e4 1764
24dc5f33
TH		 1765 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
1766 if (probe_ent == NULL)
1767 return -ENOMEM;
1da177e4 1768
1da177e4
LT		 1769 probe_ent->dev = pci_dev_to_dev(pdev);
1770 INIT_LIST_HEAD(&probe_ent->node);
1771
24dc5f33
TH		 1772 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1773 if (!hpriv)
1774 return -ENOMEM;
1da177e4
LT		 1775
1776 probe_ent->sht = ahci_port_info[board_idx].sht;
cca3974e 1777 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1da177e4
LT		 1778 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1779 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1780 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1781
1782 probe_ent->irq = pdev->irq;
1d6f359a 1783 probe_ent->irq_flags = IRQF_SHARED;
0d5ff566 1784 probe_ent->iomap = pcim_iomap_table(pdev);
1da177e4
LT		 1785 probe_ent->private_data = hpriv;
1786
1787 /* initialize adapter */
d447df14
TH		 1788 ahci_save_initial_config(probe_ent);
1789
1da177e4
LT		 1790 rc = ahci_host_init(probe_ent);
1791 if (rc)
24dc5f33 1792 return rc;
1da177e4 1793
cca3974e 1794 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
71f0737b 1795 (hpriv->cap & HOST_CAP_NCQ))
cca3974e 1796 probe_ent->port_flags |= ATA_FLAG_NCQ;
12fad3f9 1797
1da177e4
LT		 1798 ahci_print_info(probe_ent);
1799
24dc5f33
TH		 1800 if (!ata_device_add(probe_ent))
1801 return -ENODEV;
1da177e4 1802
24dc5f33 1803 devm_kfree(dev, probe_ent);
1da177e4 1804 return 0;
907f4678 1805}
1da177e4
LT		 1806
1807static int __init ahci_init(void)
1808{
b7887196 1809 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1810}
1811
1da177e4
LT		 1812static void __exit ahci_exit(void)
1813{
1814 pci_unregister_driver(&ahci_pci_driver);
1815}
1816
1817
1818MODULE_AUTHOR("Jeff Garzik");
1819MODULE_DESCRIPTION("AHCI SATA low-level driver");
1820MODULE_LICENSE("GPL");
1821MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1822MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1823
1824module_init(ahci_init);
1825module_exit(ahci_exit);
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