[net-next-2.6.git] / crypto / async_tx / async_memset.c

/*
 * memory fill offload engine support
 *
 * Copyright © 2006, Intel Corporation.
 *
 *      Dan Williams <dan.j.williams@intel.com>
 *
 *      with architecture considerations by:
 *      Neil Brown <neilb@suse.de>
 *      Jeff Garzik <jeff@garzik.org>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/async_tx.h>

/**
 * async_memset - attempt to fill memory with a dma engine.
 * @dest: destination page
 * @val: fill value
 * @offset: offset in pages to start transaction
 * @len: length in bytes
 *
 * honored flags: ASYNC_TX_ACK
 */
struct dma_async_tx_descriptor *
async_memset(struct page *dest, int val, unsigned int offset, size_t len,
	     struct async_submit_ctl *submit)
{
	struct dma_chan *chan = async_tx_find_channel(submit, DMA_MEMSET,
						      &dest, 1, NULL, 0, len);
	struct dma_device *device = chan ? chan->device : NULL;
	struct dma_async_tx_descriptor *tx = NULL;

	if (device) {
		dma_addr_t dma_dest;
		unsigned long dma_prep_flags = 0;

		if (submit->cb_fn)
			dma_prep_flags |= DMA_PREP_INTERRUPT;
		if (submit->flags & ASYNC_TX_FENCE)
			dma_prep_flags |= DMA_PREP_FENCE;
		dma_dest = dma_map_page(device->dev, dest, offset, len,
					DMA_FROM_DEVICE);

		tx = device->device_prep_dma_memset(chan, dma_dest, val, len,
						    dma_prep_flags);
	}

	if (tx) {
		pr_debug("%s: (async) len: %zu\n", __func__, len);
		async_tx_submit(chan, tx, submit);
	} else { /* run the memset synchronously */
		void *dest_buf;
		pr_debug("%s: (sync) len: %zu\n", __func__, len);

		dest_buf = page_address(dest) + offset;

		/* wait for any prerequisite operations */
		async_tx_quiesce(&submit->depend_tx);

		memset(dest_buf, val, len);

		async_tx_sync_epilog(submit);
	}

	return tx;
}
EXPORT_SYMBOL_GPL(async_memset);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("asynchronous memset api");
MODULE_LICENSE("GPL");
Commit	Line	Data
9bc89cd8 DW	1	/*
	2	* memory fill offload engine support
	3	*
	4	* Copyright © 2006, Intel Corporation.
	5	*
	6	* Dan Williams <dan.j.williams@intel.com>
	7	*
	8	* with architecture considerations by:
	9	* Neil Brown <neilb@suse.de>
	10	* Jeff Garzik <jeff@garzik.org>
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms and conditions of the GNU General Public License,
	14	* version 2, as published by the Free Software Foundation.
	15	*
	16	* This program is distributed in the hope it will be useful, but WITHOUT
	17	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	19	* more details.
	20	*
	21	* You should have received a copy of the GNU General Public License along with
	22	* this program; if not, write to the Free Software Foundation, Inc.,
	23	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	24	*
	25	*/
	26	#include <linux/kernel.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/mm.h>
	29	#include <linux/dma-mapping.h>
	30	#include <linux/async_tx.h>
	31
	32	/**
	33	* async_memset - attempt to fill memory with a dma engine.
	34	* @dest: destination page
	35	* @val: fill value
	36	* @offset: offset in pages to start transaction
	37	* @len: length in bytes
a08abd8c DW	38	*
a08abd8c DW	39	* honored flags: ASYNC_TX_ACK
9bc89cd8 DW	40	*/
9bc89cd8 DW	41	struct dma_async_tx_descriptor *
a08abd8c DW	42	async_memset(struct page *dest, int val, unsigned int offset, size_t len,
a08abd8c DW	43	struct async_submit_ctl *submit)
9bc89cd8	44	{
a08abd8c	45	struct dma_chan *chan = async_tx_find_channel(submit, DMA_MEMSET,
47437b2c	46	&dest, 1, NULL, 0, len);
9bc89cd8	47	struct dma_device *device = chan ? chan->device : NULL;
0036731c	48	struct dma_async_tx_descriptor *tx = NULL;
9bc89cd8	49
0036731c DW	50	if (device) {
0036731c DW	51	dma_addr_t dma_dest;
0403e382	52	unsigned long dma_prep_flags = 0;
9bc89cd8	53
0403e382 DW	54	if (submit->cb_fn)
	55	dma_prep_flags \|= DMA_PREP_INTERRUPT;
	56	if (submit->flags & ASYNC_TX_FENCE)
	57	dma_prep_flags \|= DMA_PREP_FENCE;
0036731c	58	dma_dest = dma_map_page(device->dev, dest, offset, len,
d909b347	59	DMA_FROM_DEVICE);
9bc89cd8	60
0036731c	61	tx = device->device_prep_dma_memset(chan, dma_dest, val, len,
d4c56f97	62	dma_prep_flags);
0036731c DW	63	}
	64
	65	if (tx) {
3280ab3e	66	pr_debug("%s: (async) len: %zu\n", __func__, len);
a08abd8c	67	async_tx_submit(chan, tx, submit);
9bc89cd8 DW	68	} else { /* run the memset synchronously */
9bc89cd8 DW	69	void *dest_buf;
3280ab3e	70	pr_debug("%s: (sync) len: %zu\n", __func__, len);
9bc89cd8	71
a08abd8c	72	dest_buf = page_address(dest) + offset;
9bc89cd8 DW	73
9bc89cd8 DW	74	/* wait for any prerequisite operations */
a08abd8c	75	async_tx_quiesce(&submit->depend_tx);
9bc89cd8 DW	76
	77	memset(dest_buf, val, len);
	78
a08abd8c	79	async_tx_sync_epilog(submit);
9bc89cd8 DW	80	}
	81
	82	return tx;
	83	}
	84	EXPORT_SYMBOL_GPL(async_memset);
	85
9bc89cd8 DW	86	MODULE_AUTHOR("Intel Corporation");
	87	MODULE_DESCRIPTION("asynchronous memset api");
	88	MODULE_LICENSE("GPL");