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Commit | Line | Data |
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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/bitops.h> | |
35 | #include <linux/pci_ids.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/calgary.h> | |
40 | #include <asm/tce.h> | |
41 | #include <asm/pci-direct.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/dma.h> | |
b34e90b8 | 44 | #include <asm/rio.h> |
e465058d | 45 | |
bff6547b MBY |
46 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
47 | int use_calgary __read_mostly = 1; | |
48 | #else | |
49 | int use_calgary __read_mostly = 0; | |
50 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
51 | ||
e465058d JM |
52 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
53 | #define PCI_VENDOR_DEVICE_ID_CALGARY \ | |
54 | (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16) | |
55 | ||
56 | /* we need these for register space address calculation */ | |
57 | #define START_ADDRESS 0xfe000000 | |
58 | #define CHASSIS_BASE 0 | |
59 | #define ONE_BASED_CHASSIS_NUM 1 | |
60 | ||
61 | /* register offsets inside the host bridge space */ | |
cb01fc72 MBY |
62 | #define CALGARY_CONFIG_REG 0x0108 |
63 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
64 | #define PHB_PLSSR_OFFSET 0x0120 |
65 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
66 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
67 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
68 | #define PHB_MEM_1_LOW 0x0190 | |
69 | #define PHB_MEM_1_HIGH 0x01A0 | |
70 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
71 | #define PHB_MEM_1_SIZE 0x01C0 | |
72 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
73 | #define PHB_AER_OFFSET 0x0200 | |
74 | #define PHB_CONFIG_0_HIGH 0x0220 | |
75 | #define PHB_CONFIG_0_LOW 0x0230 | |
76 | #define PHB_CONFIG_0_END 0x0240 | |
77 | #define PHB_MEM_2_LOW 0x02B0 | |
78 | #define PHB_MEM_2_HIGH 0x02C0 | |
79 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
80 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
81 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
82 | ||
83 | /* PHB_CONFIG_RW */ | |
84 | #define PHB_TCE_ENABLE 0x20000000 | |
85 | #define PHB_SLOT_DISABLE 0x1C000000 | |
86 | #define PHB_DAC_DISABLE 0x01000000 | |
87 | #define PHB_MEM2_ENABLE 0x00400000 | |
88 | #define PHB_MCSR_ENABLE 0x00100000 | |
89 | /* TAR (Table Address Register) */ | |
90 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
91 | #define TAR_VALID 0x0000000000000008UL | |
92 | /* CSR (Channel/DMA Status Register) */ | |
93 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 MBY |
94 | /* CCR (Calgary Configuration Register) */ |
95 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL | |
e465058d JM |
96 | |
97 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 98 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
99 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
100 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
101 | #define PHBS_PER_CALGARY 4 |
102 | ||
103 | /* register offsets in Calgary's internal register space */ | |
104 | static const unsigned long tar_offsets[] = { | |
105 | 0x0580 /* TAR0 */, | |
106 | 0x0588 /* TAR1 */, | |
107 | 0x0590 /* TAR2 */, | |
108 | 0x0598 /* TAR3 */ | |
109 | }; | |
110 | ||
111 | static const unsigned long split_queue_offsets[] = { | |
112 | 0x4870 /* SPLIT QUEUE 0 */, | |
113 | 0x5870 /* SPLIT QUEUE 1 */, | |
114 | 0x6870 /* SPLIT QUEUE 2 */, | |
115 | 0x7870 /* SPLIT QUEUE 3 */ | |
116 | }; | |
117 | ||
118 | static const unsigned long phb_offsets[] = { | |
119 | 0x8000 /* PHB0 */, | |
120 | 0x9000 /* PHB1 */, | |
121 | 0xA000 /* PHB2 */, | |
122 | 0xB000 /* PHB3 */ | |
123 | }; | |
124 | ||
b34e90b8 LV |
125 | /* PHB debug registers */ |
126 | ||
127 | static const unsigned long phb_debug_offsets[] = { | |
128 | 0x4000 /* PHB 0 DEBUG */, | |
129 | 0x5000 /* PHB 1 DEBUG */, | |
130 | 0x6000 /* PHB 2 DEBUG */, | |
131 | 0x7000 /* PHB 3 DEBUG */ | |
132 | }; | |
133 | ||
134 | /* | |
135 | * STUFF register for each debug PHB, | |
136 | * byte 1 = start bus number, byte 2 = end bus number | |
137 | */ | |
138 | ||
139 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
140 | ||
310adfdd MBY |
141 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
142 | ||
e465058d JM |
143 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
144 | static int translate_empty_slots __read_mostly = 0; | |
145 | static int calgary_detected __read_mostly = 0; | |
146 | ||
b34e90b8 LV |
147 | static struct rio_table_hdr *rio_table_hdr __initdata; |
148 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 149 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 150 | |
f38db651 MBY |
151 | struct calgary_bus_info { |
152 | void *tce_space; | |
0577f148 | 153 | unsigned char translation_disabled; |
f38db651 | 154 | signed char phbid; |
b34e90b8 | 155 | void __iomem *bbar; |
f38db651 MBY |
156 | }; |
157 | ||
ff297b8c MBY |
158 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
159 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
160 | ||
161 | static struct cal_chipset_ops calgary_chip_ops = { | |
162 | .handle_quirks = calgary_handle_quirks, | |
163 | .tce_cache_blast = calgary_tce_cache_blast | |
164 | }; | |
e465058d | 165 | |
ff297b8c | 166 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d JM |
167 | |
168 | /* enable this to stress test the chip's TCE cache */ | |
169 | #ifdef CONFIG_IOMMU_DEBUG | |
de684652 MBY |
170 | int debugging __read_mostly = 1; |
171 | ||
796e4390 MBY |
172 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
173 | int expected, unsigned long start, unsigned long end) | |
174 | { | |
175 | unsigned long idx = start; | |
176 | ||
177 | BUG_ON(start >= end); | |
178 | ||
179 | while (idx < end) { | |
180 | if (!!test_bit(idx, bitmap) != expected) | |
181 | return idx; | |
182 | ++idx; | |
183 | } | |
184 | ||
185 | /* all bits have the expected value */ | |
186 | return ~0UL; | |
187 | } | |
de684652 MBY |
188 | #else /* debugging is disabled */ |
189 | int debugging __read_mostly = 0; | |
190 | ||
796e4390 MBY |
191 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
192 | int expected, unsigned long start, unsigned long end) | |
193 | { | |
194 | return ~0UL; | |
195 | } | |
de684652 | 196 | #endif /* CONFIG_IOMMU_DEBUG */ |
e465058d JM |
197 | |
198 | static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen) | |
199 | { | |
200 | unsigned int npages; | |
201 | ||
202 | npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK); | |
203 | npages >>= PAGE_SHIFT; | |
204 | ||
205 | return npages; | |
206 | } | |
207 | ||
208 | static inline int translate_phb(struct pci_dev* dev) | |
209 | { | |
f38db651 | 210 | int disabled = bus_info[dev->bus->number].translation_disabled; |
e465058d JM |
211 | return !disabled; |
212 | } | |
213 | ||
214 | static void iommu_range_reserve(struct iommu_table *tbl, | |
215 | unsigned long start_addr, unsigned int npages) | |
216 | { | |
217 | unsigned long index; | |
218 | unsigned long end; | |
796e4390 | 219 | unsigned long badbit; |
e465058d JM |
220 | |
221 | index = start_addr >> PAGE_SHIFT; | |
222 | ||
223 | /* bail out if we're asked to reserve a region we don't cover */ | |
224 | if (index >= tbl->it_size) | |
225 | return; | |
226 | ||
227 | end = index + npages; | |
228 | if (end > tbl->it_size) /* don't go off the table */ | |
229 | end = tbl->it_size; | |
230 | ||
796e4390 MBY |
231 | badbit = verify_bit_range(tbl->it_map, 0, index, end); |
232 | if (badbit != ~0UL) { | |
233 | if (printk_ratelimit()) | |
e465058d JM |
234 | printk(KERN_ERR "Calgary: entry already allocated at " |
235 | "0x%lx tbl %p dma 0x%lx npages %u\n", | |
796e4390 | 236 | badbit, tbl, start_addr, npages); |
e465058d | 237 | } |
796e4390 MBY |
238 | |
239 | set_bit_string(tbl->it_map, index, npages); | |
e465058d JM |
240 | } |
241 | ||
242 | static unsigned long iommu_range_alloc(struct iommu_table *tbl, | |
243 | unsigned int npages) | |
244 | { | |
245 | unsigned long offset; | |
246 | ||
247 | BUG_ON(npages == 0); | |
248 | ||
249 | offset = find_next_zero_string(tbl->it_map, tbl->it_hint, | |
250 | tbl->it_size, npages); | |
251 | if (offset == ~0UL) { | |
ff297b8c | 252 | tbl->chip_ops->tce_cache_blast(tbl); |
e465058d JM |
253 | offset = find_next_zero_string(tbl->it_map, 0, |
254 | tbl->it_size, npages); | |
255 | if (offset == ~0UL) { | |
256 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
257 | if (panic_on_overflow) | |
258 | panic("Calgary: fix the allocator.\n"); | |
259 | else | |
260 | return bad_dma_address; | |
261 | } | |
262 | } | |
263 | ||
264 | set_bit_string(tbl->it_map, offset, npages); | |
265 | tbl->it_hint = offset + npages; | |
266 | BUG_ON(tbl->it_hint > tbl->it_size); | |
267 | ||
268 | return offset; | |
269 | } | |
270 | ||
271 | static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr, | |
272 | unsigned int npages, int direction) | |
273 | { | |
274 | unsigned long entry, flags; | |
275 | dma_addr_t ret = bad_dma_address; | |
276 | ||
277 | spin_lock_irqsave(&tbl->it_lock, flags); | |
278 | ||
279 | entry = iommu_range_alloc(tbl, npages); | |
280 | ||
281 | if (unlikely(entry == bad_dma_address)) | |
282 | goto error; | |
283 | ||
284 | /* set the return dma address */ | |
285 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
286 | ||
287 | /* put the TCEs in the HW table */ | |
288 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
289 | direction); | |
290 | ||
291 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
292 | ||
293 | return ret; | |
294 | ||
295 | error: | |
296 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
297 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " | |
298 | "iommu %p\n", npages, tbl); | |
299 | return bad_dma_address; | |
300 | } | |
301 | ||
302 | static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
303 | unsigned int npages) | |
304 | { | |
305 | unsigned long entry; | |
796e4390 | 306 | unsigned long badbit; |
310adfdd MBY |
307 | unsigned long badend; |
308 | ||
309 | /* were we called with bad_dma_address? */ | |
310 | badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE); | |
311 | if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) { | |
312 | printk(KERN_ERR "Calgary: driver tried unmapping bad DMA " | |
313 | "address 0x%Lx\n", dma_addr); | |
314 | WARN_ON(1); | |
315 | return; | |
316 | } | |
e465058d JM |
317 | |
318 | entry = dma_addr >> PAGE_SHIFT; | |
319 | ||
320 | BUG_ON(entry + npages > tbl->it_size); | |
321 | ||
322 | tce_free(tbl, entry, npages); | |
323 | ||
796e4390 MBY |
324 | badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages); |
325 | if (badbit != ~0UL) { | |
326 | if (printk_ratelimit()) | |
e465058d JM |
327 | printk(KERN_ERR "Calgary: bit is off at 0x%lx " |
328 | "tbl %p dma 0x%Lx entry 0x%lx npages %u\n", | |
796e4390 | 329 | badbit, tbl, dma_addr, entry, npages); |
e465058d JM |
330 | } |
331 | ||
332 | __clear_bit_string(tbl->it_map, entry, npages); | |
e465058d JM |
333 | } |
334 | ||
335 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
336 | unsigned int npages) | |
337 | { | |
338 | unsigned long flags; | |
339 | ||
340 | spin_lock_irqsave(&tbl->it_lock, flags); | |
341 | ||
342 | __iommu_free(tbl, dma_addr, npages); | |
343 | ||
344 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
345 | } | |
346 | ||
347 | static void __calgary_unmap_sg(struct iommu_table *tbl, | |
348 | struct scatterlist *sglist, int nelems, int direction) | |
349 | { | |
350 | while (nelems--) { | |
351 | unsigned int npages; | |
352 | dma_addr_t dma = sglist->dma_address; | |
353 | unsigned int dmalen = sglist->dma_length; | |
354 | ||
355 | if (dmalen == 0) | |
356 | break; | |
357 | ||
358 | npages = num_dma_pages(dma, dmalen); | |
359 | __iommu_free(tbl, dma, npages); | |
360 | sglist++; | |
361 | } | |
362 | } | |
363 | ||
364 | void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist, | |
365 | int nelems, int direction) | |
366 | { | |
367 | unsigned long flags; | |
368 | struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata; | |
369 | ||
370 | if (!translate_phb(to_pci_dev(dev))) | |
371 | return; | |
372 | ||
373 | spin_lock_irqsave(&tbl->it_lock, flags); | |
374 | ||
375 | __calgary_unmap_sg(tbl, sglist, nelems, direction); | |
376 | ||
377 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
378 | } | |
379 | ||
380 | static int calgary_nontranslate_map_sg(struct device* dev, | |
381 | struct scatterlist *sg, int nelems, int direction) | |
382 | { | |
383 | int i; | |
384 | ||
385 | for (i = 0; i < nelems; i++ ) { | |
386 | struct scatterlist *s = &sg[i]; | |
387 | BUG_ON(!s->page); | |
388 | s->dma_address = virt_to_bus(page_address(s->page) +s->offset); | |
389 | s->dma_length = s->length; | |
390 | } | |
391 | return nelems; | |
392 | } | |
393 | ||
394 | int calgary_map_sg(struct device *dev, struct scatterlist *sg, | |
395 | int nelems, int direction) | |
396 | { | |
397 | struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata; | |
398 | unsigned long flags; | |
399 | unsigned long vaddr; | |
400 | unsigned int npages; | |
401 | unsigned long entry; | |
402 | int i; | |
403 | ||
404 | if (!translate_phb(to_pci_dev(dev))) | |
405 | return calgary_nontranslate_map_sg(dev, sg, nelems, direction); | |
406 | ||
407 | spin_lock_irqsave(&tbl->it_lock, flags); | |
408 | ||
409 | for (i = 0; i < nelems; i++ ) { | |
410 | struct scatterlist *s = &sg[i]; | |
411 | BUG_ON(!s->page); | |
412 | ||
413 | vaddr = (unsigned long)page_address(s->page) + s->offset; | |
414 | npages = num_dma_pages(vaddr, s->length); | |
415 | ||
416 | entry = iommu_range_alloc(tbl, npages); | |
417 | if (entry == bad_dma_address) { | |
418 | /* makes sure unmap knows to stop */ | |
419 | s->dma_length = 0; | |
420 | goto error; | |
421 | } | |
422 | ||
423 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
424 | ||
425 | /* insert into HW table */ | |
426 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, | |
427 | direction); | |
428 | ||
429 | s->dma_length = s->length; | |
430 | } | |
431 | ||
432 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
433 | ||
434 | return nelems; | |
435 | error: | |
436 | __calgary_unmap_sg(tbl, sg, nelems, direction); | |
437 | for (i = 0; i < nelems; i++) { | |
438 | sg[i].dma_address = bad_dma_address; | |
439 | sg[i].dma_length = 0; | |
440 | } | |
441 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
442 | return 0; | |
443 | } | |
444 | ||
445 | dma_addr_t calgary_map_single(struct device *dev, void *vaddr, | |
446 | size_t size, int direction) | |
447 | { | |
448 | dma_addr_t dma_handle = bad_dma_address; | |
449 | unsigned long uaddr; | |
450 | unsigned int npages; | |
451 | struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata; | |
452 | ||
453 | uaddr = (unsigned long)vaddr; | |
454 | npages = num_dma_pages(uaddr, size); | |
455 | ||
456 | if (translate_phb(to_pci_dev(dev))) | |
457 | dma_handle = iommu_alloc(tbl, vaddr, npages, direction); | |
458 | else | |
459 | dma_handle = virt_to_bus(vaddr); | |
460 | ||
461 | return dma_handle; | |
462 | } | |
463 | ||
464 | void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle, | |
465 | size_t size, int direction) | |
466 | { | |
467 | struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata; | |
468 | unsigned int npages; | |
469 | ||
470 | if (!translate_phb(to_pci_dev(dev))) | |
471 | return; | |
472 | ||
473 | npages = num_dma_pages(dma_handle, size); | |
474 | iommu_free(tbl, dma_handle, npages); | |
475 | } | |
476 | ||
477 | void* calgary_alloc_coherent(struct device *dev, size_t size, | |
478 | dma_addr_t *dma_handle, gfp_t flag) | |
479 | { | |
480 | void *ret = NULL; | |
481 | dma_addr_t mapping; | |
482 | unsigned int npages, order; | |
483 | struct iommu_table *tbl; | |
484 | ||
485 | tbl = to_pci_dev(dev)->bus->self->sysdata; | |
486 | ||
487 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
488 | npages = size >> PAGE_SHIFT; | |
489 | order = get_order(size); | |
490 | ||
491 | /* alloc enough pages (and possibly more) */ | |
492 | ret = (void *)__get_free_pages(flag, order); | |
493 | if (!ret) | |
494 | goto error; | |
495 | memset(ret, 0, size); | |
496 | ||
497 | if (translate_phb(to_pci_dev(dev))) { | |
498 | /* set up tces to cover the allocated range */ | |
499 | mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL); | |
500 | if (mapping == bad_dma_address) | |
501 | goto free; | |
502 | ||
503 | *dma_handle = mapping; | |
504 | } else /* non translated slot */ | |
505 | *dma_handle = virt_to_bus(ret); | |
506 | ||
507 | return ret; | |
508 | ||
509 | free: | |
510 | free_pages((unsigned long)ret, get_order(size)); | |
511 | ret = NULL; | |
512 | error: | |
513 | return ret; | |
514 | } | |
515 | ||
e6584504 | 516 | static const struct dma_mapping_ops calgary_dma_ops = { |
e465058d JM |
517 | .alloc_coherent = calgary_alloc_coherent, |
518 | .map_single = calgary_map_single, | |
519 | .unmap_single = calgary_unmap_single, | |
520 | .map_sg = calgary_map_sg, | |
521 | .unmap_sg = calgary_unmap_sg, | |
522 | }; | |
523 | ||
b34e90b8 LV |
524 | static inline void __iomem * busno_to_bbar(unsigned char num) |
525 | { | |
526 | return bus_info[num].bbar; | |
527 | } | |
528 | ||
e465058d JM |
529 | static inline int busno_to_phbid(unsigned char num) |
530 | { | |
f38db651 | 531 | return bus_info[num].phbid; |
e465058d JM |
532 | } |
533 | ||
534 | static inline unsigned long split_queue_offset(unsigned char num) | |
535 | { | |
536 | size_t idx = busno_to_phbid(num); | |
537 | ||
538 | return split_queue_offsets[idx]; | |
539 | } | |
540 | ||
541 | static inline unsigned long tar_offset(unsigned char num) | |
542 | { | |
543 | size_t idx = busno_to_phbid(num); | |
544 | ||
545 | return tar_offsets[idx]; | |
546 | } | |
547 | ||
548 | static inline unsigned long phb_offset(unsigned char num) | |
549 | { | |
550 | size_t idx = busno_to_phbid(num); | |
551 | ||
552 | return phb_offsets[idx]; | |
553 | } | |
554 | ||
555 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
556 | { | |
557 | unsigned long target = ((unsigned long)bar) | offset; | |
558 | return (void __iomem*)target; | |
559 | } | |
560 | ||
ff297b8c | 561 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
562 | { |
563 | u64 val; | |
564 | u32 aer; | |
565 | int i = 0; | |
566 | void __iomem *bbar = tbl->bbar; | |
567 | void __iomem *target; | |
568 | ||
569 | /* disable arbitration on the bus */ | |
570 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
571 | aer = readl(target); | |
572 | writel(0, target); | |
573 | ||
574 | /* read plssr to ensure it got there */ | |
575 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
576 | val = readl(target); | |
577 | ||
578 | /* poll split queues until all DMA activity is done */ | |
579 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
580 | do { | |
581 | val = readq(target); | |
582 | i++; | |
583 | } while ((val & 0xff) != 0xff && i < 100); | |
584 | if (i == 100) | |
585 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
586 | "continuing anyway\n"); | |
587 | ||
588 | /* invalidate TCE cache */ | |
589 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
590 | writeq(tbl->tar_val, target); | |
591 | ||
592 | /* enable arbitration */ | |
593 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
594 | writel(aer, target); | |
595 | (void)readl(target); /* flush */ | |
596 | } | |
597 | ||
598 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, | |
599 | u64 limit) | |
600 | { | |
601 | unsigned int numpages; | |
602 | ||
603 | limit = limit | 0xfffff; | |
604 | limit++; | |
605 | ||
606 | numpages = ((limit - start) >> PAGE_SHIFT); | |
607 | iommu_range_reserve(dev->sysdata, start, numpages); | |
608 | } | |
609 | ||
610 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
611 | { | |
612 | void __iomem *target; | |
613 | u64 low, high, sizelow; | |
614 | u64 start, limit; | |
615 | struct iommu_table *tbl = dev->sysdata; | |
616 | unsigned char busnum = dev->bus->number; | |
617 | void __iomem *bbar = tbl->bbar; | |
618 | ||
619 | /* peripheral MEM_1 region */ | |
620 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
621 | low = be32_to_cpu(readl(target)); | |
622 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
623 | high = be32_to_cpu(readl(target)); | |
624 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
625 | sizelow = be32_to_cpu(readl(target)); | |
626 | ||
627 | start = (high << 32) | low; | |
628 | limit = sizelow; | |
629 | ||
630 | calgary_reserve_mem_region(dev, start, limit); | |
631 | } | |
632 | ||
633 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
634 | { | |
635 | void __iomem *target; | |
636 | u32 val32; | |
637 | u64 low, high, sizelow, sizehigh; | |
638 | u64 start, limit; | |
639 | struct iommu_table *tbl = dev->sysdata; | |
640 | unsigned char busnum = dev->bus->number; | |
641 | void __iomem *bbar = tbl->bbar; | |
642 | ||
643 | /* is it enabled? */ | |
644 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
645 | val32 = be32_to_cpu(readl(target)); | |
646 | if (!(val32 & PHB_MEM2_ENABLE)) | |
647 | return; | |
648 | ||
649 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
650 | low = be32_to_cpu(readl(target)); | |
651 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
652 | high = be32_to_cpu(readl(target)); | |
653 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
654 | sizelow = be32_to_cpu(readl(target)); | |
655 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
656 | sizehigh = be32_to_cpu(readl(target)); | |
657 | ||
658 | start = (high << 32) | low; | |
659 | limit = (sizehigh << 32) | sizelow; | |
660 | ||
661 | calgary_reserve_mem_region(dev, start, limit); | |
662 | } | |
663 | ||
664 | /* | |
665 | * some regions of the IO address space do not get translated, so we | |
666 | * must not give devices IO addresses in those regions. The regions | |
667 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
668 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
669 | * later. | |
670 | */ | |
671 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
672 | { | |
673 | unsigned int npages; | |
e465058d JM |
674 | u64 start; |
675 | struct iommu_table *tbl = dev->sysdata; | |
676 | ||
310adfdd MBY |
677 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
678 | iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES); | |
e465058d JM |
679 | |
680 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
681 | start = (640 * 1024); | |
682 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
683 | iommu_range_reserve(tbl, start, npages); | |
684 | ||
685 | /* reserve the two PCI peripheral memory regions in IO space */ | |
686 | calgary_reserve_peripheral_mem_1(dev); | |
687 | calgary_reserve_peripheral_mem_2(dev); | |
688 | } | |
689 | ||
690 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
691 | { | |
692 | u64 val64; | |
693 | u64 table_phys; | |
694 | void __iomem *target; | |
695 | int ret; | |
696 | struct iommu_table *tbl; | |
697 | ||
698 | /* build TCE tables for each PHB */ | |
699 | ret = build_tce_table(dev, bbar); | |
700 | if (ret) | |
701 | return ret; | |
702 | ||
f38db651 MBY |
703 | tbl = dev->sysdata; |
704 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; | |
705 | tce_free(tbl, 0, tbl->it_size); | |
706 | ||
ff297b8c MBY |
707 | tbl->chip_ops = &calgary_chip_ops; |
708 | ||
e465058d JM |
709 | calgary_reserve_regions(dev); |
710 | ||
711 | /* set TARs for each PHB */ | |
712 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
713 | val64 = be64_to_cpu(readq(target)); | |
714 | ||
715 | /* zero out all TAR bits under sw control */ | |
716 | val64 &= ~TAR_SW_BITS; | |
717 | ||
718 | tbl = dev->sysdata; | |
719 | table_phys = (u64)__pa(tbl->it_base); | |
720 | val64 |= table_phys; | |
721 | ||
722 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
723 | val64 |= (u64) specified_table_size; | |
724 | ||
725 | tbl->tar_val = cpu_to_be64(val64); | |
726 | writeq(tbl->tar_val, target); | |
727 | readq(target); /* flush */ | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
b8f4fe66 | 732 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
733 | { |
734 | u64 val64; | |
735 | struct iommu_table *tbl = dev->sysdata; | |
736 | void __iomem *target; | |
b8f4fe66 | 737 | unsigned int bitmapsz; |
e465058d JM |
738 | |
739 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
740 | val64 = be64_to_cpu(readq(target)); | |
741 | val64 &= ~TAR_SW_BITS; | |
742 | writeq(cpu_to_be64(val64), target); | |
743 | readq(target); /* flush */ | |
744 | ||
b8f4fe66 MBY |
745 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
746 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
747 | tbl->it_map = NULL; | |
748 | ||
e465058d JM |
749 | kfree(tbl); |
750 | dev->sysdata = NULL; | |
b8f4fe66 MBY |
751 | |
752 | /* Can't free bootmem allocated memory after system is up :-( */ | |
753 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
754 | } |
755 | ||
756 | static void calgary_watchdog(unsigned long data) | |
757 | { | |
758 | struct pci_dev *dev = (struct pci_dev *)data; | |
759 | struct iommu_table *tbl = dev->sysdata; | |
760 | void __iomem *bbar = tbl->bbar; | |
761 | u32 val32; | |
762 | void __iomem *target; | |
763 | ||
764 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
765 | val32 = be32_to_cpu(readl(target)); | |
766 | ||
767 | /* If no error, the agent ID in the CSR is not valid */ | |
768 | if (val32 & CSR_AGENT_MASK) { | |
70d666d6 | 769 | printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, " |
e465058d JM |
770 | "CSR = %#x\n", dev->bus->number, val32); |
771 | writel(0, target); | |
772 | ||
773 | /* Disable bus that caused the error */ | |
774 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
775 | PHB_CONFIG_RW_OFFSET); | |
776 | val32 = be32_to_cpu(readl(target)); | |
777 | val32 |= PHB_SLOT_DISABLE; | |
778 | writel(cpu_to_be32(val32), target); | |
779 | readl(target); /* flush */ | |
780 | } else { | |
781 | /* Reset the timer */ | |
782 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
783 | } | |
784 | } | |
785 | ||
a2b663f6 MBY |
786 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
787 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
788 | { |
789 | u64 val64; | |
790 | void __iomem *target; | |
58db8548 | 791 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
792 | u64 mask; |
793 | ||
794 | switch (busno_to_phbid(busnum)) { | |
795 | case 0: phb_shift = (63 - 19); | |
796 | break; | |
797 | case 1: phb_shift = (63 - 23); | |
798 | break; | |
799 | case 2: phb_shift = (63 - 27); | |
800 | break; | |
801 | case 3: phb_shift = (63 - 35); | |
802 | break; | |
803 | default: | |
804 | BUG_ON(busno_to_phbid(busnum)); | |
805 | } | |
806 | ||
807 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
808 | val64 = be64_to_cpu(readq(target)); | |
809 | ||
810 | /* zero out this PHB's timer bits */ | |
811 | mask = ~(0xFUL << phb_shift); | |
812 | val64 &= mask; | |
a2b663f6 | 813 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
814 | writeq(cpu_to_be64(val64), target); |
815 | readq(target); /* flush */ | |
816 | } | |
817 | ||
ff297b8c MBY |
818 | static void __init calgary_handle_quirks(struct iommu_table *tbl, |
819 | struct pci_dev *dev) | |
b8d2ea1b MBY |
820 | { |
821 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
822 | |
823 | /* | |
824 | * Give split completion a longer timeout on bus 1 for aic94xx | |
825 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
826 | */ | |
827 | if (busnum == 1) | |
828 | calgary_set_split_completion_timeout(tbl->bbar, busnum, | |
829 | CCR_2SEC_TIMEOUT); | |
830 | } | |
831 | ||
e465058d JM |
832 | static void __init calgary_enable_translation(struct pci_dev *dev) |
833 | { | |
834 | u32 val32; | |
835 | unsigned char busnum; | |
836 | void __iomem *target; | |
837 | void __iomem *bbar; | |
838 | struct iommu_table *tbl; | |
839 | ||
840 | busnum = dev->bus->number; | |
841 | tbl = dev->sysdata; | |
842 | bbar = tbl->bbar; | |
843 | ||
844 | /* enable TCE in PHB Config Register */ | |
845 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
846 | val32 = be32_to_cpu(readl(target)); | |
847 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
848 | ||
70d666d6 | 849 | printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum); |
e465058d JM |
850 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
851 | "bus.\n"); | |
852 | ||
853 | writel(cpu_to_be32(val32), target); | |
854 | readl(target); /* flush */ | |
855 | ||
856 | init_timer(&tbl->watchdog_timer); | |
857 | tbl->watchdog_timer.function = &calgary_watchdog; | |
858 | tbl->watchdog_timer.data = (unsigned long)dev; | |
859 | mod_timer(&tbl->watchdog_timer, jiffies); | |
860 | } | |
861 | ||
862 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
863 | { | |
864 | u32 val32; | |
865 | unsigned char busnum; | |
866 | void __iomem *target; | |
867 | void __iomem *bbar; | |
868 | struct iommu_table *tbl; | |
869 | ||
870 | busnum = dev->bus->number; | |
871 | tbl = dev->sysdata; | |
872 | bbar = tbl->bbar; | |
873 | ||
874 | /* disable TCE in PHB Config Register */ | |
875 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
876 | val32 = be32_to_cpu(readl(target)); | |
877 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
878 | ||
70d666d6 | 879 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
880 | writel(cpu_to_be32(val32), target); |
881 | readl(target); /* flush */ | |
882 | ||
883 | del_timer_sync(&tbl->watchdog_timer); | |
884 | } | |
885 | ||
a4fc520a | 886 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 887 | { |
871b1700 | 888 | pci_dev_get(dev); |
e465058d JM |
889 | dev->sysdata = NULL; |
890 | dev->bus->self = dev; | |
e465058d JM |
891 | } |
892 | ||
893 | static int __init calgary_init_one(struct pci_dev *dev) | |
894 | { | |
e465058d | 895 | void __iomem *bbar; |
ff297b8c | 896 | struct iommu_table *tbl; |
e465058d JM |
897 | int ret; |
898 | ||
dedc9937 JM |
899 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
900 | ||
eae93755 | 901 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
902 | ret = calgary_setup_tar(dev, bbar); |
903 | if (ret) | |
eae93755 | 904 | goto done; |
e465058d | 905 | |
871b1700 | 906 | pci_dev_get(dev); |
e465058d | 907 | dev->bus->self = dev; |
b8d2ea1b | 908 | |
ff297b8c MBY |
909 | tbl = dev->sysdata; |
910 | tbl->chip_ops->handle_quirks(tbl, dev); | |
b8d2ea1b | 911 | |
e465058d JM |
912 | calgary_enable_translation(dev); |
913 | ||
914 | return 0; | |
915 | ||
e465058d JM |
916 | done: |
917 | return ret; | |
918 | } | |
919 | ||
eae93755 | 920 | static int __init calgary_locate_bbars(void) |
e465058d | 921 | { |
eae93755 MBY |
922 | int ret; |
923 | int rioidx, phb, bus; | |
b34e90b8 LV |
924 | void __iomem *bbar; |
925 | void __iomem *target; | |
eae93755 | 926 | unsigned long offset; |
b34e90b8 LV |
927 | u8 start_bus, end_bus; |
928 | u32 val; | |
929 | ||
eae93755 MBY |
930 | ret = -ENODATA; |
931 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
932 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 933 | |
eae93755 | 934 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
935 | continue; |
936 | ||
937 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
938 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
939 | if (!bbar) | |
940 | goto error; | |
b34e90b8 LV |
941 | |
942 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
943 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
944 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 945 | |
b34e90b8 LV |
946 | val = be32_to_cpu(readl(target)); |
947 | start_bus = (u8)((val & 0x00FF0000) >> 16); | |
eae93755 | 948 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
b34e90b8 LV |
949 | for (bus = start_bus; bus <= end_bus; bus++) { |
950 | bus_info[bus].bbar = bbar; | |
951 | bus_info[bus].phbid = phb; | |
952 | } | |
953 | } | |
954 | } | |
955 | ||
eae93755 MBY |
956 | return 0; |
957 | ||
958 | error: | |
959 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
960 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
961 | if (bus_info[bus].bbar) | |
962 | iounmap(bus_info[bus].bbar); | |
963 | ||
964 | return ret; | |
965 | } | |
966 | ||
967 | static int __init calgary_init(void) | |
968 | { | |
969 | int ret; | |
970 | struct pci_dev *dev = NULL; | |
971 | ||
972 | ret = calgary_locate_bbars(); | |
973 | if (ret) | |
974 | return ret; | |
e465058d | 975 | |
dedc9937 | 976 | do { |
e465058d JM |
977 | dev = pci_get_device(PCI_VENDOR_ID_IBM, |
978 | PCI_DEVICE_ID_IBM_CALGARY, | |
979 | dev); | |
980 | if (!dev) | |
981 | break; | |
982 | if (!translate_phb(dev)) { | |
983 | calgary_init_one_nontraslated(dev); | |
984 | continue; | |
985 | } | |
871b1700 | 986 | if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots) |
e465058d | 987 | continue; |
871b1700 | 988 | |
e465058d JM |
989 | ret = calgary_init_one(dev); |
990 | if (ret) | |
991 | goto error; | |
dedc9937 | 992 | } while (1); |
e465058d JM |
993 | |
994 | return ret; | |
995 | ||
996 | error: | |
dedc9937 | 997 | do { |
7cd8b686 | 998 | dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM, |
e465058d JM |
999 | PCI_DEVICE_ID_IBM_CALGARY, |
1000 | dev); | |
9f2dc46d MBY |
1001 | if (!dev) |
1002 | break; | |
e465058d JM |
1003 | if (!translate_phb(dev)) { |
1004 | pci_dev_put(dev); | |
1005 | continue; | |
1006 | } | |
f38db651 | 1007 | if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots) |
e465058d | 1008 | continue; |
871b1700 | 1009 | |
e465058d | 1010 | calgary_disable_translation(dev); |
b8f4fe66 | 1011 | calgary_free_bus(dev); |
871b1700 | 1012 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
dedc9937 | 1013 | } while (1); |
e465058d JM |
1014 | |
1015 | return ret; | |
1016 | } | |
1017 | ||
1018 | static inline int __init determine_tce_table_size(u64 ram) | |
1019 | { | |
1020 | int ret; | |
1021 | ||
1022 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1023 | return specified_table_size; | |
1024 | ||
1025 | /* | |
1026 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1027 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1028 | * larger table size has twice as many entries, so shift the | |
1029 | * max ram address by 13 to divide by 8K and then look at the | |
1030 | * order of the result to choose between 0-7. | |
1031 | */ | |
1032 | ret = get_order(ram >> 13); | |
1033 | if (ret > TCE_TABLE_SIZE_8M) | |
1034 | ret = TCE_TABLE_SIZE_8M; | |
1035 | ||
1036 | return ret; | |
1037 | } | |
1038 | ||
b34e90b8 LV |
1039 | static int __init build_detail_arrays(void) |
1040 | { | |
1041 | unsigned long ptr; | |
1042 | int i, scal_detail_size, rio_detail_size; | |
1043 | ||
1044 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){ | |
1045 | printk(KERN_WARNING | |
eae93755 | 1046 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 LV |
1047 | "but system has %d nodes.\n", |
1048 | MAX_NUMNODES, rio_table_hdr->num_scal_dev); | |
1049 | return -ENODEV; | |
1050 | } | |
1051 | ||
1052 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1053 | case 2: |
1054 | scal_detail_size = 11; | |
1055 | rio_detail_size = 13; | |
1056 | break; | |
1057 | case 3: | |
1058 | scal_detail_size = 12; | |
1059 | rio_detail_size = 15; | |
1060 | break; | |
eae93755 MBY |
1061 | default: |
1062 | printk(KERN_WARNING | |
1063 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1064 | rio_table_hdr->version); | |
1065 | return -EPROTO; | |
b34e90b8 LV |
1066 | } |
1067 | ||
1068 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
1069 | for (i = 0; i < rio_table_hdr->num_scal_dev; | |
1070 | i++, ptr += scal_detail_size) | |
1071 | scal_devs[i] = (struct scal_detail *)ptr; | |
1072 | ||
1073 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1074 | i++, ptr += rio_detail_size) | |
1075 | rio_devs[i] = (struct rio_detail *)ptr; | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
e465058d JM |
1080 | void __init detect_calgary(void) |
1081 | { | |
1082 | u32 val; | |
d2105b10 | 1083 | int bus; |
e465058d | 1084 | void *tbl; |
d2105b10 | 1085 | int calgary_found = 0; |
b34e90b8 | 1086 | unsigned long ptr; |
136f1e7a | 1087 | unsigned int offset, prev_offset; |
eae93755 | 1088 | int ret; |
e465058d JM |
1089 | |
1090 | /* | |
1091 | * if the user specified iommu=off or iommu=soft or we found | |
1092 | * another HW IOMMU already, bail out. | |
1093 | */ | |
1094 | if (swiotlb || no_iommu || iommu_detected) | |
1095 | return; | |
1096 | ||
bff6547b MBY |
1097 | if (!use_calgary) |
1098 | return; | |
1099 | ||
0637a70a AK |
1100 | if (!early_pci_allowed()) |
1101 | return; | |
1102 | ||
b92cc559 MBY |
1103 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1104 | ||
b34e90b8 LV |
1105 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1106 | ||
1107 | rio_table_hdr = NULL; | |
136f1e7a | 1108 | prev_offset = 0; |
b34e90b8 | 1109 | offset = 0x180; |
136f1e7a IM |
1110 | /* |
1111 | * The next offset is stored in the 1st word. | |
1112 | * Only parse up until the offset increases: | |
1113 | */ | |
1114 | while (offset > prev_offset) { | |
b34e90b8 LV |
1115 | /* The block id is stored in the 2nd word */ |
1116 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1117 | /* set the pointer past the offset & block id */ | |
eae93755 | 1118 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1119 | break; |
1120 | } | |
136f1e7a | 1121 | prev_offset = offset; |
b34e90b8 LV |
1122 | offset = *((unsigned short *)(ptr + offset)); |
1123 | } | |
eae93755 | 1124 | if (!rio_table_hdr) { |
b92cc559 MBY |
1125 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1126 | "in EBDA - bailing!\n"); | |
b34e90b8 LV |
1127 | return; |
1128 | } | |
1129 | ||
eae93755 MBY |
1130 | ret = build_detail_arrays(); |
1131 | if (ret) { | |
b92cc559 | 1132 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
b34e90b8 | 1133 | return; |
eae93755 | 1134 | } |
b34e90b8 | 1135 | |
e465058d JM |
1136 | specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE); |
1137 | ||
d2105b10 JM |
1138 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
1139 | int dev; | |
f38db651 | 1140 | struct calgary_bus_info *info = &bus_info[bus]; |
d2105b10 | 1141 | |
e465058d JM |
1142 | if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY) |
1143 | continue; | |
d2105b10 | 1144 | |
f38db651 | 1145 | if (info->translation_disabled) |
e465058d | 1146 | continue; |
f38db651 | 1147 | |
e465058d | 1148 | /* |
d2105b10 JM |
1149 | * Scan the slots of the PCI bus to see if there is a device present. |
1150 | * The parent bus will be the zero-ith device, so start at 1. | |
e465058d | 1151 | */ |
d2105b10 JM |
1152 | for (dev = 1; dev < 8; dev++) { |
1153 | val = read_pci_config(bus, dev, 0, 0); | |
1154 | if (val != 0xffffffff || translate_empty_slots) { | |
1155 | tbl = alloc_tce_table(); | |
1156 | if (!tbl) | |
1157 | goto cleanup; | |
f38db651 | 1158 | info->tce_space = tbl; |
d2105b10 JM |
1159 | calgary_found = 1; |
1160 | break; | |
1161 | } | |
1162 | } | |
e465058d JM |
1163 | } |
1164 | ||
b92cc559 MBY |
1165 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1166 | calgary_found ? "found" : "not found"); | |
1167 | ||
d2105b10 | 1168 | if (calgary_found) { |
e465058d JM |
1169 | iommu_detected = 1; |
1170 | calgary_detected = 1; | |
de684652 MBY |
1171 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
1172 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " | |
1173 | "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, | |
1174 | debugging ? "enabled" : "disabled"); | |
e465058d JM |
1175 | } |
1176 | return; | |
1177 | ||
1178 | cleanup: | |
f38db651 MBY |
1179 | for (--bus; bus >= 0; --bus) { |
1180 | struct calgary_bus_info *info = &bus_info[bus]; | |
1181 | ||
1182 | if (info->tce_space) | |
1183 | free_tce_table(info->tce_space); | |
1184 | } | |
e465058d JM |
1185 | } |
1186 | ||
1187 | int __init calgary_iommu_init(void) | |
1188 | { | |
1189 | int ret; | |
1190 | ||
1191 | if (no_iommu || swiotlb) | |
1192 | return -ENODEV; | |
1193 | ||
1194 | if (!calgary_detected) | |
1195 | return -ENODEV; | |
1196 | ||
1197 | /* ok, we're trying to use Calgary - let's roll */ | |
1198 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1199 | ||
1200 | ret = calgary_init(); | |
1201 | if (ret) { | |
1202 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1203 | "falling back to no_iommu\n", ret); | |
1204 | if (end_pfn > MAX_DMA32_PFN) | |
1205 | printk(KERN_ERR "WARNING more than 4GB of memory, " | |
1206 | "32bit PCI may malfunction.\n"); | |
1207 | return ret; | |
1208 | } | |
1209 | ||
1210 | force_iommu = 1; | |
310adfdd | 1211 | bad_dma_address = 0x0; |
e465058d JM |
1212 | dma_ops = &calgary_dma_ops; |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | static int __init calgary_parse_options(char *p) | |
1218 | { | |
1219 | unsigned int bridge; | |
1220 | size_t len; | |
1221 | char* endp; | |
1222 | ||
1223 | while (*p) { | |
1224 | if (!strncmp(p, "64k", 3)) | |
1225 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1226 | else if (!strncmp(p, "128k", 4)) | |
1227 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1228 | else if (!strncmp(p, "256k", 4)) | |
1229 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1230 | else if (!strncmp(p, "512k", 4)) | |
1231 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1232 | else if (!strncmp(p, "1M", 2)) | |
1233 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1234 | else if (!strncmp(p, "2M", 2)) | |
1235 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1236 | else if (!strncmp(p, "4M", 2)) | |
1237 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1238 | else if (!strncmp(p, "8M", 2)) | |
1239 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1240 | ||
1241 | len = strlen("translate_empty_slots"); | |
1242 | if (!strncmp(p, "translate_empty_slots", len)) | |
1243 | translate_empty_slots = 1; | |
1244 | ||
1245 | len = strlen("disable"); | |
1246 | if (!strncmp(p, "disable", len)) { | |
1247 | p += len; | |
1248 | if (*p == '=') | |
1249 | ++p; | |
1250 | if (*p == '\0') | |
1251 | break; | |
1252 | bridge = simple_strtol(p, &endp, 0); | |
1253 | if (p == endp) | |
1254 | break; | |
1255 | ||
d2105b10 | 1256 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1257 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1258 | "translation for PHB %#x\n", bridge); |
f38db651 | 1259 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1260 | } |
1261 | } | |
1262 | ||
1263 | p = strpbrk(p, ","); | |
1264 | if (!p) | |
1265 | break; | |
1266 | ||
1267 | p++; /* skip ',' */ | |
1268 | } | |
1269 | return 1; | |
1270 | } | |
1271 | __setup("calgary=", calgary_parse_options); |