[net-next-2.6.git] / arch / x86 / pci / mmconfig_64.c

/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 *
 * This is an 64bit optimized version that always keeps the full mmconfig
 * space mapped. This allows lockless config space operation.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>

#define PREFIX "PCI: "

static char __iomem *get_virt(unsigned int seg, unsigned bus)
{
	struct pci_mmcfg_region *cfg;

	list_for_each_entry(cfg, &pci_mmcfg_list, list)
		if (cfg->segment == seg &&
		    (cfg->start_bus <= bus) &&
		    (cfg->end_bus >= bus))
			return cfg->virt;

	/* Fall back to type 0 */
	return NULL;
}

static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
{
	char __iomem *addr;

	addr = get_virt(seg, bus);
	if (!addr)
		return NULL;
	return addr + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	char __iomem *addr;

	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
	if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
err:		*value = -1;
		return -EINVAL;
	}

	addr = pci_dev_base(seg, bus, devfn);
	if (!addr)
		goto err;

	switch (len) {
	case 1:
		*value = mmio_config_readb(addr + reg);
		break;
	case 2:
		*value = mmio_config_readw(addr + reg);
		break;
	case 4:
		*value = mmio_config_readl(addr + reg);
		break;
	}

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	char __iomem *addr;

	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
	if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
		return -EINVAL;

	addr = pci_dev_base(seg, bus, devfn);
	if (!addr)
		return -EINVAL;

	switch (len) {
	case 1:
		mmio_config_writeb(addr + reg, value);
		break;
	case 2:
		mmio_config_writew(addr + reg, value);
		break;
	case 4:
		mmio_config_writel(addr + reg, value);
		break;
	}

	return 0;
}

static struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

static void __iomem * __init mcfg_ioremap(struct pci_mmcfg_region *cfg)
{
	void __iomem *addr;
	u64 start, size;
	int num_buses;

	start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
	num_buses = cfg->end_bus - cfg->start_bus + 1;
	size = PCI_MMCFG_BUS_OFFSET(num_buses);
	addr = ioremap_nocache(start, size);
	if (addr)
		addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
	return addr;
}

int __init pci_mmcfg_arch_init(void)
{
	struct pci_mmcfg_region *cfg;

	list_for_each_entry(cfg, &pci_mmcfg_list, list) {
		cfg->virt = mcfg_ioremap(cfg);
		if (!cfg->virt) {
			printk(KERN_ERR PREFIX "can't map MMCONFIG at %pR\n",
			       &cfg->res);
			pci_mmcfg_arch_free();
			return 0;
		}
	}
	raw_pci_ext_ops = &pci_mmcfg;
	return 1;
}

void __init pci_mmcfg_arch_free(void)
{
	struct pci_mmcfg_region *cfg;

	list_for_each_entry(cfg, &pci_mmcfg_list, list) {
		if (cfg->virt) {
			iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
			cfg->virt = NULL;
		}
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
15a58ed1	3	*
1da177e4 LT	4	* This is an 64bit optimized version that always keeps the full mmconfig
	5	* space mapped. This allows lockless config space operation.
	6	*/
	7
	8	#include <linux/pci.h>
	9	#include <linux/init.h>
54549391	10	#include <linux/acpi.h>
d6ece549	11	#include <linux/bitmap.h>
946f2ee5	12	#include <asm/e820.h>
82487711	13	#include <asm/pci_x86.h>
1da177e4	14
8c57786a BH	15	#define PREFIX "PCI: "
8c57786a BH	16
8b8a4e33	17	static char __iomem *get_virt(unsigned int seg, unsigned bus)
1da177e4	18	{
d215a9c8	19	struct pci_mmcfg_region *cfg;
1cde8a16	20
ff097ddd	21	list_for_each_entry(cfg, &pci_mmcfg_list, list)
d7e6b66f BH	22	if (cfg->segment == seg &&
	23	(cfg->start_bus <= bus) &&
	24	(cfg->end_bus >= bus))
3f0f5503	25	return cfg->virt;
3103039c	26
3103039c	27	/* Fall back to type 0 */
cc59853b	28	return NULL;
1cde8a16 GKH	29	}
1cde8a16 GKH	30
8b8a4e33	31	static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
1cde8a16	32	{
8b8a4e33	33	char __iomem *addr;
a0ca9909	34
d6ece549	35	addr = get_virt(seg, bus);
928cf8c6 AK	36	if (!addr)
928cf8c6 AK	37	return NULL;
df5eb1d6	38	return addr + (PCI_MMCFG_BUS_OFFSET(bus) \| (devfn << 12));
1da177e4 LT	39	}
	40
	41	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	42	unsigned int devfn, int reg, int len, u32 *value)
	43	{
8b8a4e33	44	char __iomem *addr;
1da177e4	45
928cf8c6	46	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
ecc16ba9	47	if (unlikely((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))) {
a0ca9909	48	err: *value = -1;
1da177e4	49	return -EINVAL;
49c93e84	50	}
1da177e4	51
928cf8c6 AK	52	addr = pci_dev_base(seg, bus, devfn);
928cf8c6 AK	53	if (!addr)
a0ca9909	54	goto err;
928cf8c6	55
1da177e4 LT	56	switch (len) {
1da177e4 LT	57	case 1:
3320ad99	58	*value = mmio_config_readb(addr + reg);
1da177e4 LT	59	break;
1da177e4 LT	60	case 2:
3320ad99	61	*value = mmio_config_readw(addr + reg);
1da177e4 LT	62	break;
1da177e4 LT	63	case 4:
3320ad99	64	*value = mmio_config_readl(addr + reg);
1da177e4 LT	65	break;
	66	}
	67
	68	return 0;
	69	}
	70
	71	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	72	unsigned int devfn, int reg, int len, u32 value)
	73	{
8b8a4e33	74	char __iomem *addr;
1da177e4	75
928cf8c6	76	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
1da177e4 LT	77	if (unlikely((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)))
	78	return -EINVAL;
	79
928cf8c6 AK	80	addr = pci_dev_base(seg, bus, devfn);
928cf8c6 AK	81	if (!addr)
a0ca9909	82	return -EINVAL;
928cf8c6	83
1da177e4 LT	84	switch (len) {
1da177e4 LT	85	case 1:
3320ad99	86	mmio_config_writeb(addr + reg, value);
1da177e4 LT	87	break;
1da177e4 LT	88	case 2:
3320ad99	89	mmio_config_writew(addr + reg, value);
1da177e4 LT	90	break;
1da177e4 LT	91	case 4:
3320ad99	92	mmio_config_writel(addr + reg, value);
1da177e4 LT	93	break;
	94	}
	95
	96	return 0;
	97	}
	98
	99	static struct pci_raw_ops pci_mmcfg = {
	100	.read = pci_mmcfg_read,
	101	.write = pci_mmcfg_write,
	102	};
	103
d215a9c8	104	static void __iomem * __init mcfg_ioremap(struct pci_mmcfg_region *cfg)
44de0203 OH	105	{
44de0203 OH	106	void __iomem *addr;
068258bc	107	u64 start, size;
df5eb1d6	108	int num_buses;
068258bc	109
d7e6b66f BH	110	start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
d7e6b66f BH	111	num_buses = cfg->end_bus - cfg->start_bus + 1;
df5eb1d6	112	size = PCI_MMCFG_BUS_OFFSET(num_buses);
068258bc	113	addr = ioremap_nocache(start, size);
8c57786a	114	if (addr)
d7e6b66f	115	addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
44de0203 OH	116	return addr;
	117	}
	118
b7867394	119	int __init pci_mmcfg_arch_init(void)
1da177e4	120	{
3f0f5503	121	struct pci_mmcfg_region *cfg;
b7867394	122
ff097ddd	123	list_for_each_entry(cfg, &pci_mmcfg_list, list) {
3f0f5503 BH	124	cfg->virt = mcfg_ioremap(cfg);
3f0f5503 BH	125	if (!cfg->virt) {
8c57786a BH	126	printk(KERN_ERR PREFIX "can't map MMCONFIG at %pR\n",
8c57786a BH	127	&cfg->res);
0b64ad71	128	pci_mmcfg_arch_free();
b7867394	129	return 0;
1cde8a16	130	}
1cde8a16	131	}
b6ce068a	132	raw_pci_ext_ops = &pci_mmcfg;
b7867394	133	return 1;
1da177e4	134	}
0b64ad71 YL	135
	136	void __init pci_mmcfg_arch_free(void)
	137	{
3f0f5503	138	struct pci_mmcfg_region *cfg;
0b64ad71	139
ff097ddd	140	list_for_each_entry(cfg, &pci_mmcfg_list, list) {
3f0f5503 BH	141	if (cfg->virt) {
	142	iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
	143	cfg->virt = NULL;
0b64ad71 YL	144	}
0b64ad71 YL	145	}
0b64ad71	146	}