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Commit | Line | Data |
---|---|---|
b7867394 OG |
1 | /* |
2 | * mmconfig-shared.c - Low-level direct PCI config space access via | |
3 | * MMCONFIG - common code between i386 and x86-64. | |
4 | * | |
5 | * This code does: | |
9358c693 | 6 | * - known chipset handling |
b7867394 OG |
7 | * - ACPI decoding and validation |
8 | * | |
9 | * Per-architecture code takes care of the mappings and accesses | |
10 | * themselves. | |
11 | */ | |
12 | ||
13 | #include <linux/pci.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/acpi.h> | |
5f0db7a2 | 16 | #include <linux/sfi_acpi.h> |
b7867394 | 17 | #include <linux/bitmap.h> |
9a08f7d3 | 18 | #include <linux/dmi.h> |
068258bc | 19 | #include <linux/sort.h> |
b7867394 | 20 | #include <asm/e820.h> |
82487711 | 21 | #include <asm/pci_x86.h> |
5f0db7a2 | 22 | #include <asm/acpi.h> |
b7867394 | 23 | |
f4a2d584 | 24 | #define PREFIX "PCI: " |
a192a958 | 25 | |
a5ba7971 AD |
26 | /* Indicate if the mmcfg resources have been placed into the resource table. */ |
27 | static int __initdata pci_mmcfg_resources_inserted; | |
28 | ||
7da7d360 BH |
29 | static __init void free_all_mmcfg(void) |
30 | { | |
56ddf4d3 BH |
31 | int i; |
32 | struct pci_mmcfg_region *cfg; | |
33 | ||
7da7d360 | 34 | pci_mmcfg_arch_free(); |
56ddf4d3 BH |
35 | for (i = 0; i < pci_mmcfg_config_num; i++) { |
36 | cfg = &pci_mmcfg_config[i]; | |
37 | if (cfg->res.parent) | |
38 | release_resource(&cfg->res); | |
39 | } | |
7da7d360 BH |
40 | pci_mmcfg_config_num = 0; |
41 | kfree(pci_mmcfg_config); | |
42 | pci_mmcfg_config = NULL; | |
43 | } | |
44 | ||
d215a9c8 BH |
45 | static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, |
46 | int end, u64 addr) | |
068258bc | 47 | { |
d215a9c8 | 48 | struct pci_mmcfg_region *new; |
7da7d360 BH |
49 | int new_num = pci_mmcfg_config_num + 1; |
50 | int i = pci_mmcfg_config_num; | |
56ddf4d3 BH |
51 | int num_buses; |
52 | struct resource *res; | |
068258bc | 53 | |
f7ca6984 BH |
54 | if (addr == 0) |
55 | return NULL; | |
56 | ||
068258bc YL |
57 | new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL); |
58 | if (!new) | |
7da7d360 | 59 | return NULL; |
068258bc YL |
60 | |
61 | if (pci_mmcfg_config) { | |
62 | memcpy(new, pci_mmcfg_config, | |
63 | sizeof(pci_mmcfg_config[0]) * new_num); | |
64 | kfree(pci_mmcfg_config); | |
65 | } | |
66 | pci_mmcfg_config = new; | |
068258bc | 67 | pci_mmcfg_config_num++; |
95cf1cf0 BH |
68 | |
69 | new = &pci_mmcfg_config[i]; | |
70 | ||
71 | new->address = addr; | |
72 | new->segment = segment; | |
73 | new->start_bus = start; | |
74 | new->end_bus = end; | |
7da7d360 | 75 | |
56ddf4d3 BH |
76 | num_buses = end - start + 1; |
77 | res = &new->res; | |
78 | res->start = addr + PCI_MMCFG_BUS_OFFSET(start); | |
79 | res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1; | |
80 | res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
81 | snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN, | |
82 | "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end); | |
83 | res->name = new->name; | |
84 | ||
7da7d360 | 85 | return &pci_mmcfg_config[i]; |
068258bc YL |
86 | } |
87 | ||
429d512e | 88 | static const char __init *pci_mmcfg_e7520(void) |
9358c693 OG |
89 | { |
90 | u32 win; | |
bb63b421 | 91 | raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); |
9358c693 | 92 | |
b5229dbb | 93 | win = win & 0xf000; |
068258bc YL |
94 | if (win == 0x0000 || win == 0xf000) |
95 | return NULL; | |
96 | ||
7da7d360 | 97 | if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL) |
068258bc YL |
98 | return NULL; |
99 | ||
9358c693 OG |
100 | return "Intel Corporation E7520 Memory Controller Hub"; |
101 | } | |
102 | ||
429d512e | 103 | static const char __init *pci_mmcfg_intel_945(void) |
9358c693 OG |
104 | { |
105 | u32 pciexbar, mask = 0, len = 0; | |
106 | ||
bb63b421 | 107 | raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); |
9358c693 OG |
108 | |
109 | /* Enable bit */ | |
110 | if (!(pciexbar & 1)) | |
068258bc | 111 | return NULL; |
9358c693 OG |
112 | |
113 | /* Size bits */ | |
114 | switch ((pciexbar >> 1) & 3) { | |
115 | case 0: | |
116 | mask = 0xf0000000U; | |
117 | len = 0x10000000U; | |
118 | break; | |
119 | case 1: | |
120 | mask = 0xf8000000U; | |
121 | len = 0x08000000U; | |
122 | break; | |
123 | case 2: | |
124 | mask = 0xfc000000U; | |
125 | len = 0x04000000U; | |
126 | break; | |
127 | default: | |
068258bc | 128 | return NULL; |
9358c693 OG |
129 | } |
130 | ||
131 | /* Errata #2, things break when not aligned on a 256Mb boundary */ | |
132 | /* Can only happen in 64M/128M mode */ | |
133 | ||
134 | if ((pciexbar & mask) & 0x0fffffffU) | |
068258bc | 135 | return NULL; |
9358c693 | 136 | |
b5229dbb OG |
137 | /* Don't hit the APIC registers and their friends */ |
138 | if ((pciexbar & mask) >= 0xf0000000U) | |
068258bc YL |
139 | return NULL; |
140 | ||
7da7d360 | 141 | if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL) |
068258bc YL |
142 | return NULL; |
143 | ||
9358c693 OG |
144 | return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; |
145 | } | |
146 | ||
7fd0da40 YL |
147 | static const char __init *pci_mmcfg_amd_fam10h(void) |
148 | { | |
149 | u32 low, high, address; | |
150 | u64 base, msr; | |
151 | int i; | |
7da7d360 | 152 | unsigned segnbits = 0, busnbits, end_bus; |
7fd0da40 | 153 | |
5f0b2976 YL |
154 | if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) |
155 | return NULL; | |
156 | ||
7fd0da40 YL |
157 | address = MSR_FAM10H_MMIO_CONF_BASE; |
158 | if (rdmsr_safe(address, &low, &high)) | |
159 | return NULL; | |
160 | ||
161 | msr = high; | |
162 | msr <<= 32; | |
163 | msr |= low; | |
164 | ||
165 | /* mmconfig is not enable */ | |
166 | if (!(msr & FAM10H_MMIO_CONF_ENABLE)) | |
167 | return NULL; | |
168 | ||
169 | base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); | |
170 | ||
171 | busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & | |
172 | FAM10H_MMIO_CONF_BUSRANGE_MASK; | |
173 | ||
174 | /* | |
175 | * only handle bus 0 ? | |
176 | * need to skip it | |
177 | */ | |
178 | if (!busnbits) | |
179 | return NULL; | |
180 | ||
181 | if (busnbits > 8) { | |
182 | segnbits = busnbits - 8; | |
183 | busnbits = 8; | |
184 | } | |
185 | ||
7da7d360 | 186 | end_bus = (1 << busnbits) - 1; |
068258bc | 187 | for (i = 0; i < (1 << segnbits); i++) |
7da7d360 BH |
188 | if (pci_mmconfig_add(i, 0, end_bus, |
189 | base + (1<<28) * i) == NULL) { | |
190 | free_all_mmcfg(); | |
191 | return NULL; | |
192 | } | |
7fd0da40 YL |
193 | |
194 | return "AMD Family 10h NB"; | |
195 | } | |
196 | ||
5546d6f5 ES |
197 | static bool __initdata mcp55_checked; |
198 | static const char __init *pci_mmcfg_nvidia_mcp55(void) | |
199 | { | |
200 | int bus; | |
201 | int mcp55_mmconf_found = 0; | |
202 | ||
203 | static const u32 extcfg_regnum = 0x90; | |
204 | static const u32 extcfg_regsize = 4; | |
205 | static const u32 extcfg_enable_mask = 1<<31; | |
206 | static const u32 extcfg_start_mask = 0xff<<16; | |
207 | static const int extcfg_start_shift = 16; | |
208 | static const u32 extcfg_size_mask = 0x3<<28; | |
209 | static const int extcfg_size_shift = 28; | |
210 | static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20}; | |
211 | static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff}; | |
212 | static const int extcfg_base_lshift = 25; | |
213 | ||
214 | /* | |
215 | * do check if amd fam10h already took over | |
216 | */ | |
217 | if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked) | |
218 | return NULL; | |
219 | ||
220 | mcp55_checked = true; | |
221 | for (bus = 0; bus < 256; bus++) { | |
222 | u64 base; | |
223 | u32 l, extcfg; | |
224 | u16 vendor, device; | |
225 | int start, size_index, end; | |
226 | ||
227 | raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l); | |
228 | vendor = l & 0xffff; | |
229 | device = (l >> 16) & 0xffff; | |
230 | ||
231 | if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) | |
232 | continue; | |
233 | ||
234 | raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum, | |
235 | extcfg_regsize, &extcfg); | |
236 | ||
237 | if (!(extcfg & extcfg_enable_mask)) | |
238 | continue; | |
239 | ||
5546d6f5 ES |
240 | size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift; |
241 | base = extcfg & extcfg_base_mask[size_index]; | |
242 | /* base could > 4G */ | |
243 | base <<= extcfg_base_lshift; | |
244 | start = (extcfg & extcfg_start_mask) >> extcfg_start_shift; | |
245 | end = start + extcfg_sizebus[size_index] - 1; | |
7da7d360 BH |
246 | if (pci_mmconfig_add(0, start, end, base) == NULL) |
247 | continue; | |
5546d6f5 ES |
248 | mcp55_mmconf_found++; |
249 | } | |
250 | ||
251 | if (!mcp55_mmconf_found) | |
252 | return NULL; | |
253 | ||
254 | return "nVidia MCP55"; | |
255 | } | |
256 | ||
9358c693 | 257 | struct pci_mmcfg_hostbridge_probe { |
7fd0da40 YL |
258 | u32 bus; |
259 | u32 devfn; | |
9358c693 OG |
260 | u32 vendor; |
261 | u32 device; | |
262 | const char *(*probe)(void); | |
263 | }; | |
264 | ||
429d512e | 265 | static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { |
7fd0da40 YL |
266 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, |
267 | PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, | |
268 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, | |
269 | PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, | |
270 | { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, | |
271 | 0x1200, pci_mmcfg_amd_fam10h }, | |
272 | { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, | |
273 | 0x1200, pci_mmcfg_amd_fam10h }, | |
5546d6f5 ES |
274 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA, |
275 | 0x0369, pci_mmcfg_nvidia_mcp55 }, | |
9358c693 OG |
276 | }; |
277 | ||
068258bc YL |
278 | static int __init cmp_mmcfg(const void *x1, const void *x2) |
279 | { | |
280 | const typeof(pci_mmcfg_config[0]) *m1 = x1; | |
281 | const typeof(pci_mmcfg_config[0]) *m2 = x2; | |
282 | int start1, start2; | |
283 | ||
d7e6b66f BH |
284 | start1 = m1->start_bus; |
285 | start2 = m2->start_bus; | |
068258bc YL |
286 | |
287 | return start1 - start2; | |
288 | } | |
289 | ||
290 | static void __init pci_mmcfg_check_end_bus_number(void) | |
291 | { | |
292 | int i; | |
293 | typeof(pci_mmcfg_config[0]) *cfg, *cfgx; | |
294 | ||
295 | /* sort them at first */ | |
296 | sort(pci_mmcfg_config, pci_mmcfg_config_num, | |
297 | sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL); | |
298 | ||
299 | /* last one*/ | |
300 | if (pci_mmcfg_config_num > 0) { | |
301 | i = pci_mmcfg_config_num - 1; | |
302 | cfg = &pci_mmcfg_config[i]; | |
d7e6b66f BH |
303 | if (cfg->end_bus < cfg->start_bus) |
304 | cfg->end_bus = 255; | |
068258bc YL |
305 | } |
306 | ||
307 | /* don't overlap please */ | |
308 | for (i = 0; i < pci_mmcfg_config_num - 1; i++) { | |
309 | cfg = &pci_mmcfg_config[i]; | |
310 | cfgx = &pci_mmcfg_config[i+1]; | |
311 | ||
d7e6b66f BH |
312 | if (cfg->end_bus < cfg->start_bus) |
313 | cfg->end_bus = 255; | |
068258bc | 314 | |
d7e6b66f BH |
315 | if (cfg->end_bus >= cfgx->start_bus) |
316 | cfg->end_bus = cfgx->start_bus - 1; | |
068258bc YL |
317 | } |
318 | } | |
319 | ||
9358c693 OG |
320 | static int __init pci_mmcfg_check_hostbridge(void) |
321 | { | |
322 | u32 l; | |
7fd0da40 | 323 | u32 bus, devfn; |
9358c693 OG |
324 | u16 vendor, device; |
325 | int i; | |
326 | const char *name; | |
327 | ||
bb63b421 YL |
328 | if (!raw_pci_ops) |
329 | return 0; | |
330 | ||
7da7d360 | 331 | free_all_mmcfg(); |
9358c693 | 332 | |
068258bc | 333 | for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) { |
7fd0da40 YL |
334 | bus = pci_mmcfg_probes[i].bus; |
335 | devfn = pci_mmcfg_probes[i].devfn; | |
bb63b421 | 336 | raw_pci_ops->read(0, bus, devfn, 0, 4, &l); |
7fd0da40 YL |
337 | vendor = l & 0xffff; |
338 | device = (l >> 16) & 0xffff; | |
339 | ||
068258bc | 340 | name = NULL; |
429d512e OH |
341 | if (pci_mmcfg_probes[i].vendor == vendor && |
342 | pci_mmcfg_probes[i].device == device) | |
9358c693 OG |
343 | name = pci_mmcfg_probes[i].probe(); |
344 | ||
068258bc YL |
345 | if (name) |
346 | printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n", | |
347 | name); | |
9358c693 OG |
348 | } |
349 | ||
068258bc YL |
350 | /* some end_bus_number is crazy, fix it */ |
351 | pci_mmcfg_check_end_bus_number(); | |
352 | ||
353 | return pci_mmcfg_config_num != 0; | |
9358c693 OG |
354 | } |
355 | ||
ebd60cd6 | 356 | static void __init pci_mmcfg_insert_resources(void) |
6a0668fc | 357 | { |
6a0668fc | 358 | int i; |
56ddf4d3 | 359 | struct pci_mmcfg_region *cfg; |
6a0668fc | 360 | |
56ddf4d3 BH |
361 | for (i = 0; i < pci_mmcfg_config_num; i++) { |
362 | cfg = &pci_mmcfg_config[i]; | |
363 | insert_resource(&iomem_resource, &cfg->res); | |
6a0668fc | 364 | } |
a5ba7971 AD |
365 | |
366 | /* Mark that the resources have been inserted. */ | |
367 | pci_mmcfg_resources_inserted = 1; | |
6a0668fc OG |
368 | } |
369 | ||
7752d5cf RH |
370 | static acpi_status __init check_mcfg_resource(struct acpi_resource *res, |
371 | void *data) | |
372 | { | |
373 | struct resource *mcfg_res = data; | |
374 | struct acpi_resource_address64 address; | |
375 | acpi_status status; | |
376 | ||
377 | if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { | |
378 | struct acpi_resource_fixed_memory32 *fixmem32 = | |
379 | &res->data.fixed_memory32; | |
380 | if (!fixmem32) | |
381 | return AE_OK; | |
382 | if ((mcfg_res->start >= fixmem32->address) && | |
75e613cd | 383 | (mcfg_res->end < (fixmem32->address + |
7752d5cf RH |
384 | fixmem32->address_length))) { |
385 | mcfg_res->flags = 1; | |
386 | return AE_CTRL_TERMINATE; | |
387 | } | |
388 | } | |
389 | if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && | |
390 | (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) | |
391 | return AE_OK; | |
392 | ||
393 | status = acpi_resource_to_address64(res, &address); | |
394 | if (ACPI_FAILURE(status) || | |
395 | (address.address_length <= 0) || | |
396 | (address.resource_type != ACPI_MEMORY_RANGE)) | |
397 | return AE_OK; | |
398 | ||
399 | if ((mcfg_res->start >= address.minimum) && | |
75e613cd | 400 | (mcfg_res->end < (address.minimum + address.address_length))) { |
7752d5cf RH |
401 | mcfg_res->flags = 1; |
402 | return AE_CTRL_TERMINATE; | |
403 | } | |
404 | return AE_OK; | |
405 | } | |
406 | ||
407 | static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, | |
408 | void *context, void **rv) | |
409 | { | |
410 | struct resource *mcfg_res = context; | |
411 | ||
412 | acpi_walk_resources(handle, METHOD_NAME__CRS, | |
413 | check_mcfg_resource, context); | |
414 | ||
415 | if (mcfg_res->flags) | |
416 | return AE_CTRL_TERMINATE; | |
417 | ||
418 | return AE_OK; | |
419 | } | |
420 | ||
a83fe32f | 421 | static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used) |
7752d5cf RH |
422 | { |
423 | struct resource mcfg_res; | |
424 | ||
425 | mcfg_res.start = start; | |
75e613cd | 426 | mcfg_res.end = end - 1; |
7752d5cf RH |
427 | mcfg_res.flags = 0; |
428 | ||
429 | acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); | |
430 | ||
431 | if (!mcfg_res.flags) | |
432 | acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, | |
433 | NULL); | |
434 | ||
435 | return mcfg_res.flags; | |
436 | } | |
437 | ||
a83fe32f YL |
438 | typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type); |
439 | ||
440 | static int __init is_mmconf_reserved(check_reserved_t is_reserved, | |
441 | u64 addr, u64 size, int i, | |
442 | typeof(pci_mmcfg_config[0]) *cfg, int with_e820) | |
443 | { | |
444 | u64 old_size = size; | |
56ddf4d3 | 445 | int valid = 0, num_buses; |
a83fe32f | 446 | |
044cd809 | 447 | while (!is_reserved(addr, addr + size, E820_RESERVED)) { |
a83fe32f YL |
448 | size >>= 1; |
449 | if (size < (16UL<<20)) | |
450 | break; | |
451 | } | |
452 | ||
453 | if (size >= (16UL<<20) || size == old_size) { | |
454 | printk(KERN_NOTICE | |
455 | "PCI: MCFG area at %Lx reserved in %s\n", | |
456 | addr, with_e820?"E820":"ACPI motherboard resources"); | |
457 | valid = 1; | |
458 | ||
459 | if (old_size != size) { | |
d7e6b66f BH |
460 | /* update end_bus */ |
461 | cfg->end_bus = cfg->start_bus + ((size>>20) - 1); | |
56ddf4d3 BH |
462 | num_buses = cfg->end_bus - cfg->start_bus + 1; |
463 | cfg->res.end = cfg->res.start + | |
464 | PCI_MMCFG_BUS_OFFSET(num_buses) - 1; | |
465 | snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN, | |
466 | "PCI MMCONFIG %04x [bus %02x-%02x]", | |
467 | cfg->segment, cfg->start_bus, cfg->end_bus); | |
a83fe32f YL |
468 | printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx " |
469 | "segment %hu buses %u - %u\n", | |
d7e6b66f BH |
470 | i, (unsigned long)cfg->address, cfg->segment, |
471 | (unsigned int)cfg->start_bus, | |
472 | (unsigned int)cfg->end_bus); | |
a83fe32f YL |
473 | } |
474 | } | |
475 | ||
476 | return valid; | |
477 | } | |
478 | ||
bb63b421 | 479 | static void __init pci_mmcfg_reject_broken(int early) |
44de0203 | 480 | { |
26054ed0 | 481 | typeof(pci_mmcfg_config[0]) *cfg; |
7752d5cf | 482 | int i; |
26054ed0 | 483 | |
f7ca6984 | 484 | if (pci_mmcfg_config_num == 0) |
26054ed0 OH |
485 | return; |
486 | ||
7752d5cf | 487 | for (i = 0; i < pci_mmcfg_config_num; i++) { |
56ddf4d3 | 488 | int valid = 0; |
a83fe32f YL |
489 | u64 addr, size; |
490 | ||
7752d5cf | 491 | cfg = &pci_mmcfg_config[i]; |
56ddf4d3 BH |
492 | addr = cfg->res.start; |
493 | size = resource_size(&cfg->res); | |
05c58b8a | 494 | printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx " |
7752d5cf | 495 | "segment %hu buses %u - %u\n", |
d7e6b66f BH |
496 | i, (unsigned long)cfg->address, cfg->segment, |
497 | (unsigned int)cfg->start_bus, | |
498 | (unsigned int)cfg->end_bus); | |
05c58b8a | 499 | |
5f0db7a2 | 500 | if (!early && !acpi_disabled) |
a83fe32f | 501 | valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0); |
05c58b8a YL |
502 | |
503 | if (valid) | |
504 | continue; | |
505 | ||
506 | if (!early) | |
7752d5cf RH |
507 | printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" |
508 | " reserved in ACPI motherboard resources\n", | |
509 | cfg->address); | |
a83fe32f | 510 | |
05c58b8a | 511 | /* Don't try to do this check unless configuration |
bb63b421 | 512 | type 1 is available. how about type 2 ?*/ |
a83fe32f YL |
513 | if (raw_pci_ops) |
514 | valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1); | |
05c58b8a YL |
515 | |
516 | if (!valid) | |
517 | goto reject; | |
44de0203 | 518 | } |
7752d5cf | 519 | |
26054ed0 OH |
520 | return; |
521 | ||
522 | reject: | |
ef310237 | 523 | printk(KERN_INFO "PCI: Not using MMCONFIG.\n"); |
7da7d360 | 524 | free_all_mmcfg(); |
44de0203 OH |
525 | } |
526 | ||
05c58b8a | 527 | static int __initdata known_bridge; |
7752d5cf | 528 | |
c4bf2f37 | 529 | /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ |
d215a9c8 | 530 | struct pci_mmcfg_region *pci_mmcfg_config; |
c4bf2f37 LB |
531 | int pci_mmcfg_config_num; |
532 | ||
9a08f7d3 BH |
533 | static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, |
534 | struct acpi_mcfg_allocation *cfg) | |
c4bf2f37 | 535 | { |
9a08f7d3 BH |
536 | int year; |
537 | ||
538 | if (cfg->address < 0xFFFFFFFF) | |
539 | return 0; | |
540 | ||
c4bf2f37 | 541 | if (!strcmp(mcfg->header.oem_id, "SGI")) |
9a08f7d3 | 542 | return 0; |
c4bf2f37 | 543 | |
9a08f7d3 BH |
544 | if (mcfg->header.revision >= 1) { |
545 | if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && | |
546 | year >= 2010) | |
547 | return 0; | |
548 | } | |
549 | ||
550 | printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx " | |
551 | "is above 4GB, ignored\n", cfg->pci_segment, | |
552 | cfg->start_bus_number, cfg->end_bus_number, cfg->address); | |
553 | return -EINVAL; | |
c4bf2f37 LB |
554 | } |
555 | ||
556 | static int __init pci_parse_mcfg(struct acpi_table_header *header) | |
557 | { | |
558 | struct acpi_table_mcfg *mcfg; | |
d3578ef7 | 559 | struct acpi_mcfg_allocation *cfg_table, *cfg; |
c4bf2f37 | 560 | unsigned long i; |
7da7d360 | 561 | int entries; |
c4bf2f37 LB |
562 | |
563 | if (!header) | |
564 | return -EINVAL; | |
565 | ||
566 | mcfg = (struct acpi_table_mcfg *)header; | |
567 | ||
568 | /* how many config structures do we have */ | |
7da7d360 | 569 | free_all_mmcfg(); |
e823d6ff | 570 | entries = 0; |
c4bf2f37 LB |
571 | i = header->length - sizeof(struct acpi_table_mcfg); |
572 | while (i >= sizeof(struct acpi_mcfg_allocation)) { | |
e823d6ff | 573 | entries++; |
c4bf2f37 LB |
574 | i -= sizeof(struct acpi_mcfg_allocation); |
575 | }; | |
e823d6ff | 576 | if (entries == 0) { |
c4bf2f37 LB |
577 | printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); |
578 | return -ENODEV; | |
579 | } | |
580 | ||
d3578ef7 | 581 | cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1]; |
e823d6ff | 582 | for (i = 0; i < entries; i++) { |
d3578ef7 BH |
583 | cfg = &cfg_table[i]; |
584 | if (acpi_mcfg_check_entry(mcfg, cfg)) { | |
7da7d360 | 585 | free_all_mmcfg(); |
c4bf2f37 LB |
586 | return -ENODEV; |
587 | } | |
7da7d360 BH |
588 | |
589 | if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, | |
590 | cfg->end_bus_number, cfg->address) == NULL) { | |
591 | printk(KERN_WARNING PREFIX | |
592 | "no memory for MCFG entries\n"); | |
593 | free_all_mmcfg(); | |
594 | return -ENOMEM; | |
595 | } | |
c4bf2f37 LB |
596 | } |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
968cbfad | 601 | static void __init __pci_mmcfg_init(int early) |
b7867394 | 602 | { |
7752d5cf | 603 | /* MMCONFIG disabled */ |
b7867394 OG |
604 | if ((pci_probe & PCI_PROBE_MMCONF) == 0) |
605 | return; | |
606 | ||
7752d5cf | 607 | /* MMCONFIG already enabled */ |
05c58b8a | 608 | if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) |
7752d5cf | 609 | return; |
9358c693 | 610 | |
05c58b8a YL |
611 | /* for late to exit */ |
612 | if (known_bridge) | |
613 | return; | |
7752d5cf | 614 | |
bb63b421 | 615 | if (early) { |
05c58b8a YL |
616 | if (pci_mmcfg_check_hostbridge()) |
617 | known_bridge = 1; | |
618 | } | |
619 | ||
068258bc | 620 | if (!known_bridge) |
5f0db7a2 | 621 | acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); |
068258bc YL |
622 | |
623 | pci_mmcfg_reject_broken(early); | |
b7867394 | 624 | |
f7ca6984 | 625 | if (pci_mmcfg_config_num == 0) |
b7867394 OG |
626 | return; |
627 | ||
ebd60cd6 | 628 | if (pci_mmcfg_arch_init()) |
b7867394 | 629 | pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; |
ebd60cd6 | 630 | else { |
a5ba7971 AD |
631 | /* |
632 | * Signal not to attempt to insert mmcfg resources because | |
633 | * the architecture mmcfg setup could not initialize. | |
634 | */ | |
635 | pci_mmcfg_resources_inserted = 1; | |
b7867394 OG |
636 | } |
637 | } | |
a5ba7971 | 638 | |
bb63b421 | 639 | void __init pci_mmcfg_early_init(void) |
05c58b8a | 640 | { |
bb63b421 | 641 | __pci_mmcfg_init(1); |
05c58b8a YL |
642 | } |
643 | ||
644 | void __init pci_mmcfg_late_init(void) | |
645 | { | |
bb63b421 | 646 | __pci_mmcfg_init(0); |
05c58b8a YL |
647 | } |
648 | ||
a5ba7971 AD |
649 | static int __init pci_mmcfg_late_insert_resources(void) |
650 | { | |
651 | /* | |
652 | * If resources are already inserted or we are not using MMCONFIG, | |
653 | * don't insert the resources. | |
654 | */ | |
655 | if ((pci_mmcfg_resources_inserted == 1) || | |
656 | (pci_probe & PCI_PROBE_MMCONF) == 0 || | |
f7ca6984 | 657 | (pci_mmcfg_config_num == 0)) |
a5ba7971 AD |
658 | return 1; |
659 | ||
660 | /* | |
661 | * Attempt to insert the mmcfg resources but not with the busy flag | |
662 | * marked so it won't cause request errors when __request_region is | |
663 | * called. | |
664 | */ | |
ebd60cd6 | 665 | pci_mmcfg_insert_resources(); |
a5ba7971 AD |
666 | |
667 | return 0; | |
668 | } | |
669 | ||
670 | /* | |
671 | * Perform MMCONFIG resource insertion after PCI initialization to allow for | |
672 | * misprogrammed MCFG tables that state larger sizes but actually conflict | |
673 | * with other system resources. | |
674 | */ | |
675 | late_initcall(pci_mmcfg_late_insert_resources); |