[net-next-2.6.git] / arch / x86 / pci / amd_bus.c

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/topology.h>
#include <linux/cpu.h>
#include <linux/range.h>

#include <asm/pci_x86.h>

#ifdef CONFIG_X86_64
#include <asm/pci-direct.h>
#endif

#include "bus_numa.h"

/*
 * This discovers the pcibus <-> node mapping on AMD K8.
 * also get peer root bus resource for io,mmio
 */

#ifdef CONFIG_X86_64

struct pci_hostbridge_probe {
	u32 bus;
	u32 slot;
	u32 vendor;
	u32 device;
};

static struct pci_hostbridge_probe pci_probes[] __initdata = {
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
};

static u64 __initdata fam10h_mmconf_start;
static u64 __initdata fam10h_mmconf_end;
static void __init get_pci_mmcfg_amd_fam10h_range(void)
{
	u32 address;
	u64 base, msr;
	unsigned segn_busn_bits;

	/* assume all cpus from fam10h have mmconf */
        if (boot_cpu_data.x86 < 0x10)
		return;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	rdmsrl(address, msr);

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	fam10h_mmconf_start = base;
	fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
}

#define RANGE_NUM 16

/**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 * Registers found in the K8 northbridge
 */
static int __init early_fill_mp_bus_info(void)
{
	int i;
	int j;
	unsigned bus;
	unsigned slot;
	int node;
	int link;
	int def_node;
	int def_link;
	struct pci_root_info *info;
	u32 reg;
	struct resource *res;
	u64 start;
	u64 end;
	struct range range[RANGE_NUM];
	u64 val;
	u32 address;
	bool found;

	if (!early_pci_allowed())
		return -1;

	found = false;
	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
		u32 id;
		u16 device;
		u16 vendor;

		bus = pci_probes[i].bus;
		slot = pci_probes[i].slot;
		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);

		vendor = id & 0xffff;
		device = (id>>16) & 0xffff;
		if (pci_probes[i].vendor == vendor &&
		    pci_probes[i].device == device) {
			found = true;
			break;
		}
	}

	if (!found)
		return 0;

	pci_root_num = 0;
	for (i = 0; i < 4; i++) {
		int min_bus;
		int max_bus;
		reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));

		/* Check if that register is enabled for bus range */
		if ((reg & 7) != 3)
			continue;

		min_bus = (reg >> 16) & 0xff;
		max_bus = (reg >> 24) & 0xff;
		node = (reg >> 4) & 0x07;
#ifdef CONFIG_NUMA
		for (j = min_bus; j <= max_bus; j++)
			set_mp_bus_to_node(j, node);
#endif
		link = (reg >> 8) & 0x03;

		info = &pci_root_info[pci_root_num];
		info->bus_min = min_bus;
		info->bus_max = max_bus;
		info->node = node;
		info->link = link;
		sprintf(info->name, "PCI Bus #%02x", min_bus);
		pci_root_num++;
	}

	/* get the default node and link for left over res */
	reg = read_pci_config(bus, slot, 0, 0x60);
	def_node = (reg >> 8) & 0x07;
	reg = read_pci_config(bus, slot, 0, 0x64);
	def_link = (reg >> 8) & 0x03;

	memset(range, 0, sizeof(range));
	range[0].end = 0xffff;
	/* io port resource */
	for (i = 0; i < 4; i++) {
		reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xfff000;
		reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xfff000) | 0xfff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];
		printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
		       node, link, start, end);

		/* kernel only handle 16 bit only */
		if (end > 0xffff)
			end = 0xffff;
		update_res(info, start, end, IORESOURCE_IO, 1);
		subtract_range(range, RANGE_NUM, start, end);
	}
	/* add left over io port range to def node/link, [0, 0xffff] */
	/* find the position */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_IO, 1);
		}
	}

	memset(range, 0, sizeof(range));
	/* 0xfd00000000-0xffffffffff for HT */
	range[0].end = (0xfdULL<<32) - 1;

	/* need to take out [0, TOM) for RAM*/
	address = MSR_K8_TOP_MEM1;
	rdmsrl(address, val);
	end = (val & 0xffffff800000ULL);
	printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
	if (end < (1ULL<<32))
		subtract_range(range, RANGE_NUM, 0, end - 1);

	/* get mmconfig */
	get_pci_mmcfg_amd_fam10h_range();
	/* need to take out mmconf range */
	if (fam10h_mmconf_end) {
		printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
		subtract_range(range, RANGE_NUM, fam10h_mmconf_start, fam10h_mmconf_end);
	}

	/* mmio resource */
	for (i = 0; i < 8; i++) {
		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xffffff00; /* 39:16 on 31:8*/
		start <<= 8;
		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xffffff00);
		end <<= 8;
		end |= 0xffff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];

		printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
		       node, link, start, end);
		/*
		 * some sick allocation would have range overlap with fam10h
		 * mmconf range, so need to update start and end.
		 */
		if (fam10h_mmconf_end) {
			int changed = 0;
			u64 endx = 0;
			if (start >= fam10h_mmconf_start &&
			    start <= fam10h_mmconf_end) {
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}

			if (end >= fam10h_mmconf_start &&
			    end <= fam10h_mmconf_end) {
				end = fam10h_mmconf_start - 1;
				changed = 1;
			}

			if (start < fam10h_mmconf_start &&
			    end > fam10h_mmconf_end) {
				/* we got a hole */
				endx = fam10h_mmconf_start - 1;
				update_res(info, start, endx, IORESOURCE_MEM, 0);
				subtract_range(range, RANGE_NUM, start, endx);
				printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}
			if (changed) {
				if (start <= end) {
					printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
				} else {
					printk(KERN_CONT "%s\n", endx?"":" ==> none");
					continue;
				}
			}
		}

		update_res(info, start, end, IORESOURCE_MEM, 1);
		subtract_range(range, RANGE_NUM, start, end);
		printk(KERN_CONT "\n");
	}

	/* need to take out [4G, TOM2) for RAM*/
	/* SYS_CFG */
	address = MSR_K8_SYSCFG;
	rdmsrl(address, val);
	/* TOP_MEM2 is enabled? */
	if (val & (1<<21)) {
		/* TOP_MEM2 */
		address = MSR_K8_TOP_MEM2;
		rdmsrl(address, val);
		end = (val & 0xffffff800000ULL);
		printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
		subtract_range(range, RANGE_NUM, 1ULL<<32, end - 1);
	}

	/*
	 * add left over mmio range to def node/link ?
	 * that is tricky, just record range in from start_min to 4G
	 */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];

		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_MEM, 1);
		}
	}

	for (i = 0; i < pci_root_num; i++) {
		int res_num;
		int busnum;

		info = &pci_root_info[i];
		res_num = info->res_num;
		busnum = info->bus_min;
		printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
		       info->bus_min, info->bus_max, info->node, info->link);
		for (j = 0; j < res_num; j++) {
			res = &info->res[j];
			printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
			       busnum, j,
			       (res->flags & IORESOURCE_IO)?"io port":"mmio",
			       res->start, res->end);
		}
	}

	return 0;
}

#else  /* !CONFIG_X86_64 */

static int __init early_fill_mp_bus_info(void) { return 0; }

#endif /* !CONFIG_X86_64 */

/* common 32/64 bit code */

#define ENABLE_CF8_EXT_CFG      (1ULL << 46)

static void enable_pci_io_ecs(void *unused)
{
	u64 reg;
	rdmsrl(MSR_AMD64_NB_CFG, reg);
	if (!(reg & ENABLE_CF8_EXT_CFG)) {
		reg |= ENABLE_CF8_EXT_CFG;
		wrmsrl(MSR_AMD64_NB_CFG, reg);
	}
}

static int __cpuinit amd_cpu_notify(struct notifier_block *self,
				    unsigned long action, void *hcpu)
{
	int cpu = (long)hcpu;
	switch (action) {
	case CPU_ONLINE:
	case CPU_ONLINE_FROZEN:
		smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
		break;
	default:
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block __cpuinitdata amd_cpu_notifier = {
	.notifier_call	= amd_cpu_notify,
};

static int __init pci_io_ecs_init(void)
{
	int cpu;

	/* assume all cpus from fam10h have IO ECS */
        if (boot_cpu_data.x86 < 0x10)
		return 0;

	register_cpu_notifier(&amd_cpu_notifier);
	for_each_online_cpu(cpu)
		amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
			       (void *)(long)cpu);
	pci_probe |= PCI_HAS_IO_ECS;

	return 0;
}

static int __init amd_postcore_init(void)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	early_fill_mp_bus_info();
	pci_io_ecs_init();

	return 0;
}

postcore_initcall(amd_postcore_init);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
1da177e4 LT	2	#include <linux/pci.h>
d199a048	3	#include <linux/topology.h>
91ede005	4	#include <linux/cpu.h>
27811d8c YL	5	#include <linux/range.h>
27811d8c YL	6
82487711	7	#include <asm/pci_x86.h>
3a27dd1c RR	8
3a27dd1c RR	9	#ifdef CONFIG_X86_64
871d5f8d	10	#include <asm/pci-direct.h>
d199a048	11	#endif
1da177e4	12
99935a7a YL	13	#include "bus_numa.h"
99935a7a YL	14
1da177e4 LT	15	/*
1da177e4 LT	16	* This discovers the pcibus <-> node mapping on AMD K8.
30a18d6c	17	* also get peer root bus resource for io,mmio
1da177e4 LT	18	*/
1da177e4 LT	19
d199a048	20	#ifdef CONFIG_X86_64
871d5f8d	21
30a18d6c YL	22	struct pci_hostbridge_probe {
	23	u32 bus;
	24	u32 slot;
	25	u32 vendor;
	26	u32 device;
	27	};
	28
	29	static struct pci_hostbridge_probe pci_probes[] __initdata = {
	30	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	31	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	32	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	33	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
	34	};
	35
6e184f29 YL	36	static u64 __initdata fam10h_mmconf_start;
	37	static u64 __initdata fam10h_mmconf_end;
	38	static void __init get_pci_mmcfg_amd_fam10h_range(void)
	39	{
	40	u32 address;
	41	u64 base, msr;
	42	unsigned segn_busn_bits;
	43
	44	/* assume all cpus from fam10h have mmconf */
	45	if (boot_cpu_data.x86 < 0x10)
	46	return;
	47
	48	address = MSR_FAM10H_MMIO_CONF_BASE;
	49	rdmsrl(address, msr);
	50
	51	/* mmconfig is not enable */
	52	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	53	return;
	54
	55	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	56
	57	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	58	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	59
	60	fam10h_mmconf_start = base;
	61	fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
	62	}
	63
27811d8c YL	64	#define RANGE_NUM 16
27811d8c YL	65
1da177e4	66	/**
871d5f8d YL	67	* early_fill_mp_bus_to_node()
871d5f8d YL	68	* called before pcibios_scan_root and pci_scan_bus
1da177e4 LT	69	* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
	70	* Registers found in the K8 northbridge
	71	*/
30a18d6c	72	static int __init early_fill_mp_bus_info(void)
1da177e4	73	{
30a18d6c YL	74	int i;
	75	int j;
	76	unsigned bus;
871d5f8d	77	unsigned slot;
35ddd068	78	int node;
30a18d6c YL	79	int link;
	80	int def_node;
	81	int def_link;
	82	struct pci_root_info *info;
	83	u32 reg;
	84	struct resource *res;
97445c3b YL	85	u64 start;
97445c3b YL	86	u64 end;
27811d8c	87	struct range range[RANGE_NUM];
30a18d6c YL	88	u64 val;
30a18d6c YL	89	u32 address;
3e3da00c	90	bool found;
1da177e4	91
871d5f8d YL	92	if (!early_pci_allowed())
	93	return -1;
	94
3e3da00c	95	found = false;
30a18d6c YL	96	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
	97	u32 id;
	98	u16 device;
	99	u16 vendor;
35ddd068	100
30a18d6c YL	101	bus = pci_probes[i].bus;
	102	slot = pci_probes[i].slot;
	103	id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
35ddd068	104
30a18d6c YL	105	vendor = id & 0xffff;
	106	device = (id>>16) & 0xffff;
	107	if (pci_probes[i].vendor == vendor &&
	108	pci_probes[i].device == device) {
3e3da00c	109	found = true;
30a18d6c YL	110	break;
	111	}
	112	}
	113
3e3da00c	114	if (!found)
30a18d6c	115	return 0;
35ddd068	116
30a18d6c YL	117	pci_root_num = 0;
	118	for (i = 0; i < 4; i++) {
	119	int min_bus;
	120	int max_bus;
	121	reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
35ddd068 YL	122
35ddd068 YL	123	/* Check if that register is enabled for bus range */
30a18d6c	124	if ((reg & 7) != 3)
35ddd068 YL	125	continue;
35ddd068 YL	126
30a18d6c YL	127	min_bus = (reg >> 16) & 0xff;
	128	max_bus = (reg >> 24) & 0xff;
	129	node = (reg >> 4) & 0x07;
	130	#ifdef CONFIG_NUMA
35ddd068	131	for (j = min_bus; j <= max_bus; j++)
2547089c	132	set_mp_bus_to_node(j, node);
30a18d6c YL	133	#endif
	134	link = (reg >> 8) & 0x03;
	135
	136	info = &pci_root_info[pci_root_num];
	137	info->bus_min = min_bus;
	138	info->bus_max = max_bus;
	139	info->node = node;
	140	info->link = link;
	141	sprintf(info->name, "PCI Bus #%02x", min_bus);
	142	pci_root_num++;
1da177e4 LT	143	}
1da177e4 LT	144
30a18d6c YL	145	/* get the default node and link for left over res */
	146	reg = read_pci_config(bus, slot, 0, 0x60);
	147	def_node = (reg >> 8) & 0x07;
	148	reg = read_pci_config(bus, slot, 0, 0x64);
	149	def_link = (reg >> 8) & 0x03;
	150
	151	memset(range, 0, sizeof(range));
	152	range[0].end = 0xffff;
	153	/* io port resource */
	154	for (i = 0; i < 4; i++) {
	155	reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
	156	if (!(reg & 3))
	157	continue;
	158
	159	start = reg & 0xfff000;
	160	reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
	161	node = reg & 0x07;
	162	link = (reg >> 4) & 0x03;
	163	end = (reg & 0xfff000) \| 0xfff;
	164
	165	/* find the position */
	166	for (j = 0; j < pci_root_num; j++) {
	167	info = &pci_root_info[j];
	168	if (info->node == node && info->link == link)
	169	break;
	170	}
	171	if (j == pci_root_num)
	172	continue; /* not found */
	173
	174	info = &pci_root_info[j];
6e184f29	175	printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
97445c3b	176	node, link, start, end);
e8ee6f0a YL	177
	178	/* kernel only handle 16 bit only */
	179	if (end > 0xffff)
	180	end = 0xffff;
	181	update_res(info, start, end, IORESOURCE_IO, 1);
27811d8c	182	subtract_range(range, RANGE_NUM, start, end);
30a18d6c YL	183	}
	184	/* add left over io port range to def node/link, [0, 0xffff] */
	185	/* find the position */
	186	for (j = 0; j < pci_root_num; j++) {
	187	info = &pci_root_info[j];
	188	if (info->node == def_node && info->link == def_link)
	189	break;
	190	}
	191	if (j < pci_root_num) {
	192	info = &pci_root_info[j];
	193	for (i = 0; i < RANGE_NUM; i++) {
	194	if (!range[i].end)
	195	continue;
	196
	197	update_res(info, range[i].start, range[i].end,
	198	IORESOURCE_IO, 1);
	199	}
	200	}
	201
	202	memset(range, 0, sizeof(range));
	203	/* 0xfd00000000-0xffffffffff for HT */
6e184f29	204	range[0].end = (0xfdULL<<32) - 1;
30a18d6c YL	205
	206	/* need to take out [0, TOM) for RAM*/
	207	address = MSR_K8_TOP_MEM1;
	208	rdmsrl(address, val);
8004dd96	209	end = (val & 0xffffff800000ULL);
97445c3b	210	printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
30a18d6c	211	if (end < (1ULL<<32))
27811d8c	212	subtract_range(range, RANGE_NUM, 0, end - 1);
30a18d6c	213
6e184f29 YL	214	/* get mmconfig */
	215	get_pci_mmcfg_amd_fam10h_range();
	216	/* need to take out mmconf range */
	217	if (fam10h_mmconf_end) {
	218	printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
27811d8c	219	subtract_range(range, RANGE_NUM, fam10h_mmconf_start, fam10h_mmconf_end);
6e184f29 YL	220	}
6e184f29 YL	221
30a18d6c YL	222	/* mmio resource */
	223	for (i = 0; i < 8; i++) {
	224	reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
	225	if (!(reg & 3))
	226	continue;
	227
	228	start = reg & 0xffffff00; /* 39:16 on 31:8*/
	229	start <<= 8;
	230	reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
	231	node = reg & 0x07;
	232	link = (reg >> 4) & 0x03;
	233	end = (reg & 0xffffff00);
	234	end <<= 8;
	235	end \|= 0xffff;
	236
	237	/* find the position */
	238	for (j = 0; j < pci_root_num; j++) {
	239	info = &pci_root_info[j];
	240	if (info->node == node && info->link == link)
	241	break;
	242	}
	243	if (j == pci_root_num)
	244	continue; /* not found */
	245
	246	info = &pci_root_info[j];
6e184f29 YL	247
6e184f29 YL	248	printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
97445c3b	249	node, link, start, end);
6e184f29 YL	250	/*
	251	* some sick allocation would have range overlap with fam10h
	252	* mmconf range, so need to update start and end.
	253	*/
	254	if (fam10h_mmconf_end) {
	255	int changed = 0;
	256	u64 endx = 0;
	257	if (start >= fam10h_mmconf_start &&
	258	start <= fam10h_mmconf_end) {
	259	start = fam10h_mmconf_end + 1;
	260	changed = 1;
	261	}
	262
	263	if (end >= fam10h_mmconf_start &&
	264	end <= fam10h_mmconf_end) {
	265	end = fam10h_mmconf_start - 1;
	266	changed = 1;
	267	}
	268
	269	if (start < fam10h_mmconf_start &&
	270	end > fam10h_mmconf_end) {
	271	/* we got a hole */
	272	endx = fam10h_mmconf_start - 1;
	273	update_res(info, start, endx, IORESOURCE_MEM, 0);
27811d8c	274	subtract_range(range, RANGE_NUM, start, endx);
97445c3b	275	printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
6e184f29 YL	276	start = fam10h_mmconf_end + 1;
	277	changed = 1;
	278	}
	279	if (changed) {
	280	if (start <= end) {
97445c3b	281	printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
6e184f29 YL	282	} else {
	283	printk(KERN_CONT "%s\n", endx?"":" ==> none");
	284	continue;
	285	}
	286	}
	287	}
	288
e8ee6f0a	289	update_res(info, start, end, IORESOURCE_MEM, 1);
27811d8c	290	subtract_range(range, RANGE_NUM, start, end);
6e184f29	291	printk(KERN_CONT "\n");
30a18d6c YL	292	}
	293
	294	/* need to take out [4G, TOM2) for RAM*/
	295	/* SYS_CFG */
	296	address = MSR_K8_SYSCFG;
	297	rdmsrl(address, val);
	298	/* TOP_MEM2 is enabled? */
	299	if (val & (1<<21)) {
	300	/* TOP_MEM2 */
	301	address = MSR_K8_TOP_MEM2;
	302	rdmsrl(address, val);
8004dd96	303	end = (val & 0xffffff800000ULL);
97445c3b	304	printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
27811d8c	305	subtract_range(range, RANGE_NUM, 1ULL<<32, end - 1);
30a18d6c YL	306	}
	307
	308	/*
	309	* add left over mmio range to def node/link ?
	310	* that is tricky, just record range in from start_min to 4G
	311	*/
	312	for (j = 0; j < pci_root_num; j++) {
	313	info = &pci_root_info[j];
	314	if (info->node == def_node && info->link == def_link)
	315	break;
	316	}
	317	if (j < pci_root_num) {
	318	info = &pci_root_info[j];
	319
	320	for (i = 0; i < RANGE_NUM; i++) {
	321	if (!range[i].end)
	322	continue;
	323
	324	update_res(info, range[i].start, range[i].end,
	325	IORESOURCE_MEM, 1);
	326	}
	327	}
	328
30a18d6c YL	329	for (i = 0; i < pci_root_num; i++) {
	330	int res_num;
	331	int busnum;
	332
	333	info = &pci_root_info[i];
	334	res_num = info->res_num;
	335	busnum = info->bus_min;
99935a7a	336	printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
30a18d6c YL	337	info->bus_min, info->bus_max, info->node, info->link);
	338	for (j = 0; j < res_num; j++) {
	339	res = &info->res[j];
	340	printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
	341	busnum, j,
	342	(res->flags & IORESOURCE_IO)?"io port":"mmio",
	343	res->start, res->end);
	344	}
	345	}
	346
1da177e4 LT	347	return 0;
	348	}
	349
9b4e27b5	350	#else /* !CONFIG_X86_64 */
3a27dd1c	351
9b4e27b5 RR	352	static int __init early_fill_mp_bus_info(void) { return 0; }
	353
	354	#endif /* !CONFIG_X86_64 */
3a27dd1c RR	355
	356	/* common 32/64 bit code */
	357
	358	#define ENABLE_CF8_EXT_CFG (1ULL << 46)
	359
91ede005	360	static void enable_pci_io_ecs(void *unused)
3a27dd1c RR	361	{
	362	u64 reg;
	363	rdmsrl(MSR_AMD64_NB_CFG, reg);
	364	if (!(reg & ENABLE_CF8_EXT_CFG)) {
	365	reg \|= ENABLE_CF8_EXT_CFG;
	366	wrmsrl(MSR_AMD64_NB_CFG, reg);
	367	}
	368	}
	369
91ede005 RR	370	static int __cpuinit amd_cpu_notify(struct notifier_block *self,
91ede005 RR	371	unsigned long action, void *hcpu)
3a27dd1c	372	{
91ede005	373	int cpu = (long)hcpu;
ed21763e	374	switch (action) {
91ede005 RR	375	case CPU_ONLINE:
	376	case CPU_ONLINE_FROZEN:
	377	smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
	378	break;
	379	default:
	380	break;
	381	}
	382	return NOTIFY_OK;
	383	}
	384
	385	static struct notifier_block __cpuinitdata amd_cpu_notifier = {
	386	.notifier_call = amd_cpu_notify,
	387	};
	388
	389	static int __init pci_io_ecs_init(void)
	390	{
	391	int cpu;
	392
3a27dd1c RR	393	/* assume all cpus from fam10h have IO ECS */
	394	if (boot_cpu_data.x86 < 0x10)
	395	return 0;
91ede005 RR	396
	397	register_cpu_notifier(&amd_cpu_notifier);
	398	for_each_online_cpu(cpu)
	399	amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
	400	(void *)(long)cpu);
3a27dd1c	401	pci_probe \|= PCI_HAS_IO_ECS;
91ede005	402
3a27dd1c RR	403	return 0;
	404	}
	405
9b4e27b5 RR	406	static int __init amd_postcore_init(void)
	407	{
	408	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	409	return 0;
	410
	411	early_fill_mp_bus_info();
91ede005	412	pci_io_ecs_init();
9b4e27b5 RR	413
	414	return 0;
	415	}
	416
	417	postcore_initcall(amd_postcore_init);