[net-next-2.6.git] / arch / x86 / pci / amd_bus.c

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/topology.h>
#include <linux/cpu.h>
#include <linux/range.h>

#include <asm/pci_x86.h>

#ifdef CONFIG_X86_64
#include <asm/pci-direct.h>
#endif

#include "bus_numa.h"

/*
 * This discovers the pcibus <-> node mapping on AMD K8.
 * also get peer root bus resource for io,mmio
 */

#ifdef CONFIG_X86_64

struct pci_hostbridge_probe {
	u32 bus;
	u32 slot;
	u32 vendor;
	u32 device;
};

static struct pci_hostbridge_probe pci_probes[] __initdata = {
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
};

static u64 __initdata fam10h_mmconf_start;
static u64 __initdata fam10h_mmconf_end;
static void __init get_pci_mmcfg_amd_fam10h_range(void)
{
	u32 address;
	u64 base, msr;
	unsigned segn_busn_bits;

	/* assume all cpus from fam10h have mmconf */
        if (boot_cpu_data.x86 < 0x10)
		return;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	rdmsrl(address, msr);

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	fam10h_mmconf_start = base;
	fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
}

#define RANGE_NUM 16

/**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 * Registers found in the K8 northbridge
 */
static int __init early_fill_mp_bus_info(void)
{
	int i;
	int j;
	unsigned bus;
	unsigned slot;
	int node;
	int link;
	int def_node;
	int def_link;
	struct pci_root_info *info;
	u32 reg;
	struct resource *res;
	size_t start;
	size_t end;
	struct range range[RANGE_NUM];
	u64 val;
	u32 address;

	if (!early_pci_allowed())
		return -1;

	found_all_numa_early = 0;
	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
		u32 id;
		u16 device;
		u16 vendor;

		bus = pci_probes[i].bus;
		slot = pci_probes[i].slot;
		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);

		vendor = id & 0xffff;
		device = (id>>16) & 0xffff;
		if (pci_probes[i].vendor == vendor &&
		    pci_probes[i].device == device) {
			found_all_numa_early = 1;
			break;
		}
	}

	if (!found_all_numa_early)
		return 0;

	pci_root_num = 0;
	for (i = 0; i < 4; i++) {
		int min_bus;
		int max_bus;
		reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));

		/* Check if that register is enabled for bus range */
		if ((reg & 7) != 3)
			continue;

		min_bus = (reg >> 16) & 0xff;
		max_bus = (reg >> 24) & 0xff;
		node = (reg >> 4) & 0x07;
#ifdef CONFIG_NUMA
		for (j = min_bus; j <= max_bus; j++)
			set_mp_bus_to_node(j, node);
#endif
		link = (reg >> 8) & 0x03;

		info = &pci_root_info[pci_root_num];
		info->bus_min = min_bus;
		info->bus_max = max_bus;
		info->node = node;
		info->link = link;
		sprintf(info->name, "PCI Bus #%02x", min_bus);
		pci_root_num++;
	}

	/* get the default node and link for left over res */
	reg = read_pci_config(bus, slot, 0, 0x60);
	def_node = (reg >> 8) & 0x07;
	reg = read_pci_config(bus, slot, 0, 0x64);
	def_link = (reg >> 8) & 0x03;

	memset(range, 0, sizeof(range));
	range[0].end = 0xffff;
	/* io port resource */
	for (i = 0; i < 4; i++) {
		reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xfff000;
		reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xfff000) | 0xfff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];
		printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
		       node, link, (u64)start, (u64)end);

		/* kernel only handle 16 bit only */
		if (end > 0xffff)
			end = 0xffff;
		update_res(info, start, end, IORESOURCE_IO, 1);
		subtract_range(range, RANGE_NUM, start, end);
	}
	/* add left over io port range to def node/link, [0, 0xffff] */
	/* find the position */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_IO, 1);
		}
	}

	memset(range, 0, sizeof(range));
	/* 0xfd00000000-0xffffffffff for HT */
	range[0].end = (0xfdULL<<32) - 1;

	/* need to take out [0, TOM) for RAM*/
	address = MSR_K8_TOP_MEM1;
	rdmsrl(address, val);
	end = (val & 0xffffff800000ULL);
	printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
	if (end < (1ULL<<32))
		subtract_range(range, RANGE_NUM, 0, end - 1);

	/* get mmconfig */
	get_pci_mmcfg_amd_fam10h_range();
	/* need to take out mmconf range */
	if (fam10h_mmconf_end) {
		printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
		subtract_range(range, RANGE_NUM, fam10h_mmconf_start, fam10h_mmconf_end);
	}

	/* mmio resource */
	for (i = 0; i < 8; i++) {
		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xffffff00; /* 39:16 on 31:8*/
		start <<= 8;
		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xffffff00);
		end <<= 8;
		end |= 0xffff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];

		printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
		       node, link, (u64)start, (u64)end);
		/*
		 * some sick allocation would have range overlap with fam10h
		 * mmconf range, so need to update start and end.
		 */
		if (fam10h_mmconf_end) {
			int changed = 0;
			u64 endx = 0;
			if (start >= fam10h_mmconf_start &&
			    start <= fam10h_mmconf_end) {
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}

			if (end >= fam10h_mmconf_start &&
			    end <= fam10h_mmconf_end) {
				end = fam10h_mmconf_start - 1;
				changed = 1;
			}

			if (start < fam10h_mmconf_start &&
			    end > fam10h_mmconf_end) {
				/* we got a hole */
				endx = fam10h_mmconf_start - 1;
				update_res(info, start, endx, IORESOURCE_MEM, 0);
				subtract_range(range, RANGE_NUM, start, endx);
				printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}
			if (changed) {
				if (start <= end) {
					printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
				} else {
					printk(KERN_CONT "%s\n", endx?"":" ==> none");
					continue;
				}
			}
		}

		update_res(info, start, end, IORESOURCE_MEM, 1);
		subtract_range(range, RANGE_NUM, start, end);
		printk(KERN_CONT "\n");
	}

	/* need to take out [4G, TOM2) for RAM*/
	/* SYS_CFG */
	address = MSR_K8_SYSCFG;
	rdmsrl(address, val);
	/* TOP_MEM2 is enabled? */
	if (val & (1<<21)) {
		/* TOP_MEM2 */
		address = MSR_K8_TOP_MEM2;
		rdmsrl(address, val);
		end = (val & 0xffffff800000ULL);
		printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
		subtract_range(range, RANGE_NUM, 1ULL<<32, end - 1);
	}

	/*
	 * add left over mmio range to def node/link ?
	 * that is tricky, just record range in from start_min to 4G
	 */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];

		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_MEM, 1);
		}
	}

	for (i = 0; i < pci_root_num; i++) {
		int res_num;
		int busnum;

		info = &pci_root_info[i];
		res_num = info->res_num;
		busnum = info->bus_min;
		printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
		       info->bus_min, info->bus_max, info->node, info->link);
		for (j = 0; j < res_num; j++) {
			res = &info->res[j];
			printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
			       busnum, j,
			       (res->flags & IORESOURCE_IO)?"io port":"mmio",
			       res->start, res->end);
		}
	}

	return 0;
}

#else  /* !CONFIG_X86_64 */

static int __init early_fill_mp_bus_info(void) { return 0; }

#endif /* !CONFIG_X86_64 */

/* common 32/64 bit code */

#define ENABLE_CF8_EXT_CFG      (1ULL << 46)

static void enable_pci_io_ecs(void *unused)
{
	u64 reg;
	rdmsrl(MSR_AMD64_NB_CFG, reg);
	if (!(reg & ENABLE_CF8_EXT_CFG)) {
		reg |= ENABLE_CF8_EXT_CFG;
		wrmsrl(MSR_AMD64_NB_CFG, reg);
	}
}

static int __cpuinit amd_cpu_notify(struct notifier_block *self,
				    unsigned long action, void *hcpu)
{
	int cpu = (long)hcpu;
	switch (action) {
	case CPU_ONLINE:
	case CPU_ONLINE_FROZEN:
		smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
		break;
	default:
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block __cpuinitdata amd_cpu_notifier = {
	.notifier_call	= amd_cpu_notify,
};

static int __init pci_io_ecs_init(void)
{
	int cpu;

	/* assume all cpus from fam10h have IO ECS */
        if (boot_cpu_data.x86 < 0x10)
		return 0;

	register_cpu_notifier(&amd_cpu_notifier);
	for_each_online_cpu(cpu)
		amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
			       (void *)(long)cpu);
	pci_probe |= PCI_HAS_IO_ECS;

	return 0;
}

static int __init amd_postcore_init(void)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	early_fill_mp_bus_info();
	pci_io_ecs_init();

	return 0;
}

postcore_initcall(amd_postcore_init);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
1da177e4 LT	2	#include <linux/pci.h>
d199a048	3	#include <linux/topology.h>
91ede005	4	#include <linux/cpu.h>
27811d8c YL	5	#include <linux/range.h>
27811d8c YL	6
82487711	7	#include <asm/pci_x86.h>
3a27dd1c RR	8
3a27dd1c RR	9	#ifdef CONFIG_X86_64
871d5f8d	10	#include <asm/pci-direct.h>
d199a048	11	#endif
1da177e4	12
99935a7a YL	13	#include "bus_numa.h"
99935a7a YL	14
1da177e4 LT	15	/*
1da177e4 LT	16	* This discovers the pcibus <-> node mapping on AMD K8.
30a18d6c	17	* also get peer root bus resource for io,mmio
1da177e4 LT	18	*/
1da177e4 LT	19
d199a048	20	#ifdef CONFIG_X86_64
871d5f8d	21
30a18d6c YL	22	struct pci_hostbridge_probe {
	23	u32 bus;
	24	u32 slot;
	25	u32 vendor;
	26	u32 device;
	27	};
	28
	29	static struct pci_hostbridge_probe pci_probes[] __initdata = {
	30	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	31	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	32	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	33	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
	34	};
	35
6e184f29 YL	36	static u64 __initdata fam10h_mmconf_start;
	37	static u64 __initdata fam10h_mmconf_end;
	38	static void __init get_pci_mmcfg_amd_fam10h_range(void)
	39	{
	40	u32 address;
	41	u64 base, msr;
	42	unsigned segn_busn_bits;
	43
	44	/* assume all cpus from fam10h have mmconf */
	45	if (boot_cpu_data.x86 < 0x10)
	46	return;
	47
	48	address = MSR_FAM10H_MMIO_CONF_BASE;
	49	rdmsrl(address, msr);
	50
	51	/* mmconfig is not enable */
	52	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	53	return;
	54
	55	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	56
	57	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	58	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	59
	60	fam10h_mmconf_start = base;
	61	fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
	62	}
	63
27811d8c YL	64	#define RANGE_NUM 16
27811d8c YL	65
1da177e4	66	/**
871d5f8d YL	67	* early_fill_mp_bus_to_node()
871d5f8d YL	68	* called before pcibios_scan_root and pci_scan_bus
1da177e4 LT	69	* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
	70	* Registers found in the K8 northbridge
	71	*/
30a18d6c	72	static int __init early_fill_mp_bus_info(void)
1da177e4	73	{
30a18d6c YL	74	int i;
	75	int j;
	76	unsigned bus;
871d5f8d	77	unsigned slot;
35ddd068	78	int node;
30a18d6c YL	79	int link;
	80	int def_node;
	81	int def_link;
	82	struct pci_root_info *info;
	83	u32 reg;
	84	struct resource *res;
	85	size_t start;
	86	size_t end;
27811d8c	87	struct range range[RANGE_NUM];
30a18d6c YL	88	u64 val;
30a18d6c YL	89	u32 address;
1da177e4	90
871d5f8d YL	91	if (!early_pci_allowed())
	92	return -1;
	93
99935a7a	94	found_all_numa_early = 0;
30a18d6c YL	95	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
	96	u32 id;
	97	u16 device;
	98	u16 vendor;
35ddd068	99
30a18d6c YL	100	bus = pci_probes[i].bus;
	101	slot = pci_probes[i].slot;
	102	id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
35ddd068	103
30a18d6c YL	104	vendor = id & 0xffff;
	105	device = (id>>16) & 0xffff;
	106	if (pci_probes[i].vendor == vendor &&
	107	pci_probes[i].device == device) {
99935a7a	108	found_all_numa_early = 1;
30a18d6c YL	109	break;
	110	}
	111	}
	112
99935a7a	113	if (!found_all_numa_early)
30a18d6c	114	return 0;
35ddd068	115
30a18d6c YL	116	pci_root_num = 0;
	117	for (i = 0; i < 4; i++) {
	118	int min_bus;
	119	int max_bus;
	120	reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
35ddd068 YL	121
35ddd068 YL	122	/* Check if that register is enabled for bus range */
30a18d6c	123	if ((reg & 7) != 3)
35ddd068 YL	124	continue;
35ddd068 YL	125
30a18d6c YL	126	min_bus = (reg >> 16) & 0xff;
	127	max_bus = (reg >> 24) & 0xff;
	128	node = (reg >> 4) & 0x07;
	129	#ifdef CONFIG_NUMA
35ddd068	130	for (j = min_bus; j <= max_bus; j++)
2547089c	131	set_mp_bus_to_node(j, node);
30a18d6c YL	132	#endif
	133	link = (reg >> 8) & 0x03;
	134
	135	info = &pci_root_info[pci_root_num];
	136	info->bus_min = min_bus;
	137	info->bus_max = max_bus;
	138	info->node = node;
	139	info->link = link;
	140	sprintf(info->name, "PCI Bus #%02x", min_bus);
	141	pci_root_num++;
1da177e4 LT	142	}
1da177e4 LT	143
30a18d6c YL	144	/* get the default node and link for left over res */
	145	reg = read_pci_config(bus, slot, 0, 0x60);
	146	def_node = (reg >> 8) & 0x07;
	147	reg = read_pci_config(bus, slot, 0, 0x64);
	148	def_link = (reg >> 8) & 0x03;
	149
	150	memset(range, 0, sizeof(range));
	151	range[0].end = 0xffff;
	152	/* io port resource */
	153	for (i = 0; i < 4; i++) {
	154	reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
	155	if (!(reg & 3))
	156	continue;
	157
	158	start = reg & 0xfff000;
	159	reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
	160	node = reg & 0x07;
	161	link = (reg >> 4) & 0x03;
	162	end = (reg & 0xfff000) \| 0xfff;
	163
	164	/* find the position */
	165	for (j = 0; j < pci_root_num; j++) {
	166	info = &pci_root_info[j];
	167	if (info->node == node && info->link == link)
	168	break;
	169	}
	170	if (j == pci_root_num)
	171	continue; /* not found */
	172
	173	info = &pci_root_info[j];
6e184f29 YL	174	printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
6e184f29 YL	175	node, link, (u64)start, (u64)end);
e8ee6f0a YL	176
	177	/* kernel only handle 16 bit only */
	178	if (end > 0xffff)
	179	end = 0xffff;
	180	update_res(info, start, end, IORESOURCE_IO, 1);
27811d8c	181	subtract_range(range, RANGE_NUM, start, end);
30a18d6c YL	182	}
	183	/* add left over io port range to def node/link, [0, 0xffff] */
	184	/* find the position */
	185	for (j = 0; j < pci_root_num; j++) {
	186	info = &pci_root_info[j];
	187	if (info->node == def_node && info->link == def_link)
	188	break;
	189	}
	190	if (j < pci_root_num) {
	191	info = &pci_root_info[j];
	192	for (i = 0; i < RANGE_NUM; i++) {
	193	if (!range[i].end)
	194	continue;
	195
	196	update_res(info, range[i].start, range[i].end,
	197	IORESOURCE_IO, 1);
	198	}
	199	}
	200
	201	memset(range, 0, sizeof(range));
	202	/* 0xfd00000000-0xffffffffff for HT */
6e184f29	203	range[0].end = (0xfdULL<<32) - 1;
30a18d6c YL	204
	205	/* need to take out [0, TOM) for RAM*/
	206	address = MSR_K8_TOP_MEM1;
	207	rdmsrl(address, val);
8004dd96	208	end = (val & 0xffffff800000ULL);
30a18d6c YL	209	printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
30a18d6c YL	210	if (end < (1ULL<<32))
27811d8c	211	subtract_range(range, RANGE_NUM, 0, end - 1);
30a18d6c	212
6e184f29 YL	213	/* get mmconfig */
	214	get_pci_mmcfg_amd_fam10h_range();
	215	/* need to take out mmconf range */
	216	if (fam10h_mmconf_end) {
	217	printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
27811d8c	218	subtract_range(range, RANGE_NUM, fam10h_mmconf_start, fam10h_mmconf_end);
6e184f29 YL	219	}
6e184f29 YL	220
30a18d6c YL	221	/* mmio resource */
	222	for (i = 0; i < 8; i++) {
	223	reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
	224	if (!(reg & 3))
	225	continue;
	226
	227	start = reg & 0xffffff00; /* 39:16 on 31:8*/
	228	start <<= 8;
	229	reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
	230	node = reg & 0x07;
	231	link = (reg >> 4) & 0x03;
	232	end = (reg & 0xffffff00);
	233	end <<= 8;
	234	end \|= 0xffff;
	235
	236	/* find the position */
	237	for (j = 0; j < pci_root_num; j++) {
	238	info = &pci_root_info[j];
	239	if (info->node == node && info->link == link)
	240	break;
	241	}
	242	if (j == pci_root_num)
	243	continue; /* not found */
	244
	245	info = &pci_root_info[j];
6e184f29 YL	246
	247	printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
	248	node, link, (u64)start, (u64)end);
	249	/*
	250	* some sick allocation would have range overlap with fam10h
	251	* mmconf range, so need to update start and end.
	252	*/
	253	if (fam10h_mmconf_end) {
	254	int changed = 0;
	255	u64 endx = 0;
	256	if (start >= fam10h_mmconf_start &&
	257	start <= fam10h_mmconf_end) {
	258	start = fam10h_mmconf_end + 1;
	259	changed = 1;
	260	}
	261
	262	if (end >= fam10h_mmconf_start &&
	263	end <= fam10h_mmconf_end) {
	264	end = fam10h_mmconf_start - 1;
	265	changed = 1;
	266	}
	267
	268	if (start < fam10h_mmconf_start &&
	269	end > fam10h_mmconf_end) {
	270	/* we got a hole */
	271	endx = fam10h_mmconf_start - 1;
	272	update_res(info, start, endx, IORESOURCE_MEM, 0);
27811d8c	273	subtract_range(range, RANGE_NUM, start, endx);
6e184f29 YL	274	printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
	275	start = fam10h_mmconf_end + 1;
	276	changed = 1;
	277	}
	278	if (changed) {
	279	if (start <= end) {
	280	printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
	281	} else {
	282	printk(KERN_CONT "%s\n", endx?"":" ==> none");
	283	continue;
	284	}
	285	}
	286	}
	287
e8ee6f0a	288	update_res(info, start, end, IORESOURCE_MEM, 1);
27811d8c	289	subtract_range(range, RANGE_NUM, start, end);
6e184f29	290	printk(KERN_CONT "\n");
30a18d6c YL	291	}
	292
	293	/* need to take out [4G, TOM2) for RAM*/
	294	/* SYS_CFG */
	295	address = MSR_K8_SYSCFG;
	296	rdmsrl(address, val);
	297	/* TOP_MEM2 is enabled? */
	298	if (val & (1<<21)) {
	299	/* TOP_MEM2 */
	300	address = MSR_K8_TOP_MEM2;
	301	rdmsrl(address, val);
8004dd96	302	end = (val & 0xffffff800000ULL);
30a18d6c	303	printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
27811d8c	304	subtract_range(range, RANGE_NUM, 1ULL<<32, end - 1);
30a18d6c YL	305	}
	306
	307	/*
	308	* add left over mmio range to def node/link ?
	309	* that is tricky, just record range in from start_min to 4G
	310	*/
	311	for (j = 0; j < pci_root_num; j++) {
	312	info = &pci_root_info[j];
	313	if (info->node == def_node && info->link == def_link)
	314	break;
	315	}
	316	if (j < pci_root_num) {
	317	info = &pci_root_info[j];
	318
	319	for (i = 0; i < RANGE_NUM; i++) {
	320	if (!range[i].end)
	321	continue;
	322
	323	update_res(info, range[i].start, range[i].end,
	324	IORESOURCE_MEM, 1);
	325	}
	326	}
	327
30a18d6c YL	328	for (i = 0; i < pci_root_num; i++) {
	329	int res_num;
	330	int busnum;
	331
	332	info = &pci_root_info[i];
	333	res_num = info->res_num;
	334	busnum = info->bus_min;
99935a7a	335	printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
30a18d6c YL	336	info->bus_min, info->bus_max, info->node, info->link);
	337	for (j = 0; j < res_num; j++) {
	338	res = &info->res[j];
	339	printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
	340	busnum, j,
	341	(res->flags & IORESOURCE_IO)?"io port":"mmio",
	342	res->start, res->end);
	343	}
	344	}
	345
1da177e4 LT	346	return 0;
	347	}
	348
9b4e27b5	349	#else /* !CONFIG_X86_64 */
3a27dd1c	350
9b4e27b5 RR	351	static int __init early_fill_mp_bus_info(void) { return 0; }
	352
	353	#endif /* !CONFIG_X86_64 */
3a27dd1c RR	354
	355	/* common 32/64 bit code */
	356
	357	#define ENABLE_CF8_EXT_CFG (1ULL << 46)
	358
91ede005	359	static void enable_pci_io_ecs(void *unused)
3a27dd1c RR	360	{
	361	u64 reg;
	362	rdmsrl(MSR_AMD64_NB_CFG, reg);
	363	if (!(reg & ENABLE_CF8_EXT_CFG)) {
	364	reg \|= ENABLE_CF8_EXT_CFG;
	365	wrmsrl(MSR_AMD64_NB_CFG, reg);
	366	}
	367	}
	368
91ede005 RR	369	static int __cpuinit amd_cpu_notify(struct notifier_block *self,
91ede005 RR	370	unsigned long action, void *hcpu)
3a27dd1c	371	{
91ede005	372	int cpu = (long)hcpu;
ed21763e	373	switch (action) {
91ede005 RR	374	case CPU_ONLINE:
	375	case CPU_ONLINE_FROZEN:
	376	smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
	377	break;
	378	default:
	379	break;
	380	}
	381	return NOTIFY_OK;
	382	}
	383
	384	static struct notifier_block __cpuinitdata amd_cpu_notifier = {
	385	.notifier_call = amd_cpu_notify,
	386	};
	387
	388	static int __init pci_io_ecs_init(void)
	389	{
	390	int cpu;
	391
3a27dd1c RR	392	/* assume all cpus from fam10h have IO ECS */
	393	if (boot_cpu_data.x86 < 0x10)
	394	return 0;
91ede005 RR	395
	396	register_cpu_notifier(&amd_cpu_notifier);
	397	for_each_online_cpu(cpu)
	398	amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
	399	(void *)(long)cpu);
3a27dd1c	400	pci_probe \|= PCI_HAS_IO_ECS;
91ede005	401
3a27dd1c RR	402	return 0;
	403	}
	404
9b4e27b5 RR	405	static int __init amd_postcore_init(void)
	406	{
	407	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	408	return 0;
	409
	410	early_fill_mp_bus_info();
91ede005	411	pci_io_ecs_init();
9b4e27b5 RR	412
	413	return 0;
	414	}
	415
	416	postcore_initcall(amd_postcore_init);