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Commit | Line | Data |
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1da177e4 LT |
1 | /** |
2 | * @file nmi_int.c | |
3 | * | |
4d4036e0 | 4 | * @remark Copyright 2002-2009 OProfile authors |
1da177e4 LT |
5 | * @remark Read the file COPYING |
6 | * | |
7 | * @author John Levon <levon@movementarian.org> | |
adf5ec0b | 8 | * @author Robert Richter <robert.richter@amd.com> |
4d4036e0 JY |
9 | * @author Barry Kasindorf <barry.kasindorf@amd.com> |
10 | * @author Jason Yeh <jason.yeh@amd.com> | |
11 | * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/oprofile.h> | |
18 | #include <linux/sysdev.h> | |
19 | #include <linux/slab.h> | |
1cfcea1b | 20 | #include <linux/moduleparam.h> |
1eeb66a1 | 21 | #include <linux/kdebug.h> |
80a8c9ff | 22 | #include <linux/cpu.h> |
1da177e4 LT |
23 | #include <asm/nmi.h> |
24 | #include <asm/msr.h> | |
25 | #include <asm/apic.h> | |
b75f53db | 26 | |
1da177e4 LT |
27 | #include "op_counter.h" |
28 | #include "op_x86_model.h" | |
2fbe7b25 | 29 | |
259a83a8 | 30 | static struct op_x86_model_spec *model; |
d18d00f5 MT |
31 | static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); |
32 | static DEFINE_PER_CPU(unsigned long, saved_lvtpc); | |
2fbe7b25 | 33 | |
6ae56b55 RR |
34 | /* must be protected with get_online_cpus()/put_online_cpus(): */ |
35 | static int nmi_enabled; | |
36 | static int ctr_running; | |
1da177e4 | 37 | |
4d4036e0 JY |
38 | struct op_counter_config counter_config[OP_MAX_COUNTER]; |
39 | ||
3370d358 RR |
40 | /* common functions */ |
41 | ||
42 | u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, | |
43 | struct op_counter_config *counter_config) | |
44 | { | |
45 | u64 val = 0; | |
46 | u16 event = (u16)counter_config->event; | |
47 | ||
48 | val |= ARCH_PERFMON_EVENTSEL_INT; | |
49 | val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; | |
50 | val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; | |
51 | val |= (counter_config->unit_mask & 0xFF) << 8; | |
52 | event &= model->event_mask ? model->event_mask : 0xFF; | |
53 | val |= event & 0xFF; | |
54 | val |= (event & 0x0F00) << 24; | |
55 | ||
56 | return val; | |
57 | } | |
58 | ||
59 | ||
c7c19f8e AB |
60 | static int profile_exceptions_notify(struct notifier_block *self, |
61 | unsigned long val, void *data) | |
1da177e4 | 62 | { |
2fbe7b25 DZ |
63 | struct die_args *args = (struct die_args *)data; |
64 | int ret = NOTIFY_DONE; | |
65 | int cpu = smp_processor_id(); | |
66 | ||
b75f53db | 67 | switch (val) { |
2fbe7b25 | 68 | case DIE_NMI: |
5b75af0a MG |
69 | case DIE_NMI_IPI: |
70 | model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)); | |
71 | ret = NOTIFY_STOP; | |
2fbe7b25 DZ |
72 | break; |
73 | default: | |
74 | break; | |
75 | } | |
76 | return ret; | |
1da177e4 | 77 | } |
2fbe7b25 | 78 | |
b75f53db | 79 | static void nmi_cpu_save_registers(struct op_msrs *msrs) |
1da177e4 | 80 | { |
b75f53db CM |
81 | struct op_msr *counters = msrs->counters; |
82 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
83 | unsigned int i; |
84 | ||
1a245c45 | 85 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
86 | if (counters[i].addr) |
87 | rdmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 | 88 | } |
b75f53db | 89 | |
1a245c45 | 90 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
91 | if (controls[i].addr) |
92 | rdmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 LT |
93 | } |
94 | } | |
95 | ||
b28d1b92 RR |
96 | static void nmi_cpu_start(void *dummy) |
97 | { | |
98 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); | |
2623a1d5 RR |
99 | if (!msrs->controls) |
100 | WARN_ON_ONCE(1); | |
101 | else | |
102 | model->start(msrs); | |
b28d1b92 RR |
103 | } |
104 | ||
105 | static int nmi_start(void) | |
106 | { | |
6ae56b55 | 107 | get_online_cpus(); |
b28d1b92 | 108 | on_each_cpu(nmi_cpu_start, NULL, 1); |
6ae56b55 RR |
109 | ctr_running = 1; |
110 | put_online_cpus(); | |
b28d1b92 RR |
111 | return 0; |
112 | } | |
113 | ||
114 | static void nmi_cpu_stop(void *dummy) | |
115 | { | |
116 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); | |
2623a1d5 RR |
117 | if (!msrs->controls) |
118 | WARN_ON_ONCE(1); | |
119 | else | |
120 | model->stop(msrs); | |
b28d1b92 RR |
121 | } |
122 | ||
123 | static void nmi_stop(void) | |
124 | { | |
6ae56b55 | 125 | get_online_cpus(); |
b28d1b92 | 126 | on_each_cpu(nmi_cpu_stop, NULL, 1); |
6ae56b55 RR |
127 | ctr_running = 0; |
128 | put_online_cpus(); | |
b28d1b92 RR |
129 | } |
130 | ||
d8471ad3 RR |
131 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
132 | ||
133 | static DEFINE_PER_CPU(int, switch_index); | |
134 | ||
39e97f40 RR |
135 | static inline int has_mux(void) |
136 | { | |
137 | return !!model->switch_ctrl; | |
138 | } | |
139 | ||
d8471ad3 RR |
140 | inline int op_x86_phys_to_virt(int phys) |
141 | { | |
142 | return __get_cpu_var(switch_index) + phys; | |
143 | } | |
144 | ||
61d149d5 RR |
145 | inline int op_x86_virt_to_phys(int virt) |
146 | { | |
147 | return virt % model->num_counters; | |
148 | } | |
149 | ||
6ab82f95 RR |
150 | static void nmi_shutdown_mux(void) |
151 | { | |
152 | int i; | |
39e97f40 RR |
153 | |
154 | if (!has_mux()) | |
155 | return; | |
156 | ||
6ab82f95 RR |
157 | for_each_possible_cpu(i) { |
158 | kfree(per_cpu(cpu_msrs, i).multiplex); | |
159 | per_cpu(cpu_msrs, i).multiplex = NULL; | |
160 | per_cpu(switch_index, i) = 0; | |
161 | } | |
162 | } | |
163 | ||
164 | static int nmi_setup_mux(void) | |
165 | { | |
166 | size_t multiplex_size = | |
167 | sizeof(struct op_msr) * model->num_virt_counters; | |
168 | int i; | |
39e97f40 RR |
169 | |
170 | if (!has_mux()) | |
171 | return 1; | |
172 | ||
6ab82f95 RR |
173 | for_each_possible_cpu(i) { |
174 | per_cpu(cpu_msrs, i).multiplex = | |
c17c8fbf | 175 | kzalloc(multiplex_size, GFP_KERNEL); |
6ab82f95 RR |
176 | if (!per_cpu(cpu_msrs, i).multiplex) |
177 | return 0; | |
178 | } | |
39e97f40 | 179 | |
6ab82f95 RR |
180 | return 1; |
181 | } | |
182 | ||
48fb4b46 RR |
183 | static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) |
184 | { | |
185 | int i; | |
186 | struct op_msr *multiplex = msrs->multiplex; | |
187 | ||
39e97f40 RR |
188 | if (!has_mux()) |
189 | return; | |
190 | ||
48fb4b46 RR |
191 | for (i = 0; i < model->num_virt_counters; ++i) { |
192 | if (counter_config[i].enabled) { | |
193 | multiplex[i].saved = -(u64)counter_config[i].count; | |
194 | } else { | |
48fb4b46 RR |
195 | multiplex[i].saved = 0; |
196 | } | |
197 | } | |
198 | ||
199 | per_cpu(switch_index, cpu) = 0; | |
200 | } | |
201 | ||
d0f585dd RR |
202 | static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) |
203 | { | |
68dc819c | 204 | struct op_msr *counters = msrs->counters; |
d0f585dd RR |
205 | struct op_msr *multiplex = msrs->multiplex; |
206 | int i; | |
207 | ||
208 | for (i = 0; i < model->num_counters; ++i) { | |
209 | int virt = op_x86_phys_to_virt(i); | |
68dc819c RR |
210 | if (counters[i].addr) |
211 | rdmsrl(counters[i].addr, multiplex[virt].saved); | |
d0f585dd RR |
212 | } |
213 | } | |
214 | ||
215 | static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs) | |
216 | { | |
68dc819c | 217 | struct op_msr *counters = msrs->counters; |
d0f585dd RR |
218 | struct op_msr *multiplex = msrs->multiplex; |
219 | int i; | |
220 | ||
221 | for (i = 0; i < model->num_counters; ++i) { | |
222 | int virt = op_x86_phys_to_virt(i); | |
68dc819c RR |
223 | if (counters[i].addr) |
224 | wrmsrl(counters[i].addr, multiplex[virt].saved); | |
d0f585dd RR |
225 | } |
226 | } | |
227 | ||
b28d1b92 RR |
228 | static void nmi_cpu_switch(void *dummy) |
229 | { | |
230 | int cpu = smp_processor_id(); | |
231 | int si = per_cpu(switch_index, cpu); | |
232 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); | |
233 | ||
234 | nmi_cpu_stop(NULL); | |
235 | nmi_cpu_save_mpx_registers(msrs); | |
236 | ||
237 | /* move to next set */ | |
238 | si += model->num_counters; | |
d8cc108f | 239 | if ((si >= model->num_virt_counters) || (counter_config[si].count == 0)) |
b28d1b92 RR |
240 | per_cpu(switch_index, cpu) = 0; |
241 | else | |
242 | per_cpu(switch_index, cpu) = si; | |
243 | ||
244 | model->switch_ctrl(model, msrs); | |
245 | nmi_cpu_restore_mpx_registers(msrs); | |
246 | ||
247 | nmi_cpu_start(NULL); | |
248 | } | |
249 | ||
250 | ||
251 | /* | |
252 | * Quick check to see if multiplexing is necessary. | |
253 | * The check should be sufficient since counters are used | |
254 | * in ordre. | |
255 | */ | |
256 | static int nmi_multiplex_on(void) | |
257 | { | |
258 | return counter_config[model->num_counters].count ? 0 : -EINVAL; | |
259 | } | |
260 | ||
261 | static int nmi_switch_event(void) | |
262 | { | |
39e97f40 | 263 | if (!has_mux()) |
b28d1b92 RR |
264 | return -ENOSYS; /* not implemented */ |
265 | if (nmi_multiplex_on() < 0) | |
266 | return -EINVAL; /* not necessary */ | |
267 | ||
6ae56b55 RR |
268 | get_online_cpus(); |
269 | if (ctr_running) | |
270 | on_each_cpu(nmi_cpu_switch, NULL, 1); | |
271 | put_online_cpus(); | |
b28d1b92 | 272 | |
b28d1b92 RR |
273 | return 0; |
274 | } | |
275 | ||
52805144 RR |
276 | static inline void mux_init(struct oprofile_operations *ops) |
277 | { | |
278 | if (has_mux()) | |
279 | ops->switch_events = nmi_switch_event; | |
280 | } | |
281 | ||
4d015f79 RR |
282 | static void mux_clone(int cpu) |
283 | { | |
284 | if (!has_mux()) | |
285 | return; | |
286 | ||
287 | memcpy(per_cpu(cpu_msrs, cpu).multiplex, | |
288 | per_cpu(cpu_msrs, 0).multiplex, | |
289 | sizeof(struct op_msr) * model->num_virt_counters); | |
290 | } | |
291 | ||
d8471ad3 RR |
292 | #else |
293 | ||
294 | inline int op_x86_phys_to_virt(int phys) { return phys; } | |
61d149d5 | 295 | inline int op_x86_virt_to_phys(int virt) { return virt; } |
6ab82f95 RR |
296 | static inline void nmi_shutdown_mux(void) { } |
297 | static inline int nmi_setup_mux(void) { return 1; } | |
48fb4b46 RR |
298 | static inline void |
299 | nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { } | |
52805144 | 300 | static inline void mux_init(struct oprofile_operations *ops) { } |
4d015f79 | 301 | static void mux_clone(int cpu) { } |
d8471ad3 RR |
302 | |
303 | #endif | |
304 | ||
1da177e4 LT |
305 | static void free_msrs(void) |
306 | { | |
307 | int i; | |
c8912599 | 308 | for_each_possible_cpu(i) { |
d18d00f5 MT |
309 | kfree(per_cpu(cpu_msrs, i).counters); |
310 | per_cpu(cpu_msrs, i).counters = NULL; | |
311 | kfree(per_cpu(cpu_msrs, i).controls); | |
312 | per_cpu(cpu_msrs, i).controls = NULL; | |
1da177e4 | 313 | } |
8f5a2dd8 | 314 | nmi_shutdown_mux(); |
1da177e4 LT |
315 | } |
316 | ||
1da177e4 LT |
317 | static int allocate_msrs(void) |
318 | { | |
1da177e4 LT |
319 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
320 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; | |
321 | ||
4c168eaf | 322 | int i; |
0939c17c | 323 | for_each_possible_cpu(i) { |
c17c8fbf | 324 | per_cpu(cpu_msrs, i).counters = kzalloc(counters_size, |
6ab82f95 RR |
325 | GFP_KERNEL); |
326 | if (!per_cpu(cpu_msrs, i).counters) | |
8f5a2dd8 | 327 | goto fail; |
c17c8fbf | 328 | per_cpu(cpu_msrs, i).controls = kzalloc(controls_size, |
6ab82f95 RR |
329 | GFP_KERNEL); |
330 | if (!per_cpu(cpu_msrs, i).controls) | |
8f5a2dd8 | 331 | goto fail; |
1da177e4 LT |
332 | } |
333 | ||
8f5a2dd8 RR |
334 | if (!nmi_setup_mux()) |
335 | goto fail; | |
336 | ||
6ab82f95 | 337 | return 1; |
8f5a2dd8 RR |
338 | |
339 | fail: | |
340 | free_msrs(); | |
341 | return 0; | |
1da177e4 LT |
342 | } |
343 | ||
b75f53db | 344 | static void nmi_cpu_setup(void *dummy) |
1da177e4 LT |
345 | { |
346 | int cpu = smp_processor_id(); | |
d18d00f5 | 347 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
44ab9a6b | 348 | nmi_cpu_save_registers(msrs); |
1da177e4 | 349 | spin_lock(&oprofilefs_lock); |
ef8828dd | 350 | model->setup_ctrs(model, msrs); |
6bfccd09 | 351 | nmi_cpu_setup_mux(cpu, msrs); |
1da177e4 | 352 | spin_unlock(&oprofilefs_lock); |
d18d00f5 | 353 | per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC); |
1da177e4 LT |
354 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
355 | } | |
356 | ||
2fbe7b25 DZ |
357 | static struct notifier_block profile_exceptions_nb = { |
358 | .notifier_call = profile_exceptions_notify, | |
359 | .next = NULL, | |
5b75af0a | 360 | .priority = 2 |
2fbe7b25 | 361 | }; |
1da177e4 LT |
362 | |
363 | static int nmi_setup(void) | |
364 | { | |
b75f53db | 365 | int err = 0; |
6c977aad | 366 | int cpu; |
2fbe7b25 | 367 | |
1da177e4 | 368 | if (!allocate_msrs()) |
8f5a2dd8 | 369 | return -ENOMEM; |
2fbe7b25 | 370 | |
4c168eaf | 371 | /* We need to serialize save and setup for HT because the subset |
1da177e4 LT |
372 | * of msrs are distinct for save and setup operations |
373 | */ | |
6c977aad AK |
374 | |
375 | /* Assume saved/restored counters are the same on all CPUs */ | |
8617f98c RR |
376 | err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0)); |
377 | if (err) | |
378 | goto fail; | |
379 | ||
b75f53db | 380 | for_each_possible_cpu(cpu) { |
4d015f79 RR |
381 | if (!cpu) |
382 | continue; | |
383 | ||
384 | memcpy(per_cpu(cpu_msrs, cpu).counters, | |
385 | per_cpu(cpu_msrs, 0).counters, | |
386 | sizeof(struct op_msr) * model->num_counters); | |
387 | ||
388 | memcpy(per_cpu(cpu_msrs, cpu).controls, | |
389 | per_cpu(cpu_msrs, 0).controls, | |
390 | sizeof(struct op_msr) * model->num_controls); | |
391 | ||
392 | mux_clone(cpu); | |
6c977aad | 393 | } |
8f5a2dd8 RR |
394 | |
395 | err = register_die_notifier(&profile_exceptions_nb); | |
396 | if (err) | |
397 | goto fail; | |
398 | ||
6ae56b55 | 399 | get_online_cpus(); |
15c8b6c1 | 400 | on_each_cpu(nmi_cpu_setup, NULL, 1); |
1da177e4 | 401 | nmi_enabled = 1; |
6ae56b55 RR |
402 | put_online_cpus(); |
403 | ||
1da177e4 | 404 | return 0; |
8f5a2dd8 RR |
405 | fail: |
406 | free_msrs(); | |
407 | return err; | |
1da177e4 LT |
408 | } |
409 | ||
44ab9a6b | 410 | static void nmi_cpu_restore_registers(struct op_msrs *msrs) |
1da177e4 | 411 | { |
b75f53db CM |
412 | struct op_msr *counters = msrs->counters; |
413 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
414 | unsigned int i; |
415 | ||
1a245c45 | 416 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
417 | if (controls[i].addr) |
418 | wrmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 | 419 | } |
b75f53db | 420 | |
1a245c45 | 421 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
422 | if (counters[i].addr) |
423 | wrmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 LT |
424 | } |
425 | } | |
1da177e4 | 426 | |
b75f53db | 427 | static void nmi_cpu_shutdown(void *dummy) |
1da177e4 LT |
428 | { |
429 | unsigned int v; | |
430 | int cpu = smp_processor_id(); | |
82a22528 | 431 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
b75f53db | 432 | |
1da177e4 LT |
433 | /* restoring APIC_LVTPC can trigger an apic error because the delivery |
434 | * mode and vector nr combination can be illegal. That's by design: on | |
435 | * power on apic lvt contain a zero vector nr which are legal only for | |
436 | * NMI delivery mode. So inhibit apic err before restoring lvtpc | |
437 | */ | |
438 | v = apic_read(APIC_LVTERR); | |
439 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
d18d00f5 | 440 | apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); |
1da177e4 | 441 | apic_write(APIC_LVTERR, v); |
44ab9a6b | 442 | nmi_cpu_restore_registers(msrs); |
1da177e4 LT |
443 | } |
444 | ||
1da177e4 LT |
445 | static void nmi_shutdown(void) |
446 | { | |
b61e06f2 AR |
447 | struct op_msrs *msrs; |
448 | ||
6ae56b55 | 449 | get_online_cpus(); |
15c8b6c1 | 450 | on_each_cpu(nmi_cpu_shutdown, NULL, 1); |
6ae56b55 RR |
451 | nmi_enabled = 0; |
452 | ctr_running = 0; | |
453 | put_online_cpus(); | |
2fbe7b25 | 454 | unregister_die_notifier(&profile_exceptions_nb); |
b61e06f2 | 455 | msrs = &get_cpu_var(cpu_msrs); |
d18d00f5 | 456 | model->shutdown(msrs); |
1da177e4 | 457 | free_msrs(); |
93e1ade5 | 458 | put_cpu_var(cpu_msrs); |
1da177e4 LT |
459 | } |
460 | ||
6ae56b55 RR |
461 | static void nmi_cpu_up(void *dummy) |
462 | { | |
463 | if (nmi_enabled) | |
464 | nmi_cpu_setup(dummy); | |
465 | if (ctr_running) | |
466 | nmi_cpu_start(dummy); | |
467 | } | |
468 | ||
469 | static void nmi_cpu_down(void *dummy) | |
470 | { | |
471 | if (ctr_running) | |
472 | nmi_cpu_stop(dummy); | |
473 | if (nmi_enabled) | |
474 | nmi_cpu_shutdown(dummy); | |
475 | } | |
476 | ||
b75f53db | 477 | static int nmi_create_files(struct super_block *sb, struct dentry *root) |
1da177e4 LT |
478 | { |
479 | unsigned int i; | |
480 | ||
4d4036e0 | 481 | for (i = 0; i < model->num_virt_counters; ++i) { |
b75f53db | 482 | struct dentry *dir; |
0c6856f7 | 483 | char buf[4]; |
b75f53db CM |
484 | |
485 | /* quick little hack to _not_ expose a counter if it is not | |
cb9c448c DZ |
486 | * available for use. This should protect userspace app. |
487 | * NOTE: assumes 1:1 mapping here (that counters are organized | |
488 | * sequentially in their struct assignment). | |
489 | */ | |
11be1a7b | 490 | if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i))) |
cb9c448c DZ |
491 | continue; |
492 | ||
0c6856f7 | 493 | snprintf(buf, sizeof(buf), "%d", i); |
1da177e4 | 494 | dir = oprofilefs_mkdir(sb, root, buf); |
b75f53db CM |
495 | oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); |
496 | oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); | |
497 | oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); | |
498 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); | |
499 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); | |
500 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); | |
1da177e4 LT |
501 | } |
502 | ||
503 | return 0; | |
504 | } | |
b75f53db | 505 | |
69046d43 RR |
506 | static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action, |
507 | void *data) | |
508 | { | |
509 | int cpu = (unsigned long)data; | |
510 | switch (action) { | |
511 | case CPU_DOWN_FAILED: | |
512 | case CPU_ONLINE: | |
6ae56b55 | 513 | smp_call_function_single(cpu, nmi_cpu_up, NULL, 0); |
69046d43 RR |
514 | break; |
515 | case CPU_DOWN_PREPARE: | |
6ae56b55 | 516 | smp_call_function_single(cpu, nmi_cpu_down, NULL, 1); |
69046d43 RR |
517 | break; |
518 | } | |
519 | return NOTIFY_DONE; | |
520 | } | |
521 | ||
522 | static struct notifier_block oprofile_cpu_nb = { | |
523 | .notifier_call = oprofile_cpu_notifier | |
524 | }; | |
69046d43 RR |
525 | |
526 | #ifdef CONFIG_PM | |
527 | ||
528 | static int nmi_suspend(struct sys_device *dev, pm_message_t state) | |
529 | { | |
530 | /* Only one CPU left, just stop that one */ | |
531 | if (nmi_enabled == 1) | |
532 | nmi_cpu_stop(NULL); | |
533 | return 0; | |
534 | } | |
535 | ||
536 | static int nmi_resume(struct sys_device *dev) | |
537 | { | |
538 | if (nmi_enabled == 1) | |
539 | nmi_cpu_start(NULL); | |
540 | return 0; | |
541 | } | |
542 | ||
543 | static struct sysdev_class oprofile_sysclass = { | |
544 | .name = "oprofile", | |
545 | .resume = nmi_resume, | |
546 | .suspend = nmi_suspend, | |
547 | }; | |
548 | ||
549 | static struct sys_device device_oprofile = { | |
550 | .id = 0, | |
551 | .cls = &oprofile_sysclass, | |
552 | }; | |
553 | ||
554 | static int __init init_sysfs(void) | |
555 | { | |
556 | int error; | |
557 | ||
558 | error = sysdev_class_register(&oprofile_sysclass); | |
559 | if (!error) | |
560 | error = sysdev_register(&device_oprofile); | |
561 | return error; | |
562 | } | |
563 | ||
564 | static void exit_sysfs(void) | |
565 | { | |
566 | sysdev_unregister(&device_oprofile); | |
567 | sysdev_class_unregister(&oprofile_sysclass); | |
568 | } | |
569 | ||
570 | #else | |
571 | #define init_sysfs() do { } while (0) | |
572 | #define exit_sysfs() do { } while (0) | |
573 | #endif /* CONFIG_PM */ | |
574 | ||
b75f53db | 575 | static int __init p4_init(char **cpu_type) |
1da177e4 LT |
576 | { |
577 | __u8 cpu_model = boot_cpu_data.x86_model; | |
578 | ||
1f3d7b60 | 579 | if (cpu_model > 6 || cpu_model == 5) |
1da177e4 LT |
580 | return 0; |
581 | ||
582 | #ifndef CONFIG_SMP | |
583 | *cpu_type = "i386/p4"; | |
584 | model = &op_p4_spec; | |
585 | return 1; | |
586 | #else | |
587 | switch (smp_num_siblings) { | |
b75f53db CM |
588 | case 1: |
589 | *cpu_type = "i386/p4"; | |
590 | model = &op_p4_spec; | |
591 | return 1; | |
592 | ||
593 | case 2: | |
594 | *cpu_type = "i386/p4-ht"; | |
595 | model = &op_p4_ht2_spec; | |
596 | return 1; | |
1da177e4 LT |
597 | } |
598 | #endif | |
599 | ||
600 | printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n"); | |
601 | printk(KERN_INFO "oprofile: Reverting to timer mode.\n"); | |
602 | return 0; | |
603 | } | |
604 | ||
7e4e0bd5 RR |
605 | static int force_arch_perfmon; |
606 | static int force_cpu_type(const char *str, struct kernel_param *kp) | |
607 | { | |
8d7ff4f2 | 608 | if (!strcmp(str, "arch_perfmon")) { |
7e4e0bd5 RR |
609 | force_arch_perfmon = 1; |
610 | printk(KERN_INFO "oprofile: forcing architectural perfmon\n"); | |
611 | } | |
612 | ||
613 | return 0; | |
614 | } | |
615 | module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0); | |
1dcdb5a9 | 616 | |
b75f53db | 617 | static int __init ppro_init(char **cpu_type) |
1da177e4 LT |
618 | { |
619 | __u8 cpu_model = boot_cpu_data.x86_model; | |
259a83a8 | 620 | struct op_x86_model_spec *spec = &op_ppro_spec; /* default */ |
1da177e4 | 621 | |
1dcdb5a9 AK |
622 | if (force_arch_perfmon && cpu_has_arch_perfmon) |
623 | return 0; | |
624 | ||
4b9f12a3 LT |
625 | switch (cpu_model) { |
626 | case 0 ... 2: | |
627 | *cpu_type = "i386/ppro"; | |
628 | break; | |
629 | case 3 ... 5: | |
630 | *cpu_type = "i386/pii"; | |
631 | break; | |
632 | case 6 ... 8: | |
3d337c65 | 633 | case 10 ... 11: |
4b9f12a3 LT |
634 | *cpu_type = "i386/piii"; |
635 | break; | |
636 | case 9: | |
3d337c65 | 637 | case 13: |
4b9f12a3 LT |
638 | *cpu_type = "i386/p6_mobile"; |
639 | break; | |
4b9f12a3 | 640 | case 14: |
64471ebe | 641 | *cpu_type = "i386/core"; |
4b9f12a3 LT |
642 | break; |
643 | case 15: case 23: | |
644 | *cpu_type = "i386/core_2"; | |
645 | break; | |
e83e452b | 646 | case 0x2e: |
6adf406f | 647 | case 26: |
802070f5 | 648 | spec = &op_arch_perfmon_spec; |
6adf406f AK |
649 | *cpu_type = "i386/core_i7"; |
650 | break; | |
651 | case 28: | |
652 | *cpu_type = "i386/atom"; | |
653 | break; | |
4b9f12a3 LT |
654 | default: |
655 | /* Unknown */ | |
1da177e4 | 656 | return 0; |
1da177e4 LT |
657 | } |
658 | ||
802070f5 | 659 | model = spec; |
1da177e4 LT |
660 | return 1; |
661 | } | |
662 | ||
405ae7d3 | 663 | /* in order to get sysfs right */ |
1da177e4 LT |
664 | static int using_nmi; |
665 | ||
96d0821c | 666 | int __init op_nmi_init(struct oprofile_operations *ops) |
1da177e4 LT |
667 | { |
668 | __u8 vendor = boot_cpu_data.x86_vendor; | |
669 | __u8 family = boot_cpu_data.x86; | |
b9917028 | 670 | char *cpu_type = NULL; |
adf5ec0b | 671 | int ret = 0; |
1da177e4 LT |
672 | |
673 | if (!cpu_has_apic) | |
674 | return -ENODEV; | |
b75f53db | 675 | |
1da177e4 | 676 | switch (vendor) { |
b75f53db CM |
677 | case X86_VENDOR_AMD: |
678 | /* Needs to be at least an Athlon (or hammer in 32bit mode) */ | |
1da177e4 | 679 | |
b75f53db | 680 | switch (family) { |
b75f53db | 681 | case 6: |
b75f53db CM |
682 | cpu_type = "i386/athlon"; |
683 | break; | |
684 | case 0xf: | |
d20f24c6 RR |
685 | /* |
686 | * Actually it could be i386/hammer too, but | |
687 | * give user space an consistent name. | |
688 | */ | |
b75f53db CM |
689 | cpu_type = "x86-64/hammer"; |
690 | break; | |
691 | case 0x10: | |
b75f53db CM |
692 | cpu_type = "x86-64/family10"; |
693 | break; | |
12f2b261 | 694 | case 0x11: |
12f2b261 BK |
695 | cpu_type = "x86-64/family11h"; |
696 | break; | |
d20f24c6 RR |
697 | default: |
698 | return -ENODEV; | |
b75f53db | 699 | } |
d20f24c6 | 700 | model = &op_amd_spec; |
b75f53db CM |
701 | break; |
702 | ||
703 | case X86_VENDOR_INTEL: | |
704 | switch (family) { | |
705 | /* Pentium IV */ | |
706 | case 0xf: | |
b9917028 | 707 | p4_init(&cpu_type); |
1da177e4 | 708 | break; |
b75f53db CM |
709 | |
710 | /* A P6-class processor */ | |
711 | case 6: | |
b9917028 | 712 | ppro_init(&cpu_type); |
1da177e4 LT |
713 | break; |
714 | ||
715 | default: | |
b9917028 | 716 | break; |
b75f53db | 717 | } |
b9917028 | 718 | |
e419294e RR |
719 | if (cpu_type) |
720 | break; | |
721 | ||
722 | if (!cpu_has_arch_perfmon) | |
b9917028 | 723 | return -ENODEV; |
e419294e RR |
724 | |
725 | /* use arch perfmon as fallback */ | |
726 | cpu_type = "i386/arch_perfmon"; | |
727 | model = &op_arch_perfmon_spec; | |
b75f53db CM |
728 | break; |
729 | ||
730 | default: | |
731 | return -ENODEV; | |
1da177e4 LT |
732 | } |
733 | ||
6ae56b55 | 734 | get_online_cpus(); |
80a8c9ff | 735 | register_cpu_notifier(&oprofile_cpu_nb); |
6ae56b55 RR |
736 | nmi_enabled = 0; |
737 | ctr_running = 0; | |
738 | put_online_cpus(); | |
216f3d9b | 739 | |
270d3e1a | 740 | /* default values, can be overwritten by model */ |
6e63ea4b RR |
741 | ops->create_files = nmi_create_files; |
742 | ops->setup = nmi_setup; | |
743 | ops->shutdown = nmi_shutdown; | |
744 | ops->start = nmi_start; | |
745 | ops->stop = nmi_stop; | |
746 | ops->cpu_type = cpu_type; | |
270d3e1a | 747 | |
adf5ec0b RR |
748 | if (model->init) |
749 | ret = model->init(ops); | |
750 | if (ret) | |
751 | return ret; | |
752 | ||
52471c67 RR |
753 | if (!model->num_virt_counters) |
754 | model->num_virt_counters = model->num_counters; | |
755 | ||
52805144 RR |
756 | mux_init(ops); |
757 | ||
405ae7d3 | 758 | init_sysfs(); |
1da177e4 | 759 | using_nmi = 1; |
1da177e4 LT |
760 | printk(KERN_INFO "oprofile: using NMI interrupt.\n"); |
761 | return 0; | |
762 | } | |
763 | ||
96d0821c | 764 | void op_nmi_exit(void) |
1da177e4 | 765 | { |
80a8c9ff | 766 | if (using_nmi) { |
405ae7d3 | 767 | exit_sysfs(); |
6ae56b55 | 768 | get_online_cpus(); |
80a8c9ff | 769 | unregister_cpu_notifier(&oprofile_cpu_nb); |
6ae56b55 RR |
770 | nmi_enabled = 0; |
771 | ctr_running = 0; | |
772 | put_online_cpus(); | |
80a8c9ff | 773 | } |
adf5ec0b RR |
774 | if (model->exit) |
775 | model->exit(); | |
1da177e4 | 776 | } |