]> bbs.cooldavid.org Git - net-next-2.6.git/blame - arch/x86/kvm/x86.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Trace shadow page lifecycle
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
674eea0f
AK		 80static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
ed85c068
AP		 86int ignore_msrs = 0;
87module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
417bc304 89struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 102 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 110 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 111 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 119 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 121 { "largepages", VM_STAT(lpages) },
417bc304
HB		 122 { NULL }
123};
124
5fb76f9b
CO		 125unsigned long segment_base(u16 selector)
126{
127 struct descriptor_table gdt;
a5f61300 128 struct desc_struct *d;
5fb76f9b
CO		 129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
135 asm("sgdt %0" : "=m"(gdt));
136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
139 u16 ldt_selector;
140
141 asm("sldt %0" : "=g"(ldt_selector));
142 table_base = segment_base(ldt_selector);
143 }
a5f61300
AK		 144 d = (struct desc_struct *)(table_base + (selector & ~7));
145 v = d->base0 | ((unsigned long)d->base1 << 16) |
146 ((unsigned long)d->base2 << 24);
5fb76f9b 147#ifdef CONFIG_X86_64
a5f61300
AK		 148 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
149 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 150#endif
151 return v;
152}
153EXPORT_SYMBOL_GPL(segment_base);
154
6866b83e
CO		 155u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
156{
157 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 158 return vcpu->arch.apic_base;
6866b83e 159 else
ad312c7c 160 return vcpu->arch.apic_base;
6866b83e
CO		 161}
162EXPORT_SYMBOL_GPL(kvm_get_apic_base);
163
164void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
165{
166 /* TODO: reserve bits check */
167 if (irqchip_in_kernel(vcpu->kvm))
168 kvm_lapic_set_base(vcpu, data);
169 else
ad312c7c 170 vcpu->arch.apic_base = data;
6866b83e
CO		 171}
172EXPORT_SYMBOL_GPL(kvm_set_apic_base);
173
298101da
AK		 174void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
175{
ad312c7c
ZX		 176 WARN_ON(vcpu->arch.exception.pending);
177 vcpu->arch.exception.pending = true;
178 vcpu->arch.exception.has_error_code = false;
179 vcpu->arch.exception.nr = nr;
298101da
AK		 180}
181EXPORT_SYMBOL_GPL(kvm_queue_exception);
182
c3c91fee
AK		 183void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
184 u32 error_code)
185{
186 ++vcpu->stat.pf_guest;
d8017474 187
71c4dfaf 188 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 189 switch(vcpu->arch.exception.nr) {
190 case DF_VECTOR:
71c4dfaf
JR		 191 /* triple fault -> shutdown */
192 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 193 return;
194 case PF_VECTOR:
195 vcpu->arch.exception.nr = DF_VECTOR;
196 vcpu->arch.exception.error_code = 0;
197 return;
198 default:
199 /* replace previous exception with a new one in a hope
200 that instruction re-execution will regenerate lost
201 exception */
202 vcpu->arch.exception.pending = false;
203 break;
71c4dfaf 204 }
c3c91fee 205 }
ad312c7c 206 vcpu->arch.cr2 = addr;
c3c91fee
AK		 207 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
208}
209
3419ffc8
SY		 210void kvm_inject_nmi(struct kvm_vcpu *vcpu)
211{
212 vcpu->arch.nmi_pending = 1;
213}
214EXPORT_SYMBOL_GPL(kvm_inject_nmi);
215
298101da
AK		 216void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
217{
ad312c7c
ZX		 218 WARN_ON(vcpu->arch.exception.pending);
219 vcpu->arch.exception.pending = true;
220 vcpu->arch.exception.has_error_code = true;
221 vcpu->arch.exception.nr = nr;
222 vcpu->arch.exception.error_code = error_code;
298101da
AK		 223}
224EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
225
226static void __queue_exception(struct kvm_vcpu *vcpu)
227{
ad312c7c
ZX		 228 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
229 vcpu->arch.exception.has_error_code,
230 vcpu->arch.exception.error_code);
298101da
AK		 231}
232
a03490ed
CO		 233/*
234 * Load the pae pdptrs. Return true is they are all valid.
235 */
236int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
237{
238 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
239 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
240 int i;
241 int ret;
ad312c7c 242 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 243
a03490ed
CO		 244 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
245 offset * sizeof(u64), sizeof(pdpte));
246 if (ret < 0) {
247 ret = 0;
248 goto out;
249 }
250 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 251 if (is_present_gpte(pdpte[i]) &&
20c466b5 252 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 253 ret = 0;
254 goto out;
255 }
256 }
257 ret = 1;
258
ad312c7c 259 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 260 __set_bit(VCPU_EXREG_PDPTR,
261 (unsigned long *)&vcpu->arch.regs_avail);
262 __set_bit(VCPU_EXREG_PDPTR,
263 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 264out:
a03490ed
CO		 265
266 return ret;
267}
cc4b6871 268EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 269
d835dfec
AK		 270static bool pdptrs_changed(struct kvm_vcpu *vcpu)
271{
ad312c7c 272 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 273 bool changed = true;
274 int r;
275
276 if (is_long_mode(vcpu) || !is_pae(vcpu))
277 return false;
278
6de4f3ad
AK		 279 if (!test_bit(VCPU_EXREG_PDPTR,
280 (unsigned long *)&vcpu->arch.regs_avail))
281 return true;
282
ad312c7c 283 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 284 if (r < 0)
285 goto out;
ad312c7c 286 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 287out:
d835dfec
AK		 288
289 return changed;
290}
291
2d3ad1f4 292void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 293{
294 if (cr0 & CR0_RESERVED_BITS) {
295 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 296 cr0, vcpu->arch.cr0);
c1a5d4f9 297 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 298 return;
299 }
300
301 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
302 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 303 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 304 return;
305 }
306
307 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
308 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
309 "and a clear PE flag\n");
c1a5d4f9 310 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 311 return;
312 }
313
314 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
315#ifdef CONFIG_X86_64
ad312c7c 316 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 317 int cs_db, cs_l;
318
319 if (!is_pae(vcpu)) {
320 printk(KERN_DEBUG "set_cr0: #GP, start paging "
321 "in long mode while PAE is disabled\n");
c1a5d4f9 322 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 323 return;
324 }
325 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
326 if (cs_l) {
327 printk(KERN_DEBUG "set_cr0: #GP, start paging "
328 "in long mode while CS.L == 1\n");
c1a5d4f9 329 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 330 return;
331
332 }
333 } else
334#endif
ad312c7c 335 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 336 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
337 "reserved bits\n");
c1a5d4f9 338 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 339 return;
340 }
341
342 }
343
344 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 345 vcpu->arch.cr0 = cr0;
a03490ed 346
a03490ed 347 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 348 return;
349}
2d3ad1f4 350EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 351
2d3ad1f4 352void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 353{
2d3ad1f4 354 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 355}
2d3ad1f4 356EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 357
2d3ad1f4 358void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 359{
a2edf57f
AK		 360 unsigned long old_cr4 = vcpu->arch.cr4;
361 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
362
a03490ed
CO		 363 if (cr4 & CR4_RESERVED_BITS) {
364 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
368
369 if (is_long_mode(vcpu)) {
370 if (!(cr4 & X86_CR4_PAE)) {
371 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
372 "in long mode\n");
c1a5d4f9 373 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 374 return;
375 }
a2edf57f
AK		 376 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
377 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 378 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 379 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 380 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 381 return;
382 }
383
384 if (cr4 & X86_CR4_VMXE) {
385 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 386 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 387 return;
388 }
389 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 390 vcpu->arch.cr4 = cr4;
5a41accd 391 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 392 kvm_mmu_reset_context(vcpu);
a03490ed 393}
2d3ad1f4 394EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 395
2d3ad1f4 396void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 397{
ad312c7c 398 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 399 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 400 kvm_mmu_flush_tlb(vcpu);
401 return;
402 }
403
a03490ed
CO		 404 if (is_long_mode(vcpu)) {
405 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
406 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 407 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 408 return;
409 }
410 } else {
411 if (is_pae(vcpu)) {
412 if (cr3 & CR3_PAE_RESERVED_BITS) {
413 printk(KERN_DEBUG
414 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 415 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 416 return;
417 }
418 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
419 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
420 "reserved bits\n");
c1a5d4f9 421 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 422 return;
423 }
424 }
425 /*
426 * We don't check reserved bits in nonpae mode, because
427 * this isn't enforced, and VMware depends on this.
428 */
429 }
430
a03490ed
CO		 431 /*
432 * Does the new cr3 value map to physical memory? (Note, we
433 * catch an invalid cr3 even in real-mode, because it would
434 * cause trouble later on when we turn on paging anyway.)
435 *
436 * A real CPU would silently accept an invalid cr3 and would
437 * attempt to use it - with largely undefined (and often hard
438 * to debug) behavior on the guest side.
439 */
440 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 441 kvm_inject_gp(vcpu, 0);
a03490ed 442 else {
ad312c7c
ZX		 443 vcpu->arch.cr3 = cr3;
444 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 445 }
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 448
2d3ad1f4 449void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 450{
451 if (cr8 & CR8_RESERVED_BITS) {
452 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 453 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 454 return;
455 }
456 if (irqchip_in_kernel(vcpu->kvm))
457 kvm_lapic_set_tpr(vcpu, cr8);
458 else
ad312c7c 459 vcpu->arch.cr8 = cr8;
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 462
2d3ad1f4 463unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 464{
465 if (irqchip_in_kernel(vcpu->kvm))
466 return kvm_lapic_get_cr8(vcpu);
467 else
ad312c7c 468 return vcpu->arch.cr8;
a03490ed 469}
2d3ad1f4 470EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 471
d8017474
AG		 472static inline u32 bit(int bitno)
473{
474 return 1 << (bitno & 31);
475}
476
043405e1
CO		 477/*
478 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
479 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
480 *
481 * This list is modified at module load time to reflect the
482 * capabilities of the host cpu.
483 */
484static u32 msrs_to_save[] = {
485 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
486 MSR_K6_STAR,
487#ifdef CONFIG_X86_64
488 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
489#endif
af24a4e4 490 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 491 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 492};
493
494static unsigned num_msrs_to_save;
495
496static u32 emulated_msrs[] = {
497 MSR_IA32_MISC_ENABLE,
498};
499
15c4a640
CO		 500static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
501{
f2b4b7dd 502 if (efer & efer_reserved_bits) {
15c4a640
CO		 503 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
504 efer);
c1a5d4f9 505 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 506 return;
507 }
508
509 if (is_paging(vcpu)
ad312c7c 510 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 511 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 512 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 513 return;
514 }
515
1b2fd70c
AG		 516 if (efer & EFER_FFXSR) {
517 struct kvm_cpuid_entry2 *feat;
518
519 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
520 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
521 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
522 kvm_inject_gp(vcpu, 0);
523 return;
524 }
525 }
526
d8017474
AG		 527 if (efer & EFER_SVME) {
528 struct kvm_cpuid_entry2 *feat;
529
530 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
531 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
532 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
533 kvm_inject_gp(vcpu, 0);
534 return;
535 }
536 }
537
15c4a640
CO		 538 kvm_x86_ops->set_efer(vcpu, efer);
539
540 efer &= ~EFER_LMA;
ad312c7c 541 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 542
ad312c7c 543 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 544
545 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
546 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 547}
548
f2b4b7dd
JR		 549void kvm_enable_efer_bits(u64 mask)
550{
551 efer_reserved_bits &= ~mask;
552}
553EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
554
555
15c4a640
CO		 556/*
557 * Writes msr value into into the appropriate "register".
558 * Returns 0 on success, non-0 otherwise.
559 * Assumes vcpu_load() was already called.
560 */
561int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
562{
563 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
564}
565
313a3dc7
CO		 566/*
567 * Adapt set_msr() to msr_io()'s calling convention
568 */
569static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
570{
571 return kvm_set_msr(vcpu, index, *data);
572}
573
18068523
GOC		 574static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
575{
576 static int version;
50d0a0f9
GH		 577 struct pvclock_wall_clock wc;
578 struct timespec now, sys, boot;
18068523
GOC		 579
580 if (!wall_clock)
581 return;
582
583 version++;
584
18068523
GOC		 585 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
586
50d0a0f9
GH		 587 /*
588 * The guest calculates current wall clock time by adding
589 * system time (updated by kvm_write_guest_time below) to the
590 * wall clock specified here. guest system time equals host
591 * system time for us, thus we must fill in host boot time here.
592 */
593 now = current_kernel_time();
594 ktime_get_ts(&sys);
595 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
596
597 wc.sec = boot.tv_sec;
598 wc.nsec = boot.tv_nsec;
599 wc.version = version;
18068523
GOC		 600
601 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
602
603 version++;
604 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 605}
606
50d0a0f9
GH		 607static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
608{
609 uint32_t quotient, remainder;
610
611 /* Don't try to replace with do_div(), this one calculates
612 * "(dividend << 32) / divisor" */
613 __asm__ ( "divl %4"
614 : "=a" (quotient), "=d" (remainder)
615 : "0" (0), "1" (dividend), "r" (divisor) );
616 return quotient;
617}
618
619static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
620{
621 uint64_t nsecs = 1000000000LL;
622 int32_t shift = 0;
623 uint64_t tps64;
624 uint32_t tps32;
625
626 tps64 = tsc_khz * 1000LL;
627 while (tps64 > nsecs*2) {
628 tps64 >>= 1;
629 shift--;
630 }
631
632 tps32 = (uint32_t)tps64;
633 while (tps32 <= (uint32_t)nsecs) {
634 tps32 <<= 1;
635 shift++;
636 }
637
638 hv_clock->tsc_shift = shift;
639 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
640
641 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 642 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 643 hv_clock->tsc_to_system_mul);
644}
645
c8076604
GH		 646static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
647
18068523
GOC		 648static void kvm_write_guest_time(struct kvm_vcpu *v)
649{
650 struct timespec ts;
651 unsigned long flags;
652 struct kvm_vcpu_arch *vcpu = &v->arch;
653 void *shared_kaddr;
463656c0 654 unsigned long this_tsc_khz;
18068523
GOC		 655
656 if ((!vcpu->time_page))
657 return;
658
463656c0
AK		 659 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
660 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
661 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
662 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 663 }
463656c0 664 put_cpu_var(cpu_tsc_khz);
50d0a0f9 665
18068523
GOC		 666 /* Keep irq disabled to prevent changes to the clock */
667 local_irq_save(flags);
af24a4e4 668 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 669 ktime_get_ts(&ts);
670 local_irq_restore(flags);
671
672 /* With all the info we got, fill in the values */
673
674 vcpu->hv_clock.system_time = ts.tv_nsec +
675 (NSEC_PER_SEC * (u64)ts.tv_sec);
676 /*
677 * The interface expects us to write an even number signaling that the
678 * update is finished. Since the guest won't see the intermediate
50d0a0f9 679 * state, we just increase by 2 at the end.
18068523 680 */
50d0a0f9 681 vcpu->hv_clock.version += 2;
18068523
GOC		 682
683 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
684
685 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 686 sizeof(vcpu->hv_clock));
18068523
GOC		 687
688 kunmap_atomic(shared_kaddr, KM_USER0);
689
690 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
691}
692
c8076604
GH		 693static int kvm_request_guest_time_update(struct kvm_vcpu *v)
694{
695 struct kvm_vcpu_arch *vcpu = &v->arch;
696
697 if (!vcpu->time_page)
698 return 0;
699 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
700 return 1;
701}
702
9ba075a6
AK		 703static bool msr_mtrr_valid(unsigned msr)
704{
705 switch (msr) {
706 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
707 case MSR_MTRRfix64K_00000:
708 case MSR_MTRRfix16K_80000:
709 case MSR_MTRRfix16K_A0000:
710 case MSR_MTRRfix4K_C0000:
711 case MSR_MTRRfix4K_C8000:
712 case MSR_MTRRfix4K_D0000:
713 case MSR_MTRRfix4K_D8000:
714 case MSR_MTRRfix4K_E0000:
715 case MSR_MTRRfix4K_E8000:
716 case MSR_MTRRfix4K_F0000:
717 case MSR_MTRRfix4K_F8000:
718 case MSR_MTRRdefType:
719 case MSR_IA32_CR_PAT:
720 return true;
721 case 0x2f8:
722 return true;
723 }
724 return false;
725}
726
d6289b93
MT		 727static bool valid_pat_type(unsigned t)
728{
729 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
730}
731
732static bool valid_mtrr_type(unsigned t)
733{
734 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
735}
736
737static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
738{
739 int i;
740
741 if (!msr_mtrr_valid(msr))
742 return false;
743
744 if (msr == MSR_IA32_CR_PAT) {
745 for (i = 0; i < 8; i++)
746 if (!valid_pat_type((data >> (i * 8)) & 0xff))
747 return false;
748 return true;
749 } else if (msr == MSR_MTRRdefType) {
750 if (data & ~0xcff)
751 return false;
752 return valid_mtrr_type(data & 0xff);
753 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
754 for (i = 0; i < 8 ; i++)
755 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
756 return false;
757 return true;
758 }
759
760 /* variable MTRRs */
761 return valid_mtrr_type(data & 0xff);
762}
763
9ba075a6
AK		 764static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
765{
0bed3b56
SY		 766 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
767
d6289b93 768 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 769 return 1;
770
0bed3b56
SY		 771 if (msr == MSR_MTRRdefType) {
772 vcpu->arch.mtrr_state.def_type = data;
773 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
774 } else if (msr == MSR_MTRRfix64K_00000)
775 p[0] = data;
776 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
777 p[1 + msr - MSR_MTRRfix16K_80000] = data;
778 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
779 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
780 else if (msr == MSR_IA32_CR_PAT)
781 vcpu->arch.pat = data;
782 else { /* Variable MTRRs */
783 int idx, is_mtrr_mask;
784 u64 *pt;
785
786 idx = (msr - 0x200) / 2;
787 is_mtrr_mask = msr - 0x200 - 2 * idx;
788 if (!is_mtrr_mask)
789 pt =
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
791 else
792 pt =
793 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
794 *pt = data;
795 }
796
797 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 798 return 0;
799}
15c4a640 800
890ca9ae 801static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 802{
890ca9ae
HY		 803 u64 mcg_cap = vcpu->arch.mcg_cap;
804 unsigned bank_num = mcg_cap & 0xff;
805
15c4a640 806 switch (msr) {
15c4a640 807 case MSR_IA32_MCG_STATUS:
890ca9ae 808 vcpu->arch.mcg_status = data;
15c4a640 809 break;
c7ac679c 810 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 811 if (!(mcg_cap & MCG_CTL_P))
812 return 1;
813 if (data != 0 && data != ~(u64)0)
814 return -1;
815 vcpu->arch.mcg_ctl = data;
816 break;
817 default:
818 if (msr >= MSR_IA32_MC0_CTL &&
819 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
820 u32 offset = msr - MSR_IA32_MC0_CTL;
821 /* only 0 or all 1s can be written to IA32_MCi_CTL */
822 if ((offset & 0x3) == 0 &&
823 data != 0 && data != ~(u64)0)
824 return -1;
825 vcpu->arch.mce_banks[offset] = data;
826 break;
827 }
828 return 1;
829 }
830 return 0;
831}
832
833int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
834{
835 switch (msr) {
836 case MSR_EFER:
837 set_efer(vcpu, data);
c7ac679c 838 break;
8f1589d9
AP		 839 case MSR_K7_HWCR:
840 data &= ~(u64)0x40; /* ignore flush filter disable */
841 if (data != 0) {
842 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
843 data);
844 return 1;
845 }
846 break;
c323c0e5
AP		 847 case MSR_AMD64_NB_CFG:
848 break;
b5e2fec0
AG		 849 case MSR_IA32_DEBUGCTLMSR:
850 if (!data) {
851 /* We support the non-activated case already */
852 break;
853 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
854 /* Values other than LBR and BTF are vendor-specific,
855 thus reserved and should throw a #GP */
856 return 1;
857 }
858 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
859 __func__, data);
860 break;
15c4a640
CO		 861 case MSR_IA32_UCODE_REV:
862 case MSR_IA32_UCODE_WRITE:
61a6bd67 863 case MSR_VM_HSAVE_PA:
6098ca93 864 case MSR_AMD64_PATCH_LOADER:
15c4a640 865 break;
9ba075a6
AK		 866 case 0x200 ... 0x2ff:
867 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 868 case MSR_IA32_APICBASE:
869 kvm_set_apic_base(vcpu, data);
870 break;
0105d1a5
GN		 871 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
872 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 873 case MSR_IA32_MISC_ENABLE:
ad312c7c 874 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 875 break;
18068523
GOC		 876 case MSR_KVM_WALL_CLOCK:
877 vcpu->kvm->arch.wall_clock = data;
878 kvm_write_wall_clock(vcpu->kvm, data);
879 break;
880 case MSR_KVM_SYSTEM_TIME: {
881 if (vcpu->arch.time_page) {
882 kvm_release_page_dirty(vcpu->arch.time_page);
883 vcpu->arch.time_page = NULL;
884 }
885
886 vcpu->arch.time = data;
887
888 /* we verify if the enable bit is set... */
889 if (!(data & 1))
890 break;
891
892 /* ...but clean it before doing the actual write */
893 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
894
18068523
GOC		 895 vcpu->arch.time_page =
896 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 897
898 if (is_error_page(vcpu->arch.time_page)) {
899 kvm_release_page_clean(vcpu->arch.time_page);
900 vcpu->arch.time_page = NULL;
901 }
902
c8076604 903 kvm_request_guest_time_update(vcpu);
18068523
GOC		 904 break;
905 }
890ca9ae
HY		 906 case MSR_IA32_MCG_CTL:
907 case MSR_IA32_MCG_STATUS:
908 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
909 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 910
911 /* Performance counters are not protected by a CPUID bit,
912 * so we should check all of them in the generic path for the sake of
913 * cross vendor migration.
914 * Writing a zero into the event select MSRs disables them,
915 * which we perfectly emulate ;-). Any other value should be at least
916 * reported, some guests depend on them.
917 */
918 case MSR_P6_EVNTSEL0:
919 case MSR_P6_EVNTSEL1:
920 case MSR_K7_EVNTSEL0:
921 case MSR_K7_EVNTSEL1:
922 case MSR_K7_EVNTSEL2:
923 case MSR_K7_EVNTSEL3:
924 if (data != 0)
925 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
926 "0x%x data 0x%llx\n", msr, data);
927 break;
928 /* at least RHEL 4 unconditionally writes to the perfctr registers,
929 * so we ignore writes to make it happy.
930 */
931 case MSR_P6_PERFCTR0:
932 case MSR_P6_PERFCTR1:
933 case MSR_K7_PERFCTR0:
934 case MSR_K7_PERFCTR1:
935 case MSR_K7_PERFCTR2:
936 case MSR_K7_PERFCTR3:
937 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
938 "0x%x data 0x%llx\n", msr, data);
939 break;
15c4a640 940 default:
ed85c068
AP		 941 if (!ignore_msrs) {
942 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
943 msr, data);
944 return 1;
945 } else {
946 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
947 msr, data);
948 break;
949 }
15c4a640
CO		 950 }
951 return 0;
952}
953EXPORT_SYMBOL_GPL(kvm_set_msr_common);
954
955
956/*
957 * Reads an msr value (of 'msr_index') into 'pdata'.
958 * Returns 0 on success, non-0 otherwise.
959 * Assumes vcpu_load() was already called.
960 */
961int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
962{
963 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
964}
965
9ba075a6
AK		 966static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
967{
0bed3b56
SY		 968 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
969
9ba075a6
AK		 970 if (!msr_mtrr_valid(msr))
971 return 1;
972
0bed3b56
SY		 973 if (msr == MSR_MTRRdefType)
974 *pdata = vcpu->arch.mtrr_state.def_type +
975 (vcpu->arch.mtrr_state.enabled << 10);
976 else if (msr == MSR_MTRRfix64K_00000)
977 *pdata = p[0];
978 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
979 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
980 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
981 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
982 else if (msr == MSR_IA32_CR_PAT)
983 *pdata = vcpu->arch.pat;
984 else { /* Variable MTRRs */
985 int idx, is_mtrr_mask;
986 u64 *pt;
987
988 idx = (msr - 0x200) / 2;
989 is_mtrr_mask = msr - 0x200 - 2 * idx;
990 if (!is_mtrr_mask)
991 pt =
992 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
993 else
994 pt =
995 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
996 *pdata = *pt;
997 }
998
9ba075a6
AK		 999 return 0;
1000}
1001
890ca9ae 1002static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1003{
1004 u64 data;
890ca9ae
HY		 1005 u64 mcg_cap = vcpu->arch.mcg_cap;
1006 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1007
1008 switch (msr) {
15c4a640
CO		 1009 case MSR_IA32_P5_MC_ADDR:
1010 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1011 data = 0;
1012 break;
15c4a640 1013 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1014 data = vcpu->arch.mcg_cap;
1015 break;
c7ac679c 1016 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1017 if (!(mcg_cap & MCG_CTL_P))
1018 return 1;
1019 data = vcpu->arch.mcg_ctl;
1020 break;
1021 case MSR_IA32_MCG_STATUS:
1022 data = vcpu->arch.mcg_status;
1023 break;
1024 default:
1025 if (msr >= MSR_IA32_MC0_CTL &&
1026 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1027 u32 offset = msr - MSR_IA32_MC0_CTL;
1028 data = vcpu->arch.mce_banks[offset];
1029 break;
1030 }
1031 return 1;
1032 }
1033 *pdata = data;
1034 return 0;
1035}
1036
1037int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1038{
1039 u64 data;
1040
1041 switch (msr) {
890ca9ae 1042 case MSR_IA32_PLATFORM_ID:
15c4a640 1043 case MSR_IA32_UCODE_REV:
15c4a640 1044 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1045 case MSR_IA32_DEBUGCTLMSR:
1046 case MSR_IA32_LASTBRANCHFROMIP:
1047 case MSR_IA32_LASTBRANCHTOIP:
1048 case MSR_IA32_LASTINTFROMIP:
1049 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1050 case MSR_K8_SYSCFG:
1051 case MSR_K7_HWCR:
61a6bd67 1052 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1053 case MSR_P6_EVNTSEL0:
1054 case MSR_P6_EVNTSEL1:
9e699624 1055 case MSR_K7_EVNTSEL0:
1fdbd48c 1056 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1057 case MSR_AMD64_NB_CFG:
15c4a640
CO		 1058 data = 0;
1059 break;
9ba075a6
AK		 1060 case MSR_MTRRcap:
1061 data = 0x500 | KVM_NR_VAR_MTRR;
1062 break;
1063 case 0x200 ... 0x2ff:
1064 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1065 case 0xcd: /* fsb frequency */
1066 data = 3;
1067 break;
1068 case MSR_IA32_APICBASE:
1069 data = kvm_get_apic_base(vcpu);
1070 break;
0105d1a5
GN		 1071 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1072 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1073 break;
15c4a640 1074 case MSR_IA32_MISC_ENABLE:
ad312c7c 1075 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1076 break;
847f0ad8
AG		 1077 case MSR_IA32_PERF_STATUS:
1078 /* TSC increment by tick */
1079 data = 1000ULL;
1080 /* CPU multiplier */
1081 data |= (((uint64_t)4ULL) << 40);
1082 break;
15c4a640 1083 case MSR_EFER:
ad312c7c 1084 data = vcpu->arch.shadow_efer;
15c4a640 1085 break;
18068523
GOC		 1086 case MSR_KVM_WALL_CLOCK:
1087 data = vcpu->kvm->arch.wall_clock;
1088 break;
1089 case MSR_KVM_SYSTEM_TIME:
1090 data = vcpu->arch.time;
1091 break;
890ca9ae
HY		 1092 case MSR_IA32_P5_MC_ADDR:
1093 case MSR_IA32_P5_MC_TYPE:
1094 case MSR_IA32_MCG_CAP:
1095 case MSR_IA32_MCG_CTL:
1096 case MSR_IA32_MCG_STATUS:
1097 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1098 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1099 default:
ed85c068
AP		 1100 if (!ignore_msrs) {
1101 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1102 return 1;
1103 } else {
1104 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1105 data = 0;
1106 }
1107 break;
15c4a640
CO		 1108 }
1109 *pdata = data;
1110 return 0;
1111}
1112EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1113
313a3dc7
CO		 1114/*
1115 * Read or write a bunch of msrs. All parameters are kernel addresses.
1116 *
1117 * @return number of msrs set successfully.
1118 */
1119static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1120 struct kvm_msr_entry *entries,
1121 int (*do_msr)(struct kvm_vcpu *vcpu,
1122 unsigned index, u64 *data))
1123{
1124 int i;
1125
1126 vcpu_load(vcpu);
1127
3200f405 1128 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1129 for (i = 0; i < msrs->nmsrs; ++i)
1130 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1131 break;
3200f405 1132 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1133
1134 vcpu_put(vcpu);
1135
1136 return i;
1137}
1138
1139/*
1140 * Read or write a bunch of msrs. Parameters are user addresses.
1141 *
1142 * @return number of msrs set successfully.
1143 */
1144static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1145 int (*do_msr)(struct kvm_vcpu *vcpu,
1146 unsigned index, u64 *data),
1147 int writeback)
1148{
1149 struct kvm_msrs msrs;
1150 struct kvm_msr_entry *entries;
1151 int r, n;
1152 unsigned size;
1153
1154 r = -EFAULT;
1155 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1156 goto out;
1157
1158 r = -E2BIG;
1159 if (msrs.nmsrs >= MAX_IO_MSRS)
1160 goto out;
1161
1162 r = -ENOMEM;
1163 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1164 entries = vmalloc(size);
1165 if (!entries)
1166 goto out;
1167
1168 r = -EFAULT;
1169 if (copy_from_user(entries, user_msrs->entries, size))
1170 goto out_free;
1171
1172 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1173 if (r < 0)
1174 goto out_free;
1175
1176 r = -EFAULT;
1177 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1178 goto out_free;
1179
1180 r = n;
1181
1182out_free:
1183 vfree(entries);
1184out:
1185 return r;
1186}
1187
018d00d2
ZX		 1188int kvm_dev_ioctl_check_extension(long ext)
1189{
1190 int r;
1191
1192 switch (ext) {
1193 case KVM_CAP_IRQCHIP:
1194 case KVM_CAP_HLT:
1195 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1196 case KVM_CAP_SET_TSS_ADDR:
07716717 1197 case KVM_CAP_EXT_CPUID:
c8076604 1198 case KVM_CAP_CLOCKSOURCE:
7837699f 1199 case KVM_CAP_PIT:
a28e4f5a 1200 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1201 case KVM_CAP_MP_STATE:
ed848624 1202 case KVM_CAP_SYNC_MMU:
52d939a0 1203 case KVM_CAP_REINJECT_CONTROL:
4925663a 1204 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1205 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1206 case KVM_CAP_IRQFD:
c5ff41ce 1207 case KVM_CAP_PIT2:
018d00d2
ZX		 1208 r = 1;
1209 break;
542472b5
LV		 1210 case KVM_CAP_COALESCED_MMIO:
1211 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1212 break;
774ead3a
AK		 1213 case KVM_CAP_VAPIC:
1214 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1215 break;
f725230a
AK		 1216 case KVM_CAP_NR_VCPUS:
1217 r = KVM_MAX_VCPUS;
1218 break;
a988b910
AK		 1219 case KVM_CAP_NR_MEMSLOTS:
1220 r = KVM_MEMORY_SLOTS;
1221 break;
2f333bcb
MT		 1222 case KVM_CAP_PV_MMU:
1223 r = !tdp_enabled;
1224 break;
62c476c7 1225 case KVM_CAP_IOMMU:
19de40a8 1226 r = iommu_found();
62c476c7 1227 break;
890ca9ae
HY		 1228 case KVM_CAP_MCE:
1229 r = KVM_MAX_MCE_BANKS;
1230 break;
018d00d2
ZX		 1231 default:
1232 r = 0;
1233 break;
1234 }
1235 return r;
1236
1237}
1238
043405e1
CO		 1239long kvm_arch_dev_ioctl(struct file *filp,
1240 unsigned int ioctl, unsigned long arg)
1241{
1242 void __user *argp = (void __user *)arg;
1243 long r;
1244
1245 switch (ioctl) {
1246 case KVM_GET_MSR_INDEX_LIST: {
1247 struct kvm_msr_list __user *user_msr_list = argp;
1248 struct kvm_msr_list msr_list;
1249 unsigned n;
1250
1251 r = -EFAULT;
1252 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1253 goto out;
1254 n = msr_list.nmsrs;
1255 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1256 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1257 goto out;
1258 r = -E2BIG;
e125e7b6 1259 if (n < msr_list.nmsrs)
043405e1
CO		 1260 goto out;
1261 r = -EFAULT;
1262 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1263 num_msrs_to_save * sizeof(u32)))
1264 goto out;
e125e7b6 1265 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1266 &emulated_msrs,
1267 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1268 goto out;
1269 r = 0;
1270 break;
1271 }
674eea0f
AK		 1272 case KVM_GET_SUPPORTED_CPUID: {
1273 struct kvm_cpuid2 __user *cpuid_arg = argp;
1274 struct kvm_cpuid2 cpuid;
1275
1276 r = -EFAULT;
1277 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1278 goto out;
1279 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1280 cpuid_arg->entries);
674eea0f
AK		 1281 if (r)
1282 goto out;
1283
1284 r = -EFAULT;
1285 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1286 goto out;
1287 r = 0;
1288 break;
1289 }
890ca9ae
HY		 1290 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1291 u64 mce_cap;
1292
1293 mce_cap = KVM_MCE_CAP_SUPPORTED;
1294 r = -EFAULT;
1295 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1296 goto out;
1297 r = 0;
1298 break;
1299 }
043405e1
CO		 1300 default:
1301 r = -EINVAL;
1302 }
1303out:
1304 return r;
1305}
1306
313a3dc7
CO		 1307void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1308{
1309 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1310 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1311}
1312
1313void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1314{
1315 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1316 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1317}
1318
07716717 1319static int is_efer_nx(void)
313a3dc7 1320{
e286e86e 1321 unsigned long long efer = 0;
313a3dc7 1322
e286e86e 1323 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1324 return efer & EFER_NX;
1325}
1326
1327static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1328{
1329 int i;
1330 struct kvm_cpuid_entry2 *e, *entry;
1331
313a3dc7 1332 entry = NULL;
ad312c7c
ZX		 1333 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1334 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1335 if (e->function == 0x80000001) {
1336 entry = e;
1337 break;
1338 }
1339 }
07716717 1340 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1341 entry->edx &= ~(1 << 20);
1342 printk(KERN_INFO "kvm: guest NX capability removed\n");
1343 }
1344}
1345
07716717 1346/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1347static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1348 struct kvm_cpuid *cpuid,
1349 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1350{
1351 int r, i;
1352 struct kvm_cpuid_entry *cpuid_entries;
1353
1354 r = -E2BIG;
1355 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1356 goto out;
1357 r = -ENOMEM;
1358 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1359 if (!cpuid_entries)
1360 goto out;
1361 r = -EFAULT;
1362 if (copy_from_user(cpuid_entries, entries,
1363 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1364 goto out_free;
1365 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1366 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1367 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1368 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1369 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1370 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1371 vcpu->arch.cpuid_entries[i].index = 0;
1372 vcpu->arch.cpuid_entries[i].flags = 0;
1373 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1374 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1375 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1376 }
1377 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1378 cpuid_fix_nx_cap(vcpu);
1379 r = 0;
fc61b800 1380 kvm_apic_set_version(vcpu);
07716717
DK		 1381
1382out_free:
1383 vfree(cpuid_entries);
1384out:
1385 return r;
1386}
1387
1388static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1389 struct kvm_cpuid2 *cpuid,
1390 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1391{
1392 int r;
1393
1394 r = -E2BIG;
1395 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1396 goto out;
1397 r = -EFAULT;
ad312c7c 1398 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1399 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1400 goto out;
ad312c7c 1401 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1402 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1403 return 0;
1404
1405out:
1406 return r;
1407}
1408
07716717 1409static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1410 struct kvm_cpuid2 *cpuid,
1411 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1412{
1413 int r;
1414
1415 r = -E2BIG;
ad312c7c 1416 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1417 goto out;
1418 r = -EFAULT;
ad312c7c 1419 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1420 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1421 goto out;
1422 return 0;
1423
1424out:
ad312c7c 1425 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1426 return r;
1427}
1428
07716717 1429static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1430 u32 index)
07716717
DK		 1431{
1432 entry->function = function;
1433 entry->index = index;
1434 cpuid_count(entry->function, entry->index,
19355475 1435 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1436 entry->flags = 0;
1437}
1438
7faa4ee1
AK		 1439#define F(x) bit(X86_FEATURE_##x)
1440
07716717
DK		 1441static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1442 u32 index, int *nent, int maxnent)
1443{
7faa4ee1 1444 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1445#ifdef CONFIG_X86_64
7faa4ee1
AK		 1446 unsigned f_lm = F(LM);
1447#else
1448 unsigned f_lm = 0;
07716717 1449#endif
7faa4ee1
AK		 1450
1451 /* cpuid 1.edx */
1452 const u32 kvm_supported_word0_x86_features =
1453 F(FPU) | F(VME) | F(DE) | F(PSE) |
1454 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1455 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1456 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1457 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1458 0 /* Reserved, DS, ACPI */ | F(MMX) |
1459 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1460 0 /* HTT, TM, Reserved, PBE */;
1461 /* cpuid 0x80000001.edx */
1462 const u32 kvm_supported_word1_x86_features =
1463 F(FPU) | F(VME) | F(DE) | F(PSE) |
1464 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1465 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1466 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1467 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1468 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1469 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1470 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1471 /* cpuid 1.ecx */
1472 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1473 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1474 0 /* DS-CPL, VMX, SMX, EST */ |
1475 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1476 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1477 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1478 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1479 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1480 /* cpuid 0x80000001.ecx */
07716717 1481 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1482 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1483 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1484 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1485 0 /* SKINIT */ | 0 /* WDT */;
07716717 1486
19355475 1487 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1488 get_cpu();
1489 do_cpuid_1_ent(entry, function, index);
1490 ++*nent;
1491
1492 switch (function) {
1493 case 0:
1494 entry->eax = min(entry->eax, (u32)0xb);
1495 break;
1496 case 1:
1497 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1498 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1499 break;
1500 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1501 * may return different values. This forces us to get_cpu() before
1502 * issuing the first command, and also to emulate this annoying behavior
1503 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1504 case 2: {
1505 int t, times = entry->eax & 0xff;
1506
1507 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1508 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1509 for (t = 1; t < times && *nent < maxnent; ++t) {
1510 do_cpuid_1_ent(&entry[t], function, 0);
1511 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1512 ++*nent;
1513 }
1514 break;
1515 }
1516 /* function 4 and 0xb have additional index. */
1517 case 4: {
14af3f3c 1518 int i, cache_type;
07716717
DK		 1519
1520 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1521 /* read more entries until cache_type is zero */
14af3f3c
HH		 1522 for (i = 1; *nent < maxnent; ++i) {
1523 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1524 if (!cache_type)
1525 break;
14af3f3c
HH		 1526 do_cpuid_1_ent(&entry[i], function, i);
1527 entry[i].flags |=
07716717
DK		 1528 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1529 ++*nent;
1530 }
1531 break;
1532 }
1533 case 0xb: {
14af3f3c 1534 int i, level_type;
07716717
DK		 1535
1536 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1537 /* read more entries until level_type is zero */
14af3f3c 1538 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1539 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1540 if (!level_type)
1541 break;
14af3f3c
HH		 1542 do_cpuid_1_ent(&entry[i], function, i);
1543 entry[i].flags |=
07716717
DK		 1544 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1545 ++*nent;
1546 }
1547 break;
1548 }
1549 case 0x80000000:
1550 entry->eax = min(entry->eax, 0x8000001a);
1551 break;
1552 case 0x80000001:
1553 entry->edx &= kvm_supported_word1_x86_features;
1554 entry->ecx &= kvm_supported_word6_x86_features;
1555 break;
1556 }
1557 put_cpu();
1558}
1559
7faa4ee1
AK		 1560#undef F
1561
674eea0f 1562static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1563 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1564{
1565 struct kvm_cpuid_entry2 *cpuid_entries;
1566 int limit, nent = 0, r = -E2BIG;
1567 u32 func;
1568
1569 if (cpuid->nent < 1)
1570 goto out;
1571 r = -ENOMEM;
1572 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1573 if (!cpuid_entries)
1574 goto out;
1575
1576 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1577 limit = cpuid_entries[0].eax;
1578 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1579 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1580 &nent, cpuid->nent);
07716717
DK		 1581 r = -E2BIG;
1582 if (nent >= cpuid->nent)
1583 goto out_free;
1584
1585 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1586 limit = cpuid_entries[nent - 1].eax;
1587 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1588 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1589 &nent, cpuid->nent);
cb007648
MM		 1590 r = -E2BIG;
1591 if (nent >= cpuid->nent)
1592 goto out_free;
1593
07716717
DK		 1594 r = -EFAULT;
1595 if (copy_to_user(entries, cpuid_entries,
19355475 1596 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1597 goto out_free;
1598 cpuid->nent = nent;
1599 r = 0;
1600
1601out_free:
1602 vfree(cpuid_entries);
1603out:
1604 return r;
1605}
1606
313a3dc7
CO		 1607static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1608 struct kvm_lapic_state *s)
1609{
1610 vcpu_load(vcpu);
ad312c7c 1611 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1612 vcpu_put(vcpu);
1613
1614 return 0;
1615}
1616
1617static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1618 struct kvm_lapic_state *s)
1619{
1620 vcpu_load(vcpu);
ad312c7c 1621 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1622 kvm_apic_post_state_restore(vcpu);
1623 vcpu_put(vcpu);
1624
1625 return 0;
1626}
1627
f77bc6a4
ZX		 1628static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1629 struct kvm_interrupt *irq)
1630{
1631 if (irq->irq < 0 || irq->irq >= 256)
1632 return -EINVAL;
1633 if (irqchip_in_kernel(vcpu->kvm))
1634 return -ENXIO;
1635 vcpu_load(vcpu);
1636
66fd3f7f 1637 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1638
1639 vcpu_put(vcpu);
1640
1641 return 0;
1642}
1643
c4abb7c9
JK		 1644static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1645{
1646 vcpu_load(vcpu);
1647 kvm_inject_nmi(vcpu);
1648 vcpu_put(vcpu);
1649
1650 return 0;
1651}
1652
b209749f
AK		 1653static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1654 struct kvm_tpr_access_ctl *tac)
1655{
1656 if (tac->flags)
1657 return -EINVAL;
1658 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1659 return 0;
1660}
1661
890ca9ae
HY		 1662static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1663 u64 mcg_cap)
1664{
1665 int r;
1666 unsigned bank_num = mcg_cap & 0xff, bank;
1667
1668 r = -EINVAL;
1669 if (!bank_num)
1670 goto out;
1671 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1672 goto out;
1673 r = 0;
1674 vcpu->arch.mcg_cap = mcg_cap;
1675 /* Init IA32_MCG_CTL to all 1s */
1676 if (mcg_cap & MCG_CTL_P)
1677 vcpu->arch.mcg_ctl = ~(u64)0;
1678 /* Init IA32_MCi_CTL to all 1s */
1679 for (bank = 0; bank < bank_num; bank++)
1680 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1681out:
1682 return r;
1683}
1684
1685static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1686 struct kvm_x86_mce *mce)
1687{
1688 u64 mcg_cap = vcpu->arch.mcg_cap;
1689 unsigned bank_num = mcg_cap & 0xff;
1690 u64 *banks = vcpu->arch.mce_banks;
1691
1692 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1693 return -EINVAL;
1694 /*
1695 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1696 * reporting is disabled
1697 */
1698 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1699 vcpu->arch.mcg_ctl != ~(u64)0)
1700 return 0;
1701 banks += 4 * mce->bank;
1702 /*
1703 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1704 * reporting is disabled for the bank
1705 */
1706 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1707 return 0;
1708 if (mce->status & MCI_STATUS_UC) {
1709 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1710 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1711 printk(KERN_DEBUG "kvm: set_mce: "
1712 "injects mce exception while "
1713 "previous one is in progress!\n");
1714 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1715 return 0;
1716 }
1717 if (banks[1] & MCI_STATUS_VAL)
1718 mce->status |= MCI_STATUS_OVER;
1719 banks[2] = mce->addr;
1720 banks[3] = mce->misc;
1721 vcpu->arch.mcg_status = mce->mcg_status;
1722 banks[1] = mce->status;
1723 kvm_queue_exception(vcpu, MC_VECTOR);
1724 } else if (!(banks[1] & MCI_STATUS_VAL)
1725 || !(banks[1] & MCI_STATUS_UC)) {
1726 if (banks[1] & MCI_STATUS_VAL)
1727 mce->status |= MCI_STATUS_OVER;
1728 banks[2] = mce->addr;
1729 banks[3] = mce->misc;
1730 banks[1] = mce->status;
1731 } else
1732 banks[1] |= MCI_STATUS_OVER;
1733 return 0;
1734}
1735
313a3dc7
CO		 1736long kvm_arch_vcpu_ioctl(struct file *filp,
1737 unsigned int ioctl, unsigned long arg)
1738{
1739 struct kvm_vcpu *vcpu = filp->private_data;
1740 void __user *argp = (void __user *)arg;
1741 int r;
b772ff36 1742 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1743
1744 switch (ioctl) {
1745 case KVM_GET_LAPIC: {
b772ff36 1746 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1747
b772ff36
DH		 1748 r = -ENOMEM;
1749 if (!lapic)
1750 goto out;
1751 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1752 if (r)
1753 goto out;
1754 r = -EFAULT;
b772ff36 1755 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1756 goto out;
1757 r = 0;
1758 break;
1759 }
1760 case KVM_SET_LAPIC: {
b772ff36
DH		 1761 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1762 r = -ENOMEM;
1763 if (!lapic)
1764 goto out;
313a3dc7 1765 r = -EFAULT;
b772ff36 1766 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1767 goto out;
b772ff36 1768 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1769 if (r)
1770 goto out;
1771 r = 0;
1772 break;
1773 }
f77bc6a4
ZX		 1774 case KVM_INTERRUPT: {
1775 struct kvm_interrupt irq;
1776
1777 r = -EFAULT;
1778 if (copy_from_user(&irq, argp, sizeof irq))
1779 goto out;
1780 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1781 if (r)
1782 goto out;
1783 r = 0;
1784 break;
1785 }
c4abb7c9
JK		 1786 case KVM_NMI: {
1787 r = kvm_vcpu_ioctl_nmi(vcpu);
1788 if (r)
1789 goto out;
1790 r = 0;
1791 break;
1792 }
313a3dc7
CO		 1793 case KVM_SET_CPUID: {
1794 struct kvm_cpuid __user *cpuid_arg = argp;
1795 struct kvm_cpuid cpuid;
1796
1797 r = -EFAULT;
1798 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1799 goto out;
1800 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1801 if (r)
1802 goto out;
1803 break;
1804 }
07716717
DK		 1805 case KVM_SET_CPUID2: {
1806 struct kvm_cpuid2 __user *cpuid_arg = argp;
1807 struct kvm_cpuid2 cpuid;
1808
1809 r = -EFAULT;
1810 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1811 goto out;
1812 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1813 cpuid_arg->entries);
07716717
DK		 1814 if (r)
1815 goto out;
1816 break;
1817 }
1818 case KVM_GET_CPUID2: {
1819 struct kvm_cpuid2 __user *cpuid_arg = argp;
1820 struct kvm_cpuid2 cpuid;
1821
1822 r = -EFAULT;
1823 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1824 goto out;
1825 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1826 cpuid_arg->entries);
07716717
DK		 1827 if (r)
1828 goto out;
1829 r = -EFAULT;
1830 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1831 goto out;
1832 r = 0;
1833 break;
1834 }
313a3dc7
CO		 1835 case KVM_GET_MSRS:
1836 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1837 break;
1838 case KVM_SET_MSRS:
1839 r = msr_io(vcpu, argp, do_set_msr, 0);
1840 break;
b209749f
AK		 1841 case KVM_TPR_ACCESS_REPORTING: {
1842 struct kvm_tpr_access_ctl tac;
1843
1844 r = -EFAULT;
1845 if (copy_from_user(&tac, argp, sizeof tac))
1846 goto out;
1847 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1848 if (r)
1849 goto out;
1850 r = -EFAULT;
1851 if (copy_to_user(argp, &tac, sizeof tac))
1852 goto out;
1853 r = 0;
1854 break;
1855 };
b93463aa
AK		 1856 case KVM_SET_VAPIC_ADDR: {
1857 struct kvm_vapic_addr va;
1858
1859 r = -EINVAL;
1860 if (!irqchip_in_kernel(vcpu->kvm))
1861 goto out;
1862 r = -EFAULT;
1863 if (copy_from_user(&va, argp, sizeof va))
1864 goto out;
1865 r = 0;
1866 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1867 break;
1868 }
890ca9ae
HY		 1869 case KVM_X86_SETUP_MCE: {
1870 u64 mcg_cap;
1871
1872 r = -EFAULT;
1873 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1874 goto out;
1875 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1876 break;
1877 }
1878 case KVM_X86_SET_MCE: {
1879 struct kvm_x86_mce mce;
1880
1881 r = -EFAULT;
1882 if (copy_from_user(&mce, argp, sizeof mce))
1883 goto out;
1884 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1885 break;
1886 }
313a3dc7
CO		 1887 default:
1888 r = -EINVAL;
1889 }
1890out:
7a6ce84c 1891 kfree(lapic);
313a3dc7
CO		 1892 return r;
1893}
1894
1fe779f8
CO		 1895static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1896{
1897 int ret;
1898
1899 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1900 return -1;
1901 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1902 return ret;
1903}
1904
1905static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1906 u32 kvm_nr_mmu_pages)
1907{
1908 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1909 return -EINVAL;
1910
72dc67a6 1911 down_write(&kvm->slots_lock);
7c8a83b7 1912 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1913
1914 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1915 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1916
7c8a83b7 1917 spin_unlock(&kvm->mmu_lock);
72dc67a6 1918 up_write(&kvm->slots_lock);
1fe779f8
CO		 1919 return 0;
1920}
1921
1922static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1923{
f05e70ac 1924 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1925}
1926
e9f85cde
ZX		 1927gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1928{
1929 int i;
1930 struct kvm_mem_alias *alias;
1931
d69fb81f
ZX		 1932 for (i = 0; i < kvm->arch.naliases; ++i) {
1933 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1934 if (gfn >= alias->base_gfn
1935 && gfn < alias->base_gfn + alias->npages)
1936 return alias->target_gfn + gfn - alias->base_gfn;
1937 }
1938 return gfn;
1939}
1940
1fe779f8
CO		 1941/*
1942 * Set a new alias region. Aliases map a portion of physical memory into
1943 * another portion. This is useful for memory windows, for example the PC
1944 * VGA region.
1945 */
1946static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1947 struct kvm_memory_alias *alias)
1948{
1949 int r, n;
1950 struct kvm_mem_alias *p;
1951
1952 r = -EINVAL;
1953 /* General sanity checks */
1954 if (alias->memory_size & (PAGE_SIZE - 1))
1955 goto out;
1956 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1957 goto out;
1958 if (alias->slot >= KVM_ALIAS_SLOTS)
1959 goto out;
1960 if (alias->guest_phys_addr + alias->memory_size
1961 < alias->guest_phys_addr)
1962 goto out;
1963 if (alias->target_phys_addr + alias->memory_size
1964 < alias->target_phys_addr)
1965 goto out;
1966
72dc67a6 1967 down_write(&kvm->slots_lock);
a1708ce8 1968 spin_lock(&kvm->mmu_lock);
1fe779f8 1969
d69fb81f 1970 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1971 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1972 p->npages = alias->memory_size >> PAGE_SHIFT;
1973 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1974
1975 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1976 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1977 break;
d69fb81f 1978 kvm->arch.naliases = n;
1fe779f8 1979
a1708ce8 1980 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1981 kvm_mmu_zap_all(kvm);
1982
72dc67a6 1983 up_write(&kvm->slots_lock);
1fe779f8
CO		 1984
1985 return 0;
1986
1987out:
1988 return r;
1989}
1990
1991static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1992{
1993 int r;
1994
1995 r = 0;
1996 switch (chip->chip_id) {
1997 case KVM_IRQCHIP_PIC_MASTER:
1998 memcpy(&chip->chip.pic,
1999 &pic_irqchip(kvm)->pics[0],
2000 sizeof(struct kvm_pic_state));
2001 break;
2002 case KVM_IRQCHIP_PIC_SLAVE:
2003 memcpy(&chip->chip.pic,
2004 &pic_irqchip(kvm)->pics[1],
2005 sizeof(struct kvm_pic_state));
2006 break;
2007 case KVM_IRQCHIP_IOAPIC:
2008 memcpy(&chip->chip.ioapic,
2009 ioapic_irqchip(kvm),
2010 sizeof(struct kvm_ioapic_state));
2011 break;
2012 default:
2013 r = -EINVAL;
2014 break;
2015 }
2016 return r;
2017}
2018
2019static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2020{
2021 int r;
2022
2023 r = 0;
2024 switch (chip->chip_id) {
2025 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2026 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2027 memcpy(&pic_irqchip(kvm)->pics[0],
2028 &chip->chip.pic,
2029 sizeof(struct kvm_pic_state));
894a9c55 2030 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2031 break;
2032 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2033 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2034 memcpy(&pic_irqchip(kvm)->pics[1],
2035 &chip->chip.pic,
2036 sizeof(struct kvm_pic_state));
894a9c55 2037 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2038 break;
2039 case KVM_IRQCHIP_IOAPIC:
894a9c55 2040 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2041 memcpy(ioapic_irqchip(kvm),
2042 &chip->chip.ioapic,
2043 sizeof(struct kvm_ioapic_state));
894a9c55 2044 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2045 break;
2046 default:
2047 r = -EINVAL;
2048 break;
2049 }
2050 kvm_pic_update_irq(pic_irqchip(kvm));
2051 return r;
2052}
2053
e0f63cb9
SY		 2054static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2055{
2056 int r = 0;
2057
894a9c55 2058 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2059 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2060 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2061 return r;
2062}
2063
2064static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2065{
2066 int r = 0;
2067
894a9c55 2068 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2069 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2070 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
894a9c55 2071 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2072 return r;
2073}
2074
52d939a0
MT		 2075static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2076 struct kvm_reinject_control *control)
2077{
2078 if (!kvm->arch.vpit)
2079 return -ENXIO;
894a9c55 2080 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2081 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2082 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2083 return 0;
2084}
2085
5bb064dc
ZX		 2086/*
2087 * Get (and clear) the dirty memory log for a memory slot.
2088 */
2089int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2090 struct kvm_dirty_log *log)
2091{
2092 int r;
2093 int n;
2094 struct kvm_memory_slot *memslot;
2095 int is_dirty = 0;
2096
72dc67a6 2097 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2098
2099 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2100 if (r)
2101 goto out;
2102
2103 /* If nothing is dirty, don't bother messing with page tables. */
2104 if (is_dirty) {
7c8a83b7 2105 spin_lock(&kvm->mmu_lock);
5bb064dc 2106 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2107 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2108 kvm_flush_remote_tlbs(kvm);
2109 memslot = &kvm->memslots[log->slot];
2110 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2111 memset(memslot->dirty_bitmap, 0, n);
2112 }
2113 r = 0;
2114out:
72dc67a6 2115 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2116 return r;
2117}
2118
1fe779f8
CO		 2119long kvm_arch_vm_ioctl(struct file *filp,
2120 unsigned int ioctl, unsigned long arg)
2121{
2122 struct kvm *kvm = filp->private_data;
2123 void __user *argp = (void __user *)arg;
2124 int r = -EINVAL;
f0d66275
DH		 2125 /*
2126 * This union makes it completely explicit to gcc-3.x
2127 * that these two variables' stack usage should be
2128 * combined, not added together.
2129 */
2130 union {
2131 struct kvm_pit_state ps;
2132 struct kvm_memory_alias alias;
c5ff41ce 2133 struct kvm_pit_config pit_config;
f0d66275 2134 } u;
1fe779f8
CO		 2135
2136 switch (ioctl) {
2137 case KVM_SET_TSS_ADDR:
2138 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2139 if (r < 0)
2140 goto out;
2141 break;
2142 case KVM_SET_MEMORY_REGION: {
2143 struct kvm_memory_region kvm_mem;
2144 struct kvm_userspace_memory_region kvm_userspace_mem;
2145
2146 r = -EFAULT;
2147 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2148 goto out;
2149 kvm_userspace_mem.slot = kvm_mem.slot;
2150 kvm_userspace_mem.flags = kvm_mem.flags;
2151 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2152 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2153 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2154 if (r)
2155 goto out;
2156 break;
2157 }
2158 case KVM_SET_NR_MMU_PAGES:
2159 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2160 if (r)
2161 goto out;
2162 break;
2163 case KVM_GET_NR_MMU_PAGES:
2164 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2165 break;
f0d66275 2166 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2167 r = -EFAULT;
f0d66275 2168 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2169 goto out;
f0d66275 2170 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2171 if (r)
2172 goto out;
2173 break;
1fe779f8
CO		 2174 case KVM_CREATE_IRQCHIP:
2175 r = -ENOMEM;
d7deeeb0
ZX		 2176 kvm->arch.vpic = kvm_create_pic(kvm);
2177 if (kvm->arch.vpic) {
1fe779f8
CO		 2178 r = kvm_ioapic_init(kvm);
2179 if (r) {
d7deeeb0
ZX		 2180 kfree(kvm->arch.vpic);
2181 kvm->arch.vpic = NULL;
1fe779f8
CO		 2182 goto out;
2183 }
2184 } else
2185 goto out;
399ec807
AK		 2186 r = kvm_setup_default_irq_routing(kvm);
2187 if (r) {
2188 kfree(kvm->arch.vpic);
2189 kfree(kvm->arch.vioapic);
2190 goto out;
2191 }
1fe779f8 2192 break;
7837699f 2193 case KVM_CREATE_PIT:
c5ff41ce
JK		 2194 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2195 goto create_pit;
2196 case KVM_CREATE_PIT2:
2197 r = -EFAULT;
2198 if (copy_from_user(&u.pit_config, argp,
2199 sizeof(struct kvm_pit_config)))
2200 goto out;
2201 create_pit:
108b5669 2202 down_write(&kvm->slots_lock);
269e05e4
AK		 2203 r = -EEXIST;
2204 if (kvm->arch.vpit)
2205 goto create_pit_unlock;
7837699f 2206 r = -ENOMEM;
c5ff41ce 2207 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2208 if (kvm->arch.vpit)
2209 r = 0;
269e05e4 2210 create_pit_unlock:
108b5669 2211 up_write(&kvm->slots_lock);
7837699f 2212 break;
4925663a 2213 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2214 case KVM_IRQ_LINE: {
2215 struct kvm_irq_level irq_event;
2216
2217 r = -EFAULT;
2218 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2219 goto out;
2220 if (irqchip_in_kernel(kvm)) {
4925663a 2221 __s32 status;
fa40a821 2222 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2223 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2224 irq_event.irq, irq_event.level);
fa40a821 2225 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2226 if (ioctl == KVM_IRQ_LINE_STATUS) {
2227 irq_event.status = status;
2228 if (copy_to_user(argp, &irq_event,
2229 sizeof irq_event))
2230 goto out;
2231 }
1fe779f8
CO		 2232 r = 0;
2233 }
2234 break;
2235 }
2236 case KVM_GET_IRQCHIP: {
2237 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2238 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2239
f0d66275
DH		 2240 r = -ENOMEM;
2241 if (!chip)
1fe779f8 2242 goto out;
f0d66275
DH		 2243 r = -EFAULT;
2244 if (copy_from_user(chip, argp, sizeof *chip))
2245 goto get_irqchip_out;
1fe779f8
CO		 2246 r = -ENXIO;
2247 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2248 goto get_irqchip_out;
2249 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2250 if (r)
f0d66275 2251 goto get_irqchip_out;
1fe779f8 2252 r = -EFAULT;
f0d66275
DH		 2253 if (copy_to_user(argp, chip, sizeof *chip))
2254 goto get_irqchip_out;
1fe779f8 2255 r = 0;
f0d66275
DH		 2256 get_irqchip_out:
2257 kfree(chip);
2258 if (r)
2259 goto out;
1fe779f8
CO		 2260 break;
2261 }
2262 case KVM_SET_IRQCHIP: {
2263 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2264 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2265
f0d66275
DH		 2266 r = -ENOMEM;
2267 if (!chip)
1fe779f8 2268 goto out;
f0d66275
DH		 2269 r = -EFAULT;
2270 if (copy_from_user(chip, argp, sizeof *chip))
2271 goto set_irqchip_out;
1fe779f8
CO		 2272 r = -ENXIO;
2273 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2274 goto set_irqchip_out;
2275 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2276 if (r)
f0d66275 2277 goto set_irqchip_out;
1fe779f8 2278 r = 0;
f0d66275
DH		 2279 set_irqchip_out:
2280 kfree(chip);
2281 if (r)
2282 goto out;
1fe779f8
CO		 2283 break;
2284 }
e0f63cb9 2285 case KVM_GET_PIT: {
e0f63cb9 2286 r = -EFAULT;
f0d66275 2287 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2288 goto out;
2289 r = -ENXIO;
2290 if (!kvm->arch.vpit)
2291 goto out;
f0d66275 2292 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2293 if (r)
2294 goto out;
2295 r = -EFAULT;
f0d66275 2296 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2297 goto out;
2298 r = 0;
2299 break;
2300 }
2301 case KVM_SET_PIT: {
e0f63cb9 2302 r = -EFAULT;
f0d66275 2303 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2304 goto out;
2305 r = -ENXIO;
2306 if (!kvm->arch.vpit)
2307 goto out;
f0d66275 2308 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2309 if (r)
2310 goto out;
2311 r = 0;
2312 break;
2313 }
52d939a0
MT		 2314 case KVM_REINJECT_CONTROL: {
2315 struct kvm_reinject_control control;
2316 r = -EFAULT;
2317 if (copy_from_user(&control, argp, sizeof(control)))
2318 goto out;
2319 r = kvm_vm_ioctl_reinject(kvm, &control);
2320 if (r)
2321 goto out;
2322 r = 0;
2323 break;
2324 }
1fe779f8
CO		 2325 default:
2326 ;
2327 }
2328out:
2329 return r;
2330}
2331
a16b043c 2332static void kvm_init_msr_list(void)
043405e1
CO		 2333{
2334 u32 dummy[2];
2335 unsigned i, j;
2336
2337 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2338 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2339 continue;
2340 if (j < i)
2341 msrs_to_save[j] = msrs_to_save[i];
2342 j++;
2343 }
2344 num_msrs_to_save = j;
2345}
2346
bda9020e
MT		 2347static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2348 const void *v)
bbd9b64e 2349{
bda9020e
MT		 2350 if (vcpu->arch.apic &&
2351 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2352 return 0;
bbd9b64e 2353
bda9020e 2354 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2355}
2356
bda9020e 2357static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2358{
bda9020e
MT		 2359 if (vcpu->arch.apic &&
2360 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2361 return 0;
bbd9b64e 2362
bda9020e 2363 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2364}
2365
cded19f3
HE		 2366static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2367 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2368{
2369 void *data = val;
10589a46 2370 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2371
2372 while (bytes) {
ad312c7c 2373 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2374 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2375 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2376 int ret;
2377
10589a46
MT		 2378 if (gpa == UNMAPPED_GVA) {
2379 r = X86EMUL_PROPAGATE_FAULT;
2380 goto out;
2381 }
77c2002e 2382 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2383 if (ret < 0) {
2384 r = X86EMUL_UNHANDLEABLE;
2385 goto out;
2386 }
bbd9b64e 2387
77c2002e
IE		 2388 bytes -= toread;
2389 data += toread;
2390 addr += toread;
bbd9b64e 2391 }
10589a46 2392out:
10589a46 2393 return r;
bbd9b64e 2394}
77c2002e 2395
cded19f3
HE		 2396static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2397 struct kvm_vcpu *vcpu)
77c2002e
IE		 2398{
2399 void *data = val;
2400 int r = X86EMUL_CONTINUE;
2401
2402 while (bytes) {
2403 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2404 unsigned offset = addr & (PAGE_SIZE-1);
2405 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2406 int ret;
2407
2408 if (gpa == UNMAPPED_GVA) {
2409 r = X86EMUL_PROPAGATE_FAULT;
2410 goto out;
2411 }
2412 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2413 if (ret < 0) {
2414 r = X86EMUL_UNHANDLEABLE;
2415 goto out;
2416 }
2417
2418 bytes -= towrite;
2419 data += towrite;
2420 addr += towrite;
2421 }
2422out:
2423 return r;
2424}
2425
bbd9b64e 2426
bbd9b64e
CO		 2427static int emulator_read_emulated(unsigned long addr,
2428 void *val,
2429 unsigned int bytes,
2430 struct kvm_vcpu *vcpu)
2431{
bbd9b64e
CO		 2432 gpa_t gpa;
2433
2434 if (vcpu->mmio_read_completed) {
2435 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2436 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2437 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2438 vcpu->mmio_read_completed = 0;
2439 return X86EMUL_CONTINUE;
2440 }
2441
ad312c7c 2442 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2443
2444 /* For APIC access vmexit */
2445 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2446 goto mmio;
2447
77c2002e
IE		 2448 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2449 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2450 return X86EMUL_CONTINUE;
2451 if (gpa == UNMAPPED_GVA)
2452 return X86EMUL_PROPAGATE_FAULT;
2453
2454mmio:
2455 /*
2456 * Is this MMIO handled locally?
2457 */
aec51dc4
AK		 2458 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2459 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e 2460 return X86EMUL_CONTINUE;
aec51dc4
AK		 2461 }
2462
2463 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2464
2465 vcpu->mmio_needed = 1;
2466 vcpu->mmio_phys_addr = gpa;
2467 vcpu->mmio_size = bytes;
2468 vcpu->mmio_is_write = 0;
2469
2470 return X86EMUL_UNHANDLEABLE;
2471}
2472
3200f405 2473int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2474 const void *val, int bytes)
bbd9b64e
CO		 2475{
2476 int ret;
2477
2478 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2479 if (ret < 0)
bbd9b64e 2480 return 0;
ad218f85 2481 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2482 return 1;
2483}
2484
2485static int emulator_write_emulated_onepage(unsigned long addr,
2486 const void *val,
2487 unsigned int bytes,
2488 struct kvm_vcpu *vcpu)
2489{
10589a46
MT		 2490 gpa_t gpa;
2491
10589a46 2492 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2493
2494 if (gpa == UNMAPPED_GVA) {
c3c91fee 2495 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2496 return X86EMUL_PROPAGATE_FAULT;
2497 }
2498
2499 /* For APIC access vmexit */
2500 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2501 goto mmio;
2502
2503 if (emulator_write_phys(vcpu, gpa, val, bytes))
2504 return X86EMUL_CONTINUE;
2505
2506mmio:
aec51dc4 2507 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2508 /*
2509 * Is this MMIO handled locally?
2510 */
bda9020e 2511 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2512 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2513
2514 vcpu->mmio_needed = 1;
2515 vcpu->mmio_phys_addr = gpa;
2516 vcpu->mmio_size = bytes;
2517 vcpu->mmio_is_write = 1;
2518 memcpy(vcpu->mmio_data, val, bytes);
2519
2520 return X86EMUL_CONTINUE;
2521}
2522
2523int emulator_write_emulated(unsigned long addr,
2524 const void *val,
2525 unsigned int bytes,
2526 struct kvm_vcpu *vcpu)
2527{
2528 /* Crossing a page boundary? */
2529 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2530 int rc, now;
2531
2532 now = -addr & ~PAGE_MASK;
2533 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2534 if (rc != X86EMUL_CONTINUE)
2535 return rc;
2536 addr += now;
2537 val += now;
2538 bytes -= now;
2539 }
2540 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2541}
2542EXPORT_SYMBOL_GPL(emulator_write_emulated);
2543
2544static int emulator_cmpxchg_emulated(unsigned long addr,
2545 const void *old,
2546 const void *new,
2547 unsigned int bytes,
2548 struct kvm_vcpu *vcpu)
2549{
2550 static int reported;
2551
2552 if (!reported) {
2553 reported = 1;
2554 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2555 }
2bacc55c
MT		 2556#ifndef CONFIG_X86_64
2557 /* guests cmpxchg8b have to be emulated atomically */
2558 if (bytes == 8) {
10589a46 2559 gpa_t gpa;
2bacc55c 2560 struct page *page;
c0b49b0d 2561 char *kaddr;
2bacc55c
MT		 2562 u64 val;
2563
10589a46
MT		 2564 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2565
2bacc55c
MT		 2566 if (gpa == UNMAPPED_GVA ||
2567 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2568 goto emul_write;
2569
2570 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2571 goto emul_write;
2572
2573 val = *(u64 *)new;
72dc67a6 2574
2bacc55c 2575 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2576
c0b49b0d
AM		 2577 kaddr = kmap_atomic(page, KM_USER0);
2578 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2579 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2580 kvm_release_page_dirty(page);
2581 }
3200f405 2582emul_write:
2bacc55c
MT		 2583#endif
2584
bbd9b64e
CO		 2585 return emulator_write_emulated(addr, new, bytes, vcpu);
2586}
2587
2588static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2589{
2590 return kvm_x86_ops->get_segment_base(vcpu, seg);
2591}
2592
2593int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2594{
a7052897 2595 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2596 return X86EMUL_CONTINUE;
2597}
2598
2599int emulate_clts(struct kvm_vcpu *vcpu)
2600{
ad312c7c 2601 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2602 return X86EMUL_CONTINUE;
2603}
2604
2605int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2606{
2607 struct kvm_vcpu *vcpu = ctxt->vcpu;
2608
2609 switch (dr) {
2610 case 0 ... 3:
2611 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2612 return X86EMUL_CONTINUE;
2613 default:
b8688d51 2614 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2615 return X86EMUL_UNHANDLEABLE;
2616 }
2617}
2618
2619int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2620{
2621 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2622 int exception;
2623
2624 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2625 if (exception) {
2626 /* FIXME: better handling */
2627 return X86EMUL_UNHANDLEABLE;
2628 }
2629 return X86EMUL_CONTINUE;
2630}
2631
2632void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2633{
bbd9b64e 2634 u8 opcodes[4];
5fdbf976 2635 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2636 unsigned long rip_linear;
2637
f76c710d 2638 if (!printk_ratelimit())
bbd9b64e
CO		 2639 return;
2640
25be4608
GC		 2641 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2642
77c2002e 2643 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2644
2645 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2646 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2647}
2648EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2649
14af3f3c 2650static struct x86_emulate_ops emulate_ops = {
77c2002e 2651 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2652 .read_emulated = emulator_read_emulated,
2653 .write_emulated = emulator_write_emulated,
2654 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2655};
2656
5fdbf976
MT		 2657static void cache_all_regs(struct kvm_vcpu *vcpu)
2658{
2659 kvm_register_read(vcpu, VCPU_REGS_RAX);
2660 kvm_register_read(vcpu, VCPU_REGS_RSP);
2661 kvm_register_read(vcpu, VCPU_REGS_RIP);
2662 vcpu->arch.regs_dirty = ~0;
2663}
2664
bbd9b64e
CO		 2665int emulate_instruction(struct kvm_vcpu *vcpu,
2666 struct kvm_run *run,
2667 unsigned long cr2,
2668 u16 error_code,
571008da 2669 int emulation_type)
bbd9b64e 2670{
310b5d30 2671 int r, shadow_mask;
571008da 2672 struct decode_cache *c;
bbd9b64e 2673
26eef70c 2674 kvm_clear_exception_queue(vcpu);
ad312c7c 2675 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2676 /*
2677 * TODO: fix x86_emulate.c to use guest_read/write_register
2678 * instead of direct ->regs accesses, can save hundred cycles
2679 * on Intel for instructions that don't read/change RSP, for
2680 * for example.
2681 */
2682 cache_all_regs(vcpu);
bbd9b64e
CO		 2683
2684 vcpu->mmio_is_write = 0;
ad312c7c 2685 vcpu->arch.pio.string = 0;
bbd9b64e 2686
571008da 2687 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2688 int cs_db, cs_l;
2689 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2690
ad312c7c
ZX		 2691 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2692 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2693 vcpu->arch.emulate_ctxt.mode =
2694 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2695 ? X86EMUL_MODE_REAL : cs_l
2696 ? X86EMUL_MODE_PROT64 : cs_db
2697 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2698
ad312c7c 2699 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2700
0cb5762e
AP		 2701 /* Only allow emulation of specific instructions on #UD
2702 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2703 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2704 if (emulation_type & EMULTYPE_TRAP_UD) {
2705 if (!c->twobyte)
2706 return EMULATE_FAIL;
2707 switch (c->b) {
2708 case 0x01: /* VMMCALL */
2709 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2710 return EMULATE_FAIL;
2711 break;
2712 case 0x34: /* sysenter */
2713 case 0x35: /* sysexit */
2714 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2715 return EMULATE_FAIL;
2716 break;
2717 case 0x05: /* syscall */
2718 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2719 return EMULATE_FAIL;
2720 break;
2721 default:
2722 return EMULATE_FAIL;
2723 }
2724
2725 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2726 return EMULATE_FAIL;
2727 }
571008da 2728
f2b5756b 2729 ++vcpu->stat.insn_emulation;
bbd9b64e 2730 if (r) {
f2b5756b 2731 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2732 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2733 return EMULATE_DONE;
2734 return EMULATE_FAIL;
2735 }
2736 }
2737
ba8afb6b
GN		 2738 if (emulation_type & EMULTYPE_SKIP) {
2739 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2740 return EMULATE_DONE;
2741 }
2742
ad312c7c 2743 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2744 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2745
2746 if (r == 0)
2747 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2748
ad312c7c 2749 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2750 return EMULATE_DO_MMIO;
2751
2752 if ((r || vcpu->mmio_is_write) && run) {
2753 run->exit_reason = KVM_EXIT_MMIO;
2754 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2755 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2756 run->mmio.len = vcpu->mmio_size;
2757 run->mmio.is_write = vcpu->mmio_is_write;
2758 }
2759
2760 if (r) {
2761 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2762 return EMULATE_DONE;
2763 if (!vcpu->mmio_needed) {
2764 kvm_report_emulation_failure(vcpu, "mmio");
2765 return EMULATE_FAIL;
2766 }
2767 return EMULATE_DO_MMIO;
2768 }
2769
ad312c7c 2770 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2771
2772 if (vcpu->mmio_is_write) {
2773 vcpu->mmio_needed = 0;
2774 return EMULATE_DO_MMIO;
2775 }
2776
2777 return EMULATE_DONE;
2778}
2779EXPORT_SYMBOL_GPL(emulate_instruction);
2780
de7d789a
CO		 2781static int pio_copy_data(struct kvm_vcpu *vcpu)
2782{
ad312c7c 2783 void *p = vcpu->arch.pio_data;
0f346074 2784 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2785 unsigned bytes;
0f346074 2786 int ret;
de7d789a 2787
ad312c7c
ZX		 2788 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2789 if (vcpu->arch.pio.in)
0f346074 2790 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2791 else
0f346074
IE		 2792 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2793 return ret;
de7d789a
CO		 2794}
2795
2796int complete_pio(struct kvm_vcpu *vcpu)
2797{
ad312c7c 2798 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2799 long delta;
2800 int r;
5fdbf976 2801 unsigned long val;
de7d789a
CO		 2802
2803 if (!io->string) {
5fdbf976
MT		 2804 if (io->in) {
2805 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2806 memcpy(&val, vcpu->arch.pio_data, io->size);
2807 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2808 }
de7d789a
CO		 2809 } else {
2810 if (io->in) {
2811 r = pio_copy_data(vcpu);
5fdbf976 2812 if (r)
de7d789a 2813 return r;
de7d789a
CO		 2814 }
2815
2816 delta = 1;
2817 if (io->rep) {
2818 delta *= io->cur_count;
2819 /*
2820 * The size of the register should really depend on
2821 * current address size.
2822 */
5fdbf976
MT		 2823 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2824 val -= delta;
2825 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2826 }
2827 if (io->down)
2828 delta = -delta;
2829 delta *= io->size;
5fdbf976
MT		 2830 if (io->in) {
2831 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2832 val += delta;
2833 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2834 } else {
2835 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2836 val += delta;
2837 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2838 }
de7d789a
CO		 2839 }
2840
de7d789a
CO		 2841 io->count -= io->cur_count;
2842 io->cur_count = 0;
2843
2844 return 0;
2845}
2846
bda9020e 2847static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2848{
2849 /* TODO: String I/O for in kernel device */
bda9020e 2850 int r;
de7d789a 2851
ad312c7c 2852 if (vcpu->arch.pio.in)
bda9020e
MT		 2853 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2854 vcpu->arch.pio.size, pd);
de7d789a 2855 else
bda9020e
MT		 2856 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2857 vcpu->arch.pio.size, pd);
2858 return r;
de7d789a
CO		 2859}
2860
bda9020e 2861static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2862{
ad312c7c
ZX		 2863 struct kvm_pio_request *io = &vcpu->arch.pio;
2864 void *pd = vcpu->arch.pio_data;
bda9020e 2865 int i, r = 0;
de7d789a 2866
de7d789a 2867 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2868 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2869 io->port, io->size, pd)) {
2870 r = -EOPNOTSUPP;
2871 break;
2872 }
de7d789a
CO		 2873 pd += io->size;
2874 }
bda9020e 2875 return r;
de7d789a
CO		 2876}
2877
2878int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2879 int size, unsigned port)
2880{
5fdbf976 2881 unsigned long val;
de7d789a
CO		 2882
2883 vcpu->run->exit_reason = KVM_EXIT_IO;
2884 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2885 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2886 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2887 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2888 vcpu->run->io.port = vcpu->arch.pio.port = port;
2889 vcpu->arch.pio.in = in;
2890 vcpu->arch.pio.string = 0;
2891 vcpu->arch.pio.down = 0;
ad312c7c 2892 vcpu->arch.pio.rep = 0;
de7d789a 2893
229456fc
MT		 2894 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2895 size, 1);
2714d1d3 2896
5fdbf976
MT		 2897 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2898 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2899
bda9020e 2900 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2901 complete_pio(vcpu);
2902 return 1;
2903 }
2904 return 0;
2905}
2906EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2907
2908int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2909 int size, unsigned long count, int down,
2910 gva_t address, int rep, unsigned port)
2911{
2912 unsigned now, in_page;
0f346074 2913 int ret = 0;
de7d789a
CO		 2914
2915 vcpu->run->exit_reason = KVM_EXIT_IO;
2916 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2917 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2918 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2919 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2920 vcpu->run->io.port = vcpu->arch.pio.port = port;
2921 vcpu->arch.pio.in = in;
2922 vcpu->arch.pio.string = 1;
2923 vcpu->arch.pio.down = down;
ad312c7c 2924 vcpu->arch.pio.rep = rep;
de7d789a 2925
229456fc
MT		 2926 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2927 size, count);
2714d1d3 2928
de7d789a
CO		 2929 if (!count) {
2930 kvm_x86_ops->skip_emulated_instruction(vcpu);
2931 return 1;
2932 }
2933
2934 if (!down)
2935 in_page = PAGE_SIZE - offset_in_page(address);
2936 else
2937 in_page = offset_in_page(address) + size;
2938 now = min(count, (unsigned long)in_page / size);
0f346074 2939 if (!now)
de7d789a 2940 now = 1;
de7d789a
CO		 2941 if (down) {
2942 /*
2943 * String I/O in reverse. Yuck. Kill the guest, fix later.
2944 */
2945 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2946 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2947 return 1;
2948 }
2949 vcpu->run->io.count = now;
ad312c7c 2950 vcpu->arch.pio.cur_count = now;
de7d789a 2951
ad312c7c 2952 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2953 kvm_x86_ops->skip_emulated_instruction(vcpu);
2954
0f346074 2955 vcpu->arch.pio.guest_gva = address;
de7d789a 2956
ad312c7c 2957 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2958 /* string PIO write */
2959 ret = pio_copy_data(vcpu);
0f346074
IE		 2960 if (ret == X86EMUL_PROPAGATE_FAULT) {
2961 kvm_inject_gp(vcpu, 0);
2962 return 1;
2963 }
bda9020e 2964 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 2965 complete_pio(vcpu);
ad312c7c 2966 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2967 ret = 1;
2968 }
bda9020e
MT		 2969 }
2970 /* no string PIO read support yet */
de7d789a
CO		 2971
2972 return ret;
2973}
2974EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2975
c8076604
GH		 2976static void bounce_off(void *info)
2977{
2978 /* nothing */
2979}
2980
2981static unsigned int ref_freq;
2982static unsigned long tsc_khz_ref;
2983
2984static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2985 void *data)
2986{
2987 struct cpufreq_freqs *freq = data;
2988 struct kvm *kvm;
2989 struct kvm_vcpu *vcpu;
2990 int i, send_ipi = 0;
2991
2992 if (!ref_freq)
2993 ref_freq = freq->old;
2994
2995 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2996 return 0;
2997 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2998 return 0;
2999 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3000
3001 spin_lock(&kvm_lock);
3002 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3003 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3004 if (vcpu->cpu != freq->cpu)
3005 continue;
3006 if (!kvm_request_guest_time_update(vcpu))
3007 continue;
3008 if (vcpu->cpu != smp_processor_id())
3009 send_ipi++;
3010 }
3011 }
3012 spin_unlock(&kvm_lock);
3013
3014 if (freq->old < freq->new && send_ipi) {
3015 /*
3016 * We upscale the frequency. Must make the guest
3017 * doesn't see old kvmclock values while running with
3018 * the new frequency, otherwise we risk the guest sees
3019 * time go backwards.
3020 *
3021 * In case we update the frequency for another cpu
3022 * (which might be in guest context) send an interrupt
3023 * to kick the cpu out of guest context. Next time
3024 * guest context is entered kvmclock will be updated,
3025 * so the guest will not see stale values.
3026 */
3027 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3028 }
3029 return 0;
3030}
3031
3032static struct notifier_block kvmclock_cpufreq_notifier_block = {
3033 .notifier_call = kvmclock_cpufreq_notifier
3034};
3035
f8c16bba 3036int kvm_arch_init(void *opaque)
043405e1 3037{
c8076604 3038 int r, cpu;
f8c16bba
ZX		 3039 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3040
f8c16bba
ZX		 3041 if (kvm_x86_ops) {
3042 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3043 r = -EEXIST;
3044 goto out;
f8c16bba
ZX		 3045 }
3046
3047 if (!ops->cpu_has_kvm_support()) {
3048 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3049 r = -EOPNOTSUPP;
3050 goto out;
f8c16bba
ZX		 3051 }
3052 if (ops->disabled_by_bios()) {
3053 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3054 r = -EOPNOTSUPP;
3055 goto out;
f8c16bba
ZX		 3056 }
3057
97db56ce
AK		 3058 r = kvm_mmu_module_init();
3059 if (r)
3060 goto out;
3061
3062 kvm_init_msr_list();
3063
f8c16bba 3064 kvm_x86_ops = ops;
56c6d28a 3065 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3066 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3067 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3068 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3069
3070 for_each_possible_cpu(cpu)
3071 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3072 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3073 tsc_khz_ref = tsc_khz;
3074 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3075 CPUFREQ_TRANSITION_NOTIFIER);
3076 }
3077
f8c16bba 3078 return 0;
56c6d28a
ZX		 3079
3080out:
56c6d28a 3081 return r;
043405e1 3082}
8776e519 3083
f8c16bba
ZX		 3084void kvm_arch_exit(void)
3085{
888d256e
JK		 3086 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3087 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3088 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3089 kvm_x86_ops = NULL;
56c6d28a
ZX		 3090 kvm_mmu_module_exit();
3091}
f8c16bba 3092
8776e519
HB		 3093int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3094{
3095 ++vcpu->stat.halt_exits;
3096 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3097 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3098 return 1;
3099 } else {
3100 vcpu->run->exit_reason = KVM_EXIT_HLT;
3101 return 0;
3102 }
3103}
3104EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3105
2f333bcb
MT		 3106static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3107 unsigned long a1)
3108{
3109 if (is_long_mode(vcpu))
3110 return a0;
3111 else
3112 return a0 | ((gpa_t)a1 << 32);
3113}
3114
8776e519
HB		 3115int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3116{
3117 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3118 int r = 1;
8776e519 3119
5fdbf976
MT		 3120 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3121 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3122 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3123 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3124 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3125
229456fc 3126 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3127
8776e519
HB		 3128 if (!is_long_mode(vcpu)) {
3129 nr &= 0xFFFFFFFF;
3130 a0 &= 0xFFFFFFFF;
3131 a1 &= 0xFFFFFFFF;
3132 a2 &= 0xFFFFFFFF;
3133 a3 &= 0xFFFFFFFF;
3134 }
3135
3136 switch (nr) {
b93463aa
AK		 3137 case KVM_HC_VAPIC_POLL_IRQ:
3138 ret = 0;
3139 break;
2f333bcb
MT		 3140 case KVM_HC_MMU_OP:
3141 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3142 break;
8776e519
HB		 3143 default:
3144 ret = -KVM_ENOSYS;
3145 break;
3146 }
5fdbf976 3147 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3148 ++vcpu->stat.hypercalls;
2f333bcb 3149 return r;
8776e519
HB		 3150}
3151EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3152
3153int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3154{
3155 char instruction[3];
3156 int ret = 0;
5fdbf976 3157 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3158
8776e519
HB		 3159
3160 /*
3161 * Blow out the MMU to ensure that no other VCPU has an active mapping
3162 * to ensure that the updated hypercall appears atomically across all
3163 * VCPUs.
3164 */
3165 kvm_mmu_zap_all(vcpu->kvm);
3166
8776e519 3167 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3168 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3169 != X86EMUL_CONTINUE)
3170 ret = -EFAULT;
3171
8776e519
HB		 3172 return ret;
3173}
3174
3175static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3176{
3177 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3178}
3179
3180void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3181{
3182 struct descriptor_table dt = { limit, base };
3183
3184 kvm_x86_ops->set_gdt(vcpu, &dt);
3185}
3186
3187void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3188{
3189 struct descriptor_table dt = { limit, base };
3190
3191 kvm_x86_ops->set_idt(vcpu, &dt);
3192}
3193
3194void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3195 unsigned long *rflags)
3196{
2d3ad1f4 3197 kvm_lmsw(vcpu, msw);
8776e519
HB		 3198 *rflags = kvm_x86_ops->get_rflags(vcpu);
3199}
3200
3201unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3202{
54e445ca
JR		 3203 unsigned long value;
3204
8776e519
HB		 3205 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3206 switch (cr) {
3207 case 0:
54e445ca
JR		 3208 value = vcpu->arch.cr0;
3209 break;
8776e519 3210 case 2:
54e445ca
JR		 3211 value = vcpu->arch.cr2;
3212 break;
8776e519 3213 case 3:
54e445ca
JR		 3214 value = vcpu->arch.cr3;
3215 break;
8776e519 3216 case 4:
54e445ca
JR		 3217 value = vcpu->arch.cr4;
3218 break;
152ff9be 3219 case 8:
54e445ca
JR		 3220 value = kvm_get_cr8(vcpu);
3221 break;
8776e519 3222 default:
b8688d51 3223 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3224 return 0;
3225 }
54e445ca
JR		 3226
3227 return value;
8776e519
HB		 3228}
3229
3230void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3231 unsigned long *rflags)
3232{
3233 switch (cr) {
3234 case 0:
2d3ad1f4 3235 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3236 *rflags = kvm_x86_ops->get_rflags(vcpu);
3237 break;
3238 case 2:
ad312c7c 3239 vcpu->arch.cr2 = val;
8776e519
HB		 3240 break;
3241 case 3:
2d3ad1f4 3242 kvm_set_cr3(vcpu, val);
8776e519
HB		 3243 break;
3244 case 4:
2d3ad1f4 3245 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3246 break;
152ff9be 3247 case 8:
2d3ad1f4 3248 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3249 break;
8776e519 3250 default:
b8688d51 3251 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3252 }
3253}
3254
07716717
DK		 3255static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3256{
ad312c7c
ZX		 3257 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3258 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3259
3260 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3261 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3262 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3263 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3264 if (ej->function == e->function) {
3265 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3266 return j;
3267 }
3268 }
3269 return 0; /* silence gcc, even though control never reaches here */
3270}
3271
3272/* find an entry with matching function, matching index (if needed), and that
3273 * should be read next (if it's stateful) */
3274static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3275 u32 function, u32 index)
3276{
3277 if (e->function != function)
3278 return 0;
3279 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3280 return 0;
3281 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3282 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3283 return 0;
3284 return 1;
3285}
3286
d8017474
AG		 3287struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3288 u32 function, u32 index)
8776e519
HB		 3289{
3290 int i;
d8017474 3291 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3292
ad312c7c 3293 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3294 struct kvm_cpuid_entry2 *e;
3295
ad312c7c 3296 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3297 if (is_matching_cpuid_entry(e, function, index)) {
3298 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3299 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3300 best = e;
3301 break;
3302 }
3303 /*
3304 * Both basic or both extended?
3305 */
3306 if (((e->function ^ function) & 0x80000000) == 0)
3307 if (!best || e->function > best->function)
3308 best = e;
3309 }
d8017474
AG		 3310 return best;
3311}
3312
82725b20
DE		 3313int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3314{
3315 struct kvm_cpuid_entry2 *best;
3316
3317 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3318 if (best)
3319 return best->eax & 0xff;
3320 return 36;
3321}
3322
d8017474
AG		 3323void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3324{
3325 u32 function, index;
3326 struct kvm_cpuid_entry2 *best;
3327
3328 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3329 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3330 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3331 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3332 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3333 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3334 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3335 if (best) {
5fdbf976
MT		 3336 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3337 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3338 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3339 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3340 }
8776e519 3341 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3342 trace_kvm_cpuid(function,
3343 kvm_register_read(vcpu, VCPU_REGS_RAX),
3344 kvm_register_read(vcpu, VCPU_REGS_RBX),
3345 kvm_register_read(vcpu, VCPU_REGS_RCX),
3346 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3347}
3348EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3349
b6c7a5dc
HB		 3350/*
3351 * Check if userspace requested an interrupt window, and that the
3352 * interrupt window is open.
3353 *
3354 * No need to exit to userspace if we already have an interrupt queued.
3355 */
3356static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3357 struct kvm_run *kvm_run)
3358{
8061823a 3359 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3360 kvm_run->request_interrupt_window &&
5df56646 3361 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3362}
3363
3364static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3365 struct kvm_run *kvm_run)
3366{
3367 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3368 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3369 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3370 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3371 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3372 else
b6c7a5dc 3373 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3374 kvm_arch_interrupt_allowed(vcpu) &&
3375 !kvm_cpu_has_interrupt(vcpu) &&
3376 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3377}
3378
b93463aa
AK		 3379static void vapic_enter(struct kvm_vcpu *vcpu)
3380{
3381 struct kvm_lapic *apic = vcpu->arch.apic;
3382 struct page *page;
3383
3384 if (!apic || !apic->vapic_addr)
3385 return;
3386
3387 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3388
3389 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3390}
3391
3392static void vapic_exit(struct kvm_vcpu *vcpu)
3393{
3394 struct kvm_lapic *apic = vcpu->arch.apic;
3395
3396 if (!apic || !apic->vapic_addr)
3397 return;
3398
f8b78fa3 3399 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3400 kvm_release_page_dirty(apic->vapic_page);
3401 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3402 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3403}
3404
95ba8273
GN		 3405static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3406{
3407 int max_irr, tpr;
3408
3409 if (!kvm_x86_ops->update_cr8_intercept)
3410 return;
3411
8db3baa2
GN		 3412 if (!vcpu->arch.apic->vapic_addr)
3413 max_irr = kvm_lapic_find_highest_irr(vcpu);
3414 else
3415 max_irr = -1;
95ba8273
GN		 3416
3417 if (max_irr != -1)
3418 max_irr >>= 4;
3419
3420 tpr = kvm_lapic_get_cr8(vcpu);
3421
3422 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3423}
3424
6a8b1d13 3425static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3426{
3427 /* try to reinject previous events if any */
3428 if (vcpu->arch.nmi_injected) {
3429 kvm_x86_ops->set_nmi(vcpu);
3430 return;
3431 }
3432
3433 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3434 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3435 return;
3436 }
3437
3438 /* try to inject new event if pending */
3439 if (vcpu->arch.nmi_pending) {
3440 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3441 vcpu->arch.nmi_pending = false;
3442 vcpu->arch.nmi_injected = true;
3443 kvm_x86_ops->set_nmi(vcpu);
3444 }
3445 } else if (kvm_cpu_has_interrupt(vcpu)) {
3446 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3447 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3448 false);
3449 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3450 }
3451 }
3452}
3453
d7690175 3454static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3455{
3456 int r;
6a8b1d13
GN		 3457 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3458 kvm_run->request_interrupt_window;
b6c7a5dc 3459
2e53d63a
MT		 3460 if (vcpu->requests)
3461 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3462 kvm_mmu_unload(vcpu);
3463
b6c7a5dc
HB		 3464 r = kvm_mmu_reload(vcpu);
3465 if (unlikely(r))
3466 goto out;
3467
2f52d58c
AK		 3468 if (vcpu->requests) {
3469 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3470 __kvm_migrate_timers(vcpu);
c8076604
GH		 3471 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3472 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3473 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3474 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3475 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3476 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3477 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3478 &vcpu->requests)) {
3479 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3480 r = 0;
3481 goto out;
3482 }
71c4dfaf
JR		 3483 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3484 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3485 r = 0;
3486 goto out;
3487 }
2f52d58c 3488 }
b93463aa 3489
b6c7a5dc
HB		 3490 preempt_disable();
3491
3492 kvm_x86_ops->prepare_guest_switch(vcpu);
3493 kvm_load_guest_fpu(vcpu);
3494
3495 local_irq_disable();
3496
32f88400
MT		 3497 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3498 smp_mb__after_clear_bit();
3499
d7690175 3500 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3501 local_irq_enable();
3502 preempt_enable();
3503 r = 1;
3504 goto out;
3505 }
3506
ad312c7c 3507 if (vcpu->arch.exception.pending)
298101da 3508 __queue_exception(vcpu);
eb9774f0 3509 else
95ba8273 3510 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3511
6a8b1d13
GN		 3512 /* enable NMI/IRQ window open exits if needed */
3513 if (vcpu->arch.nmi_pending)
3514 kvm_x86_ops->enable_nmi_window(vcpu);
3515 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3516 kvm_x86_ops->enable_irq_window(vcpu);
3517
95ba8273 3518 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3519 update_cr8_intercept(vcpu);
3520 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3521 }
b93463aa 3522
3200f405
MT		 3523 up_read(&vcpu->kvm->slots_lock);
3524
b6c7a5dc
HB		 3525 kvm_guest_enter();
3526
42dbaa5a
JK		 3527 get_debugreg(vcpu->arch.host_dr6, 6);
3528 get_debugreg(vcpu->arch.host_dr7, 7);
3529 if (unlikely(vcpu->arch.switch_db_regs)) {
3530 get_debugreg(vcpu->arch.host_db[0], 0);
3531 get_debugreg(vcpu->arch.host_db[1], 1);
3532 get_debugreg(vcpu->arch.host_db[2], 2);
3533 get_debugreg(vcpu->arch.host_db[3], 3);
3534
3535 set_debugreg(0, 7);
3536 set_debugreg(vcpu->arch.eff_db[0], 0);
3537 set_debugreg(vcpu->arch.eff_db[1], 1);
3538 set_debugreg(vcpu->arch.eff_db[2], 2);
3539 set_debugreg(vcpu->arch.eff_db[3], 3);
3540 }
b6c7a5dc 3541
229456fc 3542 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3543 kvm_x86_ops->run(vcpu, kvm_run);
3544
42dbaa5a
JK		 3545 if (unlikely(vcpu->arch.switch_db_regs)) {
3546 set_debugreg(0, 7);
3547 set_debugreg(vcpu->arch.host_db[0], 0);
3548 set_debugreg(vcpu->arch.host_db[1], 1);
3549 set_debugreg(vcpu->arch.host_db[2], 2);
3550 set_debugreg(vcpu->arch.host_db[3], 3);
3551 }
3552 set_debugreg(vcpu->arch.host_dr6, 6);
3553 set_debugreg(vcpu->arch.host_dr7, 7);
3554
32f88400 3555 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3556 local_irq_enable();
3557
3558 ++vcpu->stat.exits;
3559
3560 /*
3561 * We must have an instruction between local_irq_enable() and
3562 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3563 * the interrupt shadow. The stat.exits increment will do nicely.
3564 * But we need to prevent reordering, hence this barrier():
3565 */
3566 barrier();
3567
3568 kvm_guest_exit();
3569
3570 preempt_enable();
3571
3200f405
MT		 3572 down_read(&vcpu->kvm->slots_lock);
3573
b6c7a5dc
HB		 3574 /*
3575 * Profile KVM exit RIPs:
3576 */
3577 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3578 unsigned long rip = kvm_rip_read(vcpu);
3579 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3580 }
3581
298101da 3582
b93463aa
AK		 3583 kvm_lapic_sync_from_vapic(vcpu);
3584
b6c7a5dc 3585 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3586out:
3587 return r;
3588}
b6c7a5dc 3589
09cec754 3590
d7690175
MT		 3591static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3592{
3593 int r;
3594
3595 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3596 pr_debug("vcpu %d received sipi with vector # %x\n",
3597 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3598 kvm_lapic_reset(vcpu);
5f179287 3599 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3600 if (r)
3601 return r;
3602 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3603 }
3604
d7690175
MT		 3605 down_read(&vcpu->kvm->slots_lock);
3606 vapic_enter(vcpu);
3607
3608 r = 1;
3609 while (r > 0) {
af2152f5 3610 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3611 r = vcpu_enter_guest(vcpu, kvm_run);
3612 else {
3613 up_read(&vcpu->kvm->slots_lock);
3614 kvm_vcpu_block(vcpu);
3615 down_read(&vcpu->kvm->slots_lock);
3616 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3617 {
3618 switch(vcpu->arch.mp_state) {
3619 case KVM_MP_STATE_HALTED:
d7690175 3620 vcpu->arch.mp_state =
09cec754
GN		 3621 KVM_MP_STATE_RUNNABLE;
3622 case KVM_MP_STATE_RUNNABLE:
3623 break;
3624 case KVM_MP_STATE_SIPI_RECEIVED:
3625 default:
3626 r = -EINTR;
3627 break;
3628 }
3629 }
d7690175
MT		 3630 }
3631
09cec754
GN		 3632 if (r <= 0)
3633 break;
3634
3635 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3636 if (kvm_cpu_has_pending_timer(vcpu))
3637 kvm_inject_pending_timer_irqs(vcpu);
3638
3639 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3640 r = -EINTR;
3641 kvm_run->exit_reason = KVM_EXIT_INTR;
3642 ++vcpu->stat.request_irq_exits;
3643 }
3644 if (signal_pending(current)) {
3645 r = -EINTR;
3646 kvm_run->exit_reason = KVM_EXIT_INTR;
3647 ++vcpu->stat.signal_exits;
3648 }
3649 if (need_resched()) {
3650 up_read(&vcpu->kvm->slots_lock);
3651 kvm_resched(vcpu);
3652 down_read(&vcpu->kvm->slots_lock);
d7690175 3653 }
b6c7a5dc
HB		 3654 }
3655
d7690175 3656 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3657 post_kvm_run_save(vcpu, kvm_run);
3658
b93463aa
AK		 3659 vapic_exit(vcpu);
3660
b6c7a5dc
HB		 3661 return r;
3662}
3663
3664int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3665{
3666 int r;
3667 sigset_t sigsaved;
3668
3669 vcpu_load(vcpu);
3670
ac9f6dc0
AK		 3671 if (vcpu->sigset_active)
3672 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3673
a4535290 3674 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3675 kvm_vcpu_block(vcpu);
d7690175 3676 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3677 r = -EAGAIN;
3678 goto out;
b6c7a5dc
HB		 3679 }
3680
b6c7a5dc
HB		 3681 /* re-sync apic's tpr */
3682 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3683 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3684
ad312c7c 3685 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3686 r = complete_pio(vcpu);
3687 if (r)
3688 goto out;
3689 }
3690#if CONFIG_HAS_IOMEM
3691 if (vcpu->mmio_needed) {
3692 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3693 vcpu->mmio_read_completed = 1;
3694 vcpu->mmio_needed = 0;
3200f405
MT		 3695
3696 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3697 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3698 vcpu->arch.mmio_fault_cr2, 0,
3699 EMULTYPE_NO_DECODE);
3200f405 3700 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3701 if (r == EMULATE_DO_MMIO) {
3702 /*
3703 * Read-modify-write. Back to userspace.
3704 */
3705 r = 0;
3706 goto out;
3707 }
3708 }
3709#endif
5fdbf976
MT		 3710 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3711 kvm_register_write(vcpu, VCPU_REGS_RAX,
3712 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3713
3714 r = __vcpu_run(vcpu, kvm_run);
3715
3716out:
3717 if (vcpu->sigset_active)
3718 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3719
3720 vcpu_put(vcpu);
3721 return r;
3722}
3723
3724int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3725{
3726 vcpu_load(vcpu);
3727
5fdbf976
MT		 3728 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3729 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3730 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3731 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3732 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3733 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3734 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3735 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3736#ifdef CONFIG_X86_64
5fdbf976
MT		 3737 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3738 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3739 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3740 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3741 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3742 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3743 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3744 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3745#endif
3746
5fdbf976 3747 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3748 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3749
3750 /*
3751 * Don't leak debug flags in case they were set for guest debugging
3752 */
d0bfb940 3753 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3754 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3755
3756 vcpu_put(vcpu);
3757
3758 return 0;
3759}
3760
3761int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3762{
3763 vcpu_load(vcpu);
3764
5fdbf976
MT		 3765 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3766 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3767 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3768 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3769 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3770 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3771 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3772 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3773#ifdef CONFIG_X86_64
5fdbf976
MT		 3774 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3775 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3776 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3777 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3778 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3779 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3780 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3781 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3782
b6c7a5dc
HB		 3783#endif
3784
5fdbf976 3785 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3786 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3787
b6c7a5dc 3788
b4f14abd
JK		 3789 vcpu->arch.exception.pending = false;
3790
b6c7a5dc
HB		 3791 vcpu_put(vcpu);
3792
3793 return 0;
3794}
3795
3e6e0aab
GT		 3796void kvm_get_segment(struct kvm_vcpu *vcpu,
3797 struct kvm_segment *var, int seg)
b6c7a5dc 3798{
14af3f3c 3799 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3800}
3801
3802void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3803{
3804 struct kvm_segment cs;
3805
3e6e0aab 3806 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3807 *db = cs.db;
3808 *l = cs.l;
3809}
3810EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3811
3812int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3813 struct kvm_sregs *sregs)
3814{
3815 struct descriptor_table dt;
b6c7a5dc
HB		 3816
3817 vcpu_load(vcpu);
3818
3e6e0aab
GT		 3819 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3820 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3821 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3822 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3823 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3824 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3825
3e6e0aab
GT		 3826 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3827 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3828
3829 kvm_x86_ops->get_idt(vcpu, &dt);
3830 sregs->idt.limit = dt.limit;
3831 sregs->idt.base = dt.base;
3832 kvm_x86_ops->get_gdt(vcpu, &dt);
3833 sregs->gdt.limit = dt.limit;
3834 sregs->gdt.base = dt.base;
3835
3836 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3837 sregs->cr0 = vcpu->arch.cr0;
3838 sregs->cr2 = vcpu->arch.cr2;
3839 sregs->cr3 = vcpu->arch.cr3;
3840 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3841 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3842 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3843 sregs->apic_base = kvm_get_apic_base(vcpu);
3844
923c61bb 3845 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3846
36752c9b 3847 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3848 set_bit(vcpu->arch.interrupt.nr,
3849 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3850
b6c7a5dc
HB		 3851 vcpu_put(vcpu);
3852
3853 return 0;
3854}
3855
62d9f0db
MT		 3856int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3857 struct kvm_mp_state *mp_state)
3858{
3859 vcpu_load(vcpu);
3860 mp_state->mp_state = vcpu->arch.mp_state;
3861 vcpu_put(vcpu);
3862 return 0;
3863}
3864
3865int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3866 struct kvm_mp_state *mp_state)
3867{
3868 vcpu_load(vcpu);
3869 vcpu->arch.mp_state = mp_state->mp_state;
3870 vcpu_put(vcpu);
3871 return 0;
3872}
3873
3e6e0aab 3874static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3875 struct kvm_segment *var, int seg)
3876{
14af3f3c 3877 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3878}
3879
37817f29
IE		 3880static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3881 struct kvm_segment *kvm_desct)
3882{
3883 kvm_desct->base = seg_desc->base0;
3884 kvm_desct->base |= seg_desc->base1 << 16;
3885 kvm_desct->base |= seg_desc->base2 << 24;
3886 kvm_desct->limit = seg_desc->limit0;
3887 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3888 if (seg_desc->g) {
3889 kvm_desct->limit <<= 12;
3890 kvm_desct->limit |= 0xfff;
3891 }
37817f29
IE		 3892 kvm_desct->selector = selector;
3893 kvm_desct->type = seg_desc->type;
3894 kvm_desct->present = seg_desc->p;
3895 kvm_desct->dpl = seg_desc->dpl;
3896 kvm_desct->db = seg_desc->d;
3897 kvm_desct->s = seg_desc->s;
3898 kvm_desct->l = seg_desc->l;
3899 kvm_desct->g = seg_desc->g;
3900 kvm_desct->avl = seg_desc->avl;
3901 if (!selector)
3902 kvm_desct->unusable = 1;
3903 else
3904 kvm_desct->unusable = 0;
3905 kvm_desct->padding = 0;
3906}
3907
b8222ad2
AS		 3908static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3909 u16 selector,
3910 struct descriptor_table *dtable)
37817f29
IE		 3911{
3912 if (selector & 1 << 2) {
3913 struct kvm_segment kvm_seg;
3914
3e6e0aab 3915 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3916
3917 if (kvm_seg.unusable)
3918 dtable->limit = 0;
3919 else
3920 dtable->limit = kvm_seg.limit;
3921 dtable->base = kvm_seg.base;
3922 }
3923 else
3924 kvm_x86_ops->get_gdt(vcpu, dtable);
3925}
3926
3927/* allowed just for 8 bytes segments */
3928static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3929 struct desc_struct *seg_desc)
3930{
98899aa0 3931 gpa_t gpa;
37817f29
IE		 3932 struct descriptor_table dtable;
3933 u16 index = selector >> 3;
3934
b8222ad2 3935 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3936
3937 if (dtable.limit < index * 8 + 7) {
3938 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3939 return 1;
3940 }
98899aa0
MT		 3941 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3942 gpa += index * 8;
3943 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3944}
3945
3946/* allowed just for 8 bytes segments */
3947static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3948 struct desc_struct *seg_desc)
3949{
98899aa0 3950 gpa_t gpa;
37817f29
IE		 3951 struct descriptor_table dtable;
3952 u16 index = selector >> 3;
3953
b8222ad2 3954 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3955
3956 if (dtable.limit < index * 8 + 7)
3957 return 1;
98899aa0
MT		 3958 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3959 gpa += index * 8;
3960 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3961}
3962
3963static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3964 struct desc_struct *seg_desc)
3965{
3966 u32 base_addr;
3967
3968 base_addr = seg_desc->base0;
3969 base_addr |= (seg_desc->base1 << 16);
3970 base_addr |= (seg_desc->base2 << 24);
3971
98899aa0 3972 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3973}
3974
37817f29
IE		 3975static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3976{
3977 struct kvm_segment kvm_seg;
3978
3e6e0aab 3979 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3980 return kvm_seg.selector;
3981}
3982
3983static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3984 u16 selector,
3985 struct kvm_segment *kvm_seg)
3986{
3987 struct desc_struct seg_desc;
3988
3989 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3990 return 1;
3991 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3992 return 0;
3993}
3994
2259e3a7 3995static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3996{
3997 struct kvm_segment segvar = {
3998 .base = selector << 4,
3999 .limit = 0xffff,
4000 .selector = selector,
4001 .type = 3,
4002 .present = 1,
4003 .dpl = 3,
4004 .db = 0,
4005 .s = 1,
4006 .l = 0,
4007 .g = 0,
4008 .avl = 0,
4009 .unusable = 0,
4010 };
4011 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4012 return 0;
4013}
4014
3e6e0aab
GT		 4015int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4016 int type_bits, int seg)
37817f29
IE		 4017{
4018 struct kvm_segment kvm_seg;
4019
f4bbd9aa
AK		 4020 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4021 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4022 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4023 return 1;
4024 kvm_seg.type |= type_bits;
4025
4026 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4027 seg != VCPU_SREG_LDTR)
4028 if (!kvm_seg.s)
4029 kvm_seg.unusable = 1;
4030
3e6e0aab 4031 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4032 return 0;
4033}
4034
4035static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4036 struct tss_segment_32 *tss)
4037{
4038 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4039 tss->eip = kvm_rip_read(vcpu);
37817f29 4040 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4041 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4042 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4043 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4044 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4045 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4046 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4047 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4048 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4049 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4050 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4051 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4052 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4053 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4054 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4055 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4056}
4057
4058static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4059 struct tss_segment_32 *tss)
4060{
4061 kvm_set_cr3(vcpu, tss->cr3);
4062
5fdbf976 4063 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4064 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4065
5fdbf976
MT		 4066 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4067 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4068 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4069 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4070 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4071 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4072 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4073 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4074
3e6e0aab 4075 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4076 return 1;
4077
3e6e0aab 4078 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4079 return 1;
4080
3e6e0aab 4081 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4082 return 1;
4083
3e6e0aab 4084 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4085 return 1;
4086
3e6e0aab 4087 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4088 return 1;
4089
3e6e0aab 4090 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4091 return 1;
4092
3e6e0aab 4093 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4094 return 1;
4095 return 0;
4096}
4097
4098static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4099 struct tss_segment_16 *tss)
4100{
5fdbf976 4101 tss->ip = kvm_rip_read(vcpu);
37817f29 4102 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4103 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4104 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4105 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4106 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4107 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4108 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4109 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4110 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4111
4112 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4113 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4114 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4115 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4116 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4117 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4118}
4119
4120static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4121 struct tss_segment_16 *tss)
4122{
5fdbf976 4123 kvm_rip_write(vcpu, tss->ip);
37817f29 4124 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4125 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4126 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4127 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4128 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4129 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4130 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4131 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4132 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4133
3e6e0aab 4134 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4135 return 1;
4136
3e6e0aab 4137 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4138 return 1;
4139
3e6e0aab 4140 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4141 return 1;
4142
3e6e0aab 4143 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4144 return 1;
4145
3e6e0aab 4146 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4147 return 1;
4148 return 0;
4149}
4150
8b2cf73c 4151static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4152 u16 old_tss_sel, u32 old_tss_base,
4153 struct desc_struct *nseg_desc)
37817f29
IE		 4154{
4155 struct tss_segment_16 tss_segment_16;
4156 int ret = 0;
4157
34198bf8
MT		 4158 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4159 sizeof tss_segment_16))
37817f29
IE		 4160 goto out;
4161
4162 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4163
34198bf8
MT		 4164 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4165 sizeof tss_segment_16))
37817f29 4166 goto out;
34198bf8
MT		 4167
4168 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4169 &tss_segment_16, sizeof tss_segment_16))
4170 goto out;
4171
b237ac37
GN		 4172 if (old_tss_sel != 0xffff) {
4173 tss_segment_16.prev_task_link = old_tss_sel;
4174
4175 if (kvm_write_guest(vcpu->kvm,
4176 get_tss_base_addr(vcpu, nseg_desc),
4177 &tss_segment_16.prev_task_link,
4178 sizeof tss_segment_16.prev_task_link))
4179 goto out;
4180 }
4181
37817f29
IE		 4182 if (load_state_from_tss16(vcpu, &tss_segment_16))
4183 goto out;
4184
4185 ret = 1;
4186out:
4187 return ret;
4188}
4189
8b2cf73c 4190static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4191 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4192 struct desc_struct *nseg_desc)
4193{
4194 struct tss_segment_32 tss_segment_32;
4195 int ret = 0;
4196
34198bf8
MT		 4197 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4198 sizeof tss_segment_32))
37817f29
IE		 4199 goto out;
4200
4201 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4202
34198bf8
MT		 4203 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4204 sizeof tss_segment_32))
4205 goto out;
4206
4207 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4208 &tss_segment_32, sizeof tss_segment_32))
37817f29 4209 goto out;
34198bf8 4210
b237ac37
GN		 4211 if (old_tss_sel != 0xffff) {
4212 tss_segment_32.prev_task_link = old_tss_sel;
4213
4214 if (kvm_write_guest(vcpu->kvm,
4215 get_tss_base_addr(vcpu, nseg_desc),
4216 &tss_segment_32.prev_task_link,
4217 sizeof tss_segment_32.prev_task_link))
4218 goto out;
4219 }
4220
37817f29
IE		 4221 if (load_state_from_tss32(vcpu, &tss_segment_32))
4222 goto out;
4223
4224 ret = 1;
4225out:
4226 return ret;
4227}
4228
4229int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4230{
4231 struct kvm_segment tr_seg;
4232 struct desc_struct cseg_desc;
4233 struct desc_struct nseg_desc;
4234 int ret = 0;
34198bf8
MT		 4235 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4236 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4237
34198bf8 4238 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4239
34198bf8
MT		 4240 /* FIXME: Handle errors. Failure to read either TSS or their
4241 * descriptors should generate a pagefault.
4242 */
37817f29
IE		 4243 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4244 goto out;
4245
34198bf8 4246 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4247 goto out;
4248
37817f29
IE		 4249 if (reason != TASK_SWITCH_IRET) {
4250 int cpl;
4251
4252 cpl = kvm_x86_ops->get_cpl(vcpu);
4253 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4254 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4255 return 1;
4256 }
4257 }
4258
4259 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4260 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4261 return 1;
4262 }
4263
4264 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4265 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4266 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4267 }
4268
4269 if (reason == TASK_SWITCH_IRET) {
4270 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4271 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4272 }
4273
64a7ec06
GN		 4274 /* set back link to prev task only if NT bit is set in eflags
4275 note that old_tss_sel is not used afetr this point */
4276 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4277 old_tss_sel = 0xffff;
37817f29 4278
b237ac37
GN		 4279 /* set back link to prev task only if NT bit is set in eflags
4280 note that old_tss_sel is not used afetr this point */
4281 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4282 old_tss_sel = 0xffff;
4283
37817f29 4284 if (nseg_desc.type & 8)
b237ac37
GN		 4285 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4286 old_tss_base, &nseg_desc);
37817f29 4287 else
b237ac37
GN		 4288 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4289 old_tss_base, &nseg_desc);
37817f29
IE		 4290
4291 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4292 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4293 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4294 }
4295
4296 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4297 nseg_desc.type |= (1 << 1);
37817f29
IE		 4298 save_guest_segment_descriptor(vcpu, tss_selector,
4299 &nseg_desc);
4300 }
4301
4302 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4303 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4304 tr_seg.type = 11;
3e6e0aab 4305 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4306out:
37817f29
IE		 4307 return ret;
4308}
4309EXPORT_SYMBOL_GPL(kvm_task_switch);
4310
b6c7a5dc
HB		 4311int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4312 struct kvm_sregs *sregs)
4313{
4314 int mmu_reset_needed = 0;
923c61bb 4315 int pending_vec, max_bits;
b6c7a5dc
HB		 4316 struct descriptor_table dt;
4317
4318 vcpu_load(vcpu);
4319
4320 dt.limit = sregs->idt.limit;
4321 dt.base = sregs->idt.base;
4322 kvm_x86_ops->set_idt(vcpu, &dt);
4323 dt.limit = sregs->gdt.limit;
4324 dt.base = sregs->gdt.base;
4325 kvm_x86_ops->set_gdt(vcpu, &dt);
4326
ad312c7c
ZX		 4327 vcpu->arch.cr2 = sregs->cr2;
4328 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4329 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4330
2d3ad1f4 4331 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4332
ad312c7c 4333 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4334 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4335 kvm_set_apic_base(vcpu, sregs->apic_base);
4336
4337 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4338
ad312c7c 4339 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4340 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4341 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4342
ad312c7c 4343 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4344 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4345 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4346 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4347
4348 if (mmu_reset_needed)
4349 kvm_mmu_reset_context(vcpu);
4350
923c61bb
GN		 4351 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4352 pending_vec = find_first_bit(
4353 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4354 if (pending_vec < max_bits) {
66fd3f7f 4355 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4356 pr_debug("Set back pending irq %d\n", pending_vec);
4357 if (irqchip_in_kernel(vcpu->kvm))
4358 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4359 }
4360
3e6e0aab
GT		 4361 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4362 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4363 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4364 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4365 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4366 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4367
3e6e0aab
GT		 4368 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4369 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4370
9c3e4aab 4371 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4372 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4373 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4374 !(vcpu->arch.cr0 & X86_CR0_PE))
4375 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4376
b6c7a5dc
HB		 4377 vcpu_put(vcpu);
4378
4379 return 0;
4380}
4381
d0bfb940
JK		 4382int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4383 struct kvm_guest_debug *dbg)
b6c7a5dc 4384{
ae675ef0 4385 int i, r;
b6c7a5dc
HB		 4386
4387 vcpu_load(vcpu);
4388
ae675ef0
JK		 4389 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4390 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4391 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4392 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4393 vcpu->arch.switch_db_regs =
4394 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4395 } else {
4396 for (i = 0; i < KVM_NR_DB_REGS; i++)
4397 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4398 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4399 }
4400
b6c7a5dc
HB		 4401 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4402
d0bfb940
JK		 4403 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4404 kvm_queue_exception(vcpu, DB_VECTOR);
4405 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4406 kvm_queue_exception(vcpu, BP_VECTOR);
4407
b6c7a5dc
HB		 4408 vcpu_put(vcpu);
4409
4410 return r;
4411}
4412
d0752060
HB		 4413/*
4414 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4415 * we have asm/x86/processor.h
4416 */
4417struct fxsave {
4418 u16 cwd;
4419 u16 swd;
4420 u16 twd;
4421 u16 fop;
4422 u64 rip;
4423 u64 rdp;
4424 u32 mxcsr;
4425 u32 mxcsr_mask;
4426 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4427#ifdef CONFIG_X86_64
4428 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4429#else
4430 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4431#endif
4432};
4433
8b006791
ZX		 4434/*
4435 * Translate a guest virtual address to a guest physical address.
4436 */
4437int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4438 struct kvm_translation *tr)
4439{
4440 unsigned long vaddr = tr->linear_address;
4441 gpa_t gpa;
4442
4443 vcpu_load(vcpu);
72dc67a6 4444 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4445 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4446 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4447 tr->physical_address = gpa;
4448 tr->valid = gpa != UNMAPPED_GVA;
4449 tr->writeable = 1;
4450 tr->usermode = 0;
8b006791
ZX		 4451 vcpu_put(vcpu);
4452
4453 return 0;
4454}
4455
d0752060
HB		 4456int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4457{
ad312c7c 4458 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4459
4460 vcpu_load(vcpu);
4461
4462 memcpy(fpu->fpr, fxsave->st_space, 128);
4463 fpu->fcw = fxsave->cwd;
4464 fpu->fsw = fxsave->swd;
4465 fpu->ftwx = fxsave->twd;
4466 fpu->last_opcode = fxsave->fop;
4467 fpu->last_ip = fxsave->rip;
4468 fpu->last_dp = fxsave->rdp;
4469 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4470
4471 vcpu_put(vcpu);
4472
4473 return 0;
4474}
4475
4476int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4477{
ad312c7c 4478 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4479
4480 vcpu_load(vcpu);
4481
4482 memcpy(fxsave->st_space, fpu->fpr, 128);
4483 fxsave->cwd = fpu->fcw;
4484 fxsave->swd = fpu->fsw;
4485 fxsave->twd = fpu->ftwx;
4486 fxsave->fop = fpu->last_opcode;
4487 fxsave->rip = fpu->last_ip;
4488 fxsave->rdp = fpu->last_dp;
4489 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4490
4491 vcpu_put(vcpu);
4492
4493 return 0;
4494}
4495
4496void fx_init(struct kvm_vcpu *vcpu)
4497{
4498 unsigned after_mxcsr_mask;
4499
bc1a34f1
AA		 4500 /*
4501 * Touch the fpu the first time in non atomic context as if
4502 * this is the first fpu instruction the exception handler
4503 * will fire before the instruction returns and it'll have to
4504 * allocate ram with GFP_KERNEL.
4505 */
4506 if (!used_math())
d6e88aec 4507 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4508
d0752060
HB		 4509 /* Initialize guest FPU by resetting ours and saving into guest's */
4510 preempt_disable();
d6e88aec
AK		 4511 kvm_fx_save(&vcpu->arch.host_fx_image);
4512 kvm_fx_finit();
4513 kvm_fx_save(&vcpu->arch.guest_fx_image);
4514 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4515 preempt_enable();
4516
ad312c7c 4517 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4518 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4519 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4520 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4521 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4522}
4523EXPORT_SYMBOL_GPL(fx_init);
4524
4525void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4526{
4527 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4528 return;
4529
4530 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4531 kvm_fx_save(&vcpu->arch.host_fx_image);
4532 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4533}
4534EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4535
4536void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4537{
4538 if (!vcpu->guest_fpu_loaded)
4539 return;
4540
4541 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4542 kvm_fx_save(&vcpu->arch.guest_fx_image);
4543 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4544 ++vcpu->stat.fpu_reload;
d0752060
HB		 4545}
4546EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4547
4548void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4549{
7f1ea208
JR		 4550 if (vcpu->arch.time_page) {
4551 kvm_release_page_dirty(vcpu->arch.time_page);
4552 vcpu->arch.time_page = NULL;
4553 }
4554
e9b11c17
ZX		 4555 kvm_x86_ops->vcpu_free(vcpu);
4556}
4557
4558struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4559 unsigned int id)
4560{
26e5215f
AK		 4561 return kvm_x86_ops->vcpu_create(kvm, id);
4562}
e9b11c17 4563
26e5215f
AK		 4564int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4565{
4566 int r;
e9b11c17
ZX		 4567
4568 /* We do fxsave: this must be aligned. */
ad312c7c 4569 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4570
0bed3b56 4571 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4572 vcpu_load(vcpu);
4573 r = kvm_arch_vcpu_reset(vcpu);
4574 if (r == 0)
4575 r = kvm_mmu_setup(vcpu);
4576 vcpu_put(vcpu);
4577 if (r < 0)
4578 goto free_vcpu;
4579
26e5215f 4580 return 0;
e9b11c17
ZX		 4581free_vcpu:
4582 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4583 return r;
e9b11c17
ZX		 4584}
4585
d40ccc62 4586void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4587{
4588 vcpu_load(vcpu);
4589 kvm_mmu_unload(vcpu);
4590 vcpu_put(vcpu);
4591
4592 kvm_x86_ops->vcpu_free(vcpu);
4593}
4594
4595int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4596{
448fa4a9
JK		 4597 vcpu->arch.nmi_pending = false;
4598 vcpu->arch.nmi_injected = false;
4599
42dbaa5a
JK		 4600 vcpu->arch.switch_db_regs = 0;
4601 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4602 vcpu->arch.dr6 = DR6_FIXED_1;
4603 vcpu->arch.dr7 = DR7_FIXED_1;
4604
e9b11c17
ZX		 4605 return kvm_x86_ops->vcpu_reset(vcpu);
4606}
4607
4608void kvm_arch_hardware_enable(void *garbage)
4609{
4610 kvm_x86_ops->hardware_enable(garbage);
4611}
4612
4613void kvm_arch_hardware_disable(void *garbage)
4614{
4615 kvm_x86_ops->hardware_disable(garbage);
4616}
4617
4618int kvm_arch_hardware_setup(void)
4619{
4620 return kvm_x86_ops->hardware_setup();
4621}
4622
4623void kvm_arch_hardware_unsetup(void)
4624{
4625 kvm_x86_ops->hardware_unsetup();
4626}
4627
4628void kvm_arch_check_processor_compat(void *rtn)
4629{
4630 kvm_x86_ops->check_processor_compatibility(rtn);
4631}
4632
4633int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4634{
4635 struct page *page;
4636 struct kvm *kvm;
4637 int r;
4638
4639 BUG_ON(vcpu->kvm == NULL);
4640 kvm = vcpu->kvm;
4641
ad312c7c 4642 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4643 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4644 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4645 else
a4535290 4646 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4647
4648 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4649 if (!page) {
4650 r = -ENOMEM;
4651 goto fail;
4652 }
ad312c7c 4653 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4654
4655 r = kvm_mmu_create(vcpu);
4656 if (r < 0)
4657 goto fail_free_pio_data;
4658
4659 if (irqchip_in_kernel(kvm)) {
4660 r = kvm_create_lapic(vcpu);
4661 if (r < 0)
4662 goto fail_mmu_destroy;
4663 }
4664
890ca9ae
HY		 4665 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4666 GFP_KERNEL);
4667 if (!vcpu->arch.mce_banks) {
4668 r = -ENOMEM;
4669 goto fail_mmu_destroy;
4670 }
4671 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4672
e9b11c17
ZX		 4673 return 0;
4674
4675fail_mmu_destroy:
4676 kvm_mmu_destroy(vcpu);
4677fail_free_pio_data:
ad312c7c 4678 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4679fail:
4680 return r;
4681}
4682
4683void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4684{
4685 kvm_free_lapic(vcpu);
3200f405 4686 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4687 kvm_mmu_destroy(vcpu);
3200f405 4688 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4689 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4690}
d19a9cd2
ZX		 4691
4692struct kvm *kvm_arch_create_vm(void)
4693{
4694 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4695
4696 if (!kvm)
4697 return ERR_PTR(-ENOMEM);
4698
f05e70ac 4699 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4700 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4701
5550af4d
SY		 4702 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4703 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4704
53f658b3
MT		 4705 rdtscll(kvm->arch.vm_init_tsc);
4706
d19a9cd2
ZX		 4707 return kvm;
4708}
4709
4710static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4711{
4712 vcpu_load(vcpu);
4713 kvm_mmu_unload(vcpu);
4714 vcpu_put(vcpu);
4715}
4716
4717static void kvm_free_vcpus(struct kvm *kvm)
4718{
4719 unsigned int i;
988a2cae 4720 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4721
4722 /*
4723 * Unpin any mmu pages first.
4724 */
988a2cae
GN		 4725 kvm_for_each_vcpu(i, vcpu, kvm)
4726 kvm_unload_vcpu_mmu(vcpu);
4727 kvm_for_each_vcpu(i, vcpu, kvm)
4728 kvm_arch_vcpu_free(vcpu);
4729
4730 mutex_lock(&kvm->lock);
4731 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4732 kvm->vcpus[i] = NULL;
d19a9cd2 4733
988a2cae
GN		 4734 atomic_set(&kvm->online_vcpus, 0);
4735 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4736}
4737
ad8ba2cd
SY		 4738void kvm_arch_sync_events(struct kvm *kvm)
4739{
ba4cef31 4740 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4741}
4742
d19a9cd2
ZX		 4743void kvm_arch_destroy_vm(struct kvm *kvm)
4744{
6eb55818 4745 kvm_iommu_unmap_guest(kvm);
7837699f 4746 kvm_free_pit(kvm);
d7deeeb0
ZX		 4747 kfree(kvm->arch.vpic);
4748 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4749 kvm_free_vcpus(kvm);
4750 kvm_free_physmem(kvm);
3d45830c
AK		 4751 if (kvm->arch.apic_access_page)
4752 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4753 if (kvm->arch.ept_identity_pagetable)
4754 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4755 kfree(kvm);
4756}
0de10343
ZX		 4757
4758int kvm_arch_set_memory_region(struct kvm *kvm,
4759 struct kvm_userspace_memory_region *mem,
4760 struct kvm_memory_slot old,
4761 int user_alloc)
4762{
4763 int npages = mem->memory_size >> PAGE_SHIFT;
4764 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4765
4766 /*To keep backward compatibility with older userspace,
4767 *x86 needs to hanlde !user_alloc case.
4768 */
4769 if (!user_alloc) {
4770 if (npages && !old.rmap) {
604b38ac
AA		 4771 unsigned long userspace_addr;
4772
72dc67a6 4773 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4774 userspace_addr = do_mmap(NULL, 0,
4775 npages * PAGE_SIZE,
4776 PROT_READ | PROT_WRITE,
acee3c04 4777 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4778 0);
72dc67a6 4779 up_write(&current->mm->mmap_sem);
0de10343 4780
604b38ac
AA		 4781 if (IS_ERR((void *)userspace_addr))
4782 return PTR_ERR((void *)userspace_addr);
4783
4784 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4785 spin_lock(&kvm->mmu_lock);
4786 memslot->userspace_addr = userspace_addr;
4787 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4788 } else {
4789 if (!old.user_alloc && old.rmap) {
4790 int ret;
4791
72dc67a6 4792 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4793 ret = do_munmap(current->mm, old.userspace_addr,
4794 old.npages * PAGE_SIZE);
72dc67a6 4795 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4796 if (ret < 0)
4797 printk(KERN_WARNING
4798 "kvm_vm_ioctl_set_memory_region: "
4799 "failed to munmap memory\n");
4800 }
4801 }
4802 }
4803
7c8a83b7 4804 spin_lock(&kvm->mmu_lock);
f05e70ac 4805 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4806 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4807 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4808 }
4809
4810 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4811 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4812 kvm_flush_remote_tlbs(kvm);
4813
4814 return 0;
4815}
1d737c8a 4816
34d4cb8f
MT		 4817void kvm_arch_flush_shadow(struct kvm *kvm)
4818{
4819 kvm_mmu_zap_all(kvm);
8986ecc0 4820 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4821}
4822
1d737c8a
ZX		 4823int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4824{
a4535290 4825 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4826 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4827 || vcpu->arch.nmi_pending;
1d737c8a 4828}
5736199a 4829
5736199a
ZX		 4830void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4831{
32f88400
MT		 4832 int me;
4833 int cpu = vcpu->cpu;
5736199a
ZX		 4834
4835 if (waitqueue_active(&vcpu->wq)) {
4836 wake_up_interruptible(&vcpu->wq);
4837 ++vcpu->stat.halt_wakeup;
4838 }
32f88400
MT		 4839
4840 me = get_cpu();
4841 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4842 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4843 smp_send_reschedule(cpu);
e9571ed5 4844 put_cpu();
5736199a 4845}
78646121
GN		 4846
4847int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4848{
4849 return kvm_x86_ops->interrupt_allowed(vcpu);
4850}
229456fc
MT		 4851
4852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Clone of davem's net-next-2.6 tree