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x86: Add EFER descriptions for FFXSR
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
043405e1
CO		 39
40#include <asm/uaccess.h>
d825ed0a 41#include <asm/msr.h>
a5f61300 42#include <asm/desc.h>
0bed3b56 43#include <asm/mtrr.h>
043405e1 44
313a3dc7 45#define MAX_IO_MSRS 256
a03490ed
CO		 46#define CR0_RESERVED_BITS \
47 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
48 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
49 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
50#define CR4_RESERVED_BITS \
51 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
52 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
53 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
54 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
55
56#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 57/* EFER defaults:
58 * - enable syscall per default because its emulated by KVM
59 * - enable LME and LMA per default on 64 bit KVM
60 */
61#ifdef CONFIG_X86_64
62static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
63#else
64static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
65#endif
313a3dc7 66
ba1389b7
AK		 67#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
68#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 69
674eea0f
AK		 70static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
71 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 72struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
73 u32 function, u32 index);
674eea0f 74
97896d04 75struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 76EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 77
417bc304 78struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 79 { "pf_fixed", VCPU_STAT(pf_fixed) },
80 { "pf_guest", VCPU_STAT(pf_guest) },
81 { "tlb_flush", VCPU_STAT(tlb_flush) },
82 { "invlpg", VCPU_STAT(invlpg) },
83 { "exits", VCPU_STAT(exits) },
84 { "io_exits", VCPU_STAT(io_exits) },
85 { "mmio_exits", VCPU_STAT(mmio_exits) },
86 { "signal_exits", VCPU_STAT(signal_exits) },
87 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 88 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 89 { "halt_exits", VCPU_STAT(halt_exits) },
90 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 91 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 92 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 93 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 94 { "irq_exits", VCPU_STAT(irq_exits) },
95 { "host_state_reload", VCPU_STAT(host_state_reload) },
96 { "efer_reload", VCPU_STAT(efer_reload) },
97 { "fpu_reload", VCPU_STAT(fpu_reload) },
98 { "insn_emulation", VCPU_STAT(insn_emulation) },
99 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 100 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 101 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 102 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
103 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
104 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
105 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
106 { "mmu_flooded", VM_STAT(mmu_flooded) },
107 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 108 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 109 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 110 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 111 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 112 { "largepages", VM_STAT(lpages) },
417bc304
HB		 113 { NULL }
114};
115
5fb76f9b
CO		 116unsigned long segment_base(u16 selector)
117{
118 struct descriptor_table gdt;
a5f61300 119 struct desc_struct *d;
5fb76f9b
CO		 120 unsigned long table_base;
121 unsigned long v;
122
123 if (selector == 0)
124 return 0;
125
126 asm("sgdt %0" : "=m"(gdt));
127 table_base = gdt.base;
128
129 if (selector & 4) { /* from ldt */
130 u16 ldt_selector;
131
132 asm("sldt %0" : "=g"(ldt_selector));
133 table_base = segment_base(ldt_selector);
134 }
a5f61300
AK		 135 d = (struct desc_struct *)(table_base + (selector & ~7));
136 v = d->base0 | ((unsigned long)d->base1 << 16) |
137 ((unsigned long)d->base2 << 24);
5fb76f9b 138#ifdef CONFIG_X86_64
a5f61300
AK		 139 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
140 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 141#endif
142 return v;
143}
144EXPORT_SYMBOL_GPL(segment_base);
145
6866b83e
CO		 146u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
147{
148 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 149 return vcpu->arch.apic_base;
6866b83e 150 else
ad312c7c 151 return vcpu->arch.apic_base;
6866b83e
CO		 152}
153EXPORT_SYMBOL_GPL(kvm_get_apic_base);
154
155void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
156{
157 /* TODO: reserve bits check */
158 if (irqchip_in_kernel(vcpu->kvm))
159 kvm_lapic_set_base(vcpu, data);
160 else
ad312c7c 161 vcpu->arch.apic_base = data;
6866b83e
CO		 162}
163EXPORT_SYMBOL_GPL(kvm_set_apic_base);
164
298101da
AK		 165void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
166{
ad312c7c
ZX		 167 WARN_ON(vcpu->arch.exception.pending);
168 vcpu->arch.exception.pending = true;
169 vcpu->arch.exception.has_error_code = false;
170 vcpu->arch.exception.nr = nr;
298101da
AK		 171}
172EXPORT_SYMBOL_GPL(kvm_queue_exception);
173
c3c91fee
AK		 174void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
175 u32 error_code)
176{
177 ++vcpu->stat.pf_guest;
d8017474 178
71c4dfaf
JR		 179 if (vcpu->arch.exception.pending) {
180 if (vcpu->arch.exception.nr == PF_VECTOR) {
181 printk(KERN_DEBUG "kvm: inject_page_fault:"
182 " double fault 0x%lx\n", addr);
183 vcpu->arch.exception.nr = DF_VECTOR;
184 vcpu->arch.exception.error_code = 0;
185 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
186 /* triple fault -> shutdown */
187 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
188 }
c3c91fee
AK		 189 return;
190 }
ad312c7c 191 vcpu->arch.cr2 = addr;
c3c91fee
AK		 192 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
193}
194
3419ffc8
SY		 195void kvm_inject_nmi(struct kvm_vcpu *vcpu)
196{
197 vcpu->arch.nmi_pending = 1;
198}
199EXPORT_SYMBOL_GPL(kvm_inject_nmi);
200
298101da
AK		 201void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
202{
ad312c7c
ZX		 203 WARN_ON(vcpu->arch.exception.pending);
204 vcpu->arch.exception.pending = true;
205 vcpu->arch.exception.has_error_code = true;
206 vcpu->arch.exception.nr = nr;
207 vcpu->arch.exception.error_code = error_code;
298101da
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
210
211static void __queue_exception(struct kvm_vcpu *vcpu)
212{
ad312c7c
ZX		 213 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
214 vcpu->arch.exception.has_error_code,
215 vcpu->arch.exception.error_code);
298101da
AK		 216}
217
a03490ed
CO		 218/*
219 * Load the pae pdptrs. Return true is they are all valid.
220 */
221int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
222{
223 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
224 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
225 int i;
226 int ret;
ad312c7c 227 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 228
a03490ed
CO		 229 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
230 offset * sizeof(u64), sizeof(pdpte));
231 if (ret < 0) {
232 ret = 0;
233 goto out;
234 }
235 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
236 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
237 ret = 0;
238 goto out;
239 }
240 }
241 ret = 1;
242
ad312c7c 243 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 244out:
a03490ed
CO		 245
246 return ret;
247}
cc4b6871 248EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 249
d835dfec
AK		 250static bool pdptrs_changed(struct kvm_vcpu *vcpu)
251{
ad312c7c 252 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 253 bool changed = true;
254 int r;
255
256 if (is_long_mode(vcpu) || !is_pae(vcpu))
257 return false;
258
ad312c7c 259 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 260 if (r < 0)
261 goto out;
ad312c7c 262 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 263out:
d835dfec
AK		 264
265 return changed;
266}
267
2d3ad1f4 268void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 269{
270 if (cr0 & CR0_RESERVED_BITS) {
271 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 272 cr0, vcpu->arch.cr0);
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276
277 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
278 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 279 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 280 return;
281 }
282
283 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
284 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
285 "and a clear PE flag\n");
c1a5d4f9 286 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 287 return;
288 }
289
290 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
291#ifdef CONFIG_X86_64
ad312c7c 292 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 293 int cs_db, cs_l;
294
295 if (!is_pae(vcpu)) {
296 printk(KERN_DEBUG "set_cr0: #GP, start paging "
297 "in long mode while PAE is disabled\n");
c1a5d4f9 298 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 299 return;
300 }
301 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
302 if (cs_l) {
303 printk(KERN_DEBUG "set_cr0: #GP, start paging "
304 "in long mode while CS.L == 1\n");
c1a5d4f9 305 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 306 return;
307
308 }
309 } else
310#endif
ad312c7c 311 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 312 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
313 "reserved bits\n");
c1a5d4f9 314 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 315 return;
316 }
317
318 }
319
320 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 321 vcpu->arch.cr0 = cr0;
a03490ed 322
6cffe8ca 323 kvm_mmu_sync_global(vcpu);
a03490ed 324 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 325 return;
326}
2d3ad1f4 327EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 328
2d3ad1f4 329void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 330{
2d3ad1f4 331 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 332 KVMTRACE_1D(LMSW, vcpu,
333 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
334 handler);
a03490ed 335}
2d3ad1f4 336EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 337
2d3ad1f4 338void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 339{
340 if (cr4 & CR4_RESERVED_BITS) {
341 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 342 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 343 return;
344 }
345
346 if (is_long_mode(vcpu)) {
347 if (!(cr4 & X86_CR4_PAE)) {
348 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
349 "in long mode\n");
c1a5d4f9 350 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 351 return;
352 }
353 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 354 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 355 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359
360 if (cr4 & X86_CR4_VMXE) {
361 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 366 vcpu->arch.cr4 = cr4;
5a41accd 367 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
6cffe8ca 368 kvm_mmu_sync_global(vcpu);
a03490ed 369 kvm_mmu_reset_context(vcpu);
a03490ed 370}
2d3ad1f4 371EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 372
2d3ad1f4 373void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 374{
ad312c7c 375 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 376 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 377 kvm_mmu_flush_tlb(vcpu);
378 return;
379 }
380
a03490ed
CO		 381 if (is_long_mode(vcpu)) {
382 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
383 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 384 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 385 return;
386 }
387 } else {
388 if (is_pae(vcpu)) {
389 if (cr3 & CR3_PAE_RESERVED_BITS) {
390 printk(KERN_DEBUG
391 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 392 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 393 return;
394 }
395 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
396 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
397 "reserved bits\n");
c1a5d4f9 398 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 399 return;
400 }
401 }
402 /*
403 * We don't check reserved bits in nonpae mode, because
404 * this isn't enforced, and VMware depends on this.
405 */
406 }
407
a03490ed
CO		 408 /*
409 * Does the new cr3 value map to physical memory? (Note, we
410 * catch an invalid cr3 even in real-mode, because it would
411 * cause trouble later on when we turn on paging anyway.)
412 *
413 * A real CPU would silently accept an invalid cr3 and would
414 * attempt to use it - with largely undefined (and often hard
415 * to debug) behavior on the guest side.
416 */
417 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 418 kvm_inject_gp(vcpu, 0);
a03490ed 419 else {
ad312c7c
ZX		 420 vcpu->arch.cr3 = cr3;
421 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 422 }
a03490ed 423}
2d3ad1f4 424EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 425
2d3ad1f4 426void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 427{
428 if (cr8 & CR8_RESERVED_BITS) {
429 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 430 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 431 return;
432 }
433 if (irqchip_in_kernel(vcpu->kvm))
434 kvm_lapic_set_tpr(vcpu, cr8);
435 else
ad312c7c 436 vcpu->arch.cr8 = cr8;
a03490ed 437}
2d3ad1f4 438EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 439
2d3ad1f4 440unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 441{
442 if (irqchip_in_kernel(vcpu->kvm))
443 return kvm_lapic_get_cr8(vcpu);
444 else
ad312c7c 445 return vcpu->arch.cr8;
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 448
d8017474
AG		 449static inline u32 bit(int bitno)
450{
451 return 1 << (bitno & 31);
452}
453
043405e1
CO		 454/*
455 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
456 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
457 *
458 * This list is modified at module load time to reflect the
459 * capabilities of the host cpu.
460 */
461static u32 msrs_to_save[] = {
462 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
463 MSR_K6_STAR,
464#ifdef CONFIG_X86_64
465 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
466#endif
18068523 467 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 468 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 469};
470
471static unsigned num_msrs_to_save;
472
473static u32 emulated_msrs[] = {
474 MSR_IA32_MISC_ENABLE,
475};
476
15c4a640
CO		 477static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
478{
f2b4b7dd 479 if (efer & efer_reserved_bits) {
15c4a640
CO		 480 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
481 efer);
c1a5d4f9 482 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 483 return;
484 }
485
486 if (is_paging(vcpu)
ad312c7c 487 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 488 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 489 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 490 return;
491 }
492
d8017474
AG		 493 if (efer & EFER_SVME) {
494 struct kvm_cpuid_entry2 *feat;
495
496 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
497 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
498 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
499 kvm_inject_gp(vcpu, 0);
500 return;
501 }
502 }
503
15c4a640
CO		 504 kvm_x86_ops->set_efer(vcpu, efer);
505
506 efer &= ~EFER_LMA;
ad312c7c 507 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 508
ad312c7c 509 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 510}
511
f2b4b7dd
JR		 512void kvm_enable_efer_bits(u64 mask)
513{
514 efer_reserved_bits &= ~mask;
515}
516EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
517
518
15c4a640
CO		 519/*
520 * Writes msr value into into the appropriate "register".
521 * Returns 0 on success, non-0 otherwise.
522 * Assumes vcpu_load() was already called.
523 */
524int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
525{
526 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
527}
528
313a3dc7
CO		 529/*
530 * Adapt set_msr() to msr_io()'s calling convention
531 */
532static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
533{
534 return kvm_set_msr(vcpu, index, *data);
535}
536
18068523
GOC		 537static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
538{
539 static int version;
50d0a0f9
GH		 540 struct pvclock_wall_clock wc;
541 struct timespec now, sys, boot;
18068523
GOC		 542
543 if (!wall_clock)
544 return;
545
546 version++;
547
18068523
GOC		 548 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
549
50d0a0f9
GH		 550 /*
551 * The guest calculates current wall clock time by adding
552 * system time (updated by kvm_write_guest_time below) to the
553 * wall clock specified here. guest system time equals host
554 * system time for us, thus we must fill in host boot time here.
555 */
556 now = current_kernel_time();
557 ktime_get_ts(&sys);
558 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
559
560 wc.sec = boot.tv_sec;
561 wc.nsec = boot.tv_nsec;
562 wc.version = version;
18068523
GOC		 563
564 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
565
566 version++;
567 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 568}
569
50d0a0f9
GH		 570static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
571{
572 uint32_t quotient, remainder;
573
574 /* Don't try to replace with do_div(), this one calculates
575 * "(dividend << 32) / divisor" */
576 __asm__ ( "divl %4"
577 : "=a" (quotient), "=d" (remainder)
578 : "0" (0), "1" (dividend), "r" (divisor) );
579 return quotient;
580}
581
582static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
583{
584 uint64_t nsecs = 1000000000LL;
585 int32_t shift = 0;
586 uint64_t tps64;
587 uint32_t tps32;
588
589 tps64 = tsc_khz * 1000LL;
590 while (tps64 > nsecs*2) {
591 tps64 >>= 1;
592 shift--;
593 }
594
595 tps32 = (uint32_t)tps64;
596 while (tps32 <= (uint32_t)nsecs) {
597 tps32 <<= 1;
598 shift++;
599 }
600
601 hv_clock->tsc_shift = shift;
602 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
603
604 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 605 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 606 hv_clock->tsc_to_system_mul);
607}
608
18068523
GOC		 609static void kvm_write_guest_time(struct kvm_vcpu *v)
610{
611 struct timespec ts;
612 unsigned long flags;
613 struct kvm_vcpu_arch *vcpu = &v->arch;
614 void *shared_kaddr;
615
616 if ((!vcpu->time_page))
617 return;
618
50d0a0f9
GH		 619 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
620 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
621 vcpu->hv_clock_tsc_khz = tsc_khz;
622 }
623
18068523
GOC		 624 /* Keep irq disabled to prevent changes to the clock */
625 local_irq_save(flags);
626 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
627 &vcpu->hv_clock.tsc_timestamp);
628 ktime_get_ts(&ts);
629 local_irq_restore(flags);
630
631 /* With all the info we got, fill in the values */
632
633 vcpu->hv_clock.system_time = ts.tv_nsec +
634 (NSEC_PER_SEC * (u64)ts.tv_sec);
635 /*
636 * The interface expects us to write an even number signaling that the
637 * update is finished. Since the guest won't see the intermediate
50d0a0f9 638 * state, we just increase by 2 at the end.
18068523 639 */
50d0a0f9 640 vcpu->hv_clock.version += 2;
18068523
GOC		 641
642 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
643
644 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 645 sizeof(vcpu->hv_clock));
18068523
GOC		 646
647 kunmap_atomic(shared_kaddr, KM_USER0);
648
649 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
650}
651
9ba075a6
AK		 652static bool msr_mtrr_valid(unsigned msr)
653{
654 switch (msr) {
655 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
656 case MSR_MTRRfix64K_00000:
657 case MSR_MTRRfix16K_80000:
658 case MSR_MTRRfix16K_A0000:
659 case MSR_MTRRfix4K_C0000:
660 case MSR_MTRRfix4K_C8000:
661 case MSR_MTRRfix4K_D0000:
662 case MSR_MTRRfix4K_D8000:
663 case MSR_MTRRfix4K_E0000:
664 case MSR_MTRRfix4K_E8000:
665 case MSR_MTRRfix4K_F0000:
666 case MSR_MTRRfix4K_F8000:
667 case MSR_MTRRdefType:
668 case MSR_IA32_CR_PAT:
669 return true;
670 case 0x2f8:
671 return true;
672 }
673 return false;
674}
675
676static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
677{
0bed3b56
SY		 678 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
679
9ba075a6
AK		 680 if (!msr_mtrr_valid(msr))
681 return 1;
682
0bed3b56
SY		 683 if (msr == MSR_MTRRdefType) {
684 vcpu->arch.mtrr_state.def_type = data;
685 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
686 } else if (msr == MSR_MTRRfix64K_00000)
687 p[0] = data;
688 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
689 p[1 + msr - MSR_MTRRfix16K_80000] = data;
690 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
691 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
692 else if (msr == MSR_IA32_CR_PAT)
693 vcpu->arch.pat = data;
694 else { /* Variable MTRRs */
695 int idx, is_mtrr_mask;
696 u64 *pt;
697
698 idx = (msr - 0x200) / 2;
699 is_mtrr_mask = msr - 0x200 - 2 * idx;
700 if (!is_mtrr_mask)
701 pt =
702 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
703 else
704 pt =
705 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
706 *pt = data;
707 }
708
709 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 710 return 0;
711}
15c4a640
CO		 712
713int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
714{
715 switch (msr) {
15c4a640
CO		 716 case MSR_EFER:
717 set_efer(vcpu, data);
718 break;
15c4a640
CO		 719 case MSR_IA32_MC0_STATUS:
720 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 721 __func__, data);
15c4a640
CO		 722 break;
723 case MSR_IA32_MCG_STATUS:
724 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 725 __func__, data);
15c4a640 726 break;
c7ac679c
JR		 727 case MSR_IA32_MCG_CTL:
728 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 729 __func__, data);
c7ac679c 730 break;
b5e2fec0
AG		 731 case MSR_IA32_DEBUGCTLMSR:
732 if (!data) {
733 /* We support the non-activated case already */
734 break;
735 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
736 /* Values other than LBR and BTF are vendor-specific,
737 thus reserved and should throw a #GP */
738 return 1;
739 }
740 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
741 __func__, data);
742 break;
15c4a640
CO		 743 case MSR_IA32_UCODE_REV:
744 case MSR_IA32_UCODE_WRITE:
61a6bd67 745 case MSR_VM_HSAVE_PA:
15c4a640 746 break;
9ba075a6
AK		 747 case 0x200 ... 0x2ff:
748 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 749 case MSR_IA32_APICBASE:
750 kvm_set_apic_base(vcpu, data);
751 break;
752 case MSR_IA32_MISC_ENABLE:
ad312c7c 753 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 754 break;
18068523
GOC		 755 case MSR_KVM_WALL_CLOCK:
756 vcpu->kvm->arch.wall_clock = data;
757 kvm_write_wall_clock(vcpu->kvm, data);
758 break;
759 case MSR_KVM_SYSTEM_TIME: {
760 if (vcpu->arch.time_page) {
761 kvm_release_page_dirty(vcpu->arch.time_page);
762 vcpu->arch.time_page = NULL;
763 }
764
765 vcpu->arch.time = data;
766
767 /* we verify if the enable bit is set... */
768 if (!(data & 1))
769 break;
770
771 /* ...but clean it before doing the actual write */
772 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
773
18068523
GOC		 774 vcpu->arch.time_page =
775 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 776
777 if (is_error_page(vcpu->arch.time_page)) {
778 kvm_release_page_clean(vcpu->arch.time_page);
779 vcpu->arch.time_page = NULL;
780 }
781
782 kvm_write_guest_time(vcpu);
783 break;
784 }
15c4a640 785 default:
565f1fbd 786 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 787 return 1;
788 }
789 return 0;
790}
791EXPORT_SYMBOL_GPL(kvm_set_msr_common);
792
793
794/*
795 * Reads an msr value (of 'msr_index') into 'pdata'.
796 * Returns 0 on success, non-0 otherwise.
797 * Assumes vcpu_load() was already called.
798 */
799int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
800{
801 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
802}
803
9ba075a6
AK		 804static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
805{
0bed3b56
SY		 806 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
807
9ba075a6
AK		 808 if (!msr_mtrr_valid(msr))
809 return 1;
810
0bed3b56
SY		 811 if (msr == MSR_MTRRdefType)
812 *pdata = vcpu->arch.mtrr_state.def_type +
813 (vcpu->arch.mtrr_state.enabled << 10);
814 else if (msr == MSR_MTRRfix64K_00000)
815 *pdata = p[0];
816 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
817 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
818 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
819 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
820 else if (msr == MSR_IA32_CR_PAT)
821 *pdata = vcpu->arch.pat;
822 else { /* Variable MTRRs */
823 int idx, is_mtrr_mask;
824 u64 *pt;
825
826 idx = (msr - 0x200) / 2;
827 is_mtrr_mask = msr - 0x200 - 2 * idx;
828 if (!is_mtrr_mask)
829 pt =
830 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
831 else
832 pt =
833 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
834 *pdata = *pt;
835 }
836
9ba075a6
AK		 837 return 0;
838}
839
15c4a640
CO		 840int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
841{
842 u64 data;
843
844 switch (msr) {
845 case 0xc0010010: /* SYSCFG */
846 case 0xc0010015: /* HWCR */
847 case MSR_IA32_PLATFORM_ID:
848 case MSR_IA32_P5_MC_ADDR:
849 case MSR_IA32_P5_MC_TYPE:
850 case MSR_IA32_MC0_CTL:
851 case MSR_IA32_MCG_STATUS:
852 case MSR_IA32_MCG_CAP:
c7ac679c 853 case MSR_IA32_MCG_CTL:
15c4a640
CO		 854 case MSR_IA32_MC0_MISC:
855 case MSR_IA32_MC0_MISC+4:
856 case MSR_IA32_MC0_MISC+8:
857 case MSR_IA32_MC0_MISC+12:
858 case MSR_IA32_MC0_MISC+16:
a89c1ad2 859 case MSR_IA32_MC0_MISC+20:
15c4a640 860 case MSR_IA32_UCODE_REV:
15c4a640 861 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 862 case MSR_IA32_DEBUGCTLMSR:
863 case MSR_IA32_LASTBRANCHFROMIP:
864 case MSR_IA32_LASTBRANCHTOIP:
865 case MSR_IA32_LASTINTFROMIP:
866 case MSR_IA32_LASTINTTOIP:
61a6bd67 867 case MSR_VM_HSAVE_PA:
15c4a640
CO		 868 data = 0;
869 break;
9ba075a6
AK		 870 case MSR_MTRRcap:
871 data = 0x500 | KVM_NR_VAR_MTRR;
872 break;
873 case 0x200 ... 0x2ff:
874 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 875 case 0xcd: /* fsb frequency */
876 data = 3;
877 break;
878 case MSR_IA32_APICBASE:
879 data = kvm_get_apic_base(vcpu);
880 break;
881 case MSR_IA32_MISC_ENABLE:
ad312c7c 882 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 883 break;
847f0ad8
AG		 884 case MSR_IA32_PERF_STATUS:
885 /* TSC increment by tick */
886 data = 1000ULL;
887 /* CPU multiplier */
888 data |= (((uint64_t)4ULL) << 40);
889 break;
15c4a640 890 case MSR_EFER:
ad312c7c 891 data = vcpu->arch.shadow_efer;
15c4a640 892 break;
18068523
GOC		 893 case MSR_KVM_WALL_CLOCK:
894 data = vcpu->kvm->arch.wall_clock;
895 break;
896 case MSR_KVM_SYSTEM_TIME:
897 data = vcpu->arch.time;
898 break;
15c4a640
CO		 899 default:
900 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
901 return 1;
902 }
903 *pdata = data;
904 return 0;
905}
906EXPORT_SYMBOL_GPL(kvm_get_msr_common);
907
313a3dc7
CO		 908/*
909 * Read or write a bunch of msrs. All parameters are kernel addresses.
910 *
911 * @return number of msrs set successfully.
912 */
913static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
914 struct kvm_msr_entry *entries,
915 int (*do_msr)(struct kvm_vcpu *vcpu,
916 unsigned index, u64 *data))
917{
918 int i;
919
920 vcpu_load(vcpu);
921
3200f405 922 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 923 for (i = 0; i < msrs->nmsrs; ++i)
924 if (do_msr(vcpu, entries[i].index, &entries[i].data))
925 break;
3200f405 926 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 927
928 vcpu_put(vcpu);
929
930 return i;
931}
932
933/*
934 * Read or write a bunch of msrs. Parameters are user addresses.
935 *
936 * @return number of msrs set successfully.
937 */
938static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
939 int (*do_msr)(struct kvm_vcpu *vcpu,
940 unsigned index, u64 *data),
941 int writeback)
942{
943 struct kvm_msrs msrs;
944 struct kvm_msr_entry *entries;
945 int r, n;
946 unsigned size;
947
948 r = -EFAULT;
949 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
950 goto out;
951
952 r = -E2BIG;
953 if (msrs.nmsrs >= MAX_IO_MSRS)
954 goto out;
955
956 r = -ENOMEM;
957 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
958 entries = vmalloc(size);
959 if (!entries)
960 goto out;
961
962 r = -EFAULT;
963 if (copy_from_user(entries, user_msrs->entries, size))
964 goto out_free;
965
966 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
967 if (r < 0)
968 goto out_free;
969
970 r = -EFAULT;
971 if (writeback && copy_to_user(user_msrs->entries, entries, size))
972 goto out_free;
973
974 r = n;
975
976out_free:
977 vfree(entries);
978out:
979 return r;
980}
981
018d00d2
ZX		 982int kvm_dev_ioctl_check_extension(long ext)
983{
984 int r;
985
986 switch (ext) {
987 case KVM_CAP_IRQCHIP:
988 case KVM_CAP_HLT:
989 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 990 case KVM_CAP_SET_TSS_ADDR:
07716717 991 case KVM_CAP_EXT_CPUID:
7837699f 992 case KVM_CAP_PIT:
a28e4f5a 993 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 994 case KVM_CAP_MP_STATE:
ed848624 995 case KVM_CAP_SYNC_MMU:
52d939a0 996 case KVM_CAP_REINJECT_CONTROL:
018d00d2
ZX		 997 r = 1;
998 break;
542472b5
LV		 999 case KVM_CAP_COALESCED_MMIO:
1000 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1001 break;
774ead3a
AK		 1002 case KVM_CAP_VAPIC:
1003 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1004 break;
f725230a
AK		 1005 case KVM_CAP_NR_VCPUS:
1006 r = KVM_MAX_VCPUS;
1007 break;
a988b910
AK		 1008 case KVM_CAP_NR_MEMSLOTS:
1009 r = KVM_MEMORY_SLOTS;
1010 break;
2f333bcb
MT		 1011 case KVM_CAP_PV_MMU:
1012 r = !tdp_enabled;
1013 break;
62c476c7 1014 case KVM_CAP_IOMMU:
19de40a8 1015 r = iommu_found();
62c476c7 1016 break;
abe6655d
MT		 1017 case KVM_CAP_CLOCKSOURCE:
1018 r = boot_cpu_has(X86_FEATURE_CONSTANT_TSC);
1019 break;
018d00d2
ZX		 1020 default:
1021 r = 0;
1022 break;
1023 }
1024 return r;
1025
1026}
1027
043405e1
CO		 1028long kvm_arch_dev_ioctl(struct file *filp,
1029 unsigned int ioctl, unsigned long arg)
1030{
1031 void __user *argp = (void __user *)arg;
1032 long r;
1033
1034 switch (ioctl) {
1035 case KVM_GET_MSR_INDEX_LIST: {
1036 struct kvm_msr_list __user *user_msr_list = argp;
1037 struct kvm_msr_list msr_list;
1038 unsigned n;
1039
1040 r = -EFAULT;
1041 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1042 goto out;
1043 n = msr_list.nmsrs;
1044 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1045 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1046 goto out;
1047 r = -E2BIG;
1048 if (n < num_msrs_to_save)
1049 goto out;
1050 r = -EFAULT;
1051 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1052 num_msrs_to_save * sizeof(u32)))
1053 goto out;
1054 if (copy_to_user(user_msr_list->indices
1055 + num_msrs_to_save * sizeof(u32),
1056 &emulated_msrs,
1057 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1058 goto out;
1059 r = 0;
1060 break;
1061 }
674eea0f
AK		 1062 case KVM_GET_SUPPORTED_CPUID: {
1063 struct kvm_cpuid2 __user *cpuid_arg = argp;
1064 struct kvm_cpuid2 cpuid;
1065
1066 r = -EFAULT;
1067 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1068 goto out;
1069 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1070 cpuid_arg->entries);
674eea0f
AK		 1071 if (r)
1072 goto out;
1073
1074 r = -EFAULT;
1075 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1076 goto out;
1077 r = 0;
1078 break;
1079 }
043405e1
CO		 1080 default:
1081 r = -EINVAL;
1082 }
1083out:
1084 return r;
1085}
1086
313a3dc7
CO		 1087void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1088{
1089 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1090 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1091}
1092
1093void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1094{
1095 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1096 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1097}
1098
07716717 1099static int is_efer_nx(void)
313a3dc7
CO		 1100{
1101 u64 efer;
313a3dc7
CO		 1102
1103 rdmsrl(MSR_EFER, efer);
07716717
DK		 1104 return efer & EFER_NX;
1105}
1106
1107static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1108{
1109 int i;
1110 struct kvm_cpuid_entry2 *e, *entry;
1111
313a3dc7 1112 entry = NULL;
ad312c7c
ZX		 1113 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1114 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1115 if (e->function == 0x80000001) {
1116 entry = e;
1117 break;
1118 }
1119 }
07716717 1120 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1121 entry->edx &= ~(1 << 20);
1122 printk(KERN_INFO "kvm: guest NX capability removed\n");
1123 }
1124}
1125
07716717 1126/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1127static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1128 struct kvm_cpuid *cpuid,
1129 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1130{
1131 int r, i;
1132 struct kvm_cpuid_entry *cpuid_entries;
1133
1134 r = -E2BIG;
1135 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1136 goto out;
1137 r = -ENOMEM;
1138 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1139 if (!cpuid_entries)
1140 goto out;
1141 r = -EFAULT;
1142 if (copy_from_user(cpuid_entries, entries,
1143 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1144 goto out_free;
1145 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1146 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1147 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1148 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1149 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1150 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1151 vcpu->arch.cpuid_entries[i].index = 0;
1152 vcpu->arch.cpuid_entries[i].flags = 0;
1153 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1154 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1155 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1156 }
1157 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1158 cpuid_fix_nx_cap(vcpu);
1159 r = 0;
1160
1161out_free:
1162 vfree(cpuid_entries);
1163out:
1164 return r;
1165}
1166
1167static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1168 struct kvm_cpuid2 *cpuid,
1169 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1170{
1171 int r;
1172
1173 r = -E2BIG;
1174 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1175 goto out;
1176 r = -EFAULT;
ad312c7c 1177 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1178 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1179 goto out;
ad312c7c 1180 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1181 return 0;
1182
1183out:
1184 return r;
1185}
1186
07716717 1187static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1188 struct kvm_cpuid2 *cpuid,
1189 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1190{
1191 int r;
1192
1193 r = -E2BIG;
ad312c7c 1194 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1195 goto out;
1196 r = -EFAULT;
ad312c7c 1197 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1198 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1199 goto out;
1200 return 0;
1201
1202out:
ad312c7c 1203 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1204 return r;
1205}
1206
07716717 1207static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1208 u32 index)
07716717
DK		 1209{
1210 entry->function = function;
1211 entry->index = index;
1212 cpuid_count(entry->function, entry->index,
19355475 1213 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1214 entry->flags = 0;
1215}
1216
1217static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1218 u32 index, int *nent, int maxnent)
1219{
1220 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1221 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1222 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1223 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1224 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1225 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1226 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1227 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1228 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1229 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1230 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1231 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1232 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1233 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1234 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1235 bit(X86_FEATURE_PGE) |
1236 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1237 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1238 bit(X86_FEATURE_SYSCALL) |
1239 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1240#ifdef CONFIG_X86_64
1241 bit(X86_FEATURE_LM) |
1242#endif
1243 bit(X86_FEATURE_MMXEXT) |
1244 bit(X86_FEATURE_3DNOWEXT) |
1245 bit(X86_FEATURE_3DNOW);
1246 const u32 kvm_supported_word3_x86_features =
1247 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1248 const u32 kvm_supported_word6_x86_features =
d8017474
AG		 1249 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) |
1250 bit(X86_FEATURE_SVM);
07716717 1251
19355475 1252 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1253 get_cpu();
1254 do_cpuid_1_ent(entry, function, index);
1255 ++*nent;
1256
1257 switch (function) {
1258 case 0:
1259 entry->eax = min(entry->eax, (u32)0xb);
1260 break;
1261 case 1:
1262 entry->edx &= kvm_supported_word0_x86_features;
1263 entry->ecx &= kvm_supported_word3_x86_features;
1264 break;
1265 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1266 * may return different values. This forces us to get_cpu() before
1267 * issuing the first command, and also to emulate this annoying behavior
1268 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1269 case 2: {
1270 int t, times = entry->eax & 0xff;
1271
1272 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1273 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1274 for (t = 1; t < times && *nent < maxnent; ++t) {
1275 do_cpuid_1_ent(&entry[t], function, 0);
1276 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1277 ++*nent;
1278 }
1279 break;
1280 }
1281 /* function 4 and 0xb have additional index. */
1282 case 4: {
14af3f3c 1283 int i, cache_type;
07716717
DK		 1284
1285 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1286 /* read more entries until cache_type is zero */
14af3f3c
HH		 1287 for (i = 1; *nent < maxnent; ++i) {
1288 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1289 if (!cache_type)
1290 break;
14af3f3c
HH		 1291 do_cpuid_1_ent(&entry[i], function, i);
1292 entry[i].flags |=
07716717
DK		 1293 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1294 ++*nent;
1295 }
1296 break;
1297 }
1298 case 0xb: {
14af3f3c 1299 int i, level_type;
07716717
DK		 1300
1301 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1302 /* read more entries until level_type is zero */
14af3f3c 1303 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1304 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1305 if (!level_type)
1306 break;
14af3f3c
HH		 1307 do_cpuid_1_ent(&entry[i], function, i);
1308 entry[i].flags |=
07716717
DK		 1309 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1310 ++*nent;
1311 }
1312 break;
1313 }
1314 case 0x80000000:
1315 entry->eax = min(entry->eax, 0x8000001a);
1316 break;
1317 case 0x80000001:
1318 entry->edx &= kvm_supported_word1_x86_features;
1319 entry->ecx &= kvm_supported_word6_x86_features;
1320 break;
1321 }
1322 put_cpu();
1323}
1324
674eea0f 1325static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1326 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1327{
1328 struct kvm_cpuid_entry2 *cpuid_entries;
1329 int limit, nent = 0, r = -E2BIG;
1330 u32 func;
1331
1332 if (cpuid->nent < 1)
1333 goto out;
1334 r = -ENOMEM;
1335 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1336 if (!cpuid_entries)
1337 goto out;
1338
1339 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1340 limit = cpuid_entries[0].eax;
1341 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1342 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1343 &nent, cpuid->nent);
07716717
DK		 1344 r = -E2BIG;
1345 if (nent >= cpuid->nent)
1346 goto out_free;
1347
1348 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1349 limit = cpuid_entries[nent - 1].eax;
1350 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1351 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1352 &nent, cpuid->nent);
07716717
DK		 1353 r = -EFAULT;
1354 if (copy_to_user(entries, cpuid_entries,
19355475 1355 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1356 goto out_free;
1357 cpuid->nent = nent;
1358 r = 0;
1359
1360out_free:
1361 vfree(cpuid_entries);
1362out:
1363 return r;
1364}
1365
313a3dc7
CO		 1366static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1367 struct kvm_lapic_state *s)
1368{
1369 vcpu_load(vcpu);
ad312c7c 1370 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1371 vcpu_put(vcpu);
1372
1373 return 0;
1374}
1375
1376static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1377 struct kvm_lapic_state *s)
1378{
1379 vcpu_load(vcpu);
ad312c7c 1380 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1381 kvm_apic_post_state_restore(vcpu);
1382 vcpu_put(vcpu);
1383
1384 return 0;
1385}
1386
f77bc6a4
ZX		 1387static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1388 struct kvm_interrupt *irq)
1389{
1390 if (irq->irq < 0 || irq->irq >= 256)
1391 return -EINVAL;
1392 if (irqchip_in_kernel(vcpu->kvm))
1393 return -ENXIO;
1394 vcpu_load(vcpu);
1395
ad312c7c
ZX		 1396 set_bit(irq->irq, vcpu->arch.irq_pending);
1397 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1398
1399 vcpu_put(vcpu);
1400
1401 return 0;
1402}
1403
c4abb7c9
JK		 1404static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1405{
1406 vcpu_load(vcpu);
1407 kvm_inject_nmi(vcpu);
1408 vcpu_put(vcpu);
1409
1410 return 0;
1411}
1412
b209749f
AK		 1413static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1414 struct kvm_tpr_access_ctl *tac)
1415{
1416 if (tac->flags)
1417 return -EINVAL;
1418 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1419 return 0;
1420}
1421
313a3dc7
CO		 1422long kvm_arch_vcpu_ioctl(struct file *filp,
1423 unsigned int ioctl, unsigned long arg)
1424{
1425 struct kvm_vcpu *vcpu = filp->private_data;
1426 void __user *argp = (void __user *)arg;
1427 int r;
b772ff36 1428 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1429
1430 switch (ioctl) {
1431 case KVM_GET_LAPIC: {
b772ff36 1432 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1433
b772ff36
DH		 1434 r = -ENOMEM;
1435 if (!lapic)
1436 goto out;
1437 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1438 if (r)
1439 goto out;
1440 r = -EFAULT;
b772ff36 1441 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1442 goto out;
1443 r = 0;
1444 break;
1445 }
1446 case KVM_SET_LAPIC: {
b772ff36
DH		 1447 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1448 r = -ENOMEM;
1449 if (!lapic)
1450 goto out;
313a3dc7 1451 r = -EFAULT;
b772ff36 1452 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1453 goto out;
b772ff36 1454 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1455 if (r)
1456 goto out;
1457 r = 0;
1458 break;
1459 }
f77bc6a4
ZX		 1460 case KVM_INTERRUPT: {
1461 struct kvm_interrupt irq;
1462
1463 r = -EFAULT;
1464 if (copy_from_user(&irq, argp, sizeof irq))
1465 goto out;
1466 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1467 if (r)
1468 goto out;
1469 r = 0;
1470 break;
1471 }
c4abb7c9
JK		 1472 case KVM_NMI: {
1473 r = kvm_vcpu_ioctl_nmi(vcpu);
1474 if (r)
1475 goto out;
1476 r = 0;
1477 break;
1478 }
313a3dc7
CO		 1479 case KVM_SET_CPUID: {
1480 struct kvm_cpuid __user *cpuid_arg = argp;
1481 struct kvm_cpuid cpuid;
1482
1483 r = -EFAULT;
1484 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1485 goto out;
1486 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1487 if (r)
1488 goto out;
1489 break;
1490 }
07716717
DK		 1491 case KVM_SET_CPUID2: {
1492 struct kvm_cpuid2 __user *cpuid_arg = argp;
1493 struct kvm_cpuid2 cpuid;
1494
1495 r = -EFAULT;
1496 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1497 goto out;
1498 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1499 cpuid_arg->entries);
07716717
DK		 1500 if (r)
1501 goto out;
1502 break;
1503 }
1504 case KVM_GET_CPUID2: {
1505 struct kvm_cpuid2 __user *cpuid_arg = argp;
1506 struct kvm_cpuid2 cpuid;
1507
1508 r = -EFAULT;
1509 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1510 goto out;
1511 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1512 cpuid_arg->entries);
07716717
DK		 1513 if (r)
1514 goto out;
1515 r = -EFAULT;
1516 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1517 goto out;
1518 r = 0;
1519 break;
1520 }
313a3dc7
CO		 1521 case KVM_GET_MSRS:
1522 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1523 break;
1524 case KVM_SET_MSRS:
1525 r = msr_io(vcpu, argp, do_set_msr, 0);
1526 break;
b209749f
AK		 1527 case KVM_TPR_ACCESS_REPORTING: {
1528 struct kvm_tpr_access_ctl tac;
1529
1530 r = -EFAULT;
1531 if (copy_from_user(&tac, argp, sizeof tac))
1532 goto out;
1533 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1534 if (r)
1535 goto out;
1536 r = -EFAULT;
1537 if (copy_to_user(argp, &tac, sizeof tac))
1538 goto out;
1539 r = 0;
1540 break;
1541 };
b93463aa
AK		 1542 case KVM_SET_VAPIC_ADDR: {
1543 struct kvm_vapic_addr va;
1544
1545 r = -EINVAL;
1546 if (!irqchip_in_kernel(vcpu->kvm))
1547 goto out;
1548 r = -EFAULT;
1549 if (copy_from_user(&va, argp, sizeof va))
1550 goto out;
1551 r = 0;
1552 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1553 break;
1554 }
313a3dc7
CO		 1555 default:
1556 r = -EINVAL;
1557 }
1558out:
b772ff36
DH		 1559 if (lapic)
1560 kfree(lapic);
313a3dc7
CO		 1561 return r;
1562}
1563
1fe779f8
CO		 1564static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1565{
1566 int ret;
1567
1568 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1569 return -1;
1570 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1571 return ret;
1572}
1573
1574static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1575 u32 kvm_nr_mmu_pages)
1576{
1577 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1578 return -EINVAL;
1579
72dc67a6 1580 down_write(&kvm->slots_lock);
1fe779f8
CO		 1581
1582 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1583 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1584
72dc67a6 1585 up_write(&kvm->slots_lock);
1fe779f8
CO		 1586 return 0;
1587}
1588
1589static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1590{
f05e70ac 1591 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1592}
1593
e9f85cde
ZX		 1594gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1595{
1596 int i;
1597 struct kvm_mem_alias *alias;
1598
d69fb81f
ZX		 1599 for (i = 0; i < kvm->arch.naliases; ++i) {
1600 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1601 if (gfn >= alias->base_gfn
1602 && gfn < alias->base_gfn + alias->npages)
1603 return alias->target_gfn + gfn - alias->base_gfn;
1604 }
1605 return gfn;
1606}
1607
1fe779f8
CO		 1608/*
1609 * Set a new alias region. Aliases map a portion of physical memory into
1610 * another portion. This is useful for memory windows, for example the PC
1611 * VGA region.
1612 */
1613static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1614 struct kvm_memory_alias *alias)
1615{
1616 int r, n;
1617 struct kvm_mem_alias *p;
1618
1619 r = -EINVAL;
1620 /* General sanity checks */
1621 if (alias->memory_size & (PAGE_SIZE - 1))
1622 goto out;
1623 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1624 goto out;
1625 if (alias->slot >= KVM_ALIAS_SLOTS)
1626 goto out;
1627 if (alias->guest_phys_addr + alias->memory_size
1628 < alias->guest_phys_addr)
1629 goto out;
1630 if (alias->target_phys_addr + alias->memory_size
1631 < alias->target_phys_addr)
1632 goto out;
1633
72dc67a6 1634 down_write(&kvm->slots_lock);
a1708ce8 1635 spin_lock(&kvm->mmu_lock);
1fe779f8 1636
d69fb81f 1637 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1638 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1639 p->npages = alias->memory_size >> PAGE_SHIFT;
1640 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1641
1642 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1643 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1644 break;
d69fb81f 1645 kvm->arch.naliases = n;
1fe779f8 1646
a1708ce8 1647 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1648 kvm_mmu_zap_all(kvm);
1649
72dc67a6 1650 up_write(&kvm->slots_lock);
1fe779f8
CO		 1651
1652 return 0;
1653
1654out:
1655 return r;
1656}
1657
1658static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1659{
1660 int r;
1661
1662 r = 0;
1663 switch (chip->chip_id) {
1664 case KVM_IRQCHIP_PIC_MASTER:
1665 memcpy(&chip->chip.pic,
1666 &pic_irqchip(kvm)->pics[0],
1667 sizeof(struct kvm_pic_state));
1668 break;
1669 case KVM_IRQCHIP_PIC_SLAVE:
1670 memcpy(&chip->chip.pic,
1671 &pic_irqchip(kvm)->pics[1],
1672 sizeof(struct kvm_pic_state));
1673 break;
1674 case KVM_IRQCHIP_IOAPIC:
1675 memcpy(&chip->chip.ioapic,
1676 ioapic_irqchip(kvm),
1677 sizeof(struct kvm_ioapic_state));
1678 break;
1679 default:
1680 r = -EINVAL;
1681 break;
1682 }
1683 return r;
1684}
1685
1686static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1687{
1688 int r;
1689
1690 r = 0;
1691 switch (chip->chip_id) {
1692 case KVM_IRQCHIP_PIC_MASTER:
1693 memcpy(&pic_irqchip(kvm)->pics[0],
1694 &chip->chip.pic,
1695 sizeof(struct kvm_pic_state));
1696 break;
1697 case KVM_IRQCHIP_PIC_SLAVE:
1698 memcpy(&pic_irqchip(kvm)->pics[1],
1699 &chip->chip.pic,
1700 sizeof(struct kvm_pic_state));
1701 break;
1702 case KVM_IRQCHIP_IOAPIC:
1703 memcpy(ioapic_irqchip(kvm),
1704 &chip->chip.ioapic,
1705 sizeof(struct kvm_ioapic_state));
1706 break;
1707 default:
1708 r = -EINVAL;
1709 break;
1710 }
1711 kvm_pic_update_irq(pic_irqchip(kvm));
1712 return r;
1713}
1714
e0f63cb9
SY		 1715static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1716{
1717 int r = 0;
1718
1719 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1720 return r;
1721}
1722
1723static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1724{
1725 int r = 0;
1726
1727 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1728 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1729 return r;
1730}
1731
52d939a0
MT		 1732static int kvm_vm_ioctl_reinject(struct kvm *kvm,
1733 struct kvm_reinject_control *control)
1734{
1735 if (!kvm->arch.vpit)
1736 return -ENXIO;
1737 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
1738 return 0;
1739}
1740
5bb064dc
ZX		 1741/*
1742 * Get (and clear) the dirty memory log for a memory slot.
1743 */
1744int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1745 struct kvm_dirty_log *log)
1746{
1747 int r;
1748 int n;
1749 struct kvm_memory_slot *memslot;
1750 int is_dirty = 0;
1751
72dc67a6 1752 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1753
1754 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1755 if (r)
1756 goto out;
1757
1758 /* If nothing is dirty, don't bother messing with page tables. */
1759 if (is_dirty) {
1760 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1761 kvm_flush_remote_tlbs(kvm);
1762 memslot = &kvm->memslots[log->slot];
1763 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1764 memset(memslot->dirty_bitmap, 0, n);
1765 }
1766 r = 0;
1767out:
72dc67a6 1768 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1769 return r;
1770}
1771
1fe779f8
CO		 1772long kvm_arch_vm_ioctl(struct file *filp,
1773 unsigned int ioctl, unsigned long arg)
1774{
1775 struct kvm *kvm = filp->private_data;
1776 void __user *argp = (void __user *)arg;
1777 int r = -EINVAL;
f0d66275
DH		 1778 /*
1779 * This union makes it completely explicit to gcc-3.x
1780 * that these two variables' stack usage should be
1781 * combined, not added together.
1782 */
1783 union {
1784 struct kvm_pit_state ps;
1785 struct kvm_memory_alias alias;
1786 } u;
1fe779f8
CO		 1787
1788 switch (ioctl) {
1789 case KVM_SET_TSS_ADDR:
1790 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1791 if (r < 0)
1792 goto out;
1793 break;
1794 case KVM_SET_MEMORY_REGION: {
1795 struct kvm_memory_region kvm_mem;
1796 struct kvm_userspace_memory_region kvm_userspace_mem;
1797
1798 r = -EFAULT;
1799 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1800 goto out;
1801 kvm_userspace_mem.slot = kvm_mem.slot;
1802 kvm_userspace_mem.flags = kvm_mem.flags;
1803 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1804 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1805 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1806 if (r)
1807 goto out;
1808 break;
1809 }
1810 case KVM_SET_NR_MMU_PAGES:
1811 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1812 if (r)
1813 goto out;
1814 break;
1815 case KVM_GET_NR_MMU_PAGES:
1816 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1817 break;
f0d66275 1818 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1819 r = -EFAULT;
f0d66275 1820 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1821 goto out;
f0d66275 1822 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1823 if (r)
1824 goto out;
1825 break;
1fe779f8
CO		 1826 case KVM_CREATE_IRQCHIP:
1827 r = -ENOMEM;
d7deeeb0
ZX		 1828 kvm->arch.vpic = kvm_create_pic(kvm);
1829 if (kvm->arch.vpic) {
1fe779f8
CO		 1830 r = kvm_ioapic_init(kvm);
1831 if (r) {
d7deeeb0
ZX		 1832 kfree(kvm->arch.vpic);
1833 kvm->arch.vpic = NULL;
1fe779f8
CO		 1834 goto out;
1835 }
1836 } else
1837 goto out;
399ec807
AK		 1838 r = kvm_setup_default_irq_routing(kvm);
1839 if (r) {
1840 kfree(kvm->arch.vpic);
1841 kfree(kvm->arch.vioapic);
1842 goto out;
1843 }
1fe779f8 1844 break;
7837699f 1845 case KVM_CREATE_PIT:
269e05e4
AK		 1846 mutex_lock(&kvm->lock);
1847 r = -EEXIST;
1848 if (kvm->arch.vpit)
1849 goto create_pit_unlock;
7837699f
SY		 1850 r = -ENOMEM;
1851 kvm->arch.vpit = kvm_create_pit(kvm);
1852 if (kvm->arch.vpit)
1853 r = 0;
269e05e4
AK		 1854 create_pit_unlock:
1855 mutex_unlock(&kvm->lock);
7837699f 1856 break;
1fe779f8
CO		 1857 case KVM_IRQ_LINE: {
1858 struct kvm_irq_level irq_event;
1859
1860 r = -EFAULT;
1861 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1862 goto out;
1863 if (irqchip_in_kernel(kvm)) {
1864 mutex_lock(&kvm->lock);
5550af4d
SY		 1865 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1866 irq_event.irq, irq_event.level);
1fe779f8
CO		 1867 mutex_unlock(&kvm->lock);
1868 r = 0;
1869 }
1870 break;
1871 }
1872 case KVM_GET_IRQCHIP: {
1873 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1874 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1875
f0d66275
DH		 1876 r = -ENOMEM;
1877 if (!chip)
1fe779f8 1878 goto out;
f0d66275
DH		 1879 r = -EFAULT;
1880 if (copy_from_user(chip, argp, sizeof *chip))
1881 goto get_irqchip_out;
1fe779f8
CO		 1882 r = -ENXIO;
1883 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1884 goto get_irqchip_out;
1885 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1886 if (r)
f0d66275 1887 goto get_irqchip_out;
1fe779f8 1888 r = -EFAULT;
f0d66275
DH		 1889 if (copy_to_user(argp, chip, sizeof *chip))
1890 goto get_irqchip_out;
1fe779f8 1891 r = 0;
f0d66275
DH		 1892 get_irqchip_out:
1893 kfree(chip);
1894 if (r)
1895 goto out;
1fe779f8
CO		 1896 break;
1897 }
1898 case KVM_SET_IRQCHIP: {
1899 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1900 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1901
f0d66275
DH		 1902 r = -ENOMEM;
1903 if (!chip)
1fe779f8 1904 goto out;
f0d66275
DH		 1905 r = -EFAULT;
1906 if (copy_from_user(chip, argp, sizeof *chip))
1907 goto set_irqchip_out;
1fe779f8
CO		 1908 r = -ENXIO;
1909 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1910 goto set_irqchip_out;
1911 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1912 if (r)
f0d66275 1913 goto set_irqchip_out;
1fe779f8 1914 r = 0;
f0d66275
DH		 1915 set_irqchip_out:
1916 kfree(chip);
1917 if (r)
1918 goto out;
1fe779f8
CO		 1919 break;
1920 }
e0f63cb9 1921 case KVM_GET_PIT: {
e0f63cb9 1922 r = -EFAULT;
f0d66275 1923 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1924 goto out;
1925 r = -ENXIO;
1926 if (!kvm->arch.vpit)
1927 goto out;
f0d66275 1928 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1929 if (r)
1930 goto out;
1931 r = -EFAULT;
f0d66275 1932 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1933 goto out;
1934 r = 0;
1935 break;
1936 }
1937 case KVM_SET_PIT: {
e0f63cb9 1938 r = -EFAULT;
f0d66275 1939 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1940 goto out;
1941 r = -ENXIO;
1942 if (!kvm->arch.vpit)
1943 goto out;
f0d66275 1944 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1945 if (r)
1946 goto out;
1947 r = 0;
1948 break;
1949 }
52d939a0
MT		 1950 case KVM_REINJECT_CONTROL: {
1951 struct kvm_reinject_control control;
1952 r = -EFAULT;
1953 if (copy_from_user(&control, argp, sizeof(control)))
1954 goto out;
1955 r = kvm_vm_ioctl_reinject(kvm, &control);
1956 if (r)
1957 goto out;
1958 r = 0;
1959 break;
1960 }
1fe779f8
CO		 1961 default:
1962 ;
1963 }
1964out:
1965 return r;
1966}
1967
a16b043c 1968static void kvm_init_msr_list(void)
043405e1
CO		 1969{
1970 u32 dummy[2];
1971 unsigned i, j;
1972
1973 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1974 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1975 continue;
1976 if (j < i)
1977 msrs_to_save[j] = msrs_to_save[i];
1978 j++;
1979 }
1980 num_msrs_to_save = j;
1981}
1982
bbd9b64e
CO		 1983/*
1984 * Only apic need an MMIO device hook, so shortcut now..
1985 */
1986static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1987 gpa_t addr, int len,
1988 int is_write)
bbd9b64e
CO		 1989{
1990 struct kvm_io_device *dev;
1991
ad312c7c
ZX		 1992 if (vcpu->arch.apic) {
1993 dev = &vcpu->arch.apic->dev;
92760499 1994 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1995 return dev;
1996 }
1997 return NULL;
1998}
1999
2000
2001static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2002 gpa_t addr, int len,
2003 int is_write)
bbd9b64e
CO		 2004{
2005 struct kvm_io_device *dev;
2006
92760499 2007 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2008 if (dev == NULL)
92760499
LV		 2009 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2010 is_write);
bbd9b64e
CO		 2011 return dev;
2012}
2013
77c2002e
IE		 2014int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2015 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2016{
2017 void *data = val;
10589a46 2018 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2019
2020 while (bytes) {
ad312c7c 2021 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2022 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2023 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2024 int ret;
2025
10589a46
MT		 2026 if (gpa == UNMAPPED_GVA) {
2027 r = X86EMUL_PROPAGATE_FAULT;
2028 goto out;
2029 }
77c2002e 2030 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2031 if (ret < 0) {
2032 r = X86EMUL_UNHANDLEABLE;
2033 goto out;
2034 }
bbd9b64e 2035
77c2002e
IE		 2036 bytes -= toread;
2037 data += toread;
2038 addr += toread;
bbd9b64e 2039 }
10589a46 2040out:
10589a46 2041 return r;
bbd9b64e 2042}
77c2002e
IE		 2043
2044int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2045 struct kvm_vcpu *vcpu)
2046{
2047 void *data = val;
2048 int r = X86EMUL_CONTINUE;
2049
2050 while (bytes) {
2051 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2052 unsigned offset = addr & (PAGE_SIZE-1);
2053 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2054 int ret;
2055
2056 if (gpa == UNMAPPED_GVA) {
2057 r = X86EMUL_PROPAGATE_FAULT;
2058 goto out;
2059 }
2060 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2061 if (ret < 0) {
2062 r = X86EMUL_UNHANDLEABLE;
2063 goto out;
2064 }
2065
2066 bytes -= towrite;
2067 data += towrite;
2068 addr += towrite;
2069 }
2070out:
2071 return r;
2072}
2073
bbd9b64e 2074
bbd9b64e
CO		 2075static int emulator_read_emulated(unsigned long addr,
2076 void *val,
2077 unsigned int bytes,
2078 struct kvm_vcpu *vcpu)
2079{
2080 struct kvm_io_device *mmio_dev;
2081 gpa_t gpa;
2082
2083 if (vcpu->mmio_read_completed) {
2084 memcpy(val, vcpu->mmio_data, bytes);
2085 vcpu->mmio_read_completed = 0;
2086 return X86EMUL_CONTINUE;
2087 }
2088
ad312c7c 2089 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2090
2091 /* For APIC access vmexit */
2092 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2093 goto mmio;
2094
77c2002e
IE		 2095 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2096 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2097 return X86EMUL_CONTINUE;
2098 if (gpa == UNMAPPED_GVA)
2099 return X86EMUL_PROPAGATE_FAULT;
2100
2101mmio:
2102 /*
2103 * Is this MMIO handled locally?
2104 */
10589a46 2105 mutex_lock(&vcpu->kvm->lock);
92760499 2106 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2107 if (mmio_dev) {
2108 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2109 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2110 return X86EMUL_CONTINUE;
2111 }
10589a46 2112 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2113
2114 vcpu->mmio_needed = 1;
2115 vcpu->mmio_phys_addr = gpa;
2116 vcpu->mmio_size = bytes;
2117 vcpu->mmio_is_write = 0;
2118
2119 return X86EMUL_UNHANDLEABLE;
2120}
2121
3200f405 2122int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2123 const void *val, int bytes)
bbd9b64e
CO		 2124{
2125 int ret;
2126
2127 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2128 if (ret < 0)
bbd9b64e 2129 return 0;
ad218f85 2130 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2131 return 1;
2132}
2133
2134static int emulator_write_emulated_onepage(unsigned long addr,
2135 const void *val,
2136 unsigned int bytes,
2137 struct kvm_vcpu *vcpu)
2138{
2139 struct kvm_io_device *mmio_dev;
10589a46
MT		 2140 gpa_t gpa;
2141
10589a46 2142 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2143
2144 if (gpa == UNMAPPED_GVA) {
c3c91fee 2145 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2146 return X86EMUL_PROPAGATE_FAULT;
2147 }
2148
2149 /* For APIC access vmexit */
2150 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2151 goto mmio;
2152
2153 if (emulator_write_phys(vcpu, gpa, val, bytes))
2154 return X86EMUL_CONTINUE;
2155
2156mmio:
2157 /*
2158 * Is this MMIO handled locally?
2159 */
10589a46 2160 mutex_lock(&vcpu->kvm->lock);
92760499 2161 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2162 if (mmio_dev) {
2163 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2164 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2165 return X86EMUL_CONTINUE;
2166 }
10589a46 2167 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2168
2169 vcpu->mmio_needed = 1;
2170 vcpu->mmio_phys_addr = gpa;
2171 vcpu->mmio_size = bytes;
2172 vcpu->mmio_is_write = 1;
2173 memcpy(vcpu->mmio_data, val, bytes);
2174
2175 return X86EMUL_CONTINUE;
2176}
2177
2178int emulator_write_emulated(unsigned long addr,
2179 const void *val,
2180 unsigned int bytes,
2181 struct kvm_vcpu *vcpu)
2182{
2183 /* Crossing a page boundary? */
2184 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2185 int rc, now;
2186
2187 now = -addr & ~PAGE_MASK;
2188 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2189 if (rc != X86EMUL_CONTINUE)
2190 return rc;
2191 addr += now;
2192 val += now;
2193 bytes -= now;
2194 }
2195 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2196}
2197EXPORT_SYMBOL_GPL(emulator_write_emulated);
2198
2199static int emulator_cmpxchg_emulated(unsigned long addr,
2200 const void *old,
2201 const void *new,
2202 unsigned int bytes,
2203 struct kvm_vcpu *vcpu)
2204{
2205 static int reported;
2206
2207 if (!reported) {
2208 reported = 1;
2209 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2210 }
2bacc55c
MT		 2211#ifndef CONFIG_X86_64
2212 /* guests cmpxchg8b have to be emulated atomically */
2213 if (bytes == 8) {
10589a46 2214 gpa_t gpa;
2bacc55c 2215 struct page *page;
c0b49b0d 2216 char *kaddr;
2bacc55c
MT		 2217 u64 val;
2218
10589a46
MT		 2219 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2220
2bacc55c
MT		 2221 if (gpa == UNMAPPED_GVA ||
2222 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2223 goto emul_write;
2224
2225 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2226 goto emul_write;
2227
2228 val = *(u64 *)new;
72dc67a6 2229
2bacc55c 2230 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2231
c0b49b0d
AM		 2232 kaddr = kmap_atomic(page, KM_USER0);
2233 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2234 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2235 kvm_release_page_dirty(page);
2236 }
3200f405 2237emul_write:
2bacc55c
MT		 2238#endif
2239
bbd9b64e
CO		 2240 return emulator_write_emulated(addr, new, bytes, vcpu);
2241}
2242
2243static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2244{
2245 return kvm_x86_ops->get_segment_base(vcpu, seg);
2246}
2247
2248int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2249{
a7052897 2250 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2251 return X86EMUL_CONTINUE;
2252}
2253
2254int emulate_clts(struct kvm_vcpu *vcpu)
2255{
54e445ca 2256 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2257 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2258 return X86EMUL_CONTINUE;
2259}
2260
2261int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2262{
2263 struct kvm_vcpu *vcpu = ctxt->vcpu;
2264
2265 switch (dr) {
2266 case 0 ... 3:
2267 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2268 return X86EMUL_CONTINUE;
2269 default:
b8688d51 2270 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2271 return X86EMUL_UNHANDLEABLE;
2272 }
2273}
2274
2275int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2276{
2277 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2278 int exception;
2279
2280 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2281 if (exception) {
2282 /* FIXME: better handling */
2283 return X86EMUL_UNHANDLEABLE;
2284 }
2285 return X86EMUL_CONTINUE;
2286}
2287
2288void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2289{
bbd9b64e 2290 u8 opcodes[4];
5fdbf976 2291 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2292 unsigned long rip_linear;
2293
f76c710d 2294 if (!printk_ratelimit())
bbd9b64e
CO		 2295 return;
2296
25be4608
GC		 2297 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2298
77c2002e 2299 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2300
2301 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2302 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2303}
2304EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2305
14af3f3c 2306static struct x86_emulate_ops emulate_ops = {
77c2002e 2307 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2308 .read_emulated = emulator_read_emulated,
2309 .write_emulated = emulator_write_emulated,
2310 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2311};
2312
5fdbf976
MT		 2313static void cache_all_regs(struct kvm_vcpu *vcpu)
2314{
2315 kvm_register_read(vcpu, VCPU_REGS_RAX);
2316 kvm_register_read(vcpu, VCPU_REGS_RSP);
2317 kvm_register_read(vcpu, VCPU_REGS_RIP);
2318 vcpu->arch.regs_dirty = ~0;
2319}
2320
bbd9b64e
CO		 2321int emulate_instruction(struct kvm_vcpu *vcpu,
2322 struct kvm_run *run,
2323 unsigned long cr2,
2324 u16 error_code,
571008da 2325 int emulation_type)
bbd9b64e
CO		 2326{
2327 int r;
571008da 2328 struct decode_cache *c;
bbd9b64e 2329
26eef70c 2330 kvm_clear_exception_queue(vcpu);
ad312c7c 2331 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2332 /*
2333 * TODO: fix x86_emulate.c to use guest_read/write_register
2334 * instead of direct ->regs accesses, can save hundred cycles
2335 * on Intel for instructions that don't read/change RSP, for
2336 * for example.
2337 */
2338 cache_all_regs(vcpu);
bbd9b64e
CO		 2339
2340 vcpu->mmio_is_write = 0;
ad312c7c 2341 vcpu->arch.pio.string = 0;
bbd9b64e 2342
571008da 2343 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2344 int cs_db, cs_l;
2345 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2346
ad312c7c
ZX		 2347 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2348 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2349 vcpu->arch.emulate_ctxt.mode =
2350 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2351 ? X86EMUL_MODE_REAL : cs_l
2352 ? X86EMUL_MODE_PROT64 : cs_db
2353 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2354
ad312c7c 2355 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2356
2357 /* Reject the instructions other than VMCALL/VMMCALL when
2358 * try to emulate invalid opcode */
2359 c = &vcpu->arch.emulate_ctxt.decode;
2360 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2361 (!(c->twobyte && c->b == 0x01 &&
2362 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2363 c->modrm_mod == 3 && c->modrm_rm == 1)))
2364 return EMULATE_FAIL;
2365
f2b5756b 2366 ++vcpu->stat.insn_emulation;
bbd9b64e 2367 if (r) {
f2b5756b 2368 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2369 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2370 return EMULATE_DONE;
2371 return EMULATE_FAIL;
2372 }
2373 }
2374
ad312c7c 2375 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2376
ad312c7c 2377 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2378 return EMULATE_DO_MMIO;
2379
2380 if ((r || vcpu->mmio_is_write) && run) {
2381 run->exit_reason = KVM_EXIT_MMIO;
2382 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2383 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2384 run->mmio.len = vcpu->mmio_size;
2385 run->mmio.is_write = vcpu->mmio_is_write;
2386 }
2387
2388 if (r) {
2389 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2390 return EMULATE_DONE;
2391 if (!vcpu->mmio_needed) {
2392 kvm_report_emulation_failure(vcpu, "mmio");
2393 return EMULATE_FAIL;
2394 }
2395 return EMULATE_DO_MMIO;
2396 }
2397
ad312c7c 2398 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2399
2400 if (vcpu->mmio_is_write) {
2401 vcpu->mmio_needed = 0;
2402 return EMULATE_DO_MMIO;
2403 }
2404
2405 return EMULATE_DONE;
2406}
2407EXPORT_SYMBOL_GPL(emulate_instruction);
2408
de7d789a
CO		 2409static int pio_copy_data(struct kvm_vcpu *vcpu)
2410{
ad312c7c 2411 void *p = vcpu->arch.pio_data;
0f346074 2412 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2413 unsigned bytes;
0f346074 2414 int ret;
de7d789a 2415
ad312c7c
ZX		 2416 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2417 if (vcpu->arch.pio.in)
0f346074 2418 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2419 else
0f346074
IE		 2420 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2421 return ret;
de7d789a
CO		 2422}
2423
2424int complete_pio(struct kvm_vcpu *vcpu)
2425{
ad312c7c 2426 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2427 long delta;
2428 int r;
5fdbf976 2429 unsigned long val;
de7d789a
CO		 2430
2431 if (!io->string) {
5fdbf976
MT		 2432 if (io->in) {
2433 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2434 memcpy(&val, vcpu->arch.pio_data, io->size);
2435 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2436 }
de7d789a
CO		 2437 } else {
2438 if (io->in) {
2439 r = pio_copy_data(vcpu);
5fdbf976 2440 if (r)
de7d789a 2441 return r;
de7d789a
CO		 2442 }
2443
2444 delta = 1;
2445 if (io->rep) {
2446 delta *= io->cur_count;
2447 /*
2448 * The size of the register should really depend on
2449 * current address size.
2450 */
5fdbf976
MT		 2451 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2452 val -= delta;
2453 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2454 }
2455 if (io->down)
2456 delta = -delta;
2457 delta *= io->size;
5fdbf976
MT		 2458 if (io->in) {
2459 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2460 val += delta;
2461 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2462 } else {
2463 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2464 val += delta;
2465 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2466 }
de7d789a
CO		 2467 }
2468
de7d789a
CO		 2469 io->count -= io->cur_count;
2470 io->cur_count = 0;
2471
2472 return 0;
2473}
2474
2475static void kernel_pio(struct kvm_io_device *pio_dev,
2476 struct kvm_vcpu *vcpu,
2477 void *pd)
2478{
2479 /* TODO: String I/O for in kernel device */
2480
2481 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2482 if (vcpu->arch.pio.in)
2483 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2484 vcpu->arch.pio.size,
de7d789a
CO		 2485 pd);
2486 else
ad312c7c
ZX		 2487 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2488 vcpu->arch.pio.size,
de7d789a
CO		 2489 pd);
2490 mutex_unlock(&vcpu->kvm->lock);
2491}
2492
2493static void pio_string_write(struct kvm_io_device *pio_dev,
2494 struct kvm_vcpu *vcpu)
2495{
ad312c7c
ZX		 2496 struct kvm_pio_request *io = &vcpu->arch.pio;
2497 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2498 int i;
2499
2500 mutex_lock(&vcpu->kvm->lock);
2501 for (i = 0; i < io->cur_count; i++) {
2502 kvm_iodevice_write(pio_dev, io->port,
2503 io->size,
2504 pd);
2505 pd += io->size;
2506 }
2507 mutex_unlock(&vcpu->kvm->lock);
2508}
2509
2510static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2511 gpa_t addr, int len,
2512 int is_write)
de7d789a 2513{
92760499 2514 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2515}
2516
2517int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2518 int size, unsigned port)
2519{
2520 struct kvm_io_device *pio_dev;
5fdbf976 2521 unsigned long val;
de7d789a
CO		 2522
2523 vcpu->run->exit_reason = KVM_EXIT_IO;
2524 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2525 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2526 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2527 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2528 vcpu->run->io.port = vcpu->arch.pio.port = port;
2529 vcpu->arch.pio.in = in;
2530 vcpu->arch.pio.string = 0;
2531 vcpu->arch.pio.down = 0;
ad312c7c 2532 vcpu->arch.pio.rep = 0;
de7d789a 2533
2714d1d3
FEL		 2534 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2535 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2536 handler);
2537 else
2538 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2539 handler);
2540
5fdbf976
MT		 2541 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2542 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2543
92760499 2544 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2545 if (pio_dev) {
ad312c7c 2546 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2547 complete_pio(vcpu);
2548 return 1;
2549 }
2550 return 0;
2551}
2552EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2553
2554int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2555 int size, unsigned long count, int down,
2556 gva_t address, int rep, unsigned port)
2557{
2558 unsigned now, in_page;
0f346074 2559 int ret = 0;
de7d789a
CO		 2560 struct kvm_io_device *pio_dev;
2561
2562 vcpu->run->exit_reason = KVM_EXIT_IO;
2563 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2564 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2565 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2566 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2567 vcpu->run->io.port = vcpu->arch.pio.port = port;
2568 vcpu->arch.pio.in = in;
2569 vcpu->arch.pio.string = 1;
2570 vcpu->arch.pio.down = down;
ad312c7c 2571 vcpu->arch.pio.rep = rep;
de7d789a 2572
2714d1d3
FEL		 2573 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2574 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2575 handler);
2576 else
2577 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2578 handler);
2579
de7d789a
CO		 2580 if (!count) {
2581 kvm_x86_ops->skip_emulated_instruction(vcpu);
2582 return 1;
2583 }
2584
2585 if (!down)
2586 in_page = PAGE_SIZE - offset_in_page(address);
2587 else
2588 in_page = offset_in_page(address) + size;
2589 now = min(count, (unsigned long)in_page / size);
0f346074 2590 if (!now)
de7d789a 2591 now = 1;
de7d789a
CO		 2592 if (down) {
2593 /*
2594 * String I/O in reverse. Yuck. Kill the guest, fix later.
2595 */
2596 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2597 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2598 return 1;
2599 }
2600 vcpu->run->io.count = now;
ad312c7c 2601 vcpu->arch.pio.cur_count = now;
de7d789a 2602
ad312c7c 2603 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2604 kvm_x86_ops->skip_emulated_instruction(vcpu);
2605
0f346074 2606 vcpu->arch.pio.guest_gva = address;
de7d789a 2607
92760499
LV		 2608 pio_dev = vcpu_find_pio_dev(vcpu, port,
2609 vcpu->arch.pio.cur_count,
2610 !vcpu->arch.pio.in);
ad312c7c 2611 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2612 /* string PIO write */
2613 ret = pio_copy_data(vcpu);
0f346074
IE		 2614 if (ret == X86EMUL_PROPAGATE_FAULT) {
2615 kvm_inject_gp(vcpu, 0);
2616 return 1;
2617 }
2618 if (ret == 0 && pio_dev) {
de7d789a
CO		 2619 pio_string_write(pio_dev, vcpu);
2620 complete_pio(vcpu);
ad312c7c 2621 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2622 ret = 1;
2623 }
2624 } else if (pio_dev)
2625 pr_unimpl(vcpu, "no string pio read support yet, "
2626 "port %x size %d count %ld\n",
2627 port, size, count);
2628
2629 return ret;
2630}
2631EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2632
f8c16bba 2633int kvm_arch_init(void *opaque)
043405e1 2634{
56c6d28a 2635 int r;
f8c16bba
ZX		 2636 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2637
f8c16bba
ZX		 2638 if (kvm_x86_ops) {
2639 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2640 r = -EEXIST;
2641 goto out;
f8c16bba
ZX		 2642 }
2643
2644 if (!ops->cpu_has_kvm_support()) {
2645 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2646 r = -EOPNOTSUPP;
2647 goto out;
f8c16bba
ZX		 2648 }
2649 if (ops->disabled_by_bios()) {
2650 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2651 r = -EOPNOTSUPP;
2652 goto out;
f8c16bba
ZX		 2653 }
2654
97db56ce
AK		 2655 r = kvm_mmu_module_init();
2656 if (r)
2657 goto out;
2658
2659 kvm_init_msr_list();
2660
f8c16bba 2661 kvm_x86_ops = ops;
56c6d28a 2662 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2663 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2664 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2665 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
f8c16bba 2666 return 0;
56c6d28a
ZX		 2667
2668out:
56c6d28a 2669 return r;
043405e1 2670}
8776e519 2671
f8c16bba
ZX		 2672void kvm_arch_exit(void)
2673{
2674 kvm_x86_ops = NULL;
56c6d28a
ZX		 2675 kvm_mmu_module_exit();
2676}
f8c16bba 2677
8776e519
HB		 2678int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2679{
2680 ++vcpu->stat.halt_exits;
2714d1d3 2681 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2682 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2683 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2684 return 1;
2685 } else {
2686 vcpu->run->exit_reason = KVM_EXIT_HLT;
2687 return 0;
2688 }
2689}
2690EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2691
2f333bcb
MT		 2692static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2693 unsigned long a1)
2694{
2695 if (is_long_mode(vcpu))
2696 return a0;
2697 else
2698 return a0 | ((gpa_t)a1 << 32);
2699}
2700
8776e519
HB		 2701int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2702{
2703 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2704 int r = 1;
8776e519 2705
5fdbf976
MT		 2706 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2707 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2708 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2709 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2710 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2711
2714d1d3
FEL		 2712 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2713
8776e519
HB		 2714 if (!is_long_mode(vcpu)) {
2715 nr &= 0xFFFFFFFF;
2716 a0 &= 0xFFFFFFFF;
2717 a1 &= 0xFFFFFFFF;
2718 a2 &= 0xFFFFFFFF;
2719 a3 &= 0xFFFFFFFF;
2720 }
2721
2722 switch (nr) {
b93463aa
AK		 2723 case KVM_HC_VAPIC_POLL_IRQ:
2724 ret = 0;
2725 break;
2f333bcb
MT		 2726 case KVM_HC_MMU_OP:
2727 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2728 break;
8776e519
HB		 2729 default:
2730 ret = -KVM_ENOSYS;
2731 break;
2732 }
5fdbf976 2733 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2734 ++vcpu->stat.hypercalls;
2f333bcb 2735 return r;
8776e519
HB		 2736}
2737EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2738
2739int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2740{
2741 char instruction[3];
2742 int ret = 0;
5fdbf976 2743 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2744
8776e519
HB		 2745
2746 /*
2747 * Blow out the MMU to ensure that no other VCPU has an active mapping
2748 * to ensure that the updated hypercall appears atomically across all
2749 * VCPUs.
2750 */
2751 kvm_mmu_zap_all(vcpu->kvm);
2752
8776e519 2753 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2754 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2755 != X86EMUL_CONTINUE)
2756 ret = -EFAULT;
2757
8776e519
HB		 2758 return ret;
2759}
2760
2761static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2762{
2763 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2764}
2765
2766void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2767{
2768 struct descriptor_table dt = { limit, base };
2769
2770 kvm_x86_ops->set_gdt(vcpu, &dt);
2771}
2772
2773void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2774{
2775 struct descriptor_table dt = { limit, base };
2776
2777 kvm_x86_ops->set_idt(vcpu, &dt);
2778}
2779
2780void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2781 unsigned long *rflags)
2782{
2d3ad1f4 2783 kvm_lmsw(vcpu, msw);
8776e519
HB		 2784 *rflags = kvm_x86_ops->get_rflags(vcpu);
2785}
2786
2787unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2788{
54e445ca
JR		 2789 unsigned long value;
2790
8776e519
HB		 2791 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2792 switch (cr) {
2793 case 0:
54e445ca
JR		 2794 value = vcpu->arch.cr0;
2795 break;
8776e519 2796 case 2:
54e445ca
JR		 2797 value = vcpu->arch.cr2;
2798 break;
8776e519 2799 case 3:
54e445ca
JR		 2800 value = vcpu->arch.cr3;
2801 break;
8776e519 2802 case 4:
54e445ca
JR		 2803 value = vcpu->arch.cr4;
2804 break;
152ff9be 2805 case 8:
54e445ca
JR		 2806 value = kvm_get_cr8(vcpu);
2807 break;
8776e519 2808 default:
b8688d51 2809 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2810 return 0;
2811 }
54e445ca
JR		 2812 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2813 (u32)((u64)value >> 32), handler);
2814
2815 return value;
8776e519
HB		 2816}
2817
2818void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2819 unsigned long *rflags)
2820{
54e445ca
JR		 2821 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2822 (u32)((u64)val >> 32), handler);
2823
8776e519
HB		 2824 switch (cr) {
2825 case 0:
2d3ad1f4 2826 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2827 *rflags = kvm_x86_ops->get_rflags(vcpu);
2828 break;
2829 case 2:
ad312c7c 2830 vcpu->arch.cr2 = val;
8776e519
HB		 2831 break;
2832 case 3:
2d3ad1f4 2833 kvm_set_cr3(vcpu, val);
8776e519
HB		 2834 break;
2835 case 4:
2d3ad1f4 2836 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2837 break;
152ff9be 2838 case 8:
2d3ad1f4 2839 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2840 break;
8776e519 2841 default:
b8688d51 2842 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2843 }
2844}
2845
07716717
DK		 2846static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2847{
ad312c7c
ZX		 2848 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2849 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2850
2851 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2852 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2853 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2854 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2855 if (ej->function == e->function) {
2856 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2857 return j;
2858 }
2859 }
2860 return 0; /* silence gcc, even though control never reaches here */
2861}
2862
2863/* find an entry with matching function, matching index (if needed), and that
2864 * should be read next (if it's stateful) */
2865static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2866 u32 function, u32 index)
2867{
2868 if (e->function != function)
2869 return 0;
2870 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2871 return 0;
2872 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 2873 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 2874 return 0;
2875 return 1;
2876}
2877
d8017474
AG		 2878struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
2879 u32 function, u32 index)
8776e519
HB		 2880{
2881 int i;
d8017474 2882 struct kvm_cpuid_entry2 *best = NULL;
8776e519 2883
ad312c7c 2884 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 2885 struct kvm_cpuid_entry2 *e;
2886
ad312c7c 2887 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2888 if (is_matching_cpuid_entry(e, function, index)) {
2889 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2890 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2891 best = e;
2892 break;
2893 }
2894 /*
2895 * Both basic or both extended?
2896 */
2897 if (((e->function ^ function) & 0x80000000) == 0)
2898 if (!best || e->function > best->function)
2899 best = e;
2900 }
d8017474
AG		 2901 return best;
2902}
2903
2904void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2905{
2906 u32 function, index;
2907 struct kvm_cpuid_entry2 *best;
2908
2909 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2910 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2911 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2912 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2913 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2914 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
2915 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 2916 if (best) {
5fdbf976
MT		 2917 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2918 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2919 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2920 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2921 }
8776e519 2922 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2923 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2924 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2925 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2926 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2927 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2928}
2929EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2930
b6c7a5dc
HB		 2931/*
2932 * Check if userspace requested an interrupt window, and that the
2933 * interrupt window is open.
2934 *
2935 * No need to exit to userspace if we already have an interrupt queued.
2936 */
2937static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2938 struct kvm_run *kvm_run)
2939{
ad312c7c 2940 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2941 kvm_run->request_interrupt_window &&
ad312c7c 2942 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2943 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2944}
2945
2946static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2947 struct kvm_run *kvm_run)
2948{
2949 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2950 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 2951 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 2952 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2953 kvm_run->ready_for_interrupt_injection = 1;
4531220b 2954 else
b6c7a5dc 2955 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2956 (vcpu->arch.interrupt_window_open &&
2957 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2958}
2959
b93463aa
AK		 2960static void vapic_enter(struct kvm_vcpu *vcpu)
2961{
2962 struct kvm_lapic *apic = vcpu->arch.apic;
2963 struct page *page;
2964
2965 if (!apic || !apic->vapic_addr)
2966 return;
2967
2968 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 2969
2970 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2971}
2972
2973static void vapic_exit(struct kvm_vcpu *vcpu)
2974{
2975 struct kvm_lapic *apic = vcpu->arch.apic;
2976
2977 if (!apic || !apic->vapic_addr)
2978 return;
2979
f8b78fa3 2980 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2981 kvm_release_page_dirty(apic->vapic_page);
2982 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2983 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2984}
2985
d7690175 2986static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 2987{
2988 int r;
2989
2e53d63a
MT		 2990 if (vcpu->requests)
2991 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2992 kvm_mmu_unload(vcpu);
2993
b6c7a5dc
HB		 2994 r = kvm_mmu_reload(vcpu);
2995 if (unlikely(r))
2996 goto out;
2997
2f52d58c
AK		 2998 if (vcpu->requests) {
2999 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3000 __kvm_migrate_timers(vcpu);
4731d4c7
MT		 3001 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3002 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3003 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3004 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3005 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3006 &vcpu->requests)) {
3007 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3008 r = 0;
3009 goto out;
3010 }
71c4dfaf
JR		 3011 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3012 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3013 r = 0;
3014 goto out;
3015 }
2f52d58c 3016 }
b93463aa 3017
06e05645 3018 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 3019 kvm_inject_pending_timer_irqs(vcpu);
3020
3021 preempt_disable();
3022
3023 kvm_x86_ops->prepare_guest_switch(vcpu);
3024 kvm_load_guest_fpu(vcpu);
3025
3026 local_irq_disable();
3027
d7690175 3028 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3029 local_irq_enable();
3030 preempt_enable();
3031 r = 1;
3032 goto out;
3033 }
3034
e9571ed5
MT		 3035 vcpu->guest_mode = 1;
3036 /*
3037 * Make sure that guest_mode assignment won't happen after
3038 * testing the pending IRQ vector bitmap.
3039 */
3040 smp_wmb();
3041
ad312c7c 3042 if (vcpu->arch.exception.pending)
298101da
AK		 3043 __queue_exception(vcpu);
3044 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3045 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3046 else
b6c7a5dc
HB		 3047 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3048
b93463aa
AK		 3049 kvm_lapic_sync_to_vapic(vcpu);
3050
3200f405
MT		 3051 up_read(&vcpu->kvm->slots_lock);
3052
b6c7a5dc
HB		 3053 kvm_guest_enter();
3054
42dbaa5a
JK		 3055 get_debugreg(vcpu->arch.host_dr6, 6);
3056 get_debugreg(vcpu->arch.host_dr7, 7);
3057 if (unlikely(vcpu->arch.switch_db_regs)) {
3058 get_debugreg(vcpu->arch.host_db[0], 0);
3059 get_debugreg(vcpu->arch.host_db[1], 1);
3060 get_debugreg(vcpu->arch.host_db[2], 2);
3061 get_debugreg(vcpu->arch.host_db[3], 3);
3062
3063 set_debugreg(0, 7);
3064 set_debugreg(vcpu->arch.eff_db[0], 0);
3065 set_debugreg(vcpu->arch.eff_db[1], 1);
3066 set_debugreg(vcpu->arch.eff_db[2], 2);
3067 set_debugreg(vcpu->arch.eff_db[3], 3);
3068 }
b6c7a5dc 3069
2714d1d3 3070 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3071 kvm_x86_ops->run(vcpu, kvm_run);
3072
42dbaa5a
JK		 3073 if (unlikely(vcpu->arch.switch_db_regs)) {
3074 set_debugreg(0, 7);
3075 set_debugreg(vcpu->arch.host_db[0], 0);
3076 set_debugreg(vcpu->arch.host_db[1], 1);
3077 set_debugreg(vcpu->arch.host_db[2], 2);
3078 set_debugreg(vcpu->arch.host_db[3], 3);
3079 }
3080 set_debugreg(vcpu->arch.host_dr6, 6);
3081 set_debugreg(vcpu->arch.host_dr7, 7);
3082
b6c7a5dc
HB		 3083 vcpu->guest_mode = 0;
3084 local_irq_enable();
3085
3086 ++vcpu->stat.exits;
3087
3088 /*
3089 * We must have an instruction between local_irq_enable() and
3090 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3091 * the interrupt shadow. The stat.exits increment will do nicely.
3092 * But we need to prevent reordering, hence this barrier():
3093 */
3094 barrier();
3095
3096 kvm_guest_exit();
3097
3098 preempt_enable();
3099
3200f405
MT		 3100 down_read(&vcpu->kvm->slots_lock);
3101
b6c7a5dc
HB		 3102 /*
3103 * Profile KVM exit RIPs:
3104 */
3105 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3106 unsigned long rip = kvm_rip_read(vcpu);
3107 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3108 }
3109
ad312c7c
ZX		 3110 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3111 vcpu->arch.exception.pending = false;
298101da 3112
b93463aa
AK		 3113 kvm_lapic_sync_from_vapic(vcpu);
3114
b6c7a5dc 3115 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3116out:
3117 return r;
3118}
b6c7a5dc 3119
d7690175
MT		 3120static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3121{
3122 int r;
3123
3124 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3125 pr_debug("vcpu %d received sipi with vector # %x\n",
3126 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3127 kvm_lapic_reset(vcpu);
5f179287 3128 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3129 if (r)
3130 return r;
3131 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3132 }
3133
d7690175
MT		 3134 down_read(&vcpu->kvm->slots_lock);
3135 vapic_enter(vcpu);
3136
3137 r = 1;
3138 while (r > 0) {
af2152f5 3139 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3140 r = vcpu_enter_guest(vcpu, kvm_run);
3141 else {
3142 up_read(&vcpu->kvm->slots_lock);
3143 kvm_vcpu_block(vcpu);
3144 down_read(&vcpu->kvm->slots_lock);
3145 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3146 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3147 vcpu->arch.mp_state =
3148 KVM_MP_STATE_RUNNABLE;
3149 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3150 r = -EINTR;
3151 }
3152
3153 if (r > 0) {
3154 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3155 r = -EINTR;
3156 kvm_run->exit_reason = KVM_EXIT_INTR;
3157 ++vcpu->stat.request_irq_exits;
3158 }
3159 if (signal_pending(current)) {
3160 r = -EINTR;
3161 kvm_run->exit_reason = KVM_EXIT_INTR;
3162 ++vcpu->stat.signal_exits;
3163 }
3164 if (need_resched()) {
3165 up_read(&vcpu->kvm->slots_lock);
3166 kvm_resched(vcpu);
3167 down_read(&vcpu->kvm->slots_lock);
3168 }
3169 }
b6c7a5dc
HB		 3170 }
3171
d7690175 3172 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3173 post_kvm_run_save(vcpu, kvm_run);
3174
b93463aa
AK		 3175 vapic_exit(vcpu);
3176
b6c7a5dc
HB		 3177 return r;
3178}
3179
3180int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3181{
3182 int r;
3183 sigset_t sigsaved;
3184
3185 vcpu_load(vcpu);
3186
ac9f6dc0
AK		 3187 if (vcpu->sigset_active)
3188 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3189
a4535290 3190 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3191 kvm_vcpu_block(vcpu);
d7690175 3192 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3193 r = -EAGAIN;
3194 goto out;
b6c7a5dc
HB		 3195 }
3196
b6c7a5dc
HB		 3197 /* re-sync apic's tpr */
3198 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3199 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3200
ad312c7c 3201 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3202 r = complete_pio(vcpu);
3203 if (r)
3204 goto out;
3205 }
3206#if CONFIG_HAS_IOMEM
3207 if (vcpu->mmio_needed) {
3208 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3209 vcpu->mmio_read_completed = 1;
3210 vcpu->mmio_needed = 0;
3200f405
MT		 3211
3212 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3213 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3214 vcpu->arch.mmio_fault_cr2, 0,
3215 EMULTYPE_NO_DECODE);
3200f405 3216 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3217 if (r == EMULATE_DO_MMIO) {
3218 /*
3219 * Read-modify-write. Back to userspace.
3220 */
3221 r = 0;
3222 goto out;
3223 }
3224 }
3225#endif
5fdbf976
MT		 3226 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3227 kvm_register_write(vcpu, VCPU_REGS_RAX,
3228 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3229
3230 r = __vcpu_run(vcpu, kvm_run);
3231
3232out:
3233 if (vcpu->sigset_active)
3234 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3235
3236 vcpu_put(vcpu);
3237 return r;
3238}
3239
3240int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3241{
3242 vcpu_load(vcpu);
3243
5fdbf976
MT		 3244 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3245 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3246 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3247 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3248 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3249 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3250 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3251 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3252#ifdef CONFIG_X86_64
5fdbf976
MT		 3253 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3254 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3255 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3256 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3257 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3258 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3259 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3260 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3261#endif
3262
5fdbf976 3263 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3264 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3265
3266 /*
3267 * Don't leak debug flags in case they were set for guest debugging
3268 */
d0bfb940 3269 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3270 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3271
3272 vcpu_put(vcpu);
3273
3274 return 0;
3275}
3276
3277int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3278{
3279 vcpu_load(vcpu);
3280
5fdbf976
MT		 3281 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3282 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3283 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3284 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3285 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3286 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3287 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3288 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3289#ifdef CONFIG_X86_64
5fdbf976
MT		 3290 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3291 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3292 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3293 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3294 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3295 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3296 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3297 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3298
b6c7a5dc
HB		 3299#endif
3300
5fdbf976 3301 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3302 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3303
b6c7a5dc 3304
b4f14abd
JK		 3305 vcpu->arch.exception.pending = false;
3306
b6c7a5dc
HB		 3307 vcpu_put(vcpu);
3308
3309 return 0;
3310}
3311
3e6e0aab
GT		 3312void kvm_get_segment(struct kvm_vcpu *vcpu,
3313 struct kvm_segment *var, int seg)
b6c7a5dc 3314{
14af3f3c 3315 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3316}
3317
3318void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3319{
3320 struct kvm_segment cs;
3321
3e6e0aab 3322 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3323 *db = cs.db;
3324 *l = cs.l;
3325}
3326EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3327
3328int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3329 struct kvm_sregs *sregs)
3330{
3331 struct descriptor_table dt;
3332 int pending_vec;
3333
3334 vcpu_load(vcpu);
3335
3e6e0aab
GT		 3336 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3337 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3338 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3339 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3340 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3341 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3342
3e6e0aab
GT		 3343 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3344 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3345
3346 kvm_x86_ops->get_idt(vcpu, &dt);
3347 sregs->idt.limit = dt.limit;
3348 sregs->idt.base = dt.base;
3349 kvm_x86_ops->get_gdt(vcpu, &dt);
3350 sregs->gdt.limit = dt.limit;
3351 sregs->gdt.base = dt.base;
3352
3353 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3354 sregs->cr0 = vcpu->arch.cr0;
3355 sregs->cr2 = vcpu->arch.cr2;
3356 sregs->cr3 = vcpu->arch.cr3;
3357 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3358 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3359 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3360 sregs->apic_base = kvm_get_apic_base(vcpu);
3361
3362 if (irqchip_in_kernel(vcpu->kvm)) {
3363 memset(sregs->interrupt_bitmap, 0,
3364 sizeof sregs->interrupt_bitmap);
3365 pending_vec = kvm_x86_ops->get_irq(vcpu);
3366 if (pending_vec >= 0)
3367 set_bit(pending_vec,
3368 (unsigned long *)sregs->interrupt_bitmap);
3369 } else
ad312c7c 3370 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3371 sizeof sregs->interrupt_bitmap);
3372
3373 vcpu_put(vcpu);
3374
3375 return 0;
3376}
3377
62d9f0db
MT		 3378int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3379 struct kvm_mp_state *mp_state)
3380{
3381 vcpu_load(vcpu);
3382 mp_state->mp_state = vcpu->arch.mp_state;
3383 vcpu_put(vcpu);
3384 return 0;
3385}
3386
3387int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3388 struct kvm_mp_state *mp_state)
3389{
3390 vcpu_load(vcpu);
3391 vcpu->arch.mp_state = mp_state->mp_state;
3392 vcpu_put(vcpu);
3393 return 0;
3394}
3395
3e6e0aab 3396static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3397 struct kvm_segment *var, int seg)
3398{
14af3f3c 3399 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3400}
3401
37817f29
IE		 3402static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3403 struct kvm_segment *kvm_desct)
3404{
3405 kvm_desct->base = seg_desc->base0;
3406 kvm_desct->base |= seg_desc->base1 << 16;
3407 kvm_desct->base |= seg_desc->base2 << 24;
3408 kvm_desct->limit = seg_desc->limit0;
3409 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3410 if (seg_desc->g) {
3411 kvm_desct->limit <<= 12;
3412 kvm_desct->limit |= 0xfff;
3413 }
37817f29
IE		 3414 kvm_desct->selector = selector;
3415 kvm_desct->type = seg_desc->type;
3416 kvm_desct->present = seg_desc->p;
3417 kvm_desct->dpl = seg_desc->dpl;
3418 kvm_desct->db = seg_desc->d;
3419 kvm_desct->s = seg_desc->s;
3420 kvm_desct->l = seg_desc->l;
3421 kvm_desct->g = seg_desc->g;
3422 kvm_desct->avl = seg_desc->avl;
3423 if (!selector)
3424 kvm_desct->unusable = 1;
3425 else
3426 kvm_desct->unusable = 0;
3427 kvm_desct->padding = 0;
3428}
3429
b8222ad2
AS		 3430static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3431 u16 selector,
3432 struct descriptor_table *dtable)
37817f29
IE		 3433{
3434 if (selector & 1 << 2) {
3435 struct kvm_segment kvm_seg;
3436
3e6e0aab 3437 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3438
3439 if (kvm_seg.unusable)
3440 dtable->limit = 0;
3441 else
3442 dtable->limit = kvm_seg.limit;
3443 dtable->base = kvm_seg.base;
3444 }
3445 else
3446 kvm_x86_ops->get_gdt(vcpu, dtable);
3447}
3448
3449/* allowed just for 8 bytes segments */
3450static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3451 struct desc_struct *seg_desc)
3452{
98899aa0 3453 gpa_t gpa;
37817f29
IE		 3454 struct descriptor_table dtable;
3455 u16 index = selector >> 3;
3456
b8222ad2 3457 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3458
3459 if (dtable.limit < index * 8 + 7) {
3460 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3461 return 1;
3462 }
98899aa0
MT		 3463 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3464 gpa += index * 8;
3465 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3466}
3467
3468/* allowed just for 8 bytes segments */
3469static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3470 struct desc_struct *seg_desc)
3471{
98899aa0 3472 gpa_t gpa;
37817f29
IE		 3473 struct descriptor_table dtable;
3474 u16 index = selector >> 3;
3475
b8222ad2 3476 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3477
3478 if (dtable.limit < index * 8 + 7)
3479 return 1;
98899aa0
MT		 3480 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3481 gpa += index * 8;
3482 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3483}
3484
3485static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3486 struct desc_struct *seg_desc)
3487{
3488 u32 base_addr;
3489
3490 base_addr = seg_desc->base0;
3491 base_addr |= (seg_desc->base1 << 16);
3492 base_addr |= (seg_desc->base2 << 24);
3493
98899aa0 3494 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3495}
3496
37817f29
IE		 3497static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3498{
3499 struct kvm_segment kvm_seg;
3500
3e6e0aab 3501 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3502 return kvm_seg.selector;
3503}
3504
3505static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3506 u16 selector,
3507 struct kvm_segment *kvm_seg)
3508{
3509 struct desc_struct seg_desc;
3510
3511 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3512 return 1;
3513 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3514 return 0;
3515}
3516
2259e3a7 3517static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3518{
3519 struct kvm_segment segvar = {
3520 .base = selector << 4,
3521 .limit = 0xffff,
3522 .selector = selector,
3523 .type = 3,
3524 .present = 1,
3525 .dpl = 3,
3526 .db = 0,
3527 .s = 1,
3528 .l = 0,
3529 .g = 0,
3530 .avl = 0,
3531 .unusable = 0,
3532 };
3533 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3534 return 0;
3535}
3536
3e6e0aab
GT		 3537int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3538 int type_bits, int seg)
37817f29
IE		 3539{
3540 struct kvm_segment kvm_seg;
3541
f4bbd9aa
AK		 3542 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3543 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3544 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3545 return 1;
3546 kvm_seg.type |= type_bits;
3547
3548 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3549 seg != VCPU_SREG_LDTR)
3550 if (!kvm_seg.s)
3551 kvm_seg.unusable = 1;
3552
3e6e0aab 3553 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3554 return 0;
3555}
3556
3557static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3558 struct tss_segment_32 *tss)
3559{
3560 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3561 tss->eip = kvm_rip_read(vcpu);
37817f29 3562 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3563 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3564 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3565 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3566 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3567 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3568 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3569 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3570 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3571 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3572 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3573 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3574 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3575 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3576 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3577 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3578 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3579}
3580
3581static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3582 struct tss_segment_32 *tss)
3583{
3584 kvm_set_cr3(vcpu, tss->cr3);
3585
5fdbf976 3586 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3587 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3588
5fdbf976
MT		 3589 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3590 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3591 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3592 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3593 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3594 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3595 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3596 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3597
3e6e0aab 3598 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3599 return 1;
3600
3e6e0aab 3601 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3602 return 1;
3603
3e6e0aab 3604 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3605 return 1;
3606
3e6e0aab 3607 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3608 return 1;
3609
3e6e0aab 3610 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3611 return 1;
3612
3e6e0aab 3613 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3614 return 1;
3615
3e6e0aab 3616 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3617 return 1;
3618 return 0;
3619}
3620
3621static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3622 struct tss_segment_16 *tss)
3623{
5fdbf976 3624 tss->ip = kvm_rip_read(vcpu);
37817f29 3625 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3626 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3627 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3628 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3629 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3630 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3631 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3632 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3633 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3634
3635 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3636 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3637 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3638 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3639 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3640 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3641}
3642
3643static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3644 struct tss_segment_16 *tss)
3645{
5fdbf976 3646 kvm_rip_write(vcpu, tss->ip);
37817f29 3647 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3648 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3649 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3650 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3651 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3652 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3653 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3654 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3655 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3656
3e6e0aab 3657 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3658 return 1;
3659
3e6e0aab 3660 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3661 return 1;
3662
3e6e0aab 3663 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3664 return 1;
3665
3e6e0aab 3666 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3667 return 1;
3668
3e6e0aab 3669 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3670 return 1;
3671 return 0;
3672}
3673
8b2cf73c 3674static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3675 u32 old_tss_base,
37817f29
IE		 3676 struct desc_struct *nseg_desc)
3677{
3678 struct tss_segment_16 tss_segment_16;
3679 int ret = 0;
3680
34198bf8
MT		 3681 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3682 sizeof tss_segment_16))
37817f29
IE		 3683 goto out;
3684
3685 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3686
34198bf8
MT		 3687 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3688 sizeof tss_segment_16))
37817f29 3689 goto out;
34198bf8
MT		 3690
3691 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3692 &tss_segment_16, sizeof tss_segment_16))
3693 goto out;
3694
37817f29
IE		 3695 if (load_state_from_tss16(vcpu, &tss_segment_16))
3696 goto out;
3697
3698 ret = 1;
3699out:
3700 return ret;
3701}
3702
8b2cf73c 3703static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3704 u32 old_tss_base,
37817f29
IE		 3705 struct desc_struct *nseg_desc)
3706{
3707 struct tss_segment_32 tss_segment_32;
3708 int ret = 0;
3709
34198bf8
MT		 3710 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3711 sizeof tss_segment_32))
37817f29
IE		 3712 goto out;
3713
3714 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3715
34198bf8
MT		 3716 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3717 sizeof tss_segment_32))
3718 goto out;
3719
3720 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3721 &tss_segment_32, sizeof tss_segment_32))
37817f29 3722 goto out;
34198bf8 3723
37817f29
IE		 3724 if (load_state_from_tss32(vcpu, &tss_segment_32))
3725 goto out;
3726
3727 ret = 1;
3728out:
3729 return ret;
3730}
3731
3732int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3733{
3734 struct kvm_segment tr_seg;
3735 struct desc_struct cseg_desc;
3736 struct desc_struct nseg_desc;
3737 int ret = 0;
34198bf8
MT		 3738 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3739 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3740
34198bf8 3741 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3742
34198bf8
MT		 3743 /* FIXME: Handle errors. Failure to read either TSS or their
3744 * descriptors should generate a pagefault.
3745 */
37817f29
IE		 3746 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3747 goto out;
3748
34198bf8 3749 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3750 goto out;
3751
37817f29
IE		 3752 if (reason != TASK_SWITCH_IRET) {
3753 int cpl;
3754
3755 cpl = kvm_x86_ops->get_cpl(vcpu);
3756 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3757 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3758 return 1;
3759 }
3760 }
3761
3762 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3763 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3764 return 1;
3765 }
3766
3767 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3768 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3769 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3770 }
3771
3772 if (reason == TASK_SWITCH_IRET) {
3773 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3774 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3775 }
3776
3777 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3778
3779 if (nseg_desc.type & 8)
34198bf8 3780 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3781 &nseg_desc);
3782 else
34198bf8 3783 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3784 &nseg_desc);
3785
3786 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3787 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3788 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3789 }
3790
3791 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3792 nseg_desc.type |= (1 << 1);
37817f29
IE		 3793 save_guest_segment_descriptor(vcpu, tss_selector,
3794 &nseg_desc);
3795 }
3796
3797 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3798 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3799 tr_seg.type = 11;
3e6e0aab 3800 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3801out:
37817f29
IE		 3802 return ret;
3803}
3804EXPORT_SYMBOL_GPL(kvm_task_switch);
3805
b6c7a5dc
HB		 3806int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3807 struct kvm_sregs *sregs)
3808{
3809 int mmu_reset_needed = 0;
3810 int i, pending_vec, max_bits;
3811 struct descriptor_table dt;
3812
3813 vcpu_load(vcpu);
3814
3815 dt.limit = sregs->idt.limit;
3816 dt.base = sregs->idt.base;
3817 kvm_x86_ops->set_idt(vcpu, &dt);
3818 dt.limit = sregs->gdt.limit;
3819 dt.base = sregs->gdt.base;
3820 kvm_x86_ops->set_gdt(vcpu, &dt);
3821
ad312c7c
ZX		 3822 vcpu->arch.cr2 = sregs->cr2;
3823 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3824 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3825
2d3ad1f4 3826 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3827
ad312c7c 3828 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3829 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3830 kvm_set_apic_base(vcpu, sregs->apic_base);
3831
3832 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3833
ad312c7c 3834 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3835 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3836 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3837
ad312c7c 3838 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3839 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3840 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3841 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3842
3843 if (mmu_reset_needed)
3844 kvm_mmu_reset_context(vcpu);
3845
3846 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3847 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3848 sizeof vcpu->arch.irq_pending);
3849 vcpu->arch.irq_summary = 0;
3850 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3851 if (vcpu->arch.irq_pending[i])
3852 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3853 } else {
3854 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3855 pending_vec = find_first_bit(
3856 (const unsigned long *)sregs->interrupt_bitmap,
3857 max_bits);
3858 /* Only pending external irq is handled here */
3859 if (pending_vec < max_bits) {
3860 kvm_x86_ops->set_irq(vcpu, pending_vec);
3861 pr_debug("Set back pending irq %d\n",
3862 pending_vec);
3863 }
e4825800 3864 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3865 }
3866
3e6e0aab
GT		 3867 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3868 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3869 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3870 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3871 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3872 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3873
3e6e0aab
GT		 3874 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3875 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3876
9c3e4aab
MT		 3877 /* Older userspace won't unhalt the vcpu on reset. */
3878 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3879 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3880 !(vcpu->arch.cr0 & X86_CR0_PE))
3881 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3882
b6c7a5dc
HB		 3883 vcpu_put(vcpu);
3884
3885 return 0;
3886}
3887
d0bfb940
JK		 3888int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
3889 struct kvm_guest_debug *dbg)
b6c7a5dc 3890{
ae675ef0 3891 int i, r;
b6c7a5dc
HB		 3892
3893 vcpu_load(vcpu);
3894
ae675ef0
JK		 3895 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
3896 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
3897 for (i = 0; i < KVM_NR_DB_REGS; ++i)
3898 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
3899 vcpu->arch.switch_db_regs =
3900 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
3901 } else {
3902 for (i = 0; i < KVM_NR_DB_REGS; i++)
3903 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
3904 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
3905 }
3906
b6c7a5dc
HB		 3907 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3908
d0bfb940
JK		 3909 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
3910 kvm_queue_exception(vcpu, DB_VECTOR);
3911 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
3912 kvm_queue_exception(vcpu, BP_VECTOR);
3913
b6c7a5dc
HB		 3914 vcpu_put(vcpu);
3915
3916 return r;
3917}
3918
d0752060
HB		 3919/*
3920 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3921 * we have asm/x86/processor.h
3922 */
3923struct fxsave {
3924 u16 cwd;
3925 u16 swd;
3926 u16 twd;
3927 u16 fop;
3928 u64 rip;
3929 u64 rdp;
3930 u32 mxcsr;
3931 u32 mxcsr_mask;
3932 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3933#ifdef CONFIG_X86_64
3934 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3935#else
3936 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3937#endif
3938};
3939
8b006791
ZX		 3940/*
3941 * Translate a guest virtual address to a guest physical address.
3942 */
3943int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3944 struct kvm_translation *tr)
3945{
3946 unsigned long vaddr = tr->linear_address;
3947 gpa_t gpa;
3948
3949 vcpu_load(vcpu);
72dc67a6 3950 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3951 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3952 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3953 tr->physical_address = gpa;
3954 tr->valid = gpa != UNMAPPED_GVA;
3955 tr->writeable = 1;
3956 tr->usermode = 0;
8b006791
ZX		 3957 vcpu_put(vcpu);
3958
3959 return 0;
3960}
3961
d0752060
HB		 3962int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3963{
ad312c7c 3964 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3965
3966 vcpu_load(vcpu);
3967
3968 memcpy(fpu->fpr, fxsave->st_space, 128);
3969 fpu->fcw = fxsave->cwd;
3970 fpu->fsw = fxsave->swd;
3971 fpu->ftwx = fxsave->twd;
3972 fpu->last_opcode = fxsave->fop;
3973 fpu->last_ip = fxsave->rip;
3974 fpu->last_dp = fxsave->rdp;
3975 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3976
3977 vcpu_put(vcpu);
3978
3979 return 0;
3980}
3981
3982int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3983{
ad312c7c 3984 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3985
3986 vcpu_load(vcpu);
3987
3988 memcpy(fxsave->st_space, fpu->fpr, 128);
3989 fxsave->cwd = fpu->fcw;
3990 fxsave->swd = fpu->fsw;
3991 fxsave->twd = fpu->ftwx;
3992 fxsave->fop = fpu->last_opcode;
3993 fxsave->rip = fpu->last_ip;
3994 fxsave->rdp = fpu->last_dp;
3995 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3996
3997 vcpu_put(vcpu);
3998
3999 return 0;
4000}
4001
4002void fx_init(struct kvm_vcpu *vcpu)
4003{
4004 unsigned after_mxcsr_mask;
4005
bc1a34f1
AA		 4006 /*
4007 * Touch the fpu the first time in non atomic context as if
4008 * this is the first fpu instruction the exception handler
4009 * will fire before the instruction returns and it'll have to
4010 * allocate ram with GFP_KERNEL.
4011 */
4012 if (!used_math())
d6e88aec 4013 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4014
d0752060
HB		 4015 /* Initialize guest FPU by resetting ours and saving into guest's */
4016 preempt_disable();
d6e88aec
AK		 4017 kvm_fx_save(&vcpu->arch.host_fx_image);
4018 kvm_fx_finit();
4019 kvm_fx_save(&vcpu->arch.guest_fx_image);
4020 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4021 preempt_enable();
4022
ad312c7c 4023 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4024 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4025 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4026 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4027 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4028}
4029EXPORT_SYMBOL_GPL(fx_init);
4030
4031void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4032{
4033 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4034 return;
4035
4036 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4037 kvm_fx_save(&vcpu->arch.host_fx_image);
4038 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4039}
4040EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4041
4042void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4043{
4044 if (!vcpu->guest_fpu_loaded)
4045 return;
4046
4047 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4048 kvm_fx_save(&vcpu->arch.guest_fx_image);
4049 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4050 ++vcpu->stat.fpu_reload;
d0752060
HB		 4051}
4052EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4053
4054void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4055{
4056 kvm_x86_ops->vcpu_free(vcpu);
4057}
4058
4059struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4060 unsigned int id)
4061{
26e5215f
AK		 4062 return kvm_x86_ops->vcpu_create(kvm, id);
4063}
e9b11c17 4064
26e5215f
AK		 4065int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4066{
4067 int r;
e9b11c17
ZX		 4068
4069 /* We do fxsave: this must be aligned. */
ad312c7c 4070 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4071
0bed3b56 4072 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4073 vcpu_load(vcpu);
4074 r = kvm_arch_vcpu_reset(vcpu);
4075 if (r == 0)
4076 r = kvm_mmu_setup(vcpu);
4077 vcpu_put(vcpu);
4078 if (r < 0)
4079 goto free_vcpu;
4080
26e5215f 4081 return 0;
e9b11c17
ZX		 4082free_vcpu:
4083 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4084 return r;
e9b11c17
ZX		 4085}
4086
d40ccc62 4087void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4088{
4089 vcpu_load(vcpu);
4090 kvm_mmu_unload(vcpu);
4091 vcpu_put(vcpu);
4092
4093 kvm_x86_ops->vcpu_free(vcpu);
4094}
4095
4096int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4097{
448fa4a9
JK		 4098 vcpu->arch.nmi_pending = false;
4099 vcpu->arch.nmi_injected = false;
4100
42dbaa5a
JK		 4101 vcpu->arch.switch_db_regs = 0;
4102 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4103 vcpu->arch.dr6 = DR6_FIXED_1;
4104 vcpu->arch.dr7 = DR7_FIXED_1;
4105
e9b11c17
ZX		 4106 return kvm_x86_ops->vcpu_reset(vcpu);
4107}
4108
4109void kvm_arch_hardware_enable(void *garbage)
4110{
4111 kvm_x86_ops->hardware_enable(garbage);
4112}
4113
4114void kvm_arch_hardware_disable(void *garbage)
4115{
4116 kvm_x86_ops->hardware_disable(garbage);
4117}
4118
4119int kvm_arch_hardware_setup(void)
4120{
4121 return kvm_x86_ops->hardware_setup();
4122}
4123
4124void kvm_arch_hardware_unsetup(void)
4125{
4126 kvm_x86_ops->hardware_unsetup();
4127}
4128
4129void kvm_arch_check_processor_compat(void *rtn)
4130{
4131 kvm_x86_ops->check_processor_compatibility(rtn);
4132}
4133
4134int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4135{
4136 struct page *page;
4137 struct kvm *kvm;
4138 int r;
4139
4140 BUG_ON(vcpu->kvm == NULL);
4141 kvm = vcpu->kvm;
4142
ad312c7c 4143 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4144 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4145 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4146 else
a4535290 4147 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4148
4149 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4150 if (!page) {
4151 r = -ENOMEM;
4152 goto fail;
4153 }
ad312c7c 4154 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4155
4156 r = kvm_mmu_create(vcpu);
4157 if (r < 0)
4158 goto fail_free_pio_data;
4159
4160 if (irqchip_in_kernel(kvm)) {
4161 r = kvm_create_lapic(vcpu);
4162 if (r < 0)
4163 goto fail_mmu_destroy;
4164 }
4165
4166 return 0;
4167
4168fail_mmu_destroy:
4169 kvm_mmu_destroy(vcpu);
4170fail_free_pio_data:
ad312c7c 4171 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4172fail:
4173 return r;
4174}
4175
4176void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4177{
4178 kvm_free_lapic(vcpu);
3200f405 4179 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4180 kvm_mmu_destroy(vcpu);
3200f405 4181 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4182 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4183}
d19a9cd2
ZX		 4184
4185struct kvm *kvm_arch_create_vm(void)
4186{
4187 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4188
4189 if (!kvm)
4190 return ERR_PTR(-ENOMEM);
4191
f05e70ac 4192 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4193 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4194 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4195
5550af4d
SY		 4196 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4197 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4198
53f658b3
MT		 4199 rdtscll(kvm->arch.vm_init_tsc);
4200
d19a9cd2
ZX		 4201 return kvm;
4202}
4203
4204static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4205{
4206 vcpu_load(vcpu);
4207 kvm_mmu_unload(vcpu);
4208 vcpu_put(vcpu);
4209}
4210
4211static void kvm_free_vcpus(struct kvm *kvm)
4212{
4213 unsigned int i;
4214
4215 /*
4216 * Unpin any mmu pages first.
4217 */
4218 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4219 if (kvm->vcpus[i])
4220 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4221 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4222 if (kvm->vcpus[i]) {
4223 kvm_arch_vcpu_free(kvm->vcpus[i]);
4224 kvm->vcpus[i] = NULL;
4225 }
4226 }
4227
4228}
4229
ad8ba2cd
SY		 4230void kvm_arch_sync_events(struct kvm *kvm)
4231{
ba4cef31 4232 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4233}
4234
d19a9cd2
ZX		 4235void kvm_arch_destroy_vm(struct kvm *kvm)
4236{
6eb55818 4237 kvm_iommu_unmap_guest(kvm);
7837699f 4238 kvm_free_pit(kvm);
d7deeeb0
ZX		 4239 kfree(kvm->arch.vpic);
4240 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4241 kvm_free_vcpus(kvm);
4242 kvm_free_physmem(kvm);
3d45830c
AK		 4243 if (kvm->arch.apic_access_page)
4244 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4245 if (kvm->arch.ept_identity_pagetable)
4246 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4247 kfree(kvm);
4248}
0de10343
ZX		 4249
4250int kvm_arch_set_memory_region(struct kvm *kvm,
4251 struct kvm_userspace_memory_region *mem,
4252 struct kvm_memory_slot old,
4253 int user_alloc)
4254{
4255 int npages = mem->memory_size >> PAGE_SHIFT;
4256 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4257
4258 /*To keep backward compatibility with older userspace,
4259 *x86 needs to hanlde !user_alloc case.
4260 */
4261 if (!user_alloc) {
4262 if (npages && !old.rmap) {
604b38ac
AA		 4263 unsigned long userspace_addr;
4264
72dc67a6 4265 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4266 userspace_addr = do_mmap(NULL, 0,
4267 npages * PAGE_SIZE,
4268 PROT_READ | PROT_WRITE,
acee3c04 4269 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4270 0);
72dc67a6 4271 up_write(&current->mm->mmap_sem);
0de10343 4272
604b38ac
AA		 4273 if (IS_ERR((void *)userspace_addr))
4274 return PTR_ERR((void *)userspace_addr);
4275
4276 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4277 spin_lock(&kvm->mmu_lock);
4278 memslot->userspace_addr = userspace_addr;
4279 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4280 } else {
4281 if (!old.user_alloc && old.rmap) {
4282 int ret;
4283
72dc67a6 4284 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4285 ret = do_munmap(current->mm, old.userspace_addr,
4286 old.npages * PAGE_SIZE);
72dc67a6 4287 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4288 if (ret < 0)
4289 printk(KERN_WARNING
4290 "kvm_vm_ioctl_set_memory_region: "
4291 "failed to munmap memory\n");
4292 }
4293 }
4294 }
4295
f05e70ac 4296 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4297 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4298 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4299 }
4300
4301 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4302 kvm_flush_remote_tlbs(kvm);
4303
4304 return 0;
4305}
1d737c8a 4306
34d4cb8f
MT		 4307void kvm_arch_flush_shadow(struct kvm *kvm)
4308{
4309 kvm_mmu_zap_all(kvm);
4310}
4311
1d737c8a
ZX		 4312int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4313{
a4535290 4314 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4315 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4316 || vcpu->arch.nmi_pending;
1d737c8a 4317}
5736199a
ZX		 4318
4319static void vcpu_kick_intr(void *info)
4320{
4321#ifdef DEBUG
4322 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4323 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4324#endif
4325}
4326
4327void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4328{
4329 int ipi_pcpu = vcpu->cpu;
e9571ed5 4330 int cpu = get_cpu();
5736199a
ZX		 4331
4332 if (waitqueue_active(&vcpu->wq)) {
4333 wake_up_interruptible(&vcpu->wq);
4334 ++vcpu->stat.halt_wakeup;
4335 }
e9571ed5
MT		 4336 /*
4337 * We may be called synchronously with irqs disabled in guest mode,
4338 * So need not to call smp_call_function_single() in that case.
4339 */
4340 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4341 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4342 put_cpu();
5736199a 4343}
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