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KVM: fix irq_source_id size verification
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
cb142eb7 80static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 81static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
82 struct kvm_cpuid_entry2 __user *entries);
83
97896d04 84struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 85EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 86
ed85c068
AP		 87int ignore_msrs = 0;
88module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
89
417bc304 90struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 91 { "pf_fixed", VCPU_STAT(pf_fixed) },
92 { "pf_guest", VCPU_STAT(pf_guest) },
93 { "tlb_flush", VCPU_STAT(tlb_flush) },
94 { "invlpg", VCPU_STAT(invlpg) },
95 { "exits", VCPU_STAT(exits) },
96 { "io_exits", VCPU_STAT(io_exits) },
97 { "mmio_exits", VCPU_STAT(mmio_exits) },
98 { "signal_exits", VCPU_STAT(signal_exits) },
99 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 100 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 101 { "halt_exits", VCPU_STAT(halt_exits) },
102 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 103 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 104 { "request_irq", VCPU_STAT(request_irq_exits) },
105 { "irq_exits", VCPU_STAT(irq_exits) },
106 { "host_state_reload", VCPU_STAT(host_state_reload) },
107 { "efer_reload", VCPU_STAT(efer_reload) },
108 { "fpu_reload", VCPU_STAT(fpu_reload) },
109 { "insn_emulation", VCPU_STAT(insn_emulation) },
110 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 111 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 112 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 113 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
114 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
115 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
116 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
117 { "mmu_flooded", VM_STAT(mmu_flooded) },
118 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 119 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 120 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 121 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 122 { "largepages", VM_STAT(lpages) },
417bc304
HB		 123 { NULL }
124};
125
5fb76f9b
CO		 126unsigned long segment_base(u16 selector)
127{
128 struct descriptor_table gdt;
a5f61300 129 struct desc_struct *d;
5fb76f9b
CO		 130 unsigned long table_base;
131 unsigned long v;
132
133 if (selector == 0)
134 return 0;
135
b792c344 136 kvm_get_gdt(&gdt);
5fb76f9b
CO		 137 table_base = gdt.base;
138
139 if (selector & 4) { /* from ldt */
b792c344 140 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 141
5fb76f9b
CO		 142 table_base = segment_base(ldt_selector);
143 }
a5f61300 144 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 145 v = get_desc_base(d);
5fb76f9b 146#ifdef CONFIG_X86_64
a5f61300
AK		 147 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
148 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 149#endif
150 return v;
151}
152EXPORT_SYMBOL_GPL(segment_base);
153
6866b83e
CO		 154u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
155{
156 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 157 return vcpu->arch.apic_base;
6866b83e 158 else
ad312c7c 159 return vcpu->arch.apic_base;
6866b83e
CO		 160}
161EXPORT_SYMBOL_GPL(kvm_get_apic_base);
162
163void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
164{
165 /* TODO: reserve bits check */
166 if (irqchip_in_kernel(vcpu->kvm))
167 kvm_lapic_set_base(vcpu, data);
168 else
ad312c7c 169 vcpu->arch.apic_base = data;
6866b83e
CO		 170}
171EXPORT_SYMBOL_GPL(kvm_set_apic_base);
172
298101da
AK		 173void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
174{
ad312c7c
ZX		 175 WARN_ON(vcpu->arch.exception.pending);
176 vcpu->arch.exception.pending = true;
177 vcpu->arch.exception.has_error_code = false;
178 vcpu->arch.exception.nr = nr;
298101da
AK		 179}
180EXPORT_SYMBOL_GPL(kvm_queue_exception);
181
c3c91fee
AK		 182void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
183 u32 error_code)
184{
185 ++vcpu->stat.pf_guest;
d8017474 186
71c4dfaf 187 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 188 switch(vcpu->arch.exception.nr) {
189 case DF_VECTOR:
71c4dfaf
JR		 190 /* triple fault -> shutdown */
191 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 192 return;
193 case PF_VECTOR:
194 vcpu->arch.exception.nr = DF_VECTOR;
195 vcpu->arch.exception.error_code = 0;
196 return;
197 default:
198 /* replace previous exception with a new one in a hope
199 that instruction re-execution will regenerate lost
200 exception */
201 vcpu->arch.exception.pending = false;
202 break;
71c4dfaf 203 }
c3c91fee 204 }
ad312c7c 205 vcpu->arch.cr2 = addr;
c3c91fee
AK		 206 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
207}
208
3419ffc8
SY		 209void kvm_inject_nmi(struct kvm_vcpu *vcpu)
210{
211 vcpu->arch.nmi_pending = 1;
212}
213EXPORT_SYMBOL_GPL(kvm_inject_nmi);
214
298101da
AK		 215void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
216{
ad312c7c
ZX		 217 WARN_ON(vcpu->arch.exception.pending);
218 vcpu->arch.exception.pending = true;
219 vcpu->arch.exception.has_error_code = true;
220 vcpu->arch.exception.nr = nr;
221 vcpu->arch.exception.error_code = error_code;
298101da
AK		 222}
223EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
224
0a79b009
AK		 225/*
226 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
227 * a #GP and return false.
228 */
229bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 230{
0a79b009
AK		 231 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
232 return true;
233 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
234 return false;
298101da 235}
0a79b009 236EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 237
a03490ed
CO		 238/*
239 * Load the pae pdptrs. Return true is they are all valid.
240 */
241int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
242{
243 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
244 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
245 int i;
246 int ret;
ad312c7c 247 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 248
a03490ed
CO		 249 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
250 offset * sizeof(u64), sizeof(pdpte));
251 if (ret < 0) {
252 ret = 0;
253 goto out;
254 }
255 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 256 if (is_present_gpte(pdpte[i]) &&
20c466b5 257 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 258 ret = 0;
259 goto out;
260 }
261 }
262 ret = 1;
263
ad312c7c 264 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 265 __set_bit(VCPU_EXREG_PDPTR,
266 (unsigned long *)&vcpu->arch.regs_avail);
267 __set_bit(VCPU_EXREG_PDPTR,
268 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 269out:
a03490ed
CO		 270
271 return ret;
272}
cc4b6871 273EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 274
d835dfec
AK		 275static bool pdptrs_changed(struct kvm_vcpu *vcpu)
276{
ad312c7c 277 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 278 bool changed = true;
279 int r;
280
281 if (is_long_mode(vcpu) || !is_pae(vcpu))
282 return false;
283
6de4f3ad
AK		 284 if (!test_bit(VCPU_EXREG_PDPTR,
285 (unsigned long *)&vcpu->arch.regs_avail))
286 return true;
287
ad312c7c 288 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 289 if (r < 0)
290 goto out;
ad312c7c 291 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 292out:
d835dfec
AK		 293
294 return changed;
295}
296
2d3ad1f4 297void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 298{
299 if (cr0 & CR0_RESERVED_BITS) {
300 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 301 cr0, vcpu->arch.cr0);
c1a5d4f9 302 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 303 return;
304 }
305
306 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
307 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 308 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 309 return;
310 }
311
312 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
313 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
314 "and a clear PE flag\n");
c1a5d4f9 315 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 316 return;
317 }
318
319 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
320#ifdef CONFIG_X86_64
ad312c7c 321 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 322 int cs_db, cs_l;
323
324 if (!is_pae(vcpu)) {
325 printk(KERN_DEBUG "set_cr0: #GP, start paging "
326 "in long mode while PAE is disabled\n");
c1a5d4f9 327 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 328 return;
329 }
330 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
331 if (cs_l) {
332 printk(KERN_DEBUG "set_cr0: #GP, start paging "
333 "in long mode while CS.L == 1\n");
c1a5d4f9 334 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 335 return;
336
337 }
338 } else
339#endif
ad312c7c 340 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 341 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
342 "reserved bits\n");
c1a5d4f9 343 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 344 return;
345 }
346
347 }
348
349 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 350 vcpu->arch.cr0 = cr0;
a03490ed 351
a03490ed 352 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 353 return;
354}
2d3ad1f4 355EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 356
2d3ad1f4 357void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 358{
2d3ad1f4 359 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 360}
2d3ad1f4 361EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 362
2d3ad1f4 363void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 364{
a2edf57f
AK		 365 unsigned long old_cr4 = vcpu->arch.cr4;
366 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
367
a03490ed
CO		 368 if (cr4 & CR4_RESERVED_BITS) {
369 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 370 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 371 return;
372 }
373
374 if (is_long_mode(vcpu)) {
375 if (!(cr4 & X86_CR4_PAE)) {
376 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
377 "in long mode\n");
c1a5d4f9 378 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 379 return;
380 }
a2edf57f
AK		 381 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
382 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 383 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 384 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 385 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 386 return;
387 }
388
389 if (cr4 & X86_CR4_VMXE) {
390 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 391 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 392 return;
393 }
394 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 395 vcpu->arch.cr4 = cr4;
5a41accd 396 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 397 kvm_mmu_reset_context(vcpu);
a03490ed 398}
2d3ad1f4 399EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 400
2d3ad1f4 401void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 402{
ad312c7c 403 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 404 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 405 kvm_mmu_flush_tlb(vcpu);
406 return;
407 }
408
a03490ed
CO		 409 if (is_long_mode(vcpu)) {
410 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
411 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 412 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 413 return;
414 }
415 } else {
416 if (is_pae(vcpu)) {
417 if (cr3 & CR3_PAE_RESERVED_BITS) {
418 printk(KERN_DEBUG
419 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 420 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 421 return;
422 }
423 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
424 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
425 "reserved bits\n");
c1a5d4f9 426 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 427 return;
428 }
429 }
430 /*
431 * We don't check reserved bits in nonpae mode, because
432 * this isn't enforced, and VMware depends on this.
433 */
434 }
435
a03490ed
CO		 436 /*
437 * Does the new cr3 value map to physical memory? (Note, we
438 * catch an invalid cr3 even in real-mode, because it would
439 * cause trouble later on when we turn on paging anyway.)
440 *
441 * A real CPU would silently accept an invalid cr3 and would
442 * attempt to use it - with largely undefined (and often hard
443 * to debug) behavior on the guest side.
444 */
445 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 446 kvm_inject_gp(vcpu, 0);
a03490ed 447 else {
ad312c7c
ZX		 448 vcpu->arch.cr3 = cr3;
449 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 450 }
a03490ed 451}
2d3ad1f4 452EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 453
2d3ad1f4 454void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 455{
456 if (cr8 & CR8_RESERVED_BITS) {
457 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 459 return;
460 }
461 if (irqchip_in_kernel(vcpu->kvm))
462 kvm_lapic_set_tpr(vcpu, cr8);
463 else
ad312c7c 464 vcpu->arch.cr8 = cr8;
a03490ed 465}
2d3ad1f4 466EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 467
2d3ad1f4 468unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 469{
470 if (irqchip_in_kernel(vcpu->kvm))
471 return kvm_lapic_get_cr8(vcpu);
472 else
ad312c7c 473 return vcpu->arch.cr8;
a03490ed 474}
2d3ad1f4 475EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 476
d8017474
AG		 477static inline u32 bit(int bitno)
478{
479 return 1 << (bitno & 31);
480}
481
043405e1
CO		 482/*
483 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
484 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
485 *
486 * This list is modified at module load time to reflect the
e3267cbb
GC		 487 * capabilities of the host cpu. This capabilities test skips MSRs that are
488 * kvm-specific. Those are put in the beginning of the list.
043405e1 489 */
e3267cbb
GC		 490
491#define KVM_SAVE_MSRS_BEGIN 2
043405e1 492static u32 msrs_to_save[] = {
e3267cbb 493 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
043405e1
CO		 494 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
495 MSR_K6_STAR,
496#ifdef CONFIG_X86_64
497 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
498#endif
e3267cbb 499 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 500};
501
502static unsigned num_msrs_to_save;
503
504static u32 emulated_msrs[] = {
505 MSR_IA32_MISC_ENABLE,
506};
507
15c4a640
CO		 508static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
509{
f2b4b7dd 510 if (efer & efer_reserved_bits) {
15c4a640
CO		 511 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
512 efer);
c1a5d4f9 513 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 514 return;
515 }
516
517 if (is_paging(vcpu)
ad312c7c 518 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 519 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 520 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 521 return;
522 }
523
1b2fd70c
AG		 524 if (efer & EFER_FFXSR) {
525 struct kvm_cpuid_entry2 *feat;
526
527 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
528 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
529 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
530 kvm_inject_gp(vcpu, 0);
531 return;
532 }
533 }
534
d8017474
AG		 535 if (efer & EFER_SVME) {
536 struct kvm_cpuid_entry2 *feat;
537
538 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
539 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
540 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
541 kvm_inject_gp(vcpu, 0);
542 return;
543 }
544 }
545
15c4a640
CO		 546 kvm_x86_ops->set_efer(vcpu, efer);
547
548 efer &= ~EFER_LMA;
ad312c7c 549 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 550
ad312c7c 551 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 552
553 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
554 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 555}
556
f2b4b7dd
JR		 557void kvm_enable_efer_bits(u64 mask)
558{
559 efer_reserved_bits &= ~mask;
560}
561EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
562
563
15c4a640
CO		 564/*
565 * Writes msr value into into the appropriate "register".
566 * Returns 0 on success, non-0 otherwise.
567 * Assumes vcpu_load() was already called.
568 */
569int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
570{
571 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
572}
573
313a3dc7
CO		 574/*
575 * Adapt set_msr() to msr_io()'s calling convention
576 */
577static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
578{
579 return kvm_set_msr(vcpu, index, *data);
580}
581
18068523
GOC		 582static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
583{
584 static int version;
50d0a0f9
GH		 585 struct pvclock_wall_clock wc;
586 struct timespec now, sys, boot;
18068523
GOC		 587
588 if (!wall_clock)
589 return;
590
591 version++;
592
18068523
GOC		 593 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
594
50d0a0f9
GH		 595 /*
596 * The guest calculates current wall clock time by adding
597 * system time (updated by kvm_write_guest_time below) to the
598 * wall clock specified here. guest system time equals host
599 * system time for us, thus we must fill in host boot time here.
600 */
601 now = current_kernel_time();
602 ktime_get_ts(&sys);
603 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
604
605 wc.sec = boot.tv_sec;
606 wc.nsec = boot.tv_nsec;
607 wc.version = version;
18068523
GOC		 608
609 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
610
611 version++;
612 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 613}
614
50d0a0f9
GH		 615static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
616{
617 uint32_t quotient, remainder;
618
619 /* Don't try to replace with do_div(), this one calculates
620 * "(dividend << 32) / divisor" */
621 __asm__ ( "divl %4"
622 : "=a" (quotient), "=d" (remainder)
623 : "0" (0), "1" (dividend), "r" (divisor) );
624 return quotient;
625}
626
627static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
628{
629 uint64_t nsecs = 1000000000LL;
630 int32_t shift = 0;
631 uint64_t tps64;
632 uint32_t tps32;
633
634 tps64 = tsc_khz * 1000LL;
635 while (tps64 > nsecs*2) {
636 tps64 >>= 1;
637 shift--;
638 }
639
640 tps32 = (uint32_t)tps64;
641 while (tps32 <= (uint32_t)nsecs) {
642 tps32 <<= 1;
643 shift++;
644 }
645
646 hv_clock->tsc_shift = shift;
647 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
648
649 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 650 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 651 hv_clock->tsc_to_system_mul);
652}
653
c8076604
GH		 654static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
655
18068523
GOC		 656static void kvm_write_guest_time(struct kvm_vcpu *v)
657{
658 struct timespec ts;
659 unsigned long flags;
660 struct kvm_vcpu_arch *vcpu = &v->arch;
661 void *shared_kaddr;
463656c0 662 unsigned long this_tsc_khz;
18068523
GOC		 663
664 if ((!vcpu->time_page))
665 return;
666
463656c0
AK		 667 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
668 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
669 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
670 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 671 }
463656c0 672 put_cpu_var(cpu_tsc_khz);
50d0a0f9 673
18068523
GOC		 674 /* Keep irq disabled to prevent changes to the clock */
675 local_irq_save(flags);
af24a4e4 676 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 677 ktime_get_ts(&ts);
678 local_irq_restore(flags);
679
680 /* With all the info we got, fill in the values */
681
682 vcpu->hv_clock.system_time = ts.tv_nsec +
683 (NSEC_PER_SEC * (u64)ts.tv_sec);
684 /*
685 * The interface expects us to write an even number signaling that the
686 * update is finished. Since the guest won't see the intermediate
50d0a0f9 687 * state, we just increase by 2 at the end.
18068523 688 */
50d0a0f9 689 vcpu->hv_clock.version += 2;
18068523
GOC		 690
691 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
692
693 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 694 sizeof(vcpu->hv_clock));
18068523
GOC		 695
696 kunmap_atomic(shared_kaddr, KM_USER0);
697
698 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
699}
700
c8076604
GH		 701static int kvm_request_guest_time_update(struct kvm_vcpu *v)
702{
703 struct kvm_vcpu_arch *vcpu = &v->arch;
704
705 if (!vcpu->time_page)
706 return 0;
707 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
708 return 1;
709}
710
9ba075a6
AK		 711static bool msr_mtrr_valid(unsigned msr)
712{
713 switch (msr) {
714 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
715 case MSR_MTRRfix64K_00000:
716 case MSR_MTRRfix16K_80000:
717 case MSR_MTRRfix16K_A0000:
718 case MSR_MTRRfix4K_C0000:
719 case MSR_MTRRfix4K_C8000:
720 case MSR_MTRRfix4K_D0000:
721 case MSR_MTRRfix4K_D8000:
722 case MSR_MTRRfix4K_E0000:
723 case MSR_MTRRfix4K_E8000:
724 case MSR_MTRRfix4K_F0000:
725 case MSR_MTRRfix4K_F8000:
726 case MSR_MTRRdefType:
727 case MSR_IA32_CR_PAT:
728 return true;
729 case 0x2f8:
730 return true;
731 }
732 return false;
733}
734
d6289b93
MT		 735static bool valid_pat_type(unsigned t)
736{
737 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
738}
739
740static bool valid_mtrr_type(unsigned t)
741{
742 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
743}
744
745static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
746{
747 int i;
748
749 if (!msr_mtrr_valid(msr))
750 return false;
751
752 if (msr == MSR_IA32_CR_PAT) {
753 for (i = 0; i < 8; i++)
754 if (!valid_pat_type((data >> (i * 8)) & 0xff))
755 return false;
756 return true;
757 } else if (msr == MSR_MTRRdefType) {
758 if (data & ~0xcff)
759 return false;
760 return valid_mtrr_type(data & 0xff);
761 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
762 for (i = 0; i < 8 ; i++)
763 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
764 return false;
765 return true;
766 }
767
768 /* variable MTRRs */
769 return valid_mtrr_type(data & 0xff);
770}
771
9ba075a6
AK		 772static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
773{
0bed3b56
SY		 774 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
775
d6289b93 776 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 777 return 1;
778
0bed3b56
SY		 779 if (msr == MSR_MTRRdefType) {
780 vcpu->arch.mtrr_state.def_type = data;
781 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
782 } else if (msr == MSR_MTRRfix64K_00000)
783 p[0] = data;
784 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
785 p[1 + msr - MSR_MTRRfix16K_80000] = data;
786 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
787 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
788 else if (msr == MSR_IA32_CR_PAT)
789 vcpu->arch.pat = data;
790 else { /* Variable MTRRs */
791 int idx, is_mtrr_mask;
792 u64 *pt;
793
794 idx = (msr - 0x200) / 2;
795 is_mtrr_mask = msr - 0x200 - 2 * idx;
796 if (!is_mtrr_mask)
797 pt =
798 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
799 else
800 pt =
801 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
802 *pt = data;
803 }
804
805 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 806 return 0;
807}
15c4a640 808
890ca9ae 809static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 810{
890ca9ae
HY		 811 u64 mcg_cap = vcpu->arch.mcg_cap;
812 unsigned bank_num = mcg_cap & 0xff;
813
15c4a640 814 switch (msr) {
15c4a640 815 case MSR_IA32_MCG_STATUS:
890ca9ae 816 vcpu->arch.mcg_status = data;
15c4a640 817 break;
c7ac679c 818 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 819 if (!(mcg_cap & MCG_CTL_P))
820 return 1;
821 if (data != 0 && data != ~(u64)0)
822 return -1;
823 vcpu->arch.mcg_ctl = data;
824 break;
825 default:
826 if (msr >= MSR_IA32_MC0_CTL &&
827 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
828 u32 offset = msr - MSR_IA32_MC0_CTL;
829 /* only 0 or all 1s can be written to IA32_MCi_CTL */
830 if ((offset & 0x3) == 0 &&
831 data != 0 && data != ~(u64)0)
832 return -1;
833 vcpu->arch.mce_banks[offset] = data;
834 break;
835 }
836 return 1;
837 }
838 return 0;
839}
840
ffde22ac
ES		 841static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
842{
843 struct kvm *kvm = vcpu->kvm;
844 int lm = is_long_mode(vcpu);
845 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
846 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
847 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
848 : kvm->arch.xen_hvm_config.blob_size_32;
849 u32 page_num = data & ~PAGE_MASK;
850 u64 page_addr = data & PAGE_MASK;
851 u8 *page;
852 int r;
853
854 r = -E2BIG;
855 if (page_num >= blob_size)
856 goto out;
857 r = -ENOMEM;
858 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
859 if (!page)
860 goto out;
861 r = -EFAULT;
862 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
863 goto out_free;
864 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
865 goto out_free;
866 r = 0;
867out_free:
868 kfree(page);
869out:
870 return r;
871}
872
15c4a640
CO		 873int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
874{
875 switch (msr) {
15c4a640
CO		 876 case MSR_EFER:
877 set_efer(vcpu, data);
878 break;
8f1589d9
AP		 879 case MSR_K7_HWCR:
880 data &= ~(u64)0x40; /* ignore flush filter disable */
881 if (data != 0) {
882 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
883 data);
884 return 1;
885 }
15c4a640 886 break;
f7c6d140
AP		 887 case MSR_FAM10H_MMIO_CONF_BASE:
888 if (data != 0) {
889 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
890 "0x%llx\n", data);
891 return 1;
892 }
15c4a640 893 break;
c323c0e5 894 case MSR_AMD64_NB_CFG:
c7ac679c 895 break;
b5e2fec0
AG		 896 case MSR_IA32_DEBUGCTLMSR:
897 if (!data) {
898 /* We support the non-activated case already */
899 break;
900 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
901 /* Values other than LBR and BTF are vendor-specific,
902 thus reserved and should throw a #GP */
903 return 1;
904 }
905 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
906 __func__, data);
907 break;
15c4a640
CO		 908 case MSR_IA32_UCODE_REV:
909 case MSR_IA32_UCODE_WRITE:
61a6bd67 910 case MSR_VM_HSAVE_PA:
6098ca93 911 case MSR_AMD64_PATCH_LOADER:
15c4a640 912 break;
9ba075a6
AK		 913 case 0x200 ... 0x2ff:
914 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 915 case MSR_IA32_APICBASE:
916 kvm_set_apic_base(vcpu, data);
917 break;
0105d1a5
GN		 918 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
919 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 920 case MSR_IA32_MISC_ENABLE:
ad312c7c 921 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 922 break;
18068523
GOC		 923 case MSR_KVM_WALL_CLOCK:
924 vcpu->kvm->arch.wall_clock = data;
925 kvm_write_wall_clock(vcpu->kvm, data);
926 break;
927 case MSR_KVM_SYSTEM_TIME: {
928 if (vcpu->arch.time_page) {
929 kvm_release_page_dirty(vcpu->arch.time_page);
930 vcpu->arch.time_page = NULL;
931 }
932
933 vcpu->arch.time = data;
934
935 /* we verify if the enable bit is set... */
936 if (!(data & 1))
937 break;
938
939 /* ...but clean it before doing the actual write */
940 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
941
18068523
GOC		 942 vcpu->arch.time_page =
943 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 944
945 if (is_error_page(vcpu->arch.time_page)) {
946 kvm_release_page_clean(vcpu->arch.time_page);
947 vcpu->arch.time_page = NULL;
948 }
949
c8076604 950 kvm_request_guest_time_update(vcpu);
18068523
GOC		 951 break;
952 }
890ca9ae
HY		 953 case MSR_IA32_MCG_CTL:
954 case MSR_IA32_MCG_STATUS:
955 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
956 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 957
958 /* Performance counters are not protected by a CPUID bit,
959 * so we should check all of them in the generic path for the sake of
960 * cross vendor migration.
961 * Writing a zero into the event select MSRs disables them,
962 * which we perfectly emulate ;-). Any other value should be at least
963 * reported, some guests depend on them.
964 */
965 case MSR_P6_EVNTSEL0:
966 case MSR_P6_EVNTSEL1:
967 case MSR_K7_EVNTSEL0:
968 case MSR_K7_EVNTSEL1:
969 case MSR_K7_EVNTSEL2:
970 case MSR_K7_EVNTSEL3:
971 if (data != 0)
972 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
973 "0x%x data 0x%llx\n", msr, data);
974 break;
975 /* at least RHEL 4 unconditionally writes to the perfctr registers,
976 * so we ignore writes to make it happy.
977 */
978 case MSR_P6_PERFCTR0:
979 case MSR_P6_PERFCTR1:
980 case MSR_K7_PERFCTR0:
981 case MSR_K7_PERFCTR1:
982 case MSR_K7_PERFCTR2:
983 case MSR_K7_PERFCTR3:
984 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
985 "0x%x data 0x%llx\n", msr, data);
986 break;
15c4a640 987 default:
ffde22ac
ES		 988 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
989 return xen_hvm_config(vcpu, data);
ed85c068
AP		 990 if (!ignore_msrs) {
991 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
992 msr, data);
993 return 1;
994 } else {
995 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
996 msr, data);
997 break;
998 }
15c4a640
CO		 999 }
1000 return 0;
1001}
1002EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1003
1004
1005/*
1006 * Reads an msr value (of 'msr_index') into 'pdata'.
1007 * Returns 0 on success, non-0 otherwise.
1008 * Assumes vcpu_load() was already called.
1009 */
1010int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1011{
1012 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1013}
1014
9ba075a6
AK		 1015static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1016{
0bed3b56
SY		 1017 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1018
9ba075a6
AK		 1019 if (!msr_mtrr_valid(msr))
1020 return 1;
1021
0bed3b56
SY		 1022 if (msr == MSR_MTRRdefType)
1023 *pdata = vcpu->arch.mtrr_state.def_type +
1024 (vcpu->arch.mtrr_state.enabled << 10);
1025 else if (msr == MSR_MTRRfix64K_00000)
1026 *pdata = p[0];
1027 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1028 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1029 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1030 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1031 else if (msr == MSR_IA32_CR_PAT)
1032 *pdata = vcpu->arch.pat;
1033 else { /* Variable MTRRs */
1034 int idx, is_mtrr_mask;
1035 u64 *pt;
1036
1037 idx = (msr - 0x200) / 2;
1038 is_mtrr_mask = msr - 0x200 - 2 * idx;
1039 if (!is_mtrr_mask)
1040 pt =
1041 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1042 else
1043 pt =
1044 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1045 *pdata = *pt;
1046 }
1047
9ba075a6
AK		 1048 return 0;
1049}
1050
890ca9ae 1051static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1052{
1053 u64 data;
890ca9ae
HY		 1054 u64 mcg_cap = vcpu->arch.mcg_cap;
1055 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1056
1057 switch (msr) {
15c4a640
CO		 1058 case MSR_IA32_P5_MC_ADDR:
1059 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1060 data = 0;
1061 break;
15c4a640 1062 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1063 data = vcpu->arch.mcg_cap;
1064 break;
c7ac679c 1065 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1066 if (!(mcg_cap & MCG_CTL_P))
1067 return 1;
1068 data = vcpu->arch.mcg_ctl;
1069 break;
1070 case MSR_IA32_MCG_STATUS:
1071 data = vcpu->arch.mcg_status;
1072 break;
1073 default:
1074 if (msr >= MSR_IA32_MC0_CTL &&
1075 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1076 u32 offset = msr - MSR_IA32_MC0_CTL;
1077 data = vcpu->arch.mce_banks[offset];
1078 break;
1079 }
1080 return 1;
1081 }
1082 *pdata = data;
1083 return 0;
1084}
1085
1086int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1087{
1088 u64 data;
1089
1090 switch (msr) {
890ca9ae 1091 case MSR_IA32_PLATFORM_ID:
15c4a640 1092 case MSR_IA32_UCODE_REV:
15c4a640 1093 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1094 case MSR_IA32_DEBUGCTLMSR:
1095 case MSR_IA32_LASTBRANCHFROMIP:
1096 case MSR_IA32_LASTBRANCHTOIP:
1097 case MSR_IA32_LASTINTFROMIP:
1098 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1099 case MSR_K8_SYSCFG:
1100 case MSR_K7_HWCR:
61a6bd67 1101 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1102 case MSR_P6_PERFCTR0:
1103 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1104 case MSR_P6_EVNTSEL0:
1105 case MSR_P6_EVNTSEL1:
9e699624 1106 case MSR_K7_EVNTSEL0:
1f3ee616 1107 case MSR_K7_PERFCTR0:
1fdbd48c 1108 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1109 case MSR_AMD64_NB_CFG:
f7c6d140 1110 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1111 data = 0;
1112 break;
9ba075a6
AK		 1113 case MSR_MTRRcap:
1114 data = 0x500 | KVM_NR_VAR_MTRR;
1115 break;
1116 case 0x200 ... 0x2ff:
1117 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1118 case 0xcd: /* fsb frequency */
1119 data = 3;
1120 break;
1121 case MSR_IA32_APICBASE:
1122 data = kvm_get_apic_base(vcpu);
1123 break;
0105d1a5
GN		 1124 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1125 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1126 break;
15c4a640 1127 case MSR_IA32_MISC_ENABLE:
ad312c7c 1128 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1129 break;
847f0ad8
AG		 1130 case MSR_IA32_PERF_STATUS:
1131 /* TSC increment by tick */
1132 data = 1000ULL;
1133 /* CPU multiplier */
1134 data |= (((uint64_t)4ULL) << 40);
1135 break;
15c4a640 1136 case MSR_EFER:
ad312c7c 1137 data = vcpu->arch.shadow_efer;
15c4a640 1138 break;
18068523
GOC		 1139 case MSR_KVM_WALL_CLOCK:
1140 data = vcpu->kvm->arch.wall_clock;
1141 break;
1142 case MSR_KVM_SYSTEM_TIME:
1143 data = vcpu->arch.time;
1144 break;
890ca9ae
HY		 1145 case MSR_IA32_P5_MC_ADDR:
1146 case MSR_IA32_P5_MC_TYPE:
1147 case MSR_IA32_MCG_CAP:
1148 case MSR_IA32_MCG_CTL:
1149 case MSR_IA32_MCG_STATUS:
1150 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1151 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1152 default:
ed85c068
AP		 1153 if (!ignore_msrs) {
1154 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1155 return 1;
1156 } else {
1157 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1158 data = 0;
1159 }
1160 break;
15c4a640
CO		 1161 }
1162 *pdata = data;
1163 return 0;
1164}
1165EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1166
313a3dc7
CO		 1167/*
1168 * Read or write a bunch of msrs. All parameters are kernel addresses.
1169 *
1170 * @return number of msrs set successfully.
1171 */
1172static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1173 struct kvm_msr_entry *entries,
1174 int (*do_msr)(struct kvm_vcpu *vcpu,
1175 unsigned index, u64 *data))
1176{
1177 int i;
1178
1179 vcpu_load(vcpu);
1180
3200f405 1181 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1182 for (i = 0; i < msrs->nmsrs; ++i)
1183 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1184 break;
3200f405 1185 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1186
1187 vcpu_put(vcpu);
1188
1189 return i;
1190}
1191
1192/*
1193 * Read or write a bunch of msrs. Parameters are user addresses.
1194 *
1195 * @return number of msrs set successfully.
1196 */
1197static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1198 int (*do_msr)(struct kvm_vcpu *vcpu,
1199 unsigned index, u64 *data),
1200 int writeback)
1201{
1202 struct kvm_msrs msrs;
1203 struct kvm_msr_entry *entries;
1204 int r, n;
1205 unsigned size;
1206
1207 r = -EFAULT;
1208 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1209 goto out;
1210
1211 r = -E2BIG;
1212 if (msrs.nmsrs >= MAX_IO_MSRS)
1213 goto out;
1214
1215 r = -ENOMEM;
1216 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1217 entries = vmalloc(size);
1218 if (!entries)
1219 goto out;
1220
1221 r = -EFAULT;
1222 if (copy_from_user(entries, user_msrs->entries, size))
1223 goto out_free;
1224
1225 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1226 if (r < 0)
1227 goto out_free;
1228
1229 r = -EFAULT;
1230 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1231 goto out_free;
1232
1233 r = n;
1234
1235out_free:
1236 vfree(entries);
1237out:
1238 return r;
1239}
1240
018d00d2
ZX		 1241int kvm_dev_ioctl_check_extension(long ext)
1242{
1243 int r;
1244
1245 switch (ext) {
1246 case KVM_CAP_IRQCHIP:
1247 case KVM_CAP_HLT:
1248 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1249 case KVM_CAP_SET_TSS_ADDR:
07716717 1250 case KVM_CAP_EXT_CPUID:
c8076604 1251 case KVM_CAP_CLOCKSOURCE:
7837699f 1252 case KVM_CAP_PIT:
a28e4f5a 1253 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1254 case KVM_CAP_MP_STATE:
ed848624 1255 case KVM_CAP_SYNC_MMU:
52d939a0 1256 case KVM_CAP_REINJECT_CONTROL:
4925663a 1257 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1258 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1259 case KVM_CAP_IRQFD:
d34e6b17 1260 case KVM_CAP_IOEVENTFD:
c5ff41ce 1261 case KVM_CAP_PIT2:
e9f42757 1262 case KVM_CAP_PIT_STATE2:
b927a3ce 1263 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1264 case KVM_CAP_XEN_HVM:
018d00d2
ZX		 1265 r = 1;
1266 break;
542472b5
LV		 1267 case KVM_CAP_COALESCED_MMIO:
1268 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1269 break;
774ead3a
AK		 1270 case KVM_CAP_VAPIC:
1271 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1272 break;
f725230a
AK		 1273 case KVM_CAP_NR_VCPUS:
1274 r = KVM_MAX_VCPUS;
1275 break;
a988b910
AK		 1276 case KVM_CAP_NR_MEMSLOTS:
1277 r = KVM_MEMORY_SLOTS;
1278 break;
a68a6a72
MT		 1279 case KVM_CAP_PV_MMU: /* obsolete */
1280 r = 0;
2f333bcb 1281 break;
62c476c7 1282 case KVM_CAP_IOMMU:
19de40a8 1283 r = iommu_found();
62c476c7 1284 break;
890ca9ae
HY		 1285 case KVM_CAP_MCE:
1286 r = KVM_MAX_MCE_BANKS;
1287 break;
018d00d2
ZX		 1288 default:
1289 r = 0;
1290 break;
1291 }
1292 return r;
1293
1294}
1295
043405e1
CO		 1296long kvm_arch_dev_ioctl(struct file *filp,
1297 unsigned int ioctl, unsigned long arg)
1298{
1299 void __user *argp = (void __user *)arg;
1300 long r;
1301
1302 switch (ioctl) {
1303 case KVM_GET_MSR_INDEX_LIST: {
1304 struct kvm_msr_list __user *user_msr_list = argp;
1305 struct kvm_msr_list msr_list;
1306 unsigned n;
1307
1308 r = -EFAULT;
1309 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1310 goto out;
1311 n = msr_list.nmsrs;
1312 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1313 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1314 goto out;
1315 r = -E2BIG;
e125e7b6 1316 if (n < msr_list.nmsrs)
043405e1
CO		 1317 goto out;
1318 r = -EFAULT;
1319 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1320 num_msrs_to_save * sizeof(u32)))
1321 goto out;
e125e7b6 1322 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1323 &emulated_msrs,
1324 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1325 goto out;
1326 r = 0;
1327 break;
1328 }
674eea0f
AK		 1329 case KVM_GET_SUPPORTED_CPUID: {
1330 struct kvm_cpuid2 __user *cpuid_arg = argp;
1331 struct kvm_cpuid2 cpuid;
1332
1333 r = -EFAULT;
1334 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1335 goto out;
1336 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1337 cpuid_arg->entries);
674eea0f
AK		 1338 if (r)
1339 goto out;
1340
1341 r = -EFAULT;
1342 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1343 goto out;
1344 r = 0;
1345 break;
1346 }
890ca9ae
HY		 1347 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1348 u64 mce_cap;
1349
1350 mce_cap = KVM_MCE_CAP_SUPPORTED;
1351 r = -EFAULT;
1352 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1353 goto out;
1354 r = 0;
1355 break;
1356 }
043405e1
CO		 1357 default:
1358 r = -EINVAL;
1359 }
1360out:
1361 return r;
1362}
1363
313a3dc7
CO		 1364void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1365{
1366 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1367 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1368 unsigned long khz = cpufreq_quick_get(cpu);
1369 if (!khz)
1370 khz = tsc_khz;
1371 per_cpu(cpu_tsc_khz, cpu) = khz;
1372 }
c8076604 1373 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1374}
1375
1376void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1377{
1378 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1379 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1380}
1381
07716717 1382static int is_efer_nx(void)
313a3dc7 1383{
e286e86e 1384 unsigned long long efer = 0;
313a3dc7 1385
e286e86e 1386 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1387 return efer & EFER_NX;
1388}
1389
1390static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1391{
1392 int i;
1393 struct kvm_cpuid_entry2 *e, *entry;
1394
313a3dc7 1395 entry = NULL;
ad312c7c
ZX		 1396 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1397 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1398 if (e->function == 0x80000001) {
1399 entry = e;
1400 break;
1401 }
1402 }
07716717 1403 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1404 entry->edx &= ~(1 << 20);
1405 printk(KERN_INFO "kvm: guest NX capability removed\n");
1406 }
1407}
1408
07716717 1409/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1410static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1411 struct kvm_cpuid *cpuid,
1412 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1413{
1414 int r, i;
1415 struct kvm_cpuid_entry *cpuid_entries;
1416
1417 r = -E2BIG;
1418 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1419 goto out;
1420 r = -ENOMEM;
1421 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1422 if (!cpuid_entries)
1423 goto out;
1424 r = -EFAULT;
1425 if (copy_from_user(cpuid_entries, entries,
1426 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1427 goto out_free;
1428 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1429 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1430 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1431 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1432 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1433 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1434 vcpu->arch.cpuid_entries[i].index = 0;
1435 vcpu->arch.cpuid_entries[i].flags = 0;
1436 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1437 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1438 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1439 }
1440 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1441 cpuid_fix_nx_cap(vcpu);
1442 r = 0;
fc61b800 1443 kvm_apic_set_version(vcpu);
07716717
DK		 1444
1445out_free:
1446 vfree(cpuid_entries);
1447out:
1448 return r;
1449}
1450
1451static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1452 struct kvm_cpuid2 *cpuid,
1453 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1454{
1455 int r;
1456
1457 r = -E2BIG;
1458 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1459 goto out;
1460 r = -EFAULT;
ad312c7c 1461 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1462 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1463 goto out;
ad312c7c 1464 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1465 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1466 return 0;
1467
1468out:
1469 return r;
1470}
1471
07716717 1472static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1473 struct kvm_cpuid2 *cpuid,
1474 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1475{
1476 int r;
1477
1478 r = -E2BIG;
ad312c7c 1479 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1480 goto out;
1481 r = -EFAULT;
ad312c7c 1482 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1483 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1484 goto out;
1485 return 0;
1486
1487out:
ad312c7c 1488 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1489 return r;
1490}
1491
07716717 1492static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1493 u32 index)
07716717
DK		 1494{
1495 entry->function = function;
1496 entry->index = index;
1497 cpuid_count(entry->function, entry->index,
19355475 1498 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1499 entry->flags = 0;
1500}
1501
7faa4ee1
AK		 1502#define F(x) bit(X86_FEATURE_##x)
1503
07716717
DK		 1504static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1505 u32 index, int *nent, int maxnent)
1506{
7faa4ee1 1507 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
344f414f 1508 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
07716717 1509#ifdef CONFIG_X86_64
7faa4ee1
AK		 1510 unsigned f_lm = F(LM);
1511#else
1512 unsigned f_lm = 0;
07716717 1513#endif
7faa4ee1
AK		 1514
1515 /* cpuid 1.edx */
1516 const u32 kvm_supported_word0_x86_features =
1517 F(FPU) | F(VME) | F(DE) | F(PSE) |
1518 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1519 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1520 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1521 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1522 0 /* Reserved, DS, ACPI */ | F(MMX) |
1523 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1524 0 /* HTT, TM, Reserved, PBE */;
1525 /* cpuid 0x80000001.edx */
1526 const u32 kvm_supported_word1_x86_features =
1527 F(FPU) | F(VME) | F(DE) | F(PSE) |
1528 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1529 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1530 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1531 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1532 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
344f414f 1533 F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
7faa4ee1
AK		 1534 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1535 /* cpuid 1.ecx */
1536 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1537 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1538 0 /* DS-CPL, VMX, SMX, EST */ |
1539 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1540 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1541 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1542 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1543 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1544 /* cpuid 0x80000001.ecx */
07716717 1545 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1546 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1547 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1548 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1549 0 /* SKINIT */ | 0 /* WDT */;
07716717 1550
19355475 1551 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1552 get_cpu();
1553 do_cpuid_1_ent(entry, function, index);
1554 ++*nent;
1555
1556 switch (function) {
1557 case 0:
1558 entry->eax = min(entry->eax, (u32)0xb);
1559 break;
1560 case 1:
1561 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1562 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1563 /* we support x2apic emulation even if host does not support
1564 * it since we emulate x2apic in software */
1565 entry->ecx |= F(X2APIC);
07716717
DK		 1566 break;
1567 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1568 * may return different values. This forces us to get_cpu() before
1569 * issuing the first command, and also to emulate this annoying behavior
1570 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1571 case 2: {
1572 int t, times = entry->eax & 0xff;
1573
1574 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1575 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1576 for (t = 1; t < times && *nent < maxnent; ++t) {
1577 do_cpuid_1_ent(&entry[t], function, 0);
1578 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1579 ++*nent;
1580 }
1581 break;
1582 }
1583 /* function 4 and 0xb have additional index. */
1584 case 4: {
14af3f3c 1585 int i, cache_type;
07716717
DK		 1586
1587 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1588 /* read more entries until cache_type is zero */
14af3f3c
HH		 1589 for (i = 1; *nent < maxnent; ++i) {
1590 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1591 if (!cache_type)
1592 break;
14af3f3c
HH		 1593 do_cpuid_1_ent(&entry[i], function, i);
1594 entry[i].flags |=
07716717
DK		 1595 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1596 ++*nent;
1597 }
1598 break;
1599 }
1600 case 0xb: {
14af3f3c 1601 int i, level_type;
07716717
DK		 1602
1603 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1604 /* read more entries until level_type is zero */
14af3f3c 1605 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1606 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1607 if (!level_type)
1608 break;
14af3f3c
HH		 1609 do_cpuid_1_ent(&entry[i], function, i);
1610 entry[i].flags |=
07716717
DK		 1611 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1612 ++*nent;
1613 }
1614 break;
1615 }
1616 case 0x80000000:
1617 entry->eax = min(entry->eax, 0x8000001a);
1618 break;
1619 case 0x80000001:
1620 entry->edx &= kvm_supported_word1_x86_features;
1621 entry->ecx &= kvm_supported_word6_x86_features;
1622 break;
1623 }
1624 put_cpu();
1625}
1626
7faa4ee1
AK		 1627#undef F
1628
674eea0f 1629static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1630 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1631{
1632 struct kvm_cpuid_entry2 *cpuid_entries;
1633 int limit, nent = 0, r = -E2BIG;
1634 u32 func;
1635
1636 if (cpuid->nent < 1)
1637 goto out;
6a544355
AK		 1638 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1639 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1640 r = -ENOMEM;
1641 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1642 if (!cpuid_entries)
1643 goto out;
1644
1645 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1646 limit = cpuid_entries[0].eax;
1647 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1648 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1649 &nent, cpuid->nent);
07716717
DK		 1650 r = -E2BIG;
1651 if (nent >= cpuid->nent)
1652 goto out_free;
1653
1654 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1655 limit = cpuid_entries[nent - 1].eax;
1656 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1657 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1658 &nent, cpuid->nent);
cb007648
MM		 1659 r = -E2BIG;
1660 if (nent >= cpuid->nent)
1661 goto out_free;
1662
07716717
DK		 1663 r = -EFAULT;
1664 if (copy_to_user(entries, cpuid_entries,
19355475 1665 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1666 goto out_free;
1667 cpuid->nent = nent;
1668 r = 0;
1669
1670out_free:
1671 vfree(cpuid_entries);
1672out:
1673 return r;
1674}
1675
313a3dc7
CO		 1676static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1677 struct kvm_lapic_state *s)
1678{
1679 vcpu_load(vcpu);
ad312c7c 1680 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1681 vcpu_put(vcpu);
1682
1683 return 0;
1684}
1685
1686static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1687 struct kvm_lapic_state *s)
1688{
1689 vcpu_load(vcpu);
ad312c7c 1690 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1691 kvm_apic_post_state_restore(vcpu);
cb142eb7 1692 update_cr8_intercept(vcpu);
313a3dc7
CO		 1693 vcpu_put(vcpu);
1694
1695 return 0;
1696}
1697
f77bc6a4
ZX		 1698static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1699 struct kvm_interrupt *irq)
1700{
1701 if (irq->irq < 0 || irq->irq >= 256)
1702 return -EINVAL;
1703 if (irqchip_in_kernel(vcpu->kvm))
1704 return -ENXIO;
1705 vcpu_load(vcpu);
1706
66fd3f7f 1707 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1708
1709 vcpu_put(vcpu);
1710
1711 return 0;
1712}
1713
c4abb7c9
JK		 1714static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1715{
1716 vcpu_load(vcpu);
1717 kvm_inject_nmi(vcpu);
1718 vcpu_put(vcpu);
1719
1720 return 0;
1721}
1722
b209749f
AK		 1723static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1724 struct kvm_tpr_access_ctl *tac)
1725{
1726 if (tac->flags)
1727 return -EINVAL;
1728 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1729 return 0;
1730}
1731
890ca9ae
HY		 1732static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1733 u64 mcg_cap)
1734{
1735 int r;
1736 unsigned bank_num = mcg_cap & 0xff, bank;
1737
1738 r = -EINVAL;
a9e38c3e 1739 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 1740 goto out;
1741 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1742 goto out;
1743 r = 0;
1744 vcpu->arch.mcg_cap = mcg_cap;
1745 /* Init IA32_MCG_CTL to all 1s */
1746 if (mcg_cap & MCG_CTL_P)
1747 vcpu->arch.mcg_ctl = ~(u64)0;
1748 /* Init IA32_MCi_CTL to all 1s */
1749 for (bank = 0; bank < bank_num; bank++)
1750 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1751out:
1752 return r;
1753}
1754
1755static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1756 struct kvm_x86_mce *mce)
1757{
1758 u64 mcg_cap = vcpu->arch.mcg_cap;
1759 unsigned bank_num = mcg_cap & 0xff;
1760 u64 *banks = vcpu->arch.mce_banks;
1761
1762 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1763 return -EINVAL;
1764 /*
1765 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1766 * reporting is disabled
1767 */
1768 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1769 vcpu->arch.mcg_ctl != ~(u64)0)
1770 return 0;
1771 banks += 4 * mce->bank;
1772 /*
1773 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1774 * reporting is disabled for the bank
1775 */
1776 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1777 return 0;
1778 if (mce->status & MCI_STATUS_UC) {
1779 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1780 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1781 printk(KERN_DEBUG "kvm: set_mce: "
1782 "injects mce exception while "
1783 "previous one is in progress!\n");
1784 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1785 return 0;
1786 }
1787 if (banks[1] & MCI_STATUS_VAL)
1788 mce->status |= MCI_STATUS_OVER;
1789 banks[2] = mce->addr;
1790 banks[3] = mce->misc;
1791 vcpu->arch.mcg_status = mce->mcg_status;
1792 banks[1] = mce->status;
1793 kvm_queue_exception(vcpu, MC_VECTOR);
1794 } else if (!(banks[1] & MCI_STATUS_VAL)
1795 || !(banks[1] & MCI_STATUS_UC)) {
1796 if (banks[1] & MCI_STATUS_VAL)
1797 mce->status |= MCI_STATUS_OVER;
1798 banks[2] = mce->addr;
1799 banks[3] = mce->misc;
1800 banks[1] = mce->status;
1801 } else
1802 banks[1] |= MCI_STATUS_OVER;
1803 return 0;
1804}
1805
313a3dc7
CO		 1806long kvm_arch_vcpu_ioctl(struct file *filp,
1807 unsigned int ioctl, unsigned long arg)
1808{
1809 struct kvm_vcpu *vcpu = filp->private_data;
1810 void __user *argp = (void __user *)arg;
1811 int r;
b772ff36 1812 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1813
1814 switch (ioctl) {
1815 case KVM_GET_LAPIC: {
b772ff36 1816 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1817
b772ff36
DH		 1818 r = -ENOMEM;
1819 if (!lapic)
1820 goto out;
1821 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1822 if (r)
1823 goto out;
1824 r = -EFAULT;
b772ff36 1825 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1826 goto out;
1827 r = 0;
1828 break;
1829 }
1830 case KVM_SET_LAPIC: {
b772ff36
DH		 1831 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1832 r = -ENOMEM;
1833 if (!lapic)
1834 goto out;
313a3dc7 1835 r = -EFAULT;
b772ff36 1836 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1837 goto out;
b772ff36 1838 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1839 if (r)
1840 goto out;
1841 r = 0;
1842 break;
1843 }
f77bc6a4
ZX		 1844 case KVM_INTERRUPT: {
1845 struct kvm_interrupt irq;
1846
1847 r = -EFAULT;
1848 if (copy_from_user(&irq, argp, sizeof irq))
1849 goto out;
1850 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1851 if (r)
1852 goto out;
1853 r = 0;
1854 break;
1855 }
c4abb7c9
JK		 1856 case KVM_NMI: {
1857 r = kvm_vcpu_ioctl_nmi(vcpu);
1858 if (r)
1859 goto out;
1860 r = 0;
1861 break;
1862 }
313a3dc7
CO		 1863 case KVM_SET_CPUID: {
1864 struct kvm_cpuid __user *cpuid_arg = argp;
1865 struct kvm_cpuid cpuid;
1866
1867 r = -EFAULT;
1868 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1869 goto out;
1870 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1871 if (r)
1872 goto out;
1873 break;
1874 }
07716717
DK		 1875 case KVM_SET_CPUID2: {
1876 struct kvm_cpuid2 __user *cpuid_arg = argp;
1877 struct kvm_cpuid2 cpuid;
1878
1879 r = -EFAULT;
1880 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1881 goto out;
1882 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1883 cpuid_arg->entries);
07716717
DK		 1884 if (r)
1885 goto out;
1886 break;
1887 }
1888 case KVM_GET_CPUID2: {
1889 struct kvm_cpuid2 __user *cpuid_arg = argp;
1890 struct kvm_cpuid2 cpuid;
1891
1892 r = -EFAULT;
1893 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1894 goto out;
1895 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1896 cpuid_arg->entries);
07716717
DK		 1897 if (r)
1898 goto out;
1899 r = -EFAULT;
1900 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1901 goto out;
1902 r = 0;
1903 break;
1904 }
313a3dc7
CO		 1905 case KVM_GET_MSRS:
1906 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1907 break;
1908 case KVM_SET_MSRS:
1909 r = msr_io(vcpu, argp, do_set_msr, 0);
1910 break;
b209749f
AK		 1911 case KVM_TPR_ACCESS_REPORTING: {
1912 struct kvm_tpr_access_ctl tac;
1913
1914 r = -EFAULT;
1915 if (copy_from_user(&tac, argp, sizeof tac))
1916 goto out;
1917 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1918 if (r)
1919 goto out;
1920 r = -EFAULT;
1921 if (copy_to_user(argp, &tac, sizeof tac))
1922 goto out;
1923 r = 0;
1924 break;
1925 };
b93463aa
AK		 1926 case KVM_SET_VAPIC_ADDR: {
1927 struct kvm_vapic_addr va;
1928
1929 r = -EINVAL;
1930 if (!irqchip_in_kernel(vcpu->kvm))
1931 goto out;
1932 r = -EFAULT;
1933 if (copy_from_user(&va, argp, sizeof va))
1934 goto out;
1935 r = 0;
1936 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1937 break;
1938 }
890ca9ae
HY		 1939 case KVM_X86_SETUP_MCE: {
1940 u64 mcg_cap;
1941
1942 r = -EFAULT;
1943 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1944 goto out;
1945 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1946 break;
1947 }
1948 case KVM_X86_SET_MCE: {
1949 struct kvm_x86_mce mce;
1950
1951 r = -EFAULT;
1952 if (copy_from_user(&mce, argp, sizeof mce))
1953 goto out;
1954 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1955 break;
1956 }
313a3dc7
CO		 1957 default:
1958 r = -EINVAL;
1959 }
1960out:
7a6ce84c 1961 kfree(lapic);
313a3dc7
CO		 1962 return r;
1963}
1964
1fe779f8
CO		 1965static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1966{
1967 int ret;
1968
1969 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1970 return -1;
1971 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1972 return ret;
1973}
1974
b927a3ce
SY		 1975static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
1976 u64 ident_addr)
1977{
1978 kvm->arch.ept_identity_map_addr = ident_addr;
1979 return 0;
1980}
1981
1fe779f8
CO		 1982static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1983 u32 kvm_nr_mmu_pages)
1984{
1985 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1986 return -EINVAL;
1987
72dc67a6 1988 down_write(&kvm->slots_lock);
7c8a83b7 1989 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1990
1991 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1992 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1993
7c8a83b7 1994 spin_unlock(&kvm->mmu_lock);
72dc67a6 1995 up_write(&kvm->slots_lock);
1fe779f8
CO		 1996 return 0;
1997}
1998
1999static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2000{
f05e70ac 2001 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2002}
2003
e9f85cde
ZX		 2004gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2005{
2006 int i;
2007 struct kvm_mem_alias *alias;
2008
d69fb81f
ZX		 2009 for (i = 0; i < kvm->arch.naliases; ++i) {
2010 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 2011 if (gfn >= alias->base_gfn
2012 && gfn < alias->base_gfn + alias->npages)
2013 return alias->target_gfn + gfn - alias->base_gfn;
2014 }
2015 return gfn;
2016}
2017
1fe779f8
CO		 2018/*
2019 * Set a new alias region. Aliases map a portion of physical memory into
2020 * another portion. This is useful for memory windows, for example the PC
2021 * VGA region.
2022 */
2023static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2024 struct kvm_memory_alias *alias)
2025{
2026 int r, n;
2027 struct kvm_mem_alias *p;
2028
2029 r = -EINVAL;
2030 /* General sanity checks */
2031 if (alias->memory_size & (PAGE_SIZE - 1))
2032 goto out;
2033 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2034 goto out;
2035 if (alias->slot >= KVM_ALIAS_SLOTS)
2036 goto out;
2037 if (alias->guest_phys_addr + alias->memory_size
2038 < alias->guest_phys_addr)
2039 goto out;
2040 if (alias->target_phys_addr + alias->memory_size
2041 < alias->target_phys_addr)
2042 goto out;
2043
72dc67a6 2044 down_write(&kvm->slots_lock);
a1708ce8 2045 spin_lock(&kvm->mmu_lock);
1fe779f8 2046
d69fb81f 2047 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 2048 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2049 p->npages = alias->memory_size >> PAGE_SHIFT;
2050 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
2051
2052 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 2053 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 2054 break;
d69fb81f 2055 kvm->arch.naliases = n;
1fe779f8 2056
a1708ce8 2057 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 2058 kvm_mmu_zap_all(kvm);
2059
72dc67a6 2060 up_write(&kvm->slots_lock);
1fe779f8
CO		 2061
2062 return 0;
2063
2064out:
2065 return r;
2066}
2067
2068static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2069{
2070 int r;
2071
2072 r = 0;
2073 switch (chip->chip_id) {
2074 case KVM_IRQCHIP_PIC_MASTER:
2075 memcpy(&chip->chip.pic,
2076 &pic_irqchip(kvm)->pics[0],
2077 sizeof(struct kvm_pic_state));
2078 break;
2079 case KVM_IRQCHIP_PIC_SLAVE:
2080 memcpy(&chip->chip.pic,
2081 &pic_irqchip(kvm)->pics[1],
2082 sizeof(struct kvm_pic_state));
2083 break;
2084 case KVM_IRQCHIP_IOAPIC:
eba0226b 2085 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2086 break;
2087 default:
2088 r = -EINVAL;
2089 break;
2090 }
2091 return r;
2092}
2093
2094static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2095{
2096 int r;
2097
2098 r = 0;
2099 switch (chip->chip_id) {
2100 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2101 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2102 memcpy(&pic_irqchip(kvm)->pics[0],
2103 &chip->chip.pic,
2104 sizeof(struct kvm_pic_state));
894a9c55 2105 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2106 break;
2107 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2108 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2109 memcpy(&pic_irqchip(kvm)->pics[1],
2110 &chip->chip.pic,
2111 sizeof(struct kvm_pic_state));
894a9c55 2112 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2113 break;
2114 case KVM_IRQCHIP_IOAPIC:
eba0226b 2115 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2116 break;
2117 default:
2118 r = -EINVAL;
2119 break;
2120 }
2121 kvm_pic_update_irq(pic_irqchip(kvm));
2122 return r;
2123}
2124
e0f63cb9
SY		 2125static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2126{
2127 int r = 0;
2128
894a9c55 2129 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2130 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2131 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2132 return r;
2133}
2134
2135static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2136{
2137 int r = 0;
2138
894a9c55 2139 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2140 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2141 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2142 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2143 return r;
2144}
2145
2146static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2147{
2148 int r = 0;
2149
2150 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2151 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2152 sizeof(ps->channels));
2153 ps->flags = kvm->arch.vpit->pit_state.flags;
2154 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2155 return r;
2156}
2157
2158static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2159{
2160 int r = 0, start = 0;
2161 u32 prev_legacy, cur_legacy;
2162 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2163 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2164 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2165 if (!prev_legacy && cur_legacy)
2166 start = 1;
2167 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2168 sizeof(kvm->arch.vpit->pit_state.channels));
2169 kvm->arch.vpit->pit_state.flags = ps->flags;
2170 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2171 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2172 return r;
2173}
2174
52d939a0
MT		 2175static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2176 struct kvm_reinject_control *control)
2177{
2178 if (!kvm->arch.vpit)
2179 return -ENXIO;
894a9c55 2180 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2181 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2182 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2183 return 0;
2184}
2185
5bb064dc
ZX		 2186/*
2187 * Get (and clear) the dirty memory log for a memory slot.
2188 */
2189int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2190 struct kvm_dirty_log *log)
2191{
2192 int r;
2193 int n;
2194 struct kvm_memory_slot *memslot;
2195 int is_dirty = 0;
2196
72dc67a6 2197 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2198
2199 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2200 if (r)
2201 goto out;
2202
2203 /* If nothing is dirty, don't bother messing with page tables. */
2204 if (is_dirty) {
7c8a83b7 2205 spin_lock(&kvm->mmu_lock);
5bb064dc 2206 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2207 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2208 memslot = &kvm->memslots[log->slot];
2209 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2210 memset(memslot->dirty_bitmap, 0, n);
2211 }
2212 r = 0;
2213out:
72dc67a6 2214 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2215 return r;
2216}
2217
1fe779f8
CO		 2218long kvm_arch_vm_ioctl(struct file *filp,
2219 unsigned int ioctl, unsigned long arg)
2220{
2221 struct kvm *kvm = filp->private_data;
2222 void __user *argp = (void __user *)arg;
367e1319 2223 int r = -ENOTTY;
f0d66275
DH		 2224 /*
2225 * This union makes it completely explicit to gcc-3.x
2226 * that these two variables' stack usage should be
2227 * combined, not added together.
2228 */
2229 union {
2230 struct kvm_pit_state ps;
e9f42757 2231 struct kvm_pit_state2 ps2;
f0d66275 2232 struct kvm_memory_alias alias;
c5ff41ce 2233 struct kvm_pit_config pit_config;
f0d66275 2234 } u;
1fe779f8
CO		 2235
2236 switch (ioctl) {
2237 case KVM_SET_TSS_ADDR:
2238 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2239 if (r < 0)
2240 goto out;
2241 break;
b927a3ce
SY		 2242 case KVM_SET_IDENTITY_MAP_ADDR: {
2243 u64 ident_addr;
2244
2245 r = -EFAULT;
2246 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2247 goto out;
2248 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2249 if (r < 0)
2250 goto out;
2251 break;
2252 }
1fe779f8
CO		 2253 case KVM_SET_MEMORY_REGION: {
2254 struct kvm_memory_region kvm_mem;
2255 struct kvm_userspace_memory_region kvm_userspace_mem;
2256
2257 r = -EFAULT;
2258 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2259 goto out;
2260 kvm_userspace_mem.slot = kvm_mem.slot;
2261 kvm_userspace_mem.flags = kvm_mem.flags;
2262 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2263 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2264 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2265 if (r)
2266 goto out;
2267 break;
2268 }
2269 case KVM_SET_NR_MMU_PAGES:
2270 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2271 if (r)
2272 goto out;
2273 break;
2274 case KVM_GET_NR_MMU_PAGES:
2275 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2276 break;
f0d66275 2277 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2278 r = -EFAULT;
f0d66275 2279 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2280 goto out;
f0d66275 2281 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2282 if (r)
2283 goto out;
2284 break;
1fe779f8
CO		 2285 case KVM_CREATE_IRQCHIP:
2286 r = -ENOMEM;
d7deeeb0
ZX		 2287 kvm->arch.vpic = kvm_create_pic(kvm);
2288 if (kvm->arch.vpic) {
1fe779f8
CO		 2289 r = kvm_ioapic_init(kvm);
2290 if (r) {
d7deeeb0
ZX		 2291 kfree(kvm->arch.vpic);
2292 kvm->arch.vpic = NULL;
1fe779f8
CO		 2293 goto out;
2294 }
2295 } else
2296 goto out;
399ec807
AK		 2297 r = kvm_setup_default_irq_routing(kvm);
2298 if (r) {
2299 kfree(kvm->arch.vpic);
2300 kfree(kvm->arch.vioapic);
2301 goto out;
2302 }
1fe779f8 2303 break;
7837699f 2304 case KVM_CREATE_PIT:
c5ff41ce
JK		 2305 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2306 goto create_pit;
2307 case KVM_CREATE_PIT2:
2308 r = -EFAULT;
2309 if (copy_from_user(&u.pit_config, argp,
2310 sizeof(struct kvm_pit_config)))
2311 goto out;
2312 create_pit:
108b5669 2313 down_write(&kvm->slots_lock);
269e05e4
AK		 2314 r = -EEXIST;
2315 if (kvm->arch.vpit)
2316 goto create_pit_unlock;
7837699f 2317 r = -ENOMEM;
c5ff41ce 2318 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2319 if (kvm->arch.vpit)
2320 r = 0;
269e05e4 2321 create_pit_unlock:
108b5669 2322 up_write(&kvm->slots_lock);
7837699f 2323 break;
4925663a 2324 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2325 case KVM_IRQ_LINE: {
2326 struct kvm_irq_level irq_event;
2327
2328 r = -EFAULT;
2329 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2330 goto out;
2331 if (irqchip_in_kernel(kvm)) {
4925663a 2332 __s32 status;
4925663a
GN		 2333 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2334 irq_event.irq, irq_event.level);
4925663a
GN		 2335 if (ioctl == KVM_IRQ_LINE_STATUS) {
2336 irq_event.status = status;
2337 if (copy_to_user(argp, &irq_event,
2338 sizeof irq_event))
2339 goto out;
2340 }
1fe779f8
CO		 2341 r = 0;
2342 }
2343 break;
2344 }
2345 case KVM_GET_IRQCHIP: {
2346 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2347 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2348
f0d66275
DH		 2349 r = -ENOMEM;
2350 if (!chip)
1fe779f8 2351 goto out;
f0d66275
DH		 2352 r = -EFAULT;
2353 if (copy_from_user(chip, argp, sizeof *chip))
2354 goto get_irqchip_out;
1fe779f8
CO		 2355 r = -ENXIO;
2356 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2357 goto get_irqchip_out;
2358 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2359 if (r)
f0d66275 2360 goto get_irqchip_out;
1fe779f8 2361 r = -EFAULT;
f0d66275
DH		 2362 if (copy_to_user(argp, chip, sizeof *chip))
2363 goto get_irqchip_out;
1fe779f8 2364 r = 0;
f0d66275
DH		 2365 get_irqchip_out:
2366 kfree(chip);
2367 if (r)
2368 goto out;
1fe779f8
CO		 2369 break;
2370 }
2371 case KVM_SET_IRQCHIP: {
2372 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2373 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2374
f0d66275
DH		 2375 r = -ENOMEM;
2376 if (!chip)
1fe779f8 2377 goto out;
f0d66275
DH		 2378 r = -EFAULT;
2379 if (copy_from_user(chip, argp, sizeof *chip))
2380 goto set_irqchip_out;
1fe779f8
CO		 2381 r = -ENXIO;
2382 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2383 goto set_irqchip_out;
2384 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2385 if (r)
f0d66275 2386 goto set_irqchip_out;
1fe779f8 2387 r = 0;
f0d66275
DH		 2388 set_irqchip_out:
2389 kfree(chip);
2390 if (r)
2391 goto out;
1fe779f8
CO		 2392 break;
2393 }
e0f63cb9 2394 case KVM_GET_PIT: {
e0f63cb9 2395 r = -EFAULT;
f0d66275 2396 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2397 goto out;
2398 r = -ENXIO;
2399 if (!kvm->arch.vpit)
2400 goto out;
f0d66275 2401 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2402 if (r)
2403 goto out;
2404 r = -EFAULT;
f0d66275 2405 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2406 goto out;
2407 r = 0;
2408 break;
2409 }
2410 case KVM_SET_PIT: {
e0f63cb9 2411 r = -EFAULT;
f0d66275 2412 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2413 goto out;
2414 r = -ENXIO;
2415 if (!kvm->arch.vpit)
2416 goto out;
f0d66275 2417 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2418 if (r)
2419 goto out;
2420 r = 0;
2421 break;
2422 }
e9f42757
BK		 2423 case KVM_GET_PIT2: {
2424 r = -ENXIO;
2425 if (!kvm->arch.vpit)
2426 goto out;
2427 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2428 if (r)
2429 goto out;
2430 r = -EFAULT;
2431 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2432 goto out;
2433 r = 0;
2434 break;
2435 }
2436 case KVM_SET_PIT2: {
2437 r = -EFAULT;
2438 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2439 goto out;
2440 r = -ENXIO;
2441 if (!kvm->arch.vpit)
2442 goto out;
2443 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2444 if (r)
2445 goto out;
2446 r = 0;
2447 break;
2448 }
52d939a0
MT		 2449 case KVM_REINJECT_CONTROL: {
2450 struct kvm_reinject_control control;
2451 r = -EFAULT;
2452 if (copy_from_user(&control, argp, sizeof(control)))
2453 goto out;
2454 r = kvm_vm_ioctl_reinject(kvm, &control);
2455 if (r)
2456 goto out;
2457 r = 0;
2458 break;
2459 }
ffde22ac
ES		 2460 case KVM_XEN_HVM_CONFIG: {
2461 r = -EFAULT;
2462 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2463 sizeof(struct kvm_xen_hvm_config)))
2464 goto out;
2465 r = -EINVAL;
2466 if (kvm->arch.xen_hvm_config.flags)
2467 goto out;
2468 r = 0;
2469 break;
2470 }
1fe779f8
CO		 2471 default:
2472 ;
2473 }
2474out:
2475 return r;
2476}
2477
a16b043c 2478static void kvm_init_msr_list(void)
043405e1
CO		 2479{
2480 u32 dummy[2];
2481 unsigned i, j;
2482
e3267cbb
GC		 2483 /* skip the first msrs in the list. KVM-specific */
2484 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2485 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2486 continue;
2487 if (j < i)
2488 msrs_to_save[j] = msrs_to_save[i];
2489 j++;
2490 }
2491 num_msrs_to_save = j;
2492}
2493
bda9020e
MT		 2494static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2495 const void *v)
bbd9b64e 2496{
bda9020e
MT		 2497 if (vcpu->arch.apic &&
2498 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2499 return 0;
bbd9b64e 2500
bda9020e 2501 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2502}
2503
bda9020e 2504static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2505{
bda9020e
MT		 2506 if (vcpu->arch.apic &&
2507 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2508 return 0;
bbd9b64e 2509
bda9020e 2510 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2511}
2512
cded19f3
HE		 2513static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2514 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2515{
2516 void *data = val;
10589a46 2517 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2518
2519 while (bytes) {
ad312c7c 2520 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2521 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2522 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2523 int ret;
2524
10589a46
MT		 2525 if (gpa == UNMAPPED_GVA) {
2526 r = X86EMUL_PROPAGATE_FAULT;
2527 goto out;
2528 }
77c2002e 2529 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2530 if (ret < 0) {
2531 r = X86EMUL_UNHANDLEABLE;
2532 goto out;
2533 }
bbd9b64e 2534
77c2002e
IE		 2535 bytes -= toread;
2536 data += toread;
2537 addr += toread;
bbd9b64e 2538 }
10589a46 2539out:
10589a46 2540 return r;
bbd9b64e 2541}
77c2002e 2542
cded19f3
HE		 2543static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2544 struct kvm_vcpu *vcpu)
77c2002e
IE		 2545{
2546 void *data = val;
2547 int r = X86EMUL_CONTINUE;
2548
2549 while (bytes) {
2550 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2551 unsigned offset = addr & (PAGE_SIZE-1);
2552 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2553 int ret;
2554
2555 if (gpa == UNMAPPED_GVA) {
2556 r = X86EMUL_PROPAGATE_FAULT;
2557 goto out;
2558 }
2559 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2560 if (ret < 0) {
2561 r = X86EMUL_UNHANDLEABLE;
2562 goto out;
2563 }
2564
2565 bytes -= towrite;
2566 data += towrite;
2567 addr += towrite;
2568 }
2569out:
2570 return r;
2571}
2572
bbd9b64e 2573
bbd9b64e
CO		 2574static int emulator_read_emulated(unsigned long addr,
2575 void *val,
2576 unsigned int bytes,
2577 struct kvm_vcpu *vcpu)
2578{
bbd9b64e
CO		 2579 gpa_t gpa;
2580
2581 if (vcpu->mmio_read_completed) {
2582 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2583 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2584 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2585 vcpu->mmio_read_completed = 0;
2586 return X86EMUL_CONTINUE;
2587 }
2588
ad312c7c 2589 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2590
2591 /* For APIC access vmexit */
2592 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2593 goto mmio;
2594
77c2002e
IE		 2595 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2596 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2597 return X86EMUL_CONTINUE;
2598 if (gpa == UNMAPPED_GVA)
2599 return X86EMUL_PROPAGATE_FAULT;
2600
2601mmio:
2602 /*
2603 * Is this MMIO handled locally?
2604 */
aec51dc4
AK		 2605 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2606 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2607 return X86EMUL_CONTINUE;
2608 }
aec51dc4
AK		 2609
2610 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2611
2612 vcpu->mmio_needed = 1;
2613 vcpu->mmio_phys_addr = gpa;
2614 vcpu->mmio_size = bytes;
2615 vcpu->mmio_is_write = 0;
2616
2617 return X86EMUL_UNHANDLEABLE;
2618}
2619
3200f405 2620int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2621 const void *val, int bytes)
bbd9b64e
CO		 2622{
2623 int ret;
2624
2625 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2626 if (ret < 0)
bbd9b64e 2627 return 0;
ad218f85 2628 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2629 return 1;
2630}
2631
2632static int emulator_write_emulated_onepage(unsigned long addr,
2633 const void *val,
2634 unsigned int bytes,
2635 struct kvm_vcpu *vcpu)
2636{
10589a46
MT		 2637 gpa_t gpa;
2638
10589a46 2639 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2640
2641 if (gpa == UNMAPPED_GVA) {
c3c91fee 2642 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2643 return X86EMUL_PROPAGATE_FAULT;
2644 }
2645
2646 /* For APIC access vmexit */
2647 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2648 goto mmio;
2649
2650 if (emulator_write_phys(vcpu, gpa, val, bytes))
2651 return X86EMUL_CONTINUE;
2652
2653mmio:
aec51dc4 2654 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2655 /*
2656 * Is this MMIO handled locally?
2657 */
bda9020e 2658 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2659 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2660
2661 vcpu->mmio_needed = 1;
2662 vcpu->mmio_phys_addr = gpa;
2663 vcpu->mmio_size = bytes;
2664 vcpu->mmio_is_write = 1;
2665 memcpy(vcpu->mmio_data, val, bytes);
2666
2667 return X86EMUL_CONTINUE;
2668}
2669
2670int emulator_write_emulated(unsigned long addr,
2671 const void *val,
2672 unsigned int bytes,
2673 struct kvm_vcpu *vcpu)
2674{
2675 /* Crossing a page boundary? */
2676 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2677 int rc, now;
2678
2679 now = -addr & ~PAGE_MASK;
2680 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2681 if (rc != X86EMUL_CONTINUE)
2682 return rc;
2683 addr += now;
2684 val += now;
2685 bytes -= now;
2686 }
2687 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2688}
2689EXPORT_SYMBOL_GPL(emulator_write_emulated);
2690
2691static int emulator_cmpxchg_emulated(unsigned long addr,
2692 const void *old,
2693 const void *new,
2694 unsigned int bytes,
2695 struct kvm_vcpu *vcpu)
2696{
9f51e24e 2697 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 2698#ifndef CONFIG_X86_64
2699 /* guests cmpxchg8b have to be emulated atomically */
2700 if (bytes == 8) {
10589a46 2701 gpa_t gpa;
2bacc55c 2702 struct page *page;
c0b49b0d 2703 char *kaddr;
2bacc55c
MT		 2704 u64 val;
2705
10589a46
MT		 2706 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2707
2bacc55c
MT		 2708 if (gpa == UNMAPPED_GVA ||
2709 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2710 goto emul_write;
2711
2712 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2713 goto emul_write;
2714
2715 val = *(u64 *)new;
72dc67a6 2716
2bacc55c 2717 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2718
c0b49b0d
AM		 2719 kaddr = kmap_atomic(page, KM_USER0);
2720 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2721 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2722 kvm_release_page_dirty(page);
2723 }
3200f405 2724emul_write:
2bacc55c
MT		 2725#endif
2726
bbd9b64e
CO		 2727 return emulator_write_emulated(addr, new, bytes, vcpu);
2728}
2729
2730static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2731{
2732 return kvm_x86_ops->get_segment_base(vcpu, seg);
2733}
2734
2735int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2736{
a7052897 2737 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2738 return X86EMUL_CONTINUE;
2739}
2740
2741int emulate_clts(struct kvm_vcpu *vcpu)
2742{
ad312c7c 2743 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2744 return X86EMUL_CONTINUE;
2745}
2746
2747int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2748{
2749 struct kvm_vcpu *vcpu = ctxt->vcpu;
2750
2751 switch (dr) {
2752 case 0 ... 3:
2753 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2754 return X86EMUL_CONTINUE;
2755 default:
b8688d51 2756 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2757 return X86EMUL_UNHANDLEABLE;
2758 }
2759}
2760
2761int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2762{
2763 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2764 int exception;
2765
2766 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2767 if (exception) {
2768 /* FIXME: better handling */
2769 return X86EMUL_UNHANDLEABLE;
2770 }
2771 return X86EMUL_CONTINUE;
2772}
2773
2774void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2775{
bbd9b64e 2776 u8 opcodes[4];
5fdbf976 2777 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2778 unsigned long rip_linear;
2779
f76c710d 2780 if (!printk_ratelimit())
bbd9b64e
CO		 2781 return;
2782
25be4608
GC		 2783 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2784
77c2002e 2785 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2786
2787 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2788 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2789}
2790EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2791
14af3f3c 2792static struct x86_emulate_ops emulate_ops = {
77c2002e 2793 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2794 .read_emulated = emulator_read_emulated,
2795 .write_emulated = emulator_write_emulated,
2796 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2797};
2798
5fdbf976
MT		 2799static void cache_all_regs(struct kvm_vcpu *vcpu)
2800{
2801 kvm_register_read(vcpu, VCPU_REGS_RAX);
2802 kvm_register_read(vcpu, VCPU_REGS_RSP);
2803 kvm_register_read(vcpu, VCPU_REGS_RIP);
2804 vcpu->arch.regs_dirty = ~0;
2805}
2806
bbd9b64e 2807int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 2808 unsigned long cr2,
2809 u16 error_code,
571008da 2810 int emulation_type)
bbd9b64e 2811{
310b5d30 2812 int r, shadow_mask;
571008da 2813 struct decode_cache *c;
851ba692 2814 struct kvm_run *run = vcpu->run;
bbd9b64e 2815
26eef70c 2816 kvm_clear_exception_queue(vcpu);
ad312c7c 2817 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 2818 /*
56e82318 2819 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 2820 * instead of direct ->regs accesses, can save hundred cycles
2821 * on Intel for instructions that don't read/change RSP, for
2822 * for example.
2823 */
2824 cache_all_regs(vcpu);
bbd9b64e
CO		 2825
2826 vcpu->mmio_is_write = 0;
ad312c7c 2827 vcpu->arch.pio.string = 0;
bbd9b64e 2828
571008da 2829 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2830 int cs_db, cs_l;
2831 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2832
ad312c7c 2833 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 2834 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c
ZX		 2835 vcpu->arch.emulate_ctxt.mode =
2836 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2837 ? X86EMUL_MODE_REAL : cs_l
2838 ? X86EMUL_MODE_PROT64 : cs_db
2839 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2840
ad312c7c 2841 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2842
0cb5762e
AP		 2843 /* Only allow emulation of specific instructions on #UD
2844 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2845 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2846 if (emulation_type & EMULTYPE_TRAP_UD) {
2847 if (!c->twobyte)
2848 return EMULATE_FAIL;
2849 switch (c->b) {
2850 case 0x01: /* VMMCALL */
2851 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2852 return EMULATE_FAIL;
2853 break;
2854 case 0x34: /* sysenter */
2855 case 0x35: /* sysexit */
2856 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2857 return EMULATE_FAIL;
2858 break;
2859 case 0x05: /* syscall */
2860 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2861 return EMULATE_FAIL;
2862 break;
2863 default:
2864 return EMULATE_FAIL;
2865 }
2866
2867 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2868 return EMULATE_FAIL;
2869 }
571008da 2870
f2b5756b 2871 ++vcpu->stat.insn_emulation;
bbd9b64e 2872 if (r) {
f2b5756b 2873 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2874 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2875 return EMULATE_DONE;
2876 return EMULATE_FAIL;
2877 }
2878 }
2879
ba8afb6b
GN		 2880 if (emulation_type & EMULTYPE_SKIP) {
2881 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2882 return EMULATE_DONE;
2883 }
2884
ad312c7c 2885 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2886 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2887
2888 if (r == 0)
2889 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2890
ad312c7c 2891 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2892 return EMULATE_DO_MMIO;
2893
2894 if ((r || vcpu->mmio_is_write) && run) {
2895 run->exit_reason = KVM_EXIT_MMIO;
2896 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2897 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2898 run->mmio.len = vcpu->mmio_size;
2899 run->mmio.is_write = vcpu->mmio_is_write;
2900 }
2901
2902 if (r) {
2903 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2904 return EMULATE_DONE;
2905 if (!vcpu->mmio_needed) {
2906 kvm_report_emulation_failure(vcpu, "mmio");
2907 return EMULATE_FAIL;
2908 }
2909 return EMULATE_DO_MMIO;
2910 }
2911
91586a3b 2912 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2913
2914 if (vcpu->mmio_is_write) {
2915 vcpu->mmio_needed = 0;
2916 return EMULATE_DO_MMIO;
2917 }
2918
2919 return EMULATE_DONE;
2920}
2921EXPORT_SYMBOL_GPL(emulate_instruction);
2922
de7d789a
CO		 2923static int pio_copy_data(struct kvm_vcpu *vcpu)
2924{
ad312c7c 2925 void *p = vcpu->arch.pio_data;
0f346074 2926 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2927 unsigned bytes;
0f346074 2928 int ret;
de7d789a 2929
ad312c7c
ZX		 2930 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2931 if (vcpu->arch.pio.in)
0f346074 2932 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2933 else
0f346074
IE		 2934 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2935 return ret;
de7d789a
CO		 2936}
2937
2938int complete_pio(struct kvm_vcpu *vcpu)
2939{
ad312c7c 2940 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2941 long delta;
2942 int r;
5fdbf976 2943 unsigned long val;
de7d789a
CO		 2944
2945 if (!io->string) {
5fdbf976
MT		 2946 if (io->in) {
2947 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2948 memcpy(&val, vcpu->arch.pio_data, io->size);
2949 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2950 }
de7d789a
CO		 2951 } else {
2952 if (io->in) {
2953 r = pio_copy_data(vcpu);
5fdbf976 2954 if (r)
de7d789a 2955 return r;
de7d789a
CO		 2956 }
2957
2958 delta = 1;
2959 if (io->rep) {
2960 delta *= io->cur_count;
2961 /*
2962 * The size of the register should really depend on
2963 * current address size.
2964 */
5fdbf976
MT		 2965 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2966 val -= delta;
2967 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2968 }
2969 if (io->down)
2970 delta = -delta;
2971 delta *= io->size;
5fdbf976
MT		 2972 if (io->in) {
2973 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2974 val += delta;
2975 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2976 } else {
2977 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2978 val += delta;
2979 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2980 }
de7d789a
CO		 2981 }
2982
de7d789a
CO		 2983 io->count -= io->cur_count;
2984 io->cur_count = 0;
2985
2986 return 0;
2987}
2988
bda9020e 2989static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2990{
2991 /* TODO: String I/O for in kernel device */
bda9020e 2992 int r;
de7d789a 2993
ad312c7c 2994 if (vcpu->arch.pio.in)
bda9020e
MT		 2995 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2996 vcpu->arch.pio.size, pd);
de7d789a 2997 else
bda9020e
MT		 2998 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2999 vcpu->arch.pio.size, pd);
3000 return r;
de7d789a
CO		 3001}
3002
bda9020e 3003static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3004{
ad312c7c
ZX		 3005 struct kvm_pio_request *io = &vcpu->arch.pio;
3006 void *pd = vcpu->arch.pio_data;
bda9020e 3007 int i, r = 0;
de7d789a 3008
de7d789a 3009 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 3010 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
3011 io->port, io->size, pd)) {
3012 r = -EOPNOTSUPP;
3013 break;
3014 }
de7d789a
CO		 3015 pd += io->size;
3016 }
bda9020e 3017 return r;
de7d789a
CO		 3018}
3019
851ba692 3020int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3021{
5fdbf976 3022 unsigned long val;
de7d789a
CO		 3023
3024 vcpu->run->exit_reason = KVM_EXIT_IO;
3025 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3026 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3027 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3028 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3029 vcpu->run->io.port = vcpu->arch.pio.port = port;
3030 vcpu->arch.pio.in = in;
3031 vcpu->arch.pio.string = 0;
3032 vcpu->arch.pio.down = 0;
ad312c7c 3033 vcpu->arch.pio.rep = 0;
de7d789a 3034
229456fc
MT		 3035 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3036 size, 1);
2714d1d3 3037
5fdbf976
MT		 3038 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3039 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 3040
bda9020e 3041 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3042 complete_pio(vcpu);
3043 return 1;
3044 }
3045 return 0;
3046}
3047EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3048
851ba692 3049int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3050 int size, unsigned long count, int down,
3051 gva_t address, int rep, unsigned port)
3052{
3053 unsigned now, in_page;
0f346074 3054 int ret = 0;
de7d789a
CO		 3055
3056 vcpu->run->exit_reason = KVM_EXIT_IO;
3057 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3058 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3059 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3060 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3061 vcpu->run->io.port = vcpu->arch.pio.port = port;
3062 vcpu->arch.pio.in = in;
3063 vcpu->arch.pio.string = 1;
3064 vcpu->arch.pio.down = down;
ad312c7c 3065 vcpu->arch.pio.rep = rep;
de7d789a 3066
229456fc
MT		 3067 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3068 size, count);
2714d1d3 3069
de7d789a
CO		 3070 if (!count) {
3071 kvm_x86_ops->skip_emulated_instruction(vcpu);
3072 return 1;
3073 }
3074
3075 if (!down)
3076 in_page = PAGE_SIZE - offset_in_page(address);
3077 else
3078 in_page = offset_in_page(address) + size;
3079 now = min(count, (unsigned long)in_page / size);
0f346074 3080 if (!now)
de7d789a 3081 now = 1;
de7d789a
CO		 3082 if (down) {
3083 /*
3084 * String I/O in reverse. Yuck. Kill the guest, fix later.
3085 */
3086 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3087 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3088 return 1;
3089 }
3090 vcpu->run->io.count = now;
ad312c7c 3091 vcpu->arch.pio.cur_count = now;
de7d789a 3092
ad312c7c 3093 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3094 kvm_x86_ops->skip_emulated_instruction(vcpu);
3095
0f346074 3096 vcpu->arch.pio.guest_gva = address;
de7d789a 3097
ad312c7c 3098 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3099 /* string PIO write */
3100 ret = pio_copy_data(vcpu);
0f346074
IE		 3101 if (ret == X86EMUL_PROPAGATE_FAULT) {
3102 kvm_inject_gp(vcpu, 0);
3103 return 1;
3104 }
bda9020e 3105 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3106 complete_pio(vcpu);
ad312c7c 3107 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3108 ret = 1;
3109 }
bda9020e
MT		 3110 }
3111 /* no string PIO read support yet */
de7d789a
CO		 3112
3113 return ret;
3114}
3115EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3116
c8076604
GH		 3117static void bounce_off(void *info)
3118{
3119 /* nothing */
3120}
3121
c8076604
GH		 3122static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3123 void *data)
3124{
3125 struct cpufreq_freqs *freq = data;
3126 struct kvm *kvm;
3127 struct kvm_vcpu *vcpu;
3128 int i, send_ipi = 0;
3129
c8076604
GH		 3130 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3131 return 0;
3132 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3133 return 0;
0cca7907 3134 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3135
3136 spin_lock(&kvm_lock);
3137 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3138 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3139 if (vcpu->cpu != freq->cpu)
3140 continue;
3141 if (!kvm_request_guest_time_update(vcpu))
3142 continue;
3143 if (vcpu->cpu != smp_processor_id())
3144 send_ipi++;
3145 }
3146 }
3147 spin_unlock(&kvm_lock);
3148
3149 if (freq->old < freq->new && send_ipi) {
3150 /*
3151 * We upscale the frequency. Must make the guest
3152 * doesn't see old kvmclock values while running with
3153 * the new frequency, otherwise we risk the guest sees
3154 * time go backwards.
3155 *
3156 * In case we update the frequency for another cpu
3157 * (which might be in guest context) send an interrupt
3158 * to kick the cpu out of guest context. Next time
3159 * guest context is entered kvmclock will be updated,
3160 * so the guest will not see stale values.
3161 */
3162 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3163 }
3164 return 0;
3165}
3166
3167static struct notifier_block kvmclock_cpufreq_notifier_block = {
3168 .notifier_call = kvmclock_cpufreq_notifier
3169};
3170
b820cc0c
ZA		 3171static void kvm_timer_init(void)
3172{
3173 int cpu;
3174
b820cc0c 3175 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3176 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3177 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3178 for_each_online_cpu(cpu) {
3179 unsigned long khz = cpufreq_get(cpu);
3180 if (!khz)
3181 khz = tsc_khz;
3182 per_cpu(cpu_tsc_khz, cpu) = khz;
3183 }
0cca7907
ZA		 3184 } else {
3185 for_each_possible_cpu(cpu)
3186 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3187 }
3188}
3189
f8c16bba 3190int kvm_arch_init(void *opaque)
043405e1 3191{
b820cc0c 3192 int r;
f8c16bba
ZX		 3193 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3194
f8c16bba
ZX		 3195 if (kvm_x86_ops) {
3196 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3197 r = -EEXIST;
3198 goto out;
f8c16bba
ZX		 3199 }
3200
3201 if (!ops->cpu_has_kvm_support()) {
3202 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3203 r = -EOPNOTSUPP;
3204 goto out;
f8c16bba
ZX		 3205 }
3206 if (ops->disabled_by_bios()) {
3207 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3208 r = -EOPNOTSUPP;
3209 goto out;
f8c16bba
ZX		 3210 }
3211
97db56ce
AK		 3212 r = kvm_mmu_module_init();
3213 if (r)
3214 goto out;
3215
3216 kvm_init_msr_list();
3217
f8c16bba 3218 kvm_x86_ops = ops;
56c6d28a 3219 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3220 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3221 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3222 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3223
b820cc0c 3224 kvm_timer_init();
c8076604 3225
f8c16bba 3226 return 0;
56c6d28a
ZX		 3227
3228out:
56c6d28a 3229 return r;
043405e1 3230}
8776e519 3231
f8c16bba
ZX		 3232void kvm_arch_exit(void)
3233{
888d256e
JK		 3234 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3235 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3236 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3237 kvm_x86_ops = NULL;
56c6d28a
ZX		 3238 kvm_mmu_module_exit();
3239}
f8c16bba 3240
8776e519
HB		 3241int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3242{
3243 ++vcpu->stat.halt_exits;
3244 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3245 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3246 return 1;
3247 } else {
3248 vcpu->run->exit_reason = KVM_EXIT_HLT;
3249 return 0;
3250 }
3251}
3252EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3253
2f333bcb
MT		 3254static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3255 unsigned long a1)
3256{
3257 if (is_long_mode(vcpu))
3258 return a0;
3259 else
3260 return a0 | ((gpa_t)a1 << 32);
3261}
3262
8776e519
HB		 3263int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3264{
3265 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3266 int r = 1;
8776e519 3267
5fdbf976
MT		 3268 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3269 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3270 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3271 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3272 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3273
229456fc 3274 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3275
8776e519
HB		 3276 if (!is_long_mode(vcpu)) {
3277 nr &= 0xFFFFFFFF;
3278 a0 &= 0xFFFFFFFF;
3279 a1 &= 0xFFFFFFFF;
3280 a2 &= 0xFFFFFFFF;
3281 a3 &= 0xFFFFFFFF;
3282 }
3283
07708c4a
JK		 3284 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3285 ret = -KVM_EPERM;
3286 goto out;
3287 }
3288
8776e519 3289 switch (nr) {
b93463aa
AK		 3290 case KVM_HC_VAPIC_POLL_IRQ:
3291 ret = 0;
3292 break;
2f333bcb
MT		 3293 case KVM_HC_MMU_OP:
3294 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3295 break;
8776e519
HB		 3296 default:
3297 ret = -KVM_ENOSYS;
3298 break;
3299 }
07708c4a 3300out:
5fdbf976 3301 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3302 ++vcpu->stat.hypercalls;
2f333bcb 3303 return r;
8776e519
HB		 3304}
3305EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3306
3307int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3308{
3309 char instruction[3];
3310 int ret = 0;
5fdbf976 3311 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3312
8776e519
HB		 3313
3314 /*
3315 * Blow out the MMU to ensure that no other VCPU has an active mapping
3316 * to ensure that the updated hypercall appears atomically across all
3317 * VCPUs.
3318 */
3319 kvm_mmu_zap_all(vcpu->kvm);
3320
8776e519 3321 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3322 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3323 != X86EMUL_CONTINUE)
3324 ret = -EFAULT;
3325
8776e519
HB		 3326 return ret;
3327}
3328
3329static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3330{
3331 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3332}
3333
3334void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3335{
3336 struct descriptor_table dt = { limit, base };
3337
3338 kvm_x86_ops->set_gdt(vcpu, &dt);
3339}
3340
3341void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3342{
3343 struct descriptor_table dt = { limit, base };
3344
3345 kvm_x86_ops->set_idt(vcpu, &dt);
3346}
3347
3348void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3349 unsigned long *rflags)
3350{
2d3ad1f4 3351 kvm_lmsw(vcpu, msw);
91586a3b 3352 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3353}
3354
3355unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3356{
54e445ca
JR		 3357 unsigned long value;
3358
8776e519
HB		 3359 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3360 switch (cr) {
3361 case 0:
54e445ca
JR		 3362 value = vcpu->arch.cr0;
3363 break;
8776e519 3364 case 2:
54e445ca
JR		 3365 value = vcpu->arch.cr2;
3366 break;
8776e519 3367 case 3:
54e445ca
JR		 3368 value = vcpu->arch.cr3;
3369 break;
8776e519 3370 case 4:
54e445ca
JR		 3371 value = vcpu->arch.cr4;
3372 break;
152ff9be 3373 case 8:
54e445ca
JR		 3374 value = kvm_get_cr8(vcpu);
3375 break;
8776e519 3376 default:
b8688d51 3377 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3378 return 0;
3379 }
54e445ca
JR		 3380
3381 return value;
8776e519
HB		 3382}
3383
3384void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3385 unsigned long *rflags)
3386{
3387 switch (cr) {
3388 case 0:
2d3ad1f4 3389 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
91586a3b 3390 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3391 break;
3392 case 2:
ad312c7c 3393 vcpu->arch.cr2 = val;
8776e519
HB		 3394 break;
3395 case 3:
2d3ad1f4 3396 kvm_set_cr3(vcpu, val);
8776e519
HB		 3397 break;
3398 case 4:
2d3ad1f4 3399 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3400 break;
152ff9be 3401 case 8:
2d3ad1f4 3402 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3403 break;
8776e519 3404 default:
b8688d51 3405 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3406 }
3407}
3408
07716717
DK		 3409static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3410{
ad312c7c
ZX		 3411 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3412 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3413
3414 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3415 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3416 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3417 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3418 if (ej->function == e->function) {
3419 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3420 return j;
3421 }
3422 }
3423 return 0; /* silence gcc, even though control never reaches here */
3424}
3425
3426/* find an entry with matching function, matching index (if needed), and that
3427 * should be read next (if it's stateful) */
3428static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3429 u32 function, u32 index)
3430{
3431 if (e->function != function)
3432 return 0;
3433 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3434 return 0;
3435 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3436 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3437 return 0;
3438 return 1;
3439}
3440
d8017474
AG		 3441struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3442 u32 function, u32 index)
8776e519
HB		 3443{
3444 int i;
d8017474 3445 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3446
ad312c7c 3447 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3448 struct kvm_cpuid_entry2 *e;
3449
ad312c7c 3450 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3451 if (is_matching_cpuid_entry(e, function, index)) {
3452 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3453 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3454 best = e;
3455 break;
3456 }
3457 /*
3458 * Both basic or both extended?
3459 */
3460 if (((e->function ^ function) & 0x80000000) == 0)
3461 if (!best || e->function > best->function)
3462 best = e;
3463 }
d8017474
AG		 3464 return best;
3465}
3466
82725b20
DE		 3467int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3468{
3469 struct kvm_cpuid_entry2 *best;
3470
3471 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3472 if (best)
3473 return best->eax & 0xff;
3474 return 36;
3475}
3476
d8017474
AG		 3477void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3478{
3479 u32 function, index;
3480 struct kvm_cpuid_entry2 *best;
3481
3482 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3483 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3484 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3485 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3486 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3487 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3488 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3489 if (best) {
5fdbf976
MT		 3490 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3491 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3492 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3493 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3494 }
8776e519 3495 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3496 trace_kvm_cpuid(function,
3497 kvm_register_read(vcpu, VCPU_REGS_RAX),
3498 kvm_register_read(vcpu, VCPU_REGS_RBX),
3499 kvm_register_read(vcpu, VCPU_REGS_RCX),
3500 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3501}
3502EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3503
b6c7a5dc
HB		 3504/*
3505 * Check if userspace requested an interrupt window, and that the
3506 * interrupt window is open.
3507 *
3508 * No need to exit to userspace if we already have an interrupt queued.
3509 */
851ba692 3510static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 3511{
8061823a 3512 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 3513 vcpu->run->request_interrupt_window &&
5df56646 3514 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3515}
3516
851ba692 3517static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 3518{
851ba692
AK		 3519 struct kvm_run *kvm_run = vcpu->run;
3520
91586a3b 3521 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3522 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3523 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3524 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3525 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3526 else
b6c7a5dc 3527 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3528 kvm_arch_interrupt_allowed(vcpu) &&
3529 !kvm_cpu_has_interrupt(vcpu) &&
3530 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3531}
3532
b93463aa
AK		 3533static void vapic_enter(struct kvm_vcpu *vcpu)
3534{
3535 struct kvm_lapic *apic = vcpu->arch.apic;
3536 struct page *page;
3537
3538 if (!apic || !apic->vapic_addr)
3539 return;
3540
3541 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3542
3543 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3544}
3545
3546static void vapic_exit(struct kvm_vcpu *vcpu)
3547{
3548 struct kvm_lapic *apic = vcpu->arch.apic;
3549
3550 if (!apic || !apic->vapic_addr)
3551 return;
3552
f8b78fa3 3553 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3554 kvm_release_page_dirty(apic->vapic_page);
3555 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3556 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3557}
3558
95ba8273
GN		 3559static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3560{
3561 int max_irr, tpr;
3562
3563 if (!kvm_x86_ops->update_cr8_intercept)
3564 return;
3565
88c808fd
AK		 3566 if (!vcpu->arch.apic)
3567 return;
3568
8db3baa2
GN		 3569 if (!vcpu->arch.apic->vapic_addr)
3570 max_irr = kvm_lapic_find_highest_irr(vcpu);
3571 else
3572 max_irr = -1;
95ba8273
GN		 3573
3574 if (max_irr != -1)
3575 max_irr >>= 4;
3576
3577 tpr = kvm_lapic_get_cr8(vcpu);
3578
3579 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3580}
3581
851ba692 3582static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 3583{
3584 /* try to reinject previous events if any */
b59bb7bd
GN		 3585 if (vcpu->arch.exception.pending) {
3586 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3587 vcpu->arch.exception.has_error_code,
3588 vcpu->arch.exception.error_code);
3589 return;
3590 }
3591
95ba8273
GN		 3592 if (vcpu->arch.nmi_injected) {
3593 kvm_x86_ops->set_nmi(vcpu);
3594 return;
3595 }
3596
3597 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3598 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3599 return;
3600 }
3601
3602 /* try to inject new event if pending */
3603 if (vcpu->arch.nmi_pending) {
3604 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3605 vcpu->arch.nmi_pending = false;
3606 vcpu->arch.nmi_injected = true;
3607 kvm_x86_ops->set_nmi(vcpu);
3608 }
3609 } else if (kvm_cpu_has_interrupt(vcpu)) {
3610 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3611 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3612 false);
3613 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3614 }
3615 }
3616}
3617
851ba692 3618static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 3619{
3620 int r;
6a8b1d13 3621 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 3622 vcpu->run->request_interrupt_window;
b6c7a5dc 3623
2e53d63a
MT		 3624 if (vcpu->requests)
3625 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3626 kvm_mmu_unload(vcpu);
3627
b6c7a5dc
HB		 3628 r = kvm_mmu_reload(vcpu);
3629 if (unlikely(r))
3630 goto out;
3631
2f52d58c
AK		 3632 if (vcpu->requests) {
3633 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3634 __kvm_migrate_timers(vcpu);
c8076604
GH		 3635 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3636 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3637 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3638 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3639 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3640 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3641 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3642 &vcpu->requests)) {
851ba692 3643 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 3644 r = 0;
3645 goto out;
3646 }
71c4dfaf 3647 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 3648 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 3649 r = 0;
3650 goto out;
3651 }
2f52d58c 3652 }
b93463aa 3653
b6c7a5dc
HB		 3654 preempt_disable();
3655
3656 kvm_x86_ops->prepare_guest_switch(vcpu);
3657 kvm_load_guest_fpu(vcpu);
3658
3659 local_irq_disable();
3660
32f88400
MT		 3661 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3662 smp_mb__after_clear_bit();
3663
d7690175 3664 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3665 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3666 local_irq_enable();
3667 preempt_enable();
3668 r = 1;
3669 goto out;
3670 }
3671
851ba692 3672 inject_pending_event(vcpu);
b6c7a5dc 3673
6a8b1d13
GN		 3674 /* enable NMI/IRQ window open exits if needed */
3675 if (vcpu->arch.nmi_pending)
3676 kvm_x86_ops->enable_nmi_window(vcpu);
3677 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3678 kvm_x86_ops->enable_irq_window(vcpu);
3679
95ba8273 3680 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3681 update_cr8_intercept(vcpu);
3682 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3683 }
b93463aa 3684
3200f405
MT		 3685 up_read(&vcpu->kvm->slots_lock);
3686
b6c7a5dc
HB		 3687 kvm_guest_enter();
3688
42dbaa5a 3689 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 3690 set_debugreg(0, 7);
3691 set_debugreg(vcpu->arch.eff_db[0], 0);
3692 set_debugreg(vcpu->arch.eff_db[1], 1);
3693 set_debugreg(vcpu->arch.eff_db[2], 2);
3694 set_debugreg(vcpu->arch.eff_db[3], 3);
3695 }
b6c7a5dc 3696
229456fc 3697 trace_kvm_entry(vcpu->vcpu_id);
851ba692 3698 kvm_x86_ops->run(vcpu);
b6c7a5dc 3699
3d53c27d
AK		 3700 if (unlikely(vcpu->arch.switch_db_regs || test_thread_flag(TIF_DEBUG))) {
3701 set_debugreg(current->thread.debugreg0, 0);
3702 set_debugreg(current->thread.debugreg1, 1);
3703 set_debugreg(current->thread.debugreg2, 2);
3704 set_debugreg(current->thread.debugreg3, 3);
3705 set_debugreg(current->thread.debugreg6, 6);
3706 set_debugreg(current->thread.debugreg7, 7);
42dbaa5a 3707 }
42dbaa5a 3708
32f88400 3709 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3710 local_irq_enable();
3711
3712 ++vcpu->stat.exits;
3713
3714 /*
3715 * We must have an instruction between local_irq_enable() and
3716 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3717 * the interrupt shadow. The stat.exits increment will do nicely.
3718 * But we need to prevent reordering, hence this barrier():
3719 */
3720 barrier();
3721
3722 kvm_guest_exit();
3723
3724 preempt_enable();
3725
3200f405
MT		 3726 down_read(&vcpu->kvm->slots_lock);
3727
b6c7a5dc
HB		 3728 /*
3729 * Profile KVM exit RIPs:
3730 */
3731 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3732 unsigned long rip = kvm_rip_read(vcpu);
3733 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3734 }
3735
298101da 3736
b93463aa
AK		 3737 kvm_lapic_sync_from_vapic(vcpu);
3738
851ba692 3739 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 3740out:
3741 return r;
3742}
b6c7a5dc 3743
09cec754 3744
851ba692 3745static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 3746{
3747 int r;
3748
3749 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3750 pr_debug("vcpu %d received sipi with vector # %x\n",
3751 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3752 kvm_lapic_reset(vcpu);
5f179287 3753 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3754 if (r)
3755 return r;
3756 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3757 }
3758
d7690175
MT		 3759 down_read(&vcpu->kvm->slots_lock);
3760 vapic_enter(vcpu);
3761
3762 r = 1;
3763 while (r > 0) {
af2152f5 3764 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 3765 r = vcpu_enter_guest(vcpu);
d7690175
MT		 3766 else {
3767 up_read(&vcpu->kvm->slots_lock);
3768 kvm_vcpu_block(vcpu);
3769 down_read(&vcpu->kvm->slots_lock);
3770 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3771 {
3772 switch(vcpu->arch.mp_state) {
3773 case KVM_MP_STATE_HALTED:
d7690175 3774 vcpu->arch.mp_state =
09cec754
GN		 3775 KVM_MP_STATE_RUNNABLE;
3776 case KVM_MP_STATE_RUNNABLE:
3777 break;
3778 case KVM_MP_STATE_SIPI_RECEIVED:
3779 default:
3780 r = -EINTR;
3781 break;
3782 }
3783 }
d7690175
MT		 3784 }
3785
09cec754
GN		 3786 if (r <= 0)
3787 break;
3788
3789 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3790 if (kvm_cpu_has_pending_timer(vcpu))
3791 kvm_inject_pending_timer_irqs(vcpu);
3792
851ba692 3793 if (dm_request_for_irq_injection(vcpu)) {
09cec754 3794 r = -EINTR;
851ba692 3795 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 3796 ++vcpu->stat.request_irq_exits;
3797 }
3798 if (signal_pending(current)) {
3799 r = -EINTR;
851ba692 3800 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 3801 ++vcpu->stat.signal_exits;
3802 }
3803 if (need_resched()) {
3804 up_read(&vcpu->kvm->slots_lock);
3805 kvm_resched(vcpu);
3806 down_read(&vcpu->kvm->slots_lock);
d7690175 3807 }
b6c7a5dc
HB		 3808 }
3809
d7690175 3810 up_read(&vcpu->kvm->slots_lock);
851ba692 3811 post_kvm_run_save(vcpu);
b6c7a5dc 3812
b93463aa
AK		 3813 vapic_exit(vcpu);
3814
b6c7a5dc
HB		 3815 return r;
3816}
3817
3818int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3819{
3820 int r;
3821 sigset_t sigsaved;
3822
3823 vcpu_load(vcpu);
3824
ac9f6dc0
AK		 3825 if (vcpu->sigset_active)
3826 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3827
a4535290 3828 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3829 kvm_vcpu_block(vcpu);
d7690175 3830 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3831 r = -EAGAIN;
3832 goto out;
b6c7a5dc
HB		 3833 }
3834
b6c7a5dc
HB		 3835 /* re-sync apic's tpr */
3836 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3837 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3838
ad312c7c 3839 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3840 r = complete_pio(vcpu);
3841 if (r)
3842 goto out;
3843 }
b6c7a5dc
HB		 3844 if (vcpu->mmio_needed) {
3845 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3846 vcpu->mmio_read_completed = 1;
3847 vcpu->mmio_needed = 0;
3200f405
MT		 3848
3849 down_read(&vcpu->kvm->slots_lock);
851ba692 3850 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 3851 EMULTYPE_NO_DECODE);
3200f405 3852 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3853 if (r == EMULATE_DO_MMIO) {
3854 /*
3855 * Read-modify-write. Back to userspace.
3856 */
3857 r = 0;
3858 goto out;
3859 }
3860 }
5fdbf976
MT		 3861 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3862 kvm_register_write(vcpu, VCPU_REGS_RAX,
3863 kvm_run->hypercall.ret);
b6c7a5dc 3864
851ba692 3865 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 3866
3867out:
3868 if (vcpu->sigset_active)
3869 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3870
3871 vcpu_put(vcpu);
3872 return r;
3873}
3874
3875int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3876{
3877 vcpu_load(vcpu);
3878
5fdbf976
MT		 3879 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3880 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3881 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3882 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3883 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3884 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3885 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3886 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3887#ifdef CONFIG_X86_64
5fdbf976
MT		 3888 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3889 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3890 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3891 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3892 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3893 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3894 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3895 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3896#endif
3897
5fdbf976 3898 regs->rip = kvm_rip_read(vcpu);
91586a3b 3899 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 3900
3901 vcpu_put(vcpu);
3902
3903 return 0;
3904}
3905
3906int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3907{
3908 vcpu_load(vcpu);
3909
5fdbf976
MT		 3910 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3911 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3912 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3913 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3914 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3915 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3916 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3917 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3918#ifdef CONFIG_X86_64
5fdbf976
MT		 3919 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3920 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3921 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3922 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3923 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3924 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3925 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3926 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 3927#endif
3928
5fdbf976 3929 kvm_rip_write(vcpu, regs->rip);
91586a3b 3930 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 3931
b4f14abd
JK		 3932 vcpu->arch.exception.pending = false;
3933
b6c7a5dc
HB		 3934 vcpu_put(vcpu);
3935
3936 return 0;
3937}
3938
3e6e0aab
GT		 3939void kvm_get_segment(struct kvm_vcpu *vcpu,
3940 struct kvm_segment *var, int seg)
b6c7a5dc 3941{
14af3f3c 3942 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3943}
3944
3945void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3946{
3947 struct kvm_segment cs;
3948
3e6e0aab 3949 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3950 *db = cs.db;
3951 *l = cs.l;
3952}
3953EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3954
3955int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3956 struct kvm_sregs *sregs)
3957{
3958 struct descriptor_table dt;
b6c7a5dc
HB		 3959
3960 vcpu_load(vcpu);
3961
3e6e0aab
GT		 3962 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3963 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3964 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3965 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3966 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3967 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3968
3e6e0aab
GT		 3969 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3970 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3971
3972 kvm_x86_ops->get_idt(vcpu, &dt);
3973 sregs->idt.limit = dt.limit;
3974 sregs->idt.base = dt.base;
3975 kvm_x86_ops->get_gdt(vcpu, &dt);
3976 sregs->gdt.limit = dt.limit;
3977 sregs->gdt.base = dt.base;
3978
3979 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3980 sregs->cr0 = vcpu->arch.cr0;
3981 sregs->cr2 = vcpu->arch.cr2;
3982 sregs->cr3 = vcpu->arch.cr3;
3983 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3984 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3985 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3986 sregs->apic_base = kvm_get_apic_base(vcpu);
3987
923c61bb 3988 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3989
36752c9b 3990 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3991 set_bit(vcpu->arch.interrupt.nr,
3992 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3993
b6c7a5dc
HB		 3994 vcpu_put(vcpu);
3995
3996 return 0;
3997}
3998
62d9f0db
MT		 3999int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4000 struct kvm_mp_state *mp_state)
4001{
4002 vcpu_load(vcpu);
4003 mp_state->mp_state = vcpu->arch.mp_state;
4004 vcpu_put(vcpu);
4005 return 0;
4006}
4007
4008int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4009 struct kvm_mp_state *mp_state)
4010{
4011 vcpu_load(vcpu);
4012 vcpu->arch.mp_state = mp_state->mp_state;
4013 vcpu_put(vcpu);
4014 return 0;
4015}
4016
3e6e0aab 4017static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4018 struct kvm_segment *var, int seg)
4019{
14af3f3c 4020 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4021}
4022
37817f29
IE		 4023static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4024 struct kvm_segment *kvm_desct)
4025{
46a359e7
AM		 4026 kvm_desct->base = get_desc_base(seg_desc);
4027 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4028 if (seg_desc->g) {
4029 kvm_desct->limit <<= 12;
4030 kvm_desct->limit |= 0xfff;
4031 }
37817f29
IE		 4032 kvm_desct->selector = selector;
4033 kvm_desct->type = seg_desc->type;
4034 kvm_desct->present = seg_desc->p;
4035 kvm_desct->dpl = seg_desc->dpl;
4036 kvm_desct->db = seg_desc->d;
4037 kvm_desct->s = seg_desc->s;
4038 kvm_desct->l = seg_desc->l;
4039 kvm_desct->g = seg_desc->g;
4040 kvm_desct->avl = seg_desc->avl;
4041 if (!selector)
4042 kvm_desct->unusable = 1;
4043 else
4044 kvm_desct->unusable = 0;
4045 kvm_desct->padding = 0;
4046}
4047
b8222ad2
AS		 4048static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4049 u16 selector,
4050 struct descriptor_table *dtable)
37817f29
IE		 4051{
4052 if (selector & 1 << 2) {
4053 struct kvm_segment kvm_seg;
4054
3e6e0aab 4055 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4056
4057 if (kvm_seg.unusable)
4058 dtable->limit = 0;
4059 else
4060 dtable->limit = kvm_seg.limit;
4061 dtable->base = kvm_seg.base;
4062 }
4063 else
4064 kvm_x86_ops->get_gdt(vcpu, dtable);
4065}
4066
4067/* allowed just for 8 bytes segments */
4068static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4069 struct desc_struct *seg_desc)
4070{
4071 struct descriptor_table dtable;
4072 u16 index = selector >> 3;
4073
b8222ad2 4074 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4075
4076 if (dtable.limit < index * 8 + 7) {
4077 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4078 return 1;
4079 }
d9048d32 4080 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4081}
4082
4083/* allowed just for 8 bytes segments */
4084static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4085 struct desc_struct *seg_desc)
4086{
4087 struct descriptor_table dtable;
4088 u16 index = selector >> 3;
4089
b8222ad2 4090 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4091
4092 if (dtable.limit < index * 8 + 7)
4093 return 1;
d9048d32 4094 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4095}
4096
abb39119 4097static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
37817f29
IE		 4098 struct desc_struct *seg_desc)
4099{
46a359e7 4100 u32 base_addr = get_desc_base(seg_desc);
37817f29 4101
98899aa0 4102 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4103}
4104
37817f29
IE		 4105static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4106{
4107 struct kvm_segment kvm_seg;
4108
3e6e0aab 4109 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4110 return kvm_seg.selector;
4111}
4112
4113static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4114 u16 selector,
4115 struct kvm_segment *kvm_seg)
4116{
4117 struct desc_struct seg_desc;
4118
4119 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4120 return 1;
4121 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4122 return 0;
4123}
4124
2259e3a7 4125static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4126{
4127 struct kvm_segment segvar = {
4128 .base = selector << 4,
4129 .limit = 0xffff,
4130 .selector = selector,
4131 .type = 3,
4132 .present = 1,
4133 .dpl = 3,
4134 .db = 0,
4135 .s = 1,
4136 .l = 0,
4137 .g = 0,
4138 .avl = 0,
4139 .unusable = 0,
4140 };
4141 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4142 return 0;
4143}
4144
c0c7c04b
AL		 4145static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4146{
4147 return (seg != VCPU_SREG_LDTR) &&
4148 (seg != VCPU_SREG_TR) &&
91586a3b 4149 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4150}
4151
3e6e0aab
GT		 4152int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4153 int type_bits, int seg)
37817f29
IE		 4154{
4155 struct kvm_segment kvm_seg;
4156
c0c7c04b 4157 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
f4bbd9aa 4158 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4159 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4160 return 1;
4161 kvm_seg.type |= type_bits;
4162
4163 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4164 seg != VCPU_SREG_LDTR)
4165 if (!kvm_seg.s)
4166 kvm_seg.unusable = 1;
4167
3e6e0aab 4168 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4169 return 0;
4170}
4171
4172static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4173 struct tss_segment_32 *tss)
4174{
4175 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4176 tss->eip = kvm_rip_read(vcpu);
91586a3b 4177 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4178 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4179 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4180 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4181 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4182 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4183 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4184 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4185 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4186 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4187 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4188 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4189 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4190 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4191 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4192 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4193}
4194
4195static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4196 struct tss_segment_32 *tss)
4197{
4198 kvm_set_cr3(vcpu, tss->cr3);
4199
5fdbf976 4200 kvm_rip_write(vcpu, tss->eip);
91586a3b 4201 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4202
5fdbf976
MT		 4203 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4204 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4205 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4206 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4207 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4208 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4209 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4210 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4211
3e6e0aab 4212 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4213 return 1;
4214
3e6e0aab 4215 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4216 return 1;
4217
3e6e0aab 4218 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4219 return 1;
4220
3e6e0aab 4221 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4222 return 1;
4223
3e6e0aab 4224 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4225 return 1;
4226
3e6e0aab 4227 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4228 return 1;
4229
3e6e0aab 4230 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4231 return 1;
4232 return 0;
4233}
4234
4235static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4236 struct tss_segment_16 *tss)
4237{
5fdbf976 4238 tss->ip = kvm_rip_read(vcpu);
91586a3b 4239 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4240 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4241 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4242 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4243 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4244 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4245 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4246 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4247 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4248
4249 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4250 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4251 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4252 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4253 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4254}
4255
4256static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4257 struct tss_segment_16 *tss)
4258{
5fdbf976 4259 kvm_rip_write(vcpu, tss->ip);
91586a3b 4260 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4261 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4262 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4263 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4264 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4265 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4266 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4267 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4268 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4269
3e6e0aab 4270 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4271 return 1;
4272
3e6e0aab 4273 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4274 return 1;
4275
3e6e0aab 4276 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4277 return 1;
4278
3e6e0aab 4279 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4280 return 1;
4281
3e6e0aab 4282 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4283 return 1;
4284 return 0;
4285}
4286
8b2cf73c 4287static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4288 u16 old_tss_sel, u32 old_tss_base,
4289 struct desc_struct *nseg_desc)
37817f29
IE		 4290{
4291 struct tss_segment_16 tss_segment_16;
4292 int ret = 0;
4293
34198bf8
MT		 4294 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4295 sizeof tss_segment_16))
37817f29
IE		 4296 goto out;
4297
4298 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4299
34198bf8
MT		 4300 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4301 sizeof tss_segment_16))
37817f29 4302 goto out;
34198bf8
MT		 4303
4304 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4305 &tss_segment_16, sizeof tss_segment_16))
4306 goto out;
4307
b237ac37
GN		 4308 if (old_tss_sel != 0xffff) {
4309 tss_segment_16.prev_task_link = old_tss_sel;
4310
4311 if (kvm_write_guest(vcpu->kvm,
4312 get_tss_base_addr(vcpu, nseg_desc),
4313 &tss_segment_16.prev_task_link,
4314 sizeof tss_segment_16.prev_task_link))
4315 goto out;
4316 }
4317
37817f29
IE		 4318 if (load_state_from_tss16(vcpu, &tss_segment_16))
4319 goto out;
4320
4321 ret = 1;
4322out:
4323 return ret;
4324}
4325
8b2cf73c 4326static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4327 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4328 struct desc_struct *nseg_desc)
4329{
4330 struct tss_segment_32 tss_segment_32;
4331 int ret = 0;
4332
34198bf8
MT		 4333 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4334 sizeof tss_segment_32))
37817f29
IE		 4335 goto out;
4336
4337 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4338
34198bf8
MT		 4339 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4340 sizeof tss_segment_32))
4341 goto out;
4342
4343 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4344 &tss_segment_32, sizeof tss_segment_32))
37817f29 4345 goto out;
34198bf8 4346
b237ac37
GN		 4347 if (old_tss_sel != 0xffff) {
4348 tss_segment_32.prev_task_link = old_tss_sel;
4349
4350 if (kvm_write_guest(vcpu->kvm,
4351 get_tss_base_addr(vcpu, nseg_desc),
4352 &tss_segment_32.prev_task_link,
4353 sizeof tss_segment_32.prev_task_link))
4354 goto out;
4355 }
4356
37817f29
IE		 4357 if (load_state_from_tss32(vcpu, &tss_segment_32))
4358 goto out;
4359
4360 ret = 1;
4361out:
4362 return ret;
4363}
4364
4365int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4366{
4367 struct kvm_segment tr_seg;
4368 struct desc_struct cseg_desc;
4369 struct desc_struct nseg_desc;
4370 int ret = 0;
34198bf8
MT		 4371 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4372 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4373
34198bf8 4374 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4375
34198bf8
MT		 4376 /* FIXME: Handle errors. Failure to read either TSS or their
4377 * descriptors should generate a pagefault.
4378 */
37817f29
IE		 4379 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4380 goto out;
4381
34198bf8 4382 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4383 goto out;
4384
37817f29
IE		 4385 if (reason != TASK_SWITCH_IRET) {
4386 int cpl;
4387
4388 cpl = kvm_x86_ops->get_cpl(vcpu);
4389 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4390 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4391 return 1;
4392 }
4393 }
4394
46a359e7 4395 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4396 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4397 return 1;
4398 }
4399
4400 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4401 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4402 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4403 }
4404
4405 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 4406 u32 eflags = kvm_get_rflags(vcpu);
4407 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 4408 }
4409
64a7ec06
GN		 4410 /* set back link to prev task only if NT bit is set in eflags
4411 note that old_tss_sel is not used afetr this point */
4412 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4413 old_tss_sel = 0xffff;
37817f29 4414
b237ac37
GN		 4415 /* set back link to prev task only if NT bit is set in eflags
4416 note that old_tss_sel is not used afetr this point */
4417 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4418 old_tss_sel = 0xffff;
4419
37817f29 4420 if (nseg_desc.type & 8)
b237ac37
GN		 4421 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4422 old_tss_base, &nseg_desc);
37817f29 4423 else
b237ac37
GN		 4424 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4425 old_tss_base, &nseg_desc);
37817f29
IE		 4426
4427 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 4428 u32 eflags = kvm_get_rflags(vcpu);
4429 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 4430 }
4431
4432 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4433 nseg_desc.type |= (1 << 1);
37817f29
IE		 4434 save_guest_segment_descriptor(vcpu, tss_selector,
4435 &nseg_desc);
4436 }
4437
4438 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4439 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4440 tr_seg.type = 11;
3e6e0aab 4441 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4442out:
37817f29
IE		 4443 return ret;
4444}
4445EXPORT_SYMBOL_GPL(kvm_task_switch);
4446
b6c7a5dc
HB		 4447int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4448 struct kvm_sregs *sregs)
4449{
4450 int mmu_reset_needed = 0;
923c61bb 4451 int pending_vec, max_bits;
b6c7a5dc
HB		 4452 struct descriptor_table dt;
4453
4454 vcpu_load(vcpu);
4455
4456 dt.limit = sregs->idt.limit;
4457 dt.base = sregs->idt.base;
4458 kvm_x86_ops->set_idt(vcpu, &dt);
4459 dt.limit = sregs->gdt.limit;
4460 dt.base = sregs->gdt.base;
4461 kvm_x86_ops->set_gdt(vcpu, &dt);
4462
ad312c7c
ZX		 4463 vcpu->arch.cr2 = sregs->cr2;
4464 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4465 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4466
2d3ad1f4 4467 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4468
ad312c7c 4469 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4470 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4471 kvm_set_apic_base(vcpu, sregs->apic_base);
4472
4473 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4474
ad312c7c 4475 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4476 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4477 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4478
ad312c7c 4479 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4480 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4481 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4482 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4483
4484 if (mmu_reset_needed)
4485 kvm_mmu_reset_context(vcpu);
4486
923c61bb
GN		 4487 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4488 pending_vec = find_first_bit(
4489 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4490 if (pending_vec < max_bits) {
66fd3f7f 4491 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4492 pr_debug("Set back pending irq %d\n", pending_vec);
4493 if (irqchip_in_kernel(vcpu->kvm))
4494 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4495 }
4496
3e6e0aab
GT		 4497 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4498 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4499 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4500 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4501 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4502 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4503
3e6e0aab
GT		 4504 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4505 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4506
5f0269f5
ME		 4507 update_cr8_intercept(vcpu);
4508
9c3e4aab 4509 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4510 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4511 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4512 !(vcpu->arch.cr0 & X86_CR0_PE))
4513 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4514
b6c7a5dc
HB		 4515 vcpu_put(vcpu);
4516
4517 return 0;
4518}
4519
d0bfb940
JK		 4520int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4521 struct kvm_guest_debug *dbg)
b6c7a5dc 4522{
355be0b9 4523 unsigned long rflags;
355be0b9 4524 int i;
b6c7a5dc
HB		 4525
4526 vcpu_load(vcpu);
4527
91586a3b
JK		 4528 /*
4529 * Read rflags as long as potentially injected trace flags are still
4530 * filtered out.
4531 */
4532 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4533
4534 vcpu->guest_debug = dbg->control;
4535 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4536 vcpu->guest_debug = 0;
4537
4538 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4539 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4540 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4541 vcpu->arch.switch_db_regs =
4542 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4543 } else {
4544 for (i = 0; i < KVM_NR_DB_REGS; i++)
4545 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4546 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4547 }
4548
94fe45da
JK		 4549 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4550 vcpu->arch.singlestep_cs =
4551 get_segment_selector(vcpu, VCPU_SREG_CS);
4552 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
4553 }
4554
91586a3b
JK		 4555 /*
4556 * Trigger an rflags update that will inject or remove the trace
4557 * flags.
4558 */
4559 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4560
355be0b9
JK		 4561 kvm_x86_ops->set_guest_debug(vcpu, dbg);
4562
4563 if (vcpu->guest_debug & KVM_GUESTDBG_INJECT_DB)
d0bfb940 4564 kvm_queue_exception(vcpu, DB_VECTOR);
355be0b9 4565 else if (vcpu->guest_debug & KVM_GUESTDBG_INJECT_BP)
d0bfb940
JK		 4566 kvm_queue_exception(vcpu, BP_VECTOR);
4567
b6c7a5dc
HB		 4568 vcpu_put(vcpu);
4569
355be0b9 4570 return 0;
b6c7a5dc
HB		 4571}
4572
d0752060
HB		 4573/*
4574 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4575 * we have asm/x86/processor.h
4576 */
4577struct fxsave {
4578 u16 cwd;
4579 u16 swd;
4580 u16 twd;
4581 u16 fop;
4582 u64 rip;
4583 u64 rdp;
4584 u32 mxcsr;
4585 u32 mxcsr_mask;
4586 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4587#ifdef CONFIG_X86_64
4588 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4589#else
4590 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4591#endif
4592};
4593
8b006791
ZX		 4594/*
4595 * Translate a guest virtual address to a guest physical address.
4596 */
4597int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4598 struct kvm_translation *tr)
4599{
4600 unsigned long vaddr = tr->linear_address;
4601 gpa_t gpa;
4602
4603 vcpu_load(vcpu);
72dc67a6 4604 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4605 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4606 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4607 tr->physical_address = gpa;
4608 tr->valid = gpa != UNMAPPED_GVA;
4609 tr->writeable = 1;
4610 tr->usermode = 0;
8b006791
ZX		 4611 vcpu_put(vcpu);
4612
4613 return 0;
4614}
4615
d0752060
HB		 4616int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4617{
ad312c7c 4618 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4619
4620 vcpu_load(vcpu);
4621
4622 memcpy(fpu->fpr, fxsave->st_space, 128);
4623 fpu->fcw = fxsave->cwd;
4624 fpu->fsw = fxsave->swd;
4625 fpu->ftwx = fxsave->twd;
4626 fpu->last_opcode = fxsave->fop;
4627 fpu->last_ip = fxsave->rip;
4628 fpu->last_dp = fxsave->rdp;
4629 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4630
4631 vcpu_put(vcpu);
4632
4633 return 0;
4634}
4635
4636int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4637{
ad312c7c 4638 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4639
4640 vcpu_load(vcpu);
4641
4642 memcpy(fxsave->st_space, fpu->fpr, 128);
4643 fxsave->cwd = fpu->fcw;
4644 fxsave->swd = fpu->fsw;
4645 fxsave->twd = fpu->ftwx;
4646 fxsave->fop = fpu->last_opcode;
4647 fxsave->rip = fpu->last_ip;
4648 fxsave->rdp = fpu->last_dp;
4649 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4650
4651 vcpu_put(vcpu);
4652
4653 return 0;
4654}
4655
4656void fx_init(struct kvm_vcpu *vcpu)
4657{
4658 unsigned after_mxcsr_mask;
4659
bc1a34f1
AA		 4660 /*
4661 * Touch the fpu the first time in non atomic context as if
4662 * this is the first fpu instruction the exception handler
4663 * will fire before the instruction returns and it'll have to
4664 * allocate ram with GFP_KERNEL.
4665 */
4666 if (!used_math())
d6e88aec 4667 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4668
d0752060
HB		 4669 /* Initialize guest FPU by resetting ours and saving into guest's */
4670 preempt_disable();
d6e88aec
AK		 4671 kvm_fx_save(&vcpu->arch.host_fx_image);
4672 kvm_fx_finit();
4673 kvm_fx_save(&vcpu->arch.guest_fx_image);
4674 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4675 preempt_enable();
4676
ad312c7c 4677 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4678 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4679 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4680 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4681 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4682}
4683EXPORT_SYMBOL_GPL(fx_init);
4684
4685void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4686{
4687 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4688 return;
4689
4690 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4691 kvm_fx_save(&vcpu->arch.host_fx_image);
4692 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4693}
4694EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4695
4696void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4697{
4698 if (!vcpu->guest_fpu_loaded)
4699 return;
4700
4701 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4702 kvm_fx_save(&vcpu->arch.guest_fx_image);
4703 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4704 ++vcpu->stat.fpu_reload;
d0752060
HB		 4705}
4706EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4707
4708void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4709{
7f1ea208
JR		 4710 if (vcpu->arch.time_page) {
4711 kvm_release_page_dirty(vcpu->arch.time_page);
4712 vcpu->arch.time_page = NULL;
4713 }
4714
e9b11c17
ZX		 4715 kvm_x86_ops->vcpu_free(vcpu);
4716}
4717
4718struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4719 unsigned int id)
4720{
26e5215f
AK		 4721 return kvm_x86_ops->vcpu_create(kvm, id);
4722}
e9b11c17 4723
26e5215f
AK		 4724int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4725{
4726 int r;
e9b11c17
ZX		 4727
4728 /* We do fxsave: this must be aligned. */
ad312c7c 4729 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4730
0bed3b56 4731 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4732 vcpu_load(vcpu);
4733 r = kvm_arch_vcpu_reset(vcpu);
4734 if (r == 0)
4735 r = kvm_mmu_setup(vcpu);
4736 vcpu_put(vcpu);
4737 if (r < 0)
4738 goto free_vcpu;
4739
26e5215f 4740 return 0;
e9b11c17
ZX		 4741free_vcpu:
4742 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4743 return r;
e9b11c17
ZX		 4744}
4745
d40ccc62 4746void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4747{
4748 vcpu_load(vcpu);
4749 kvm_mmu_unload(vcpu);
4750 vcpu_put(vcpu);
4751
4752 kvm_x86_ops->vcpu_free(vcpu);
4753}
4754
4755int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4756{
448fa4a9
JK		 4757 vcpu->arch.nmi_pending = false;
4758 vcpu->arch.nmi_injected = false;
4759
42dbaa5a
JK		 4760 vcpu->arch.switch_db_regs = 0;
4761 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4762 vcpu->arch.dr6 = DR6_FIXED_1;
4763 vcpu->arch.dr7 = DR7_FIXED_1;
4764
e9b11c17
ZX		 4765 return kvm_x86_ops->vcpu_reset(vcpu);
4766}
4767
10474ae8 4768int kvm_arch_hardware_enable(void *garbage)
e9b11c17 4769{
0cca7907
ZA		 4770 /*
4771 * Since this may be called from a hotplug notifcation,
4772 * we can't get the CPU frequency directly.
4773 */
4774 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4775 int cpu = raw_smp_processor_id();
4776 per_cpu(cpu_tsc_khz, cpu) = 0;
4777 }
10474ae8 4778 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 4779}
4780
4781void kvm_arch_hardware_disable(void *garbage)
4782{
4783 kvm_x86_ops->hardware_disable(garbage);
4784}
4785
4786int kvm_arch_hardware_setup(void)
4787{
4788 return kvm_x86_ops->hardware_setup();
4789}
4790
4791void kvm_arch_hardware_unsetup(void)
4792{
4793 kvm_x86_ops->hardware_unsetup();
4794}
4795
4796void kvm_arch_check_processor_compat(void *rtn)
4797{
4798 kvm_x86_ops->check_processor_compatibility(rtn);
4799}
4800
4801int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4802{
4803 struct page *page;
4804 struct kvm *kvm;
4805 int r;
4806
4807 BUG_ON(vcpu->kvm == NULL);
4808 kvm = vcpu->kvm;
4809
ad312c7c 4810 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4811 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4812 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4813 else
a4535290 4814 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4815
4816 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4817 if (!page) {
4818 r = -ENOMEM;
4819 goto fail;
4820 }
ad312c7c 4821 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4822
4823 r = kvm_mmu_create(vcpu);
4824 if (r < 0)
4825 goto fail_free_pio_data;
4826
4827 if (irqchip_in_kernel(kvm)) {
4828 r = kvm_create_lapic(vcpu);
4829 if (r < 0)
4830 goto fail_mmu_destroy;
4831 }
4832
890ca9ae
HY		 4833 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4834 GFP_KERNEL);
4835 if (!vcpu->arch.mce_banks) {
4836 r = -ENOMEM;
4837 goto fail_mmu_destroy;
4838 }
4839 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4840
e9b11c17
ZX		 4841 return 0;
4842
4843fail_mmu_destroy:
4844 kvm_mmu_destroy(vcpu);
4845fail_free_pio_data:
ad312c7c 4846 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4847fail:
4848 return r;
4849}
4850
4851void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4852{
4853 kvm_free_lapic(vcpu);
3200f405 4854 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4855 kvm_mmu_destroy(vcpu);
3200f405 4856 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4857 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4858}
d19a9cd2
ZX		 4859
4860struct kvm *kvm_arch_create_vm(void)
4861{
4862 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4863
4864 if (!kvm)
4865 return ERR_PTR(-ENOMEM);
4866
f05e70ac 4867 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4868 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4869
5550af4d
SY		 4870 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4871 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4872
53f658b3
MT		 4873 rdtscll(kvm->arch.vm_init_tsc);
4874
d19a9cd2
ZX		 4875 return kvm;
4876}
4877
4878static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4879{
4880 vcpu_load(vcpu);
4881 kvm_mmu_unload(vcpu);
4882 vcpu_put(vcpu);
4883}
4884
4885static void kvm_free_vcpus(struct kvm *kvm)
4886{
4887 unsigned int i;
988a2cae 4888 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4889
4890 /*
4891 * Unpin any mmu pages first.
4892 */
988a2cae
GN		 4893 kvm_for_each_vcpu(i, vcpu, kvm)
4894 kvm_unload_vcpu_mmu(vcpu);
4895 kvm_for_each_vcpu(i, vcpu, kvm)
4896 kvm_arch_vcpu_free(vcpu);
4897
4898 mutex_lock(&kvm->lock);
4899 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4900 kvm->vcpus[i] = NULL;
d19a9cd2 4901
988a2cae
GN		 4902 atomic_set(&kvm->online_vcpus, 0);
4903 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4904}
4905
ad8ba2cd
SY		 4906void kvm_arch_sync_events(struct kvm *kvm)
4907{
ba4cef31 4908 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4909}
4910
d19a9cd2
ZX		 4911void kvm_arch_destroy_vm(struct kvm *kvm)
4912{
6eb55818 4913 kvm_iommu_unmap_guest(kvm);
7837699f 4914 kvm_free_pit(kvm);
d7deeeb0
ZX		 4915 kfree(kvm->arch.vpic);
4916 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4917 kvm_free_vcpus(kvm);
4918 kvm_free_physmem(kvm);
3d45830c
AK		 4919 if (kvm->arch.apic_access_page)
4920 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4921 if (kvm->arch.ept_identity_pagetable)
4922 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4923 kfree(kvm);
4924}
0de10343
ZX		 4925
4926int kvm_arch_set_memory_region(struct kvm *kvm,
4927 struct kvm_userspace_memory_region *mem,
4928 struct kvm_memory_slot old,
4929 int user_alloc)
4930{
4931 int npages = mem->memory_size >> PAGE_SHIFT;
4932 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4933
4934 /*To keep backward compatibility with older userspace,
4935 *x86 needs to hanlde !user_alloc case.
4936 */
4937 if (!user_alloc) {
4938 if (npages && !old.rmap) {
604b38ac
AA		 4939 unsigned long userspace_addr;
4940
72dc67a6 4941 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4942 userspace_addr = do_mmap(NULL, 0,
4943 npages * PAGE_SIZE,
4944 PROT_READ | PROT_WRITE,
acee3c04 4945 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4946 0);
72dc67a6 4947 up_write(&current->mm->mmap_sem);
0de10343 4948
604b38ac
AA		 4949 if (IS_ERR((void *)userspace_addr))
4950 return PTR_ERR((void *)userspace_addr);
4951
4952 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4953 spin_lock(&kvm->mmu_lock);
4954 memslot->userspace_addr = userspace_addr;
4955 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4956 } else {
4957 if (!old.user_alloc && old.rmap) {
4958 int ret;
4959
72dc67a6 4960 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4961 ret = do_munmap(current->mm, old.userspace_addr,
4962 old.npages * PAGE_SIZE);
72dc67a6 4963 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4964 if (ret < 0)
4965 printk(KERN_WARNING
4966 "kvm_vm_ioctl_set_memory_region: "
4967 "failed to munmap memory\n");
4968 }
4969 }
4970 }
4971
7c8a83b7 4972 spin_lock(&kvm->mmu_lock);
f05e70ac 4973 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4974 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4975 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4976 }
4977
4978 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4979 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4980
4981 return 0;
4982}
1d737c8a 4983
34d4cb8f
MT		 4984void kvm_arch_flush_shadow(struct kvm *kvm)
4985{
4986 kvm_mmu_zap_all(kvm);
8986ecc0 4987 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4988}
4989
1d737c8a
ZX		 4990int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4991{
a4535290 4992 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 4993 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4994 || vcpu->arch.nmi_pending ||
4995 (kvm_arch_interrupt_allowed(vcpu) &&
4996 kvm_cpu_has_interrupt(vcpu));
1d737c8a 4997}
5736199a 4998
5736199a
ZX		 4999void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5000{
32f88400
MT		 5001 int me;
5002 int cpu = vcpu->cpu;
5736199a
ZX		 5003
5004 if (waitqueue_active(&vcpu->wq)) {
5005 wake_up_interruptible(&vcpu->wq);
5006 ++vcpu->stat.halt_wakeup;
5007 }
32f88400
MT		 5008
5009 me = get_cpu();
5010 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5011 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5012 smp_send_reschedule(cpu);
e9571ed5 5013 put_cpu();
5736199a 5014}
78646121
GN		 5015
5016int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5017{
5018 return kvm_x86_ops->interrupt_allowed(vcpu);
5019}
229456fc 5020
94fe45da
JK		 5021unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5022{
5023 unsigned long rflags;
5024
5025 rflags = kvm_x86_ops->get_rflags(vcpu);
5026 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5027 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5028 return rflags;
5029}
5030EXPORT_SYMBOL_GPL(kvm_get_rflags);
5031
5032void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5033{
5034 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5035 vcpu->arch.singlestep_cs ==
5036 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5037 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5038 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5039 kvm_x86_ops->set_rflags(vcpu, rflags);
5040}
5041EXPORT_SYMBOL_GPL(kvm_set_rflags);
5042
229456fc
MT		 5043EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5044EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5045EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5046EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5047EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5048EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5049EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5050EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5051EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5052EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5053EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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