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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
aec51dc4
AK		 42#include <trace/events/kvm.h>
43#undef TRACE_INCLUDE_FILE
229456fc
MT		 44#define CREATE_TRACE_POINTS
45#include "trace.h"
043405e1 46
24f1e32c 47#include <asm/debugreg.h>
043405e1 48#include <asm/uaccess.h>
d825ed0a 49#include <asm/msr.h>
a5f61300 50#include <asm/desc.h>
0bed3b56 51#include <asm/mtrr.h>
890ca9ae 52#include <asm/mce.h>
043405e1 53
313a3dc7 54#define MAX_IO_MSRS 256
a03490ed
CO		 55#define CR0_RESERVED_BITS \
56 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
57 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
58 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
59#define CR4_RESERVED_BITS \
60 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
61 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
62 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
63 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
64
65#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 66
67#define KVM_MAX_MCE_BANKS 32
68#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
69
50a37eb4
JR		 70/* EFER defaults:
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
73 */
74#ifdef CONFIG_X86_64
75static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
76#else
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
18863bdd
AK		 93#define KVM_NR_SHARED_MSRS 16
94
95struct kvm_shared_msrs_global {
96 int nr;
2bf78fa7 97 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 98};
99
100struct kvm_shared_msrs {
101 struct user_return_notifier urn;
102 bool registered;
2bf78fa7
SY		 103 struct kvm_shared_msr_values {
104 u64 host;
105 u64 curr;
106 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
110static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
111
417bc304 112struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 113 { "pf_fixed", VCPU_STAT(pf_fixed) },
114 { "pf_guest", VCPU_STAT(pf_guest) },
115 { "tlb_flush", VCPU_STAT(tlb_flush) },
116 { "invlpg", VCPU_STAT(invlpg) },
117 { "exits", VCPU_STAT(exits) },
118 { "io_exits", VCPU_STAT(io_exits) },
119 { "mmio_exits", VCPU_STAT(mmio_exits) },
120 { "signal_exits", VCPU_STAT(signal_exits) },
121 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 122 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 123 { "halt_exits", VCPU_STAT(halt_exits) },
124 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 125 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 126 { "request_irq", VCPU_STAT(request_irq_exits) },
127 { "irq_exits", VCPU_STAT(irq_exits) },
128 { "host_state_reload", VCPU_STAT(host_state_reload) },
129 { "efer_reload", VCPU_STAT(efer_reload) },
130 { "fpu_reload", VCPU_STAT(fpu_reload) },
131 { "insn_emulation", VCPU_STAT(insn_emulation) },
132 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 133 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 134 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 135 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
136 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
137 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
138 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
139 { "mmu_flooded", VM_STAT(mmu_flooded) },
140 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 141 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 142 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 143 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 144 { "largepages", VM_STAT(lpages) },
417bc304
HB		 145 { NULL }
146};
147
18863bdd
AK		 148static void kvm_on_user_return(struct user_return_notifier *urn)
149{
150 unsigned slot;
18863bdd
AK		 151 struct kvm_shared_msrs *locals
152 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 153 struct kvm_shared_msr_values *values;
18863bdd
AK		 154
155 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 156 values = &locals->values[slot];
157 if (values->host != values->curr) {
158 wrmsrl(shared_msrs_global.msrs[slot], values->host);
159 values->curr = values->host;
18863bdd
AK		 160 }
161 }
162 locals->registered = false;
163 user_return_notifier_unregister(urn);
164}
165
2bf78fa7 166static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 167{
2bf78fa7 168 struct kvm_shared_msrs *smsr;
18863bdd
AK		 169 u64 value;
170
2bf78fa7
SY		 171 smsr = &__get_cpu_var(shared_msrs);
172 /* only read, and nobody should modify it at this time,
173 * so don't need lock */
174 if (slot >= shared_msrs_global.nr) {
175 printk(KERN_ERR "kvm: invalid MSR slot!");
176 return;
177 }
178 rdmsrl_safe(msr, &value);
179 smsr->values[slot].host = value;
180 smsr->values[slot].curr = value;
181}
182
183void kvm_define_shared_msr(unsigned slot, u32 msr)
184{
18863bdd
AK		 185 if (slot >= shared_msrs_global.nr)
186 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 187 shared_msrs_global.msrs[slot] = msr;
188 /* we need ensured the shared_msr_global have been updated */
189 smp_wmb();
18863bdd
AK		 190}
191EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
192
193static void kvm_shared_msr_cpu_online(void)
194{
195 unsigned i;
18863bdd
AK		 196
197 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 198 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 199}
200
d5696725 201void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 202{
203 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
204
2bf78fa7 205 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 206 return;
2bf78fa7
SY		 207 smsr->values[slot].curr = value;
208 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 209 if (!smsr->registered) {
210 smsr->urn.on_user_return = kvm_on_user_return;
211 user_return_notifier_register(&smsr->urn);
212 smsr->registered = true;
213 }
214}
215EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
216
3548bab5
AK		 217static void drop_user_return_notifiers(void *ignore)
218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
221 if (smsr->registered)
222 kvm_on_user_return(&smsr->urn);
223}
224
5fb76f9b
CO		 225unsigned long segment_base(u16 selector)
226{
227 struct descriptor_table gdt;
a5f61300 228 struct desc_struct *d;
5fb76f9b
CO		 229 unsigned long table_base;
230 unsigned long v;
231
232 if (selector == 0)
233 return 0;
234
b792c344 235 kvm_get_gdt(&gdt);
5fb76f9b
CO		 236 table_base = gdt.base;
237
238 if (selector & 4) { /* from ldt */
b792c344 239 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 240
5fb76f9b
CO		 241 table_base = segment_base(ldt_selector);
242 }
a5f61300 243 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 244 v = get_desc_base(d);
5fb76f9b 245#ifdef CONFIG_X86_64
a5f61300
AK		 246 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
247 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 248#endif
249 return v;
250}
251EXPORT_SYMBOL_GPL(segment_base);
252
6866b83e
CO		 253u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254{
255 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 256 return vcpu->arch.apic_base;
6866b83e 257 else
ad312c7c 258 return vcpu->arch.apic_base;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
262void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
263{
264 /* TODO: reserve bits check */
265 if (irqchip_in_kernel(vcpu->kvm))
266 kvm_lapic_set_base(vcpu, data);
267 else
ad312c7c 268 vcpu->arch.apic_base = data;
6866b83e
CO		 269}
270EXPORT_SYMBOL_GPL(kvm_set_apic_base);
271
3fd28fce
ED		 272#define EXCPT_BENIGN 0
273#define EXCPT_CONTRIBUTORY 1
274#define EXCPT_PF 2
275
276static int exception_class(int vector)
277{
278 switch (vector) {
279 case PF_VECTOR:
280 return EXCPT_PF;
281 case DE_VECTOR:
282 case TS_VECTOR:
283 case NP_VECTOR:
284 case SS_VECTOR:
285 case GP_VECTOR:
286 return EXCPT_CONTRIBUTORY;
287 default:
288 break;
289 }
290 return EXCPT_BENIGN;
291}
292
293static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
294 unsigned nr, bool has_error, u32 error_code)
295{
296 u32 prev_nr;
297 int class1, class2;
298
299 if (!vcpu->arch.exception.pending) {
300 queue:
301 vcpu->arch.exception.pending = true;
302 vcpu->arch.exception.has_error_code = has_error;
303 vcpu->arch.exception.nr = nr;
304 vcpu->arch.exception.error_code = error_code;
305 return;
306 }
307
308 /* to check exception */
309 prev_nr = vcpu->arch.exception.nr;
310 if (prev_nr == DF_VECTOR) {
311 /* triple fault -> shutdown */
312 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
313 return;
314 }
315 class1 = exception_class(prev_nr);
316 class2 = exception_class(nr);
317 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
318 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
319 /* generate double fault per SDM Table 5-5 */
320 vcpu->arch.exception.pending = true;
321 vcpu->arch.exception.has_error_code = true;
322 vcpu->arch.exception.nr = DF_VECTOR;
323 vcpu->arch.exception.error_code = 0;
324 } else
325 /* replace previous exception with a new one in a hope
326 that instruction re-execution will regenerate lost
327 exception */
328 goto queue;
329}
330
298101da
AK		 331void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
3fd28fce 333 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 334}
335EXPORT_SYMBOL_GPL(kvm_queue_exception);
336
c3c91fee
AK		 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
338 u32 error_code)
339{
340 ++vcpu->stat.pf_guest;
ad312c7c 341 vcpu->arch.cr2 = addr;
c3c91fee
AK		 342 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
343}
344
3419ffc8
SY		 345void kvm_inject_nmi(struct kvm_vcpu *vcpu)
346{
347 vcpu->arch.nmi_pending = 1;
348}
349EXPORT_SYMBOL_GPL(kvm_inject_nmi);
350
298101da
AK		 351void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
352{
3fd28fce 353 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 354}
355EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
356
0a79b009
AK		 357/*
358 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
359 * a #GP and return false.
360 */
361bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 362{
0a79b009
AK		 363 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
364 return true;
365 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
366 return false;
298101da 367}
0a79b009 368EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 369
a03490ed
CO		 370/*
371 * Load the pae pdptrs. Return true is they are all valid.
372 */
373int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
374{
375 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
376 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
377 int i;
378 int ret;
ad312c7c 379 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 380
a03490ed
CO		 381 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
382 offset * sizeof(u64), sizeof(pdpte));
383 if (ret < 0) {
384 ret = 0;
385 goto out;
386 }
387 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 388 if (is_present_gpte(pdpte[i]) &&
20c466b5 389 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 390 ret = 0;
391 goto out;
392 }
393 }
394 ret = 1;
395
ad312c7c 396 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 397 __set_bit(VCPU_EXREG_PDPTR,
398 (unsigned long *)&vcpu->arch.regs_avail);
399 __set_bit(VCPU_EXREG_PDPTR,
400 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 401out:
a03490ed
CO		 402
403 return ret;
404}
cc4b6871 405EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 406
d835dfec
AK		 407static bool pdptrs_changed(struct kvm_vcpu *vcpu)
408{
ad312c7c 409 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 410 bool changed = true;
411 int r;
412
413 if (is_long_mode(vcpu) || !is_pae(vcpu))
414 return false;
415
6de4f3ad
AK		 416 if (!test_bit(VCPU_EXREG_PDPTR,
417 (unsigned long *)&vcpu->arch.regs_avail))
418 return true;
419
ad312c7c 420 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 421 if (r < 0)
422 goto out;
ad312c7c 423 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 424out:
d835dfec
AK		 425
426 return changed;
427}
428
2d3ad1f4 429void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 430{
f9a48e6a
AK		 431 cr0 |= X86_CR0_ET;
432
ab344828
GN		 433#ifdef CONFIG_X86_64
434 if (cr0 & 0xffffffff00000000UL) {
a03490ed 435 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
4d4ec087 436 cr0, kvm_read_cr0(vcpu));
c1a5d4f9 437 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 438 return;
439 }
ab344828
GN		 440#endif
441
442 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 443
444 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
445 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 446 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 447 return;
448 }
449
450 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
451 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
452 "and a clear PE flag\n");
c1a5d4f9 453 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 454 return;
455 }
456
457 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
458#ifdef CONFIG_X86_64
f6801dff 459 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 460 int cs_db, cs_l;
461
462 if (!is_pae(vcpu)) {
463 printk(KERN_DEBUG "set_cr0: #GP, start paging "
464 "in long mode while PAE is disabled\n");
c1a5d4f9 465 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 466 return;
467 }
468 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
469 if (cs_l) {
470 printk(KERN_DEBUG "set_cr0: #GP, start paging "
471 "in long mode while CS.L == 1\n");
c1a5d4f9 472 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 473 return;
474
475 }
476 } else
477#endif
ad312c7c 478 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 479 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
480 "reserved bits\n");
c1a5d4f9 481 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 482 return;
483 }
484
485 }
486
487 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 488 vcpu->arch.cr0 = cr0;
a03490ed 489
a03490ed 490 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 491 return;
492}
2d3ad1f4 493EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 494
2d3ad1f4 495void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 496{
4d4ec087 497 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 498}
2d3ad1f4 499EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 500
2d3ad1f4 501void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 502{
fc78f519 503 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 504 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
505
a03490ed
CO		 506 if (cr4 & CR4_RESERVED_BITS) {
507 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 508 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 509 return;
510 }
511
512 if (is_long_mode(vcpu)) {
513 if (!(cr4 & X86_CR4_PAE)) {
514 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
515 "in long mode\n");
c1a5d4f9 516 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 517 return;
518 }
a2edf57f
AK		 519 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
520 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 521 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 522 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 523 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 524 return;
525 }
526
527 if (cr4 & X86_CR4_VMXE) {
528 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 529 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 530 return;
531 }
532 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 533 vcpu->arch.cr4 = cr4;
5a41accd 534 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 535 kvm_mmu_reset_context(vcpu);
a03490ed 536}
2d3ad1f4 537EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 538
2d3ad1f4 539void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 540{
ad312c7c 541 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 542 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 543 kvm_mmu_flush_tlb(vcpu);
544 return;
545 }
546
a03490ed
CO		 547 if (is_long_mode(vcpu)) {
548 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
549 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 550 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 551 return;
552 }
553 } else {
554 if (is_pae(vcpu)) {
555 if (cr3 & CR3_PAE_RESERVED_BITS) {
556 printk(KERN_DEBUG
557 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 558 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 559 return;
560 }
561 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
562 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
563 "reserved bits\n");
c1a5d4f9 564 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 565 return;
566 }
567 }
568 /*
569 * We don't check reserved bits in nonpae mode, because
570 * this isn't enforced, and VMware depends on this.
571 */
572 }
573
a03490ed
CO		 574 /*
575 * Does the new cr3 value map to physical memory? (Note, we
576 * catch an invalid cr3 even in real-mode, because it would
577 * cause trouble later on when we turn on paging anyway.)
578 *
579 * A real CPU would silently accept an invalid cr3 and would
580 * attempt to use it - with largely undefined (and often hard
581 * to debug) behavior on the guest side.
582 */
583 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 584 kvm_inject_gp(vcpu, 0);
a03490ed 585 else {
ad312c7c
ZX		 586 vcpu->arch.cr3 = cr3;
587 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 588 }
a03490ed 589}
2d3ad1f4 590EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 591
2d3ad1f4 592void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 593{
594 if (cr8 & CR8_RESERVED_BITS) {
595 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 596 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 597 return;
598 }
599 if (irqchip_in_kernel(vcpu->kvm))
600 kvm_lapic_set_tpr(vcpu, cr8);
601 else
ad312c7c 602 vcpu->arch.cr8 = cr8;
a03490ed 603}
2d3ad1f4 604EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 605
2d3ad1f4 606unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 607{
608 if (irqchip_in_kernel(vcpu->kvm))
609 return kvm_lapic_get_cr8(vcpu);
610 else
ad312c7c 611 return vcpu->arch.cr8;
a03490ed 612}
2d3ad1f4 613EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 614
d8017474
AG		 615static inline u32 bit(int bitno)
616{
617 return 1 << (bitno & 31);
618}
619
043405e1
CO		 620/*
621 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
622 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
623 *
624 * This list is modified at module load time to reflect the
e3267cbb
GC		 625 * capabilities of the host cpu. This capabilities test skips MSRs that are
626 * kvm-specific. Those are put in the beginning of the list.
043405e1 627 */
e3267cbb 628
10388a07 629#define KVM_SAVE_MSRS_BEGIN 5
043405e1 630static u32 msrs_to_save[] = {
e3267cbb 631 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 632 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 633 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 634 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
635 MSR_K6_STAR,
636#ifdef CONFIG_X86_64
637 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
638#endif
e3267cbb 639 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 640};
641
642static unsigned num_msrs_to_save;
643
644static u32 emulated_msrs[] = {
645 MSR_IA32_MISC_ENABLE,
646};
647
15c4a640
CO		 648static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
649{
f2b4b7dd 650 if (efer & efer_reserved_bits) {
15c4a640
CO		 651 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
652 efer);
c1a5d4f9 653 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 654 return;
655 }
656
657 if (is_paging(vcpu)
f6801dff 658 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 659 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 660 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 661 return;
662 }
663
1b2fd70c
AG		 664 if (efer & EFER_FFXSR) {
665 struct kvm_cpuid_entry2 *feat;
666
667 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
668 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
669 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
670 kvm_inject_gp(vcpu, 0);
671 return;
672 }
673 }
674
d8017474
AG		 675 if (efer & EFER_SVME) {
676 struct kvm_cpuid_entry2 *feat;
677
678 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
679 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
680 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
681 kvm_inject_gp(vcpu, 0);
682 return;
683 }
684 }
685
15c4a640
CO		 686 kvm_x86_ops->set_efer(vcpu, efer);
687
688 efer &= ~EFER_LMA;
f6801dff 689 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 690
f6801dff 691 vcpu->arch.efer = efer;
9645bb56
AK		 692
693 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
694 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 695}
696
f2b4b7dd
JR		 697void kvm_enable_efer_bits(u64 mask)
698{
699 efer_reserved_bits &= ~mask;
700}
701EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
702
703
15c4a640
CO		 704/*
705 * Writes msr value into into the appropriate "register".
706 * Returns 0 on success, non-0 otherwise.
707 * Assumes vcpu_load() was already called.
708 */
709int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
710{
711 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
712}
713
313a3dc7
CO		 714/*
715 * Adapt set_msr() to msr_io()'s calling convention
716 */
717static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
718{
719 return kvm_set_msr(vcpu, index, *data);
720}
721
18068523
GOC		 722static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
723{
724 static int version;
50d0a0f9 725 struct pvclock_wall_clock wc;
923de3cf 726 struct timespec boot;
18068523
GOC		 727
728 if (!wall_clock)
729 return;
730
731 version++;
732
18068523
GOC		 733 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
734
50d0a0f9
GH		 735 /*
736 * The guest calculates current wall clock time by adding
737 * system time (updated by kvm_write_guest_time below) to the
738 * wall clock specified here. guest system time equals host
739 * system time for us, thus we must fill in host boot time here.
740 */
923de3cf 741 getboottime(&boot);
50d0a0f9
GH		 742
743 wc.sec = boot.tv_sec;
744 wc.nsec = boot.tv_nsec;
745 wc.version = version;
18068523
GOC		 746
747 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
748
749 version++;
750 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 751}
752
50d0a0f9
GH		 753static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
754{
755 uint32_t quotient, remainder;
756
757 /* Don't try to replace with do_div(), this one calculates
758 * "(dividend << 32) / divisor" */
759 __asm__ ( "divl %4"
760 : "=a" (quotient), "=d" (remainder)
761 : "0" (0), "1" (dividend), "r" (divisor) );
762 return quotient;
763}
764
765static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
766{
767 uint64_t nsecs = 1000000000LL;
768 int32_t shift = 0;
769 uint64_t tps64;
770 uint32_t tps32;
771
772 tps64 = tsc_khz * 1000LL;
773 while (tps64 > nsecs*2) {
774 tps64 >>= 1;
775 shift--;
776 }
777
778 tps32 = (uint32_t)tps64;
779 while (tps32 <= (uint32_t)nsecs) {
780 tps32 <<= 1;
781 shift++;
782 }
783
784 hv_clock->tsc_shift = shift;
785 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
786
787 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 788 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 789 hv_clock->tsc_to_system_mul);
790}
791
c8076604
GH		 792static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
793
18068523
GOC		 794static void kvm_write_guest_time(struct kvm_vcpu *v)
795{
796 struct timespec ts;
797 unsigned long flags;
798 struct kvm_vcpu_arch *vcpu = &v->arch;
799 void *shared_kaddr;
463656c0 800 unsigned long this_tsc_khz;
18068523
GOC		 801
802 if ((!vcpu->time_page))
803 return;
804
463656c0
AK		 805 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
806 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
807 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
808 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 809 }
463656c0 810 put_cpu_var(cpu_tsc_khz);
50d0a0f9 811
18068523
GOC		 812 /* Keep irq disabled to prevent changes to the clock */
813 local_irq_save(flags);
af24a4e4 814 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 815 ktime_get_ts(&ts);
923de3cf 816 monotonic_to_bootbased(&ts);
18068523
GOC		 817 local_irq_restore(flags);
818
819 /* With all the info we got, fill in the values */
820
821 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 822 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
823
18068523
GOC		 824 /*
825 * The interface expects us to write an even number signaling that the
826 * update is finished. Since the guest won't see the intermediate
50d0a0f9 827 * state, we just increase by 2 at the end.
18068523 828 */
50d0a0f9 829 vcpu->hv_clock.version += 2;
18068523
GOC		 830
831 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
832
833 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 834 sizeof(vcpu->hv_clock));
18068523
GOC		 835
836 kunmap_atomic(shared_kaddr, KM_USER0);
837
838 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
839}
840
c8076604
GH		 841static int kvm_request_guest_time_update(struct kvm_vcpu *v)
842{
843 struct kvm_vcpu_arch *vcpu = &v->arch;
844
845 if (!vcpu->time_page)
846 return 0;
847 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
848 return 1;
849}
850
9ba075a6
AK		 851static bool msr_mtrr_valid(unsigned msr)
852{
853 switch (msr) {
854 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
855 case MSR_MTRRfix64K_00000:
856 case MSR_MTRRfix16K_80000:
857 case MSR_MTRRfix16K_A0000:
858 case MSR_MTRRfix4K_C0000:
859 case MSR_MTRRfix4K_C8000:
860 case MSR_MTRRfix4K_D0000:
861 case MSR_MTRRfix4K_D8000:
862 case MSR_MTRRfix4K_E0000:
863 case MSR_MTRRfix4K_E8000:
864 case MSR_MTRRfix4K_F0000:
865 case MSR_MTRRfix4K_F8000:
866 case MSR_MTRRdefType:
867 case MSR_IA32_CR_PAT:
868 return true;
869 case 0x2f8:
870 return true;
871 }
872 return false;
873}
874
d6289b93
MT		 875static bool valid_pat_type(unsigned t)
876{
877 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
878}
879
880static bool valid_mtrr_type(unsigned t)
881{
882 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
883}
884
885static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
886{
887 int i;
888
889 if (!msr_mtrr_valid(msr))
890 return false;
891
892 if (msr == MSR_IA32_CR_PAT) {
893 for (i = 0; i < 8; i++)
894 if (!valid_pat_type((data >> (i * 8)) & 0xff))
895 return false;
896 return true;
897 } else if (msr == MSR_MTRRdefType) {
898 if (data & ~0xcff)
899 return false;
900 return valid_mtrr_type(data & 0xff);
901 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
902 for (i = 0; i < 8 ; i++)
903 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
904 return false;
905 return true;
906 }
907
908 /* variable MTRRs */
909 return valid_mtrr_type(data & 0xff);
910}
911
9ba075a6
AK		 912static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
913{
0bed3b56
SY		 914 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
915
d6289b93 916 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 917 return 1;
918
0bed3b56
SY		 919 if (msr == MSR_MTRRdefType) {
920 vcpu->arch.mtrr_state.def_type = data;
921 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
922 } else if (msr == MSR_MTRRfix64K_00000)
923 p[0] = data;
924 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
925 p[1 + msr - MSR_MTRRfix16K_80000] = data;
926 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
927 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
928 else if (msr == MSR_IA32_CR_PAT)
929 vcpu->arch.pat = data;
930 else { /* Variable MTRRs */
931 int idx, is_mtrr_mask;
932 u64 *pt;
933
934 idx = (msr - 0x200) / 2;
935 is_mtrr_mask = msr - 0x200 - 2 * idx;
936 if (!is_mtrr_mask)
937 pt =
938 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
939 else
940 pt =
941 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
942 *pt = data;
943 }
944
945 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 946 return 0;
947}
15c4a640 948
890ca9ae 949static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 950{
890ca9ae
HY		 951 u64 mcg_cap = vcpu->arch.mcg_cap;
952 unsigned bank_num = mcg_cap & 0xff;
953
15c4a640 954 switch (msr) {
15c4a640 955 case MSR_IA32_MCG_STATUS:
890ca9ae 956 vcpu->arch.mcg_status = data;
15c4a640 957 break;
c7ac679c 958 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 959 if (!(mcg_cap & MCG_CTL_P))
960 return 1;
961 if (data != 0 && data != ~(u64)0)
962 return -1;
963 vcpu->arch.mcg_ctl = data;
964 break;
965 default:
966 if (msr >= MSR_IA32_MC0_CTL &&
967 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
968 u32 offset = msr - MSR_IA32_MC0_CTL;
969 /* only 0 or all 1s can be written to IA32_MCi_CTL */
970 if ((offset & 0x3) == 0 &&
971 data != 0 && data != ~(u64)0)
972 return -1;
973 vcpu->arch.mce_banks[offset] = data;
974 break;
975 }
976 return 1;
977 }
978 return 0;
979}
980
ffde22ac
ES		 981static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
982{
983 struct kvm *kvm = vcpu->kvm;
984 int lm = is_long_mode(vcpu);
985 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
986 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
987 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
988 : kvm->arch.xen_hvm_config.blob_size_32;
989 u32 page_num = data & ~PAGE_MASK;
990 u64 page_addr = data & PAGE_MASK;
991 u8 *page;
992 int r;
993
994 r = -E2BIG;
995 if (page_num >= blob_size)
996 goto out;
997 r = -ENOMEM;
998 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
999 if (!page)
1000 goto out;
1001 r = -EFAULT;
1002 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1003 goto out_free;
1004 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1005 goto out_free;
1006 r = 0;
1007out_free:
1008 kfree(page);
1009out:
1010 return r;
1011}
1012
55cd8e5a
GN		 1013static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1014{
1015 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1016}
1017
1018static bool kvm_hv_msr_partition_wide(u32 msr)
1019{
1020 bool r = false;
1021 switch (msr) {
1022 case HV_X64_MSR_GUEST_OS_ID:
1023 case HV_X64_MSR_HYPERCALL:
1024 r = true;
1025 break;
1026 }
1027
1028 return r;
1029}
1030
1031static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1032{
1033 struct kvm *kvm = vcpu->kvm;
1034
1035 switch (msr) {
1036 case HV_X64_MSR_GUEST_OS_ID:
1037 kvm->arch.hv_guest_os_id = data;
1038 /* setting guest os id to zero disables hypercall page */
1039 if (!kvm->arch.hv_guest_os_id)
1040 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1041 break;
1042 case HV_X64_MSR_HYPERCALL: {
1043 u64 gfn;
1044 unsigned long addr;
1045 u8 instructions[4];
1046
1047 /* if guest os id is not set hypercall should remain disabled */
1048 if (!kvm->arch.hv_guest_os_id)
1049 break;
1050 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1051 kvm->arch.hv_hypercall = data;
1052 break;
1053 }
1054 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1055 addr = gfn_to_hva(kvm, gfn);
1056 if (kvm_is_error_hva(addr))
1057 return 1;
1058 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1059 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1060 if (copy_to_user((void __user *)addr, instructions, 4))
1061 return 1;
1062 kvm->arch.hv_hypercall = data;
1063 break;
1064 }
1065 default:
1066 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1067 "data 0x%llx\n", msr, data);
1068 return 1;
1069 }
1070 return 0;
1071}
1072
1073static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1074{
10388a07
GN		 1075 switch (msr) {
1076 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1077 unsigned long addr;
55cd8e5a 1078
10388a07
GN		 1079 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1080 vcpu->arch.hv_vapic = data;
1081 break;
1082 }
1083 addr = gfn_to_hva(vcpu->kvm, data >>
1084 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1085 if (kvm_is_error_hva(addr))
1086 return 1;
1087 if (clear_user((void __user *)addr, PAGE_SIZE))
1088 return 1;
1089 vcpu->arch.hv_vapic = data;
1090 break;
1091 }
1092 case HV_X64_MSR_EOI:
1093 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1094 case HV_X64_MSR_ICR:
1095 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1096 case HV_X64_MSR_TPR:
1097 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1098 default:
1099 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1100 "data 0x%llx\n", msr, data);
1101 return 1;
1102 }
1103
1104 return 0;
55cd8e5a
GN		 1105}
1106
15c4a640
CO		 1107int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1108{
1109 switch (msr) {
15c4a640
CO		 1110 case MSR_EFER:
1111 set_efer(vcpu, data);
1112 break;
8f1589d9
AP		 1113 case MSR_K7_HWCR:
1114 data &= ~(u64)0x40; /* ignore flush filter disable */
1115 if (data != 0) {
1116 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1117 data);
1118 return 1;
1119 }
15c4a640 1120 break;
f7c6d140
AP		 1121 case MSR_FAM10H_MMIO_CONF_BASE:
1122 if (data != 0) {
1123 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1124 "0x%llx\n", data);
1125 return 1;
1126 }
15c4a640 1127 break;
c323c0e5 1128 case MSR_AMD64_NB_CFG:
c7ac679c 1129 break;
b5e2fec0
AG		 1130 case MSR_IA32_DEBUGCTLMSR:
1131 if (!data) {
1132 /* We support the non-activated case already */
1133 break;
1134 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1135 /* Values other than LBR and BTF are vendor-specific,
1136 thus reserved and should throw a #GP */
1137 return 1;
1138 }
1139 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1140 __func__, data);
1141 break;
15c4a640
CO		 1142 case MSR_IA32_UCODE_REV:
1143 case MSR_IA32_UCODE_WRITE:
61a6bd67 1144 case MSR_VM_HSAVE_PA:
6098ca93 1145 case MSR_AMD64_PATCH_LOADER:
15c4a640 1146 break;
9ba075a6
AK		 1147 case 0x200 ... 0x2ff:
1148 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1149 case MSR_IA32_APICBASE:
1150 kvm_set_apic_base(vcpu, data);
1151 break;
0105d1a5
GN		 1152 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1153 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1154 case MSR_IA32_MISC_ENABLE:
ad312c7c 1155 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1156 break;
18068523
GOC		 1157 case MSR_KVM_WALL_CLOCK:
1158 vcpu->kvm->arch.wall_clock = data;
1159 kvm_write_wall_clock(vcpu->kvm, data);
1160 break;
1161 case MSR_KVM_SYSTEM_TIME: {
1162 if (vcpu->arch.time_page) {
1163 kvm_release_page_dirty(vcpu->arch.time_page);
1164 vcpu->arch.time_page = NULL;
1165 }
1166
1167 vcpu->arch.time = data;
1168
1169 /* we verify if the enable bit is set... */
1170 if (!(data & 1))
1171 break;
1172
1173 /* ...but clean it before doing the actual write */
1174 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1175
18068523
GOC		 1176 vcpu->arch.time_page =
1177 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1178
1179 if (is_error_page(vcpu->arch.time_page)) {
1180 kvm_release_page_clean(vcpu->arch.time_page);
1181 vcpu->arch.time_page = NULL;
1182 }
1183
c8076604 1184 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1185 break;
1186 }
890ca9ae
HY		 1187 case MSR_IA32_MCG_CTL:
1188 case MSR_IA32_MCG_STATUS:
1189 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1190 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1191
1192 /* Performance counters are not protected by a CPUID bit,
1193 * so we should check all of them in the generic path for the sake of
1194 * cross vendor migration.
1195 * Writing a zero into the event select MSRs disables them,
1196 * which we perfectly emulate ;-). Any other value should be at least
1197 * reported, some guests depend on them.
1198 */
1199 case MSR_P6_EVNTSEL0:
1200 case MSR_P6_EVNTSEL1:
1201 case MSR_K7_EVNTSEL0:
1202 case MSR_K7_EVNTSEL1:
1203 case MSR_K7_EVNTSEL2:
1204 case MSR_K7_EVNTSEL3:
1205 if (data != 0)
1206 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1207 "0x%x data 0x%llx\n", msr, data);
1208 break;
1209 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1210 * so we ignore writes to make it happy.
1211 */
1212 case MSR_P6_PERFCTR0:
1213 case MSR_P6_PERFCTR1:
1214 case MSR_K7_PERFCTR0:
1215 case MSR_K7_PERFCTR1:
1216 case MSR_K7_PERFCTR2:
1217 case MSR_K7_PERFCTR3:
1218 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1219 "0x%x data 0x%llx\n", msr, data);
1220 break;
55cd8e5a
GN		 1221 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1222 if (kvm_hv_msr_partition_wide(msr)) {
1223 int r;
1224 mutex_lock(&vcpu->kvm->lock);
1225 r = set_msr_hyperv_pw(vcpu, msr, data);
1226 mutex_unlock(&vcpu->kvm->lock);
1227 return r;
1228 } else
1229 return set_msr_hyperv(vcpu, msr, data);
1230 break;
15c4a640 1231 default:
ffde22ac
ES		 1232 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1233 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1234 if (!ignore_msrs) {
1235 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1236 msr, data);
1237 return 1;
1238 } else {
1239 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1240 msr, data);
1241 break;
1242 }
15c4a640
CO		 1243 }
1244 return 0;
1245}
1246EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1247
1248
1249/*
1250 * Reads an msr value (of 'msr_index') into 'pdata'.
1251 * Returns 0 on success, non-0 otherwise.
1252 * Assumes vcpu_load() was already called.
1253 */
1254int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1255{
1256 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1257}
1258
9ba075a6
AK		 1259static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1260{
0bed3b56
SY		 1261 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1262
9ba075a6
AK		 1263 if (!msr_mtrr_valid(msr))
1264 return 1;
1265
0bed3b56
SY		 1266 if (msr == MSR_MTRRdefType)
1267 *pdata = vcpu->arch.mtrr_state.def_type +
1268 (vcpu->arch.mtrr_state.enabled << 10);
1269 else if (msr == MSR_MTRRfix64K_00000)
1270 *pdata = p[0];
1271 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1272 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1273 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1274 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1275 else if (msr == MSR_IA32_CR_PAT)
1276 *pdata = vcpu->arch.pat;
1277 else { /* Variable MTRRs */
1278 int idx, is_mtrr_mask;
1279 u64 *pt;
1280
1281 idx = (msr - 0x200) / 2;
1282 is_mtrr_mask = msr - 0x200 - 2 * idx;
1283 if (!is_mtrr_mask)
1284 pt =
1285 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1286 else
1287 pt =
1288 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1289 *pdata = *pt;
1290 }
1291
9ba075a6
AK		 1292 return 0;
1293}
1294
890ca9ae 1295static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1296{
1297 u64 data;
890ca9ae
HY		 1298 u64 mcg_cap = vcpu->arch.mcg_cap;
1299 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1300
1301 switch (msr) {
15c4a640
CO		 1302 case MSR_IA32_P5_MC_ADDR:
1303 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1304 data = 0;
1305 break;
15c4a640 1306 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1307 data = vcpu->arch.mcg_cap;
1308 break;
c7ac679c 1309 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1310 if (!(mcg_cap & MCG_CTL_P))
1311 return 1;
1312 data = vcpu->arch.mcg_ctl;
1313 break;
1314 case MSR_IA32_MCG_STATUS:
1315 data = vcpu->arch.mcg_status;
1316 break;
1317 default:
1318 if (msr >= MSR_IA32_MC0_CTL &&
1319 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1320 u32 offset = msr - MSR_IA32_MC0_CTL;
1321 data = vcpu->arch.mce_banks[offset];
1322 break;
1323 }
1324 return 1;
1325 }
1326 *pdata = data;
1327 return 0;
1328}
1329
55cd8e5a
GN		 1330static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1331{
1332 u64 data = 0;
1333 struct kvm *kvm = vcpu->kvm;
1334
1335 switch (msr) {
1336 case HV_X64_MSR_GUEST_OS_ID:
1337 data = kvm->arch.hv_guest_os_id;
1338 break;
1339 case HV_X64_MSR_HYPERCALL:
1340 data = kvm->arch.hv_hypercall;
1341 break;
1342 default:
1343 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1344 return 1;
1345 }
1346
1347 *pdata = data;
1348 return 0;
1349}
1350
1351static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1352{
1353 u64 data = 0;
1354
1355 switch (msr) {
1356 case HV_X64_MSR_VP_INDEX: {
1357 int r;
1358 struct kvm_vcpu *v;
1359 kvm_for_each_vcpu(r, v, vcpu->kvm)
1360 if (v == vcpu)
1361 data = r;
1362 break;
1363 }
10388a07
GN		 1364 case HV_X64_MSR_EOI:
1365 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1366 case HV_X64_MSR_ICR:
1367 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1368 case HV_X64_MSR_TPR:
1369 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1370 default:
1371 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1372 return 1;
1373 }
1374 *pdata = data;
1375 return 0;
1376}
1377
890ca9ae
HY		 1378int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1379{
1380 u64 data;
1381
1382 switch (msr) {
890ca9ae 1383 case MSR_IA32_PLATFORM_ID:
15c4a640 1384 case MSR_IA32_UCODE_REV:
15c4a640 1385 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1386 case MSR_IA32_DEBUGCTLMSR:
1387 case MSR_IA32_LASTBRANCHFROMIP:
1388 case MSR_IA32_LASTBRANCHTOIP:
1389 case MSR_IA32_LASTINTFROMIP:
1390 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1391 case MSR_K8_SYSCFG:
1392 case MSR_K7_HWCR:
61a6bd67 1393 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1394 case MSR_P6_PERFCTR0:
1395 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1396 case MSR_P6_EVNTSEL0:
1397 case MSR_P6_EVNTSEL1:
9e699624 1398 case MSR_K7_EVNTSEL0:
1f3ee616 1399 case MSR_K7_PERFCTR0:
1fdbd48c 1400 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1401 case MSR_AMD64_NB_CFG:
f7c6d140 1402 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1403 data = 0;
1404 break;
9ba075a6
AK		 1405 case MSR_MTRRcap:
1406 data = 0x500 | KVM_NR_VAR_MTRR;
1407 break;
1408 case 0x200 ... 0x2ff:
1409 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1410 case 0xcd: /* fsb frequency */
1411 data = 3;
1412 break;
1413 case MSR_IA32_APICBASE:
1414 data = kvm_get_apic_base(vcpu);
1415 break;
0105d1a5
GN		 1416 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1417 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1418 break;
15c4a640 1419 case MSR_IA32_MISC_ENABLE:
ad312c7c 1420 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1421 break;
847f0ad8
AG		 1422 case MSR_IA32_PERF_STATUS:
1423 /* TSC increment by tick */
1424 data = 1000ULL;
1425 /* CPU multiplier */
1426 data |= (((uint64_t)4ULL) << 40);
1427 break;
15c4a640 1428 case MSR_EFER:
f6801dff 1429 data = vcpu->arch.efer;
15c4a640 1430 break;
18068523
GOC		 1431 case MSR_KVM_WALL_CLOCK:
1432 data = vcpu->kvm->arch.wall_clock;
1433 break;
1434 case MSR_KVM_SYSTEM_TIME:
1435 data = vcpu->arch.time;
1436 break;
890ca9ae
HY		 1437 case MSR_IA32_P5_MC_ADDR:
1438 case MSR_IA32_P5_MC_TYPE:
1439 case MSR_IA32_MCG_CAP:
1440 case MSR_IA32_MCG_CTL:
1441 case MSR_IA32_MCG_STATUS:
1442 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1443 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1444 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1445 if (kvm_hv_msr_partition_wide(msr)) {
1446 int r;
1447 mutex_lock(&vcpu->kvm->lock);
1448 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1449 mutex_unlock(&vcpu->kvm->lock);
1450 return r;
1451 } else
1452 return get_msr_hyperv(vcpu, msr, pdata);
1453 break;
15c4a640 1454 default:
ed85c068
AP		 1455 if (!ignore_msrs) {
1456 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1457 return 1;
1458 } else {
1459 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1460 data = 0;
1461 }
1462 break;
15c4a640
CO		 1463 }
1464 *pdata = data;
1465 return 0;
1466}
1467EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1468
313a3dc7
CO		 1469/*
1470 * Read or write a bunch of msrs. All parameters are kernel addresses.
1471 *
1472 * @return number of msrs set successfully.
1473 */
1474static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1475 struct kvm_msr_entry *entries,
1476 int (*do_msr)(struct kvm_vcpu *vcpu,
1477 unsigned index, u64 *data))
1478{
f656ce01 1479 int i, idx;
313a3dc7
CO		 1480
1481 vcpu_load(vcpu);
1482
f656ce01 1483 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1484 for (i = 0; i < msrs->nmsrs; ++i)
1485 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1486 break;
f656ce01 1487 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1488
1489 vcpu_put(vcpu);
1490
1491 return i;
1492}
1493
1494/*
1495 * Read or write a bunch of msrs. Parameters are user addresses.
1496 *
1497 * @return number of msrs set successfully.
1498 */
1499static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1500 int (*do_msr)(struct kvm_vcpu *vcpu,
1501 unsigned index, u64 *data),
1502 int writeback)
1503{
1504 struct kvm_msrs msrs;
1505 struct kvm_msr_entry *entries;
1506 int r, n;
1507 unsigned size;
1508
1509 r = -EFAULT;
1510 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1511 goto out;
1512
1513 r = -E2BIG;
1514 if (msrs.nmsrs >= MAX_IO_MSRS)
1515 goto out;
1516
1517 r = -ENOMEM;
1518 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1519 entries = vmalloc(size);
1520 if (!entries)
1521 goto out;
1522
1523 r = -EFAULT;
1524 if (copy_from_user(entries, user_msrs->entries, size))
1525 goto out_free;
1526
1527 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1528 if (r < 0)
1529 goto out_free;
1530
1531 r = -EFAULT;
1532 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1533 goto out_free;
1534
1535 r = n;
1536
1537out_free:
1538 vfree(entries);
1539out:
1540 return r;
1541}
1542
018d00d2
ZX		 1543int kvm_dev_ioctl_check_extension(long ext)
1544{
1545 int r;
1546
1547 switch (ext) {
1548 case KVM_CAP_IRQCHIP:
1549 case KVM_CAP_HLT:
1550 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1551 case KVM_CAP_SET_TSS_ADDR:
07716717 1552 case KVM_CAP_EXT_CPUID:
c8076604 1553 case KVM_CAP_CLOCKSOURCE:
7837699f 1554 case KVM_CAP_PIT:
a28e4f5a 1555 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1556 case KVM_CAP_MP_STATE:
ed848624 1557 case KVM_CAP_SYNC_MMU:
52d939a0 1558 case KVM_CAP_REINJECT_CONTROL:
4925663a 1559 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1560 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1561 case KVM_CAP_IRQFD:
d34e6b17 1562 case KVM_CAP_IOEVENTFD:
c5ff41ce 1563 case KVM_CAP_PIT2:
e9f42757 1564 case KVM_CAP_PIT_STATE2:
b927a3ce 1565 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1566 case KVM_CAP_XEN_HVM:
afbcf7ab 1567 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1568 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1569 case KVM_CAP_HYPERV:
10388a07 1570 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1571 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1572 case KVM_CAP_PCI_SEGMENT:
d2be1651 1573 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1574 r = 1;
1575 break;
542472b5
LV		 1576 case KVM_CAP_COALESCED_MMIO:
1577 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1578 break;
774ead3a
AK		 1579 case KVM_CAP_VAPIC:
1580 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1581 break;
f725230a
AK		 1582 case KVM_CAP_NR_VCPUS:
1583 r = KVM_MAX_VCPUS;
1584 break;
a988b910
AK		 1585 case KVM_CAP_NR_MEMSLOTS:
1586 r = KVM_MEMORY_SLOTS;
1587 break;
a68a6a72
MT		 1588 case KVM_CAP_PV_MMU: /* obsolete */
1589 r = 0;
2f333bcb 1590 break;
62c476c7 1591 case KVM_CAP_IOMMU:
19de40a8 1592 r = iommu_found();
62c476c7 1593 break;
890ca9ae
HY		 1594 case KVM_CAP_MCE:
1595 r = KVM_MAX_MCE_BANKS;
1596 break;
018d00d2
ZX		 1597 default:
1598 r = 0;
1599 break;
1600 }
1601 return r;
1602
1603}
1604
043405e1
CO		 1605long kvm_arch_dev_ioctl(struct file *filp,
1606 unsigned int ioctl, unsigned long arg)
1607{
1608 void __user *argp = (void __user *)arg;
1609 long r;
1610
1611 switch (ioctl) {
1612 case KVM_GET_MSR_INDEX_LIST: {
1613 struct kvm_msr_list __user *user_msr_list = argp;
1614 struct kvm_msr_list msr_list;
1615 unsigned n;
1616
1617 r = -EFAULT;
1618 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1619 goto out;
1620 n = msr_list.nmsrs;
1621 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1622 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1623 goto out;
1624 r = -E2BIG;
e125e7b6 1625 if (n < msr_list.nmsrs)
043405e1
CO		 1626 goto out;
1627 r = -EFAULT;
1628 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1629 num_msrs_to_save * sizeof(u32)))
1630 goto out;
e125e7b6 1631 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1632 &emulated_msrs,
1633 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1634 goto out;
1635 r = 0;
1636 break;
1637 }
674eea0f
AK		 1638 case KVM_GET_SUPPORTED_CPUID: {
1639 struct kvm_cpuid2 __user *cpuid_arg = argp;
1640 struct kvm_cpuid2 cpuid;
1641
1642 r = -EFAULT;
1643 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1644 goto out;
1645 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1646 cpuid_arg->entries);
674eea0f
AK		 1647 if (r)
1648 goto out;
1649
1650 r = -EFAULT;
1651 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1652 goto out;
1653 r = 0;
1654 break;
1655 }
890ca9ae
HY		 1656 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1657 u64 mce_cap;
1658
1659 mce_cap = KVM_MCE_CAP_SUPPORTED;
1660 r = -EFAULT;
1661 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1662 goto out;
1663 r = 0;
1664 break;
1665 }
043405e1
CO		 1666 default:
1667 r = -EINVAL;
1668 }
1669out:
1670 return r;
1671}
1672
313a3dc7
CO		 1673void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1674{
1675 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1676 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1677 unsigned long khz = cpufreq_quick_get(cpu);
1678 if (!khz)
1679 khz = tsc_khz;
1680 per_cpu(cpu_tsc_khz, cpu) = khz;
1681 }
c8076604 1682 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1683}
1684
1685void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1686{
9327fd11 1687 kvm_put_guest_fpu(vcpu);
02daab21 1688 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1689}
1690
07716717 1691static int is_efer_nx(void)
313a3dc7 1692{
e286e86e 1693 unsigned long long efer = 0;
313a3dc7 1694
e286e86e 1695 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1696 return efer & EFER_NX;
1697}
1698
1699static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1700{
1701 int i;
1702 struct kvm_cpuid_entry2 *e, *entry;
1703
313a3dc7 1704 entry = NULL;
ad312c7c
ZX		 1705 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1706 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1707 if (e->function == 0x80000001) {
1708 entry = e;
1709 break;
1710 }
1711 }
07716717 1712 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1713 entry->edx &= ~(1 << 20);
1714 printk(KERN_INFO "kvm: guest NX capability removed\n");
1715 }
1716}
1717
07716717 1718/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1719static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1720 struct kvm_cpuid *cpuid,
1721 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1722{
1723 int r, i;
1724 struct kvm_cpuid_entry *cpuid_entries;
1725
1726 r = -E2BIG;
1727 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1728 goto out;
1729 r = -ENOMEM;
1730 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1731 if (!cpuid_entries)
1732 goto out;
1733 r = -EFAULT;
1734 if (copy_from_user(cpuid_entries, entries,
1735 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1736 goto out_free;
1737 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1738 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1739 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1740 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1741 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1742 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1743 vcpu->arch.cpuid_entries[i].index = 0;
1744 vcpu->arch.cpuid_entries[i].flags = 0;
1745 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1746 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1747 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1748 }
1749 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1750 cpuid_fix_nx_cap(vcpu);
1751 r = 0;
fc61b800 1752 kvm_apic_set_version(vcpu);
0e851880 1753 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1754
1755out_free:
1756 vfree(cpuid_entries);
1757out:
1758 return r;
1759}
1760
1761static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1762 struct kvm_cpuid2 *cpuid,
1763 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1764{
1765 int r;
1766
1767 r = -E2BIG;
1768 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1769 goto out;
1770 r = -EFAULT;
ad312c7c 1771 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1772 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1773 goto out;
ad312c7c 1774 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1775 kvm_apic_set_version(vcpu);
0e851880 1776 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1777 return 0;
1778
1779out:
1780 return r;
1781}
1782
07716717 1783static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1784 struct kvm_cpuid2 *cpuid,
1785 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1786{
1787 int r;
1788
1789 r = -E2BIG;
ad312c7c 1790 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1791 goto out;
1792 r = -EFAULT;
ad312c7c 1793 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1794 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1795 goto out;
1796 return 0;
1797
1798out:
ad312c7c 1799 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1800 return r;
1801}
1802
07716717 1803static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1804 u32 index)
07716717
DK		 1805{
1806 entry->function = function;
1807 entry->index = index;
1808 cpuid_count(entry->function, entry->index,
19355475 1809 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1810 entry->flags = 0;
1811}
1812
7faa4ee1
AK		 1813#define F(x) bit(X86_FEATURE_##x)
1814
07716717
DK		 1815static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1816 u32 index, int *nent, int maxnent)
1817{
7faa4ee1 1818 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1819#ifdef CONFIG_X86_64
17cc3935
SY		 1820 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1821 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1822 unsigned f_lm = F(LM);
1823#else
17cc3935 1824 unsigned f_gbpages = 0;
7faa4ee1 1825 unsigned f_lm = 0;
07716717 1826#endif
4e47c7a6 1827 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1828
1829 /* cpuid 1.edx */
1830 const u32 kvm_supported_word0_x86_features =
1831 F(FPU) | F(VME) | F(DE) | F(PSE) |
1832 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1833 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1834 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1835 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1836 0 /* Reserved, DS, ACPI */ | F(MMX) |
1837 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1838 0 /* HTT, TM, Reserved, PBE */;
1839 /* cpuid 0x80000001.edx */
1840 const u32 kvm_supported_word1_x86_features =
1841 F(FPU) | F(VME) | F(DE) | F(PSE) |
1842 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1843 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1844 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1845 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1846 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1847 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1848 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1849 /* cpuid 1.ecx */
1850 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1851 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1852 0 /* DS-CPL, VMX, SMX, EST */ |
1853 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1854 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1855 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1856 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1857 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1858 /* cpuid 0x80000001.ecx */
07716717 1859 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1860 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1861 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1862 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1863 0 /* SKINIT */ | 0 /* WDT */;
07716717 1864
19355475 1865 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1866 get_cpu();
1867 do_cpuid_1_ent(entry, function, index);
1868 ++*nent;
1869
1870 switch (function) {
1871 case 0:
1872 entry->eax = min(entry->eax, (u32)0xb);
1873 break;
1874 case 1:
1875 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1876 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1877 /* we support x2apic emulation even if host does not support
1878 * it since we emulate x2apic in software */
1879 entry->ecx |= F(X2APIC);
07716717
DK		 1880 break;
1881 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1882 * may return different values. This forces us to get_cpu() before
1883 * issuing the first command, and also to emulate this annoying behavior
1884 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1885 case 2: {
1886 int t, times = entry->eax & 0xff;
1887
1888 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1889 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1890 for (t = 1; t < times && *nent < maxnent; ++t) {
1891 do_cpuid_1_ent(&entry[t], function, 0);
1892 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1893 ++*nent;
1894 }
1895 break;
1896 }
1897 /* function 4 and 0xb have additional index. */
1898 case 4: {
14af3f3c 1899 int i, cache_type;
07716717
DK		 1900
1901 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1902 /* read more entries until cache_type is zero */
14af3f3c
HH		 1903 for (i = 1; *nent < maxnent; ++i) {
1904 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1905 if (!cache_type)
1906 break;
14af3f3c
HH		 1907 do_cpuid_1_ent(&entry[i], function, i);
1908 entry[i].flags |=
07716717
DK		 1909 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1910 ++*nent;
1911 }
1912 break;
1913 }
1914 case 0xb: {
14af3f3c 1915 int i, level_type;
07716717
DK		 1916
1917 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1918 /* read more entries until level_type is zero */
14af3f3c 1919 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1920 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1921 if (!level_type)
1922 break;
14af3f3c
HH		 1923 do_cpuid_1_ent(&entry[i], function, i);
1924 entry[i].flags |=
07716717
DK		 1925 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1926 ++*nent;
1927 }
1928 break;
1929 }
1930 case 0x80000000:
1931 entry->eax = min(entry->eax, 0x8000001a);
1932 break;
1933 case 0x80000001:
1934 entry->edx &= kvm_supported_word1_x86_features;
1935 entry->ecx &= kvm_supported_word6_x86_features;
1936 break;
1937 }
1938 put_cpu();
1939}
1940
7faa4ee1
AK		 1941#undef F
1942
674eea0f 1943static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1944 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1945{
1946 struct kvm_cpuid_entry2 *cpuid_entries;
1947 int limit, nent = 0, r = -E2BIG;
1948 u32 func;
1949
1950 if (cpuid->nent < 1)
1951 goto out;
6a544355
AK		 1952 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1953 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1954 r = -ENOMEM;
1955 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1956 if (!cpuid_entries)
1957 goto out;
1958
1959 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1960 limit = cpuid_entries[0].eax;
1961 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1962 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1963 &nent, cpuid->nent);
07716717
DK		 1964 r = -E2BIG;
1965 if (nent >= cpuid->nent)
1966 goto out_free;
1967
1968 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1969 limit = cpuid_entries[nent - 1].eax;
1970 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1971 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1972 &nent, cpuid->nent);
cb007648
MM		 1973 r = -E2BIG;
1974 if (nent >= cpuid->nent)
1975 goto out_free;
1976
07716717
DK		 1977 r = -EFAULT;
1978 if (copy_to_user(entries, cpuid_entries,
19355475 1979 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1980 goto out_free;
1981 cpuid->nent = nent;
1982 r = 0;
1983
1984out_free:
1985 vfree(cpuid_entries);
1986out:
1987 return r;
1988}
1989
313a3dc7
CO		 1990static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1991 struct kvm_lapic_state *s)
1992{
1993 vcpu_load(vcpu);
ad312c7c 1994 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1995 vcpu_put(vcpu);
1996
1997 return 0;
1998}
1999
2000static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2001 struct kvm_lapic_state *s)
2002{
2003 vcpu_load(vcpu);
ad312c7c 2004 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2005 kvm_apic_post_state_restore(vcpu);
cb142eb7 2006 update_cr8_intercept(vcpu);
313a3dc7
CO		 2007 vcpu_put(vcpu);
2008
2009 return 0;
2010}
2011
f77bc6a4
ZX		 2012static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2013 struct kvm_interrupt *irq)
2014{
2015 if (irq->irq < 0 || irq->irq >= 256)
2016 return -EINVAL;
2017 if (irqchip_in_kernel(vcpu->kvm))
2018 return -ENXIO;
2019 vcpu_load(vcpu);
2020
66fd3f7f 2021 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2022
2023 vcpu_put(vcpu);
2024
2025 return 0;
2026}
2027
c4abb7c9
JK		 2028static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2029{
2030 vcpu_load(vcpu);
2031 kvm_inject_nmi(vcpu);
2032 vcpu_put(vcpu);
2033
2034 return 0;
2035}
2036
b209749f
AK		 2037static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2038 struct kvm_tpr_access_ctl *tac)
2039{
2040 if (tac->flags)
2041 return -EINVAL;
2042 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2043 return 0;
2044}
2045
890ca9ae
HY		 2046static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2047 u64 mcg_cap)
2048{
2049 int r;
2050 unsigned bank_num = mcg_cap & 0xff, bank;
2051
2052 r = -EINVAL;
a9e38c3e 2053 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2054 goto out;
2055 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2056 goto out;
2057 r = 0;
2058 vcpu->arch.mcg_cap = mcg_cap;
2059 /* Init IA32_MCG_CTL to all 1s */
2060 if (mcg_cap & MCG_CTL_P)
2061 vcpu->arch.mcg_ctl = ~(u64)0;
2062 /* Init IA32_MCi_CTL to all 1s */
2063 for (bank = 0; bank < bank_num; bank++)
2064 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2065out:
2066 return r;
2067}
2068
2069static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2070 struct kvm_x86_mce *mce)
2071{
2072 u64 mcg_cap = vcpu->arch.mcg_cap;
2073 unsigned bank_num = mcg_cap & 0xff;
2074 u64 *banks = vcpu->arch.mce_banks;
2075
2076 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2077 return -EINVAL;
2078 /*
2079 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2080 * reporting is disabled
2081 */
2082 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2083 vcpu->arch.mcg_ctl != ~(u64)0)
2084 return 0;
2085 banks += 4 * mce->bank;
2086 /*
2087 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2088 * reporting is disabled for the bank
2089 */
2090 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2091 return 0;
2092 if (mce->status & MCI_STATUS_UC) {
2093 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2094 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2095 printk(KERN_DEBUG "kvm: set_mce: "
2096 "injects mce exception while "
2097 "previous one is in progress!\n");
2098 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2099 return 0;
2100 }
2101 if (banks[1] & MCI_STATUS_VAL)
2102 mce->status |= MCI_STATUS_OVER;
2103 banks[2] = mce->addr;
2104 banks[3] = mce->misc;
2105 vcpu->arch.mcg_status = mce->mcg_status;
2106 banks[1] = mce->status;
2107 kvm_queue_exception(vcpu, MC_VECTOR);
2108 } else if (!(banks[1] & MCI_STATUS_VAL)
2109 || !(banks[1] & MCI_STATUS_UC)) {
2110 if (banks[1] & MCI_STATUS_VAL)
2111 mce->status |= MCI_STATUS_OVER;
2112 banks[2] = mce->addr;
2113 banks[3] = mce->misc;
2114 banks[1] = mce->status;
2115 } else
2116 banks[1] |= MCI_STATUS_OVER;
2117 return 0;
2118}
2119
3cfc3092
JK		 2120static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2121 struct kvm_vcpu_events *events)
2122{
2123 vcpu_load(vcpu);
2124
2125 events->exception.injected = vcpu->arch.exception.pending;
2126 events->exception.nr = vcpu->arch.exception.nr;
2127 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2128 events->exception.error_code = vcpu->arch.exception.error_code;
2129
2130 events->interrupt.injected = vcpu->arch.interrupt.pending;
2131 events->interrupt.nr = vcpu->arch.interrupt.nr;
2132 events->interrupt.soft = vcpu->arch.interrupt.soft;
2133
2134 events->nmi.injected = vcpu->arch.nmi_injected;
2135 events->nmi.pending = vcpu->arch.nmi_pending;
2136 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2137
2138 events->sipi_vector = vcpu->arch.sipi_vector;
2139
dab4b911
JK		 2140 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2141 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 2142
2143 vcpu_put(vcpu);
2144}
2145
2146static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2147 struct kvm_vcpu_events *events)
2148{
dab4b911
JK		 2149 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2150 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 2151 return -EINVAL;
2152
2153 vcpu_load(vcpu);
2154
2155 vcpu->arch.exception.pending = events->exception.injected;
2156 vcpu->arch.exception.nr = events->exception.nr;
2157 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2158 vcpu->arch.exception.error_code = events->exception.error_code;
2159
2160 vcpu->arch.interrupt.pending = events->interrupt.injected;
2161 vcpu->arch.interrupt.nr = events->interrupt.nr;
2162 vcpu->arch.interrupt.soft = events->interrupt.soft;
2163 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2164 kvm_pic_clear_isr_ack(vcpu->kvm);
2165
2166 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2167 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2168 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2169 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2170
dab4b911
JK		 2171 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2172 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2173
2174 vcpu_put(vcpu);
2175
2176 return 0;
2177}
2178
313a3dc7
CO		 2179long kvm_arch_vcpu_ioctl(struct file *filp,
2180 unsigned int ioctl, unsigned long arg)
2181{
2182 struct kvm_vcpu *vcpu = filp->private_data;
2183 void __user *argp = (void __user *)arg;
2184 int r;
b772ff36 2185 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2186
2187 switch (ioctl) {
2188 case KVM_GET_LAPIC: {
2204ae3c
MT		 2189 r = -EINVAL;
2190 if (!vcpu->arch.apic)
2191 goto out;
b772ff36 2192 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2193
b772ff36
DH		 2194 r = -ENOMEM;
2195 if (!lapic)
2196 goto out;
2197 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2198 if (r)
2199 goto out;
2200 r = -EFAULT;
b772ff36 2201 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2202 goto out;
2203 r = 0;
2204 break;
2205 }
2206 case KVM_SET_LAPIC: {
2204ae3c
MT		 2207 r = -EINVAL;
2208 if (!vcpu->arch.apic)
2209 goto out;
b772ff36
DH		 2210 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2211 r = -ENOMEM;
2212 if (!lapic)
2213 goto out;
313a3dc7 2214 r = -EFAULT;
b772ff36 2215 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2216 goto out;
b772ff36 2217 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2218 if (r)
2219 goto out;
2220 r = 0;
2221 break;
2222 }
f77bc6a4
ZX		 2223 case KVM_INTERRUPT: {
2224 struct kvm_interrupt irq;
2225
2226 r = -EFAULT;
2227 if (copy_from_user(&irq, argp, sizeof irq))
2228 goto out;
2229 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2230 if (r)
2231 goto out;
2232 r = 0;
2233 break;
2234 }
c4abb7c9
JK		 2235 case KVM_NMI: {
2236 r = kvm_vcpu_ioctl_nmi(vcpu);
2237 if (r)
2238 goto out;
2239 r = 0;
2240 break;
2241 }
313a3dc7
CO		 2242 case KVM_SET_CPUID: {
2243 struct kvm_cpuid __user *cpuid_arg = argp;
2244 struct kvm_cpuid cpuid;
2245
2246 r = -EFAULT;
2247 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2248 goto out;
2249 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2250 if (r)
2251 goto out;
2252 break;
2253 }
07716717
DK		 2254 case KVM_SET_CPUID2: {
2255 struct kvm_cpuid2 __user *cpuid_arg = argp;
2256 struct kvm_cpuid2 cpuid;
2257
2258 r = -EFAULT;
2259 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2260 goto out;
2261 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2262 cpuid_arg->entries);
07716717
DK		 2263 if (r)
2264 goto out;
2265 break;
2266 }
2267 case KVM_GET_CPUID2: {
2268 struct kvm_cpuid2 __user *cpuid_arg = argp;
2269 struct kvm_cpuid2 cpuid;
2270
2271 r = -EFAULT;
2272 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2273 goto out;
2274 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2275 cpuid_arg->entries);
07716717
DK		 2276 if (r)
2277 goto out;
2278 r = -EFAULT;
2279 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2280 goto out;
2281 r = 0;
2282 break;
2283 }
313a3dc7
CO		 2284 case KVM_GET_MSRS:
2285 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2286 break;
2287 case KVM_SET_MSRS:
2288 r = msr_io(vcpu, argp, do_set_msr, 0);
2289 break;
b209749f
AK		 2290 case KVM_TPR_ACCESS_REPORTING: {
2291 struct kvm_tpr_access_ctl tac;
2292
2293 r = -EFAULT;
2294 if (copy_from_user(&tac, argp, sizeof tac))
2295 goto out;
2296 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2297 if (r)
2298 goto out;
2299 r = -EFAULT;
2300 if (copy_to_user(argp, &tac, sizeof tac))
2301 goto out;
2302 r = 0;
2303 break;
2304 };
b93463aa
AK		 2305 case KVM_SET_VAPIC_ADDR: {
2306 struct kvm_vapic_addr va;
2307
2308 r = -EINVAL;
2309 if (!irqchip_in_kernel(vcpu->kvm))
2310 goto out;
2311 r = -EFAULT;
2312 if (copy_from_user(&va, argp, sizeof va))
2313 goto out;
2314 r = 0;
2315 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2316 break;
2317 }
890ca9ae
HY		 2318 case KVM_X86_SETUP_MCE: {
2319 u64 mcg_cap;
2320
2321 r = -EFAULT;
2322 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2323 goto out;
2324 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2325 break;
2326 }
2327 case KVM_X86_SET_MCE: {
2328 struct kvm_x86_mce mce;
2329
2330 r = -EFAULT;
2331 if (copy_from_user(&mce, argp, sizeof mce))
2332 goto out;
2333 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2334 break;
2335 }
3cfc3092
JK		 2336 case KVM_GET_VCPU_EVENTS: {
2337 struct kvm_vcpu_events events;
2338
2339 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2340
2341 r = -EFAULT;
2342 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2343 break;
2344 r = 0;
2345 break;
2346 }
2347 case KVM_SET_VCPU_EVENTS: {
2348 struct kvm_vcpu_events events;
2349
2350 r = -EFAULT;
2351 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2352 break;
2353
2354 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2355 break;
2356 }
313a3dc7
CO		 2357 default:
2358 r = -EINVAL;
2359 }
2360out:
7a6ce84c 2361 kfree(lapic);
313a3dc7
CO		 2362 return r;
2363}
2364
1fe779f8
CO		 2365static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2366{
2367 int ret;
2368
2369 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2370 return -1;
2371 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2372 return ret;
2373}
2374
b927a3ce
SY		 2375static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2376 u64 ident_addr)
2377{
2378 kvm->arch.ept_identity_map_addr = ident_addr;
2379 return 0;
2380}
2381
1fe779f8
CO		 2382static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2383 u32 kvm_nr_mmu_pages)
2384{
2385 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2386 return -EINVAL;
2387
79fac95e 2388 mutex_lock(&kvm->slots_lock);
7c8a83b7 2389 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2390
2391 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2392 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2393
7c8a83b7 2394 spin_unlock(&kvm->mmu_lock);
79fac95e 2395 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2396 return 0;
2397}
2398
2399static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2400{
f05e70ac 2401 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2402}
2403
a983fb23
MT		 2404gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2405{
2406 int i;
2407 struct kvm_mem_alias *alias;
2408 struct kvm_mem_aliases *aliases;
2409
2410 aliases = rcu_dereference(kvm->arch.aliases);
2411
2412 for (i = 0; i < aliases->naliases; ++i) {
2413 alias = &aliases->aliases[i];
2414 if (alias->flags & KVM_ALIAS_INVALID)
2415 continue;
2416 if (gfn >= alias->base_gfn
2417 && gfn < alias->base_gfn + alias->npages)
2418 return alias->target_gfn + gfn - alias->base_gfn;
2419 }
2420 return gfn;
2421}
2422
e9f85cde
ZX		 2423gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2424{
2425 int i;
2426 struct kvm_mem_alias *alias;
a983fb23
MT		 2427 struct kvm_mem_aliases *aliases;
2428
2429 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2430
fef9cce0
MT		 2431 for (i = 0; i < aliases->naliases; ++i) {
2432 alias = &aliases->aliases[i];
e9f85cde
ZX		 2433 if (gfn >= alias->base_gfn
2434 && gfn < alias->base_gfn + alias->npages)
2435 return alias->target_gfn + gfn - alias->base_gfn;
2436 }
2437 return gfn;
2438}
2439
1fe779f8
CO		 2440/*
2441 * Set a new alias region. Aliases map a portion of physical memory into
2442 * another portion. This is useful for memory windows, for example the PC
2443 * VGA region.
2444 */
2445static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2446 struct kvm_memory_alias *alias)
2447{
2448 int r, n;
2449 struct kvm_mem_alias *p;
a983fb23 2450 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2451
2452 r = -EINVAL;
2453 /* General sanity checks */
2454 if (alias->memory_size & (PAGE_SIZE - 1))
2455 goto out;
2456 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2457 goto out;
2458 if (alias->slot >= KVM_ALIAS_SLOTS)
2459 goto out;
2460 if (alias->guest_phys_addr + alias->memory_size
2461 < alias->guest_phys_addr)
2462 goto out;
2463 if (alias->target_phys_addr + alias->memory_size
2464 < alias->target_phys_addr)
2465 goto out;
2466
a983fb23
MT		 2467 r = -ENOMEM;
2468 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2469 if (!aliases)
2470 goto out;
2471
79fac95e 2472 mutex_lock(&kvm->slots_lock);
1fe779f8 2473
a983fb23
MT		 2474 /* invalidate any gfn reference in case of deletion/shrinking */
2475 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2476 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2477 old_aliases = kvm->arch.aliases;
2478 rcu_assign_pointer(kvm->arch.aliases, aliases);
2479 synchronize_srcu_expedited(&kvm->srcu);
2480 kvm_mmu_zap_all(kvm);
2481 kfree(old_aliases);
2482
2483 r = -ENOMEM;
2484 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2485 if (!aliases)
2486 goto out_unlock;
2487
2488 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2489
2490 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2491 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2492 p->npages = alias->memory_size >> PAGE_SHIFT;
2493 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2494 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2495
2496 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2497 if (aliases->aliases[n - 1].npages)
1fe779f8 2498 break;
fef9cce0 2499 aliases->naliases = n;
1fe779f8 2500
a983fb23
MT		 2501 old_aliases = kvm->arch.aliases;
2502 rcu_assign_pointer(kvm->arch.aliases, aliases);
2503 synchronize_srcu_expedited(&kvm->srcu);
2504 kfree(old_aliases);
2505 r = 0;
1fe779f8 2506
a983fb23 2507out_unlock:
79fac95e 2508 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2509out:
2510 return r;
2511}
2512
2513static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2514{
2515 int r;
2516
2517 r = 0;
2518 switch (chip->chip_id) {
2519 case KVM_IRQCHIP_PIC_MASTER:
2520 memcpy(&chip->chip.pic,
2521 &pic_irqchip(kvm)->pics[0],
2522 sizeof(struct kvm_pic_state));
2523 break;
2524 case KVM_IRQCHIP_PIC_SLAVE:
2525 memcpy(&chip->chip.pic,
2526 &pic_irqchip(kvm)->pics[1],
2527 sizeof(struct kvm_pic_state));
2528 break;
2529 case KVM_IRQCHIP_IOAPIC:
eba0226b 2530 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2531 break;
2532 default:
2533 r = -EINVAL;
2534 break;
2535 }
2536 return r;
2537}
2538
2539static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2540{
2541 int r;
2542
2543 r = 0;
2544 switch (chip->chip_id) {
2545 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2546 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2547 memcpy(&pic_irqchip(kvm)->pics[0],
2548 &chip->chip.pic,
2549 sizeof(struct kvm_pic_state));
fa8273e9 2550 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2551 break;
2552 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2553 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2554 memcpy(&pic_irqchip(kvm)->pics[1],
2555 &chip->chip.pic,
2556 sizeof(struct kvm_pic_state));
fa8273e9 2557 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2558 break;
2559 case KVM_IRQCHIP_IOAPIC:
eba0226b 2560 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2561 break;
2562 default:
2563 r = -EINVAL;
2564 break;
2565 }
2566 kvm_pic_update_irq(pic_irqchip(kvm));
2567 return r;
2568}
2569
e0f63cb9
SY		 2570static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2571{
2572 int r = 0;
2573
894a9c55 2574 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2575 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2576 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2577 return r;
2578}
2579
2580static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2581{
2582 int r = 0;
2583
894a9c55 2584 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2585 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2586 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2587 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2588 return r;
2589}
2590
2591static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2592{
2593 int r = 0;
2594
2595 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2596 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2597 sizeof(ps->channels));
2598 ps->flags = kvm->arch.vpit->pit_state.flags;
2599 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2600 return r;
2601}
2602
2603static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2604{
2605 int r = 0, start = 0;
2606 u32 prev_legacy, cur_legacy;
2607 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2608 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2609 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2610 if (!prev_legacy && cur_legacy)
2611 start = 1;
2612 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2613 sizeof(kvm->arch.vpit->pit_state.channels));
2614 kvm->arch.vpit->pit_state.flags = ps->flags;
2615 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2616 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2617 return r;
2618}
2619
52d939a0
MT		 2620static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2621 struct kvm_reinject_control *control)
2622{
2623 if (!kvm->arch.vpit)
2624 return -ENXIO;
894a9c55 2625 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2626 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2627 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2628 return 0;
2629}
2630
5bb064dc
ZX		 2631/*
2632 * Get (and clear) the dirty memory log for a memory slot.
2633 */
2634int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2635 struct kvm_dirty_log *log)
2636{
b050b015 2637 int r, n, i;
5bb064dc 2638 struct kvm_memory_slot *memslot;
b050b015
MT		 2639 unsigned long is_dirty = 0;
2640 unsigned long *dirty_bitmap = NULL;
5bb064dc 2641
79fac95e 2642 mutex_lock(&kvm->slots_lock);
5bb064dc 2643
b050b015
MT		 2644 r = -EINVAL;
2645 if (log->slot >= KVM_MEMORY_SLOTS)
2646 goto out;
2647
2648 memslot = &kvm->memslots->memslots[log->slot];
2649 r = -ENOENT;
2650 if (!memslot->dirty_bitmap)
2651 goto out;
2652
2653 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2654
2655 r = -ENOMEM;
2656 dirty_bitmap = vmalloc(n);
2657 if (!dirty_bitmap)
5bb064dc 2658 goto out;
b050b015
MT		 2659 memset(dirty_bitmap, 0, n);
2660
2661 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2662 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2663
2664 /* If nothing is dirty, don't bother messing with page tables. */
2665 if (is_dirty) {
b050b015
MT		 2666 struct kvm_memslots *slots, *old_slots;
2667
7c8a83b7 2668 spin_lock(&kvm->mmu_lock);
5bb064dc 2669 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2670 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2671
2672 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2673 if (!slots)
2674 goto out_free;
2675
2676 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2677 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2678
2679 old_slots = kvm->memslots;
2680 rcu_assign_pointer(kvm->memslots, slots);
2681 synchronize_srcu_expedited(&kvm->srcu);
2682 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2683 kfree(old_slots);
5bb064dc 2684 }
b050b015 2685
5bb064dc 2686 r = 0;
b050b015
MT		 2687 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2688 r = -EFAULT;
2689out_free:
2690 vfree(dirty_bitmap);
5bb064dc 2691out:
79fac95e 2692 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2693 return r;
2694}
2695
1fe779f8
CO		 2696long kvm_arch_vm_ioctl(struct file *filp,
2697 unsigned int ioctl, unsigned long arg)
2698{
2699 struct kvm *kvm = filp->private_data;
2700 void __user *argp = (void __user *)arg;
367e1319 2701 int r = -ENOTTY;
f0d66275
DH		 2702 /*
2703 * This union makes it completely explicit to gcc-3.x
2704 * that these two variables' stack usage should be
2705 * combined, not added together.
2706 */
2707 union {
2708 struct kvm_pit_state ps;
e9f42757 2709 struct kvm_pit_state2 ps2;
f0d66275 2710 struct kvm_memory_alias alias;
c5ff41ce 2711 struct kvm_pit_config pit_config;
f0d66275 2712 } u;
1fe779f8
CO		 2713
2714 switch (ioctl) {
2715 case KVM_SET_TSS_ADDR:
2716 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2717 if (r < 0)
2718 goto out;
2719 break;
b927a3ce
SY		 2720 case KVM_SET_IDENTITY_MAP_ADDR: {
2721 u64 ident_addr;
2722
2723 r = -EFAULT;
2724 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2725 goto out;
2726 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2727 if (r < 0)
2728 goto out;
2729 break;
2730 }
1fe779f8
CO		 2731 case KVM_SET_MEMORY_REGION: {
2732 struct kvm_memory_region kvm_mem;
2733 struct kvm_userspace_memory_region kvm_userspace_mem;
2734
2735 r = -EFAULT;
2736 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2737 goto out;
2738 kvm_userspace_mem.slot = kvm_mem.slot;
2739 kvm_userspace_mem.flags = kvm_mem.flags;
2740 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2741 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2742 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2743 if (r)
2744 goto out;
2745 break;
2746 }
2747 case KVM_SET_NR_MMU_PAGES:
2748 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2749 if (r)
2750 goto out;
2751 break;
2752 case KVM_GET_NR_MMU_PAGES:
2753 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2754 break;
f0d66275 2755 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2756 r = -EFAULT;
f0d66275 2757 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2758 goto out;
f0d66275 2759 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2760 if (r)
2761 goto out;
2762 break;
3ddea128
MT		 2763 case KVM_CREATE_IRQCHIP: {
2764 struct kvm_pic *vpic;
2765
2766 mutex_lock(&kvm->lock);
2767 r = -EEXIST;
2768 if (kvm->arch.vpic)
2769 goto create_irqchip_unlock;
1fe779f8 2770 r = -ENOMEM;
3ddea128
MT		 2771 vpic = kvm_create_pic(kvm);
2772 if (vpic) {
1fe779f8
CO		 2773 r = kvm_ioapic_init(kvm);
2774 if (r) {
72bb2fcd
WY		 2775 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2776 &vpic->dev);
3ddea128
MT		 2777 kfree(vpic);
2778 goto create_irqchip_unlock;
1fe779f8
CO		 2779 }
2780 } else
3ddea128
MT		 2781 goto create_irqchip_unlock;
2782 smp_wmb();
2783 kvm->arch.vpic = vpic;
2784 smp_wmb();
399ec807
AK		 2785 r = kvm_setup_default_irq_routing(kvm);
2786 if (r) {
3ddea128 2787 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2788 kvm_ioapic_destroy(kvm);
2789 kvm_destroy_pic(kvm);
3ddea128 2790 mutex_unlock(&kvm->irq_lock);
399ec807 2791 }
3ddea128
MT		 2792 create_irqchip_unlock:
2793 mutex_unlock(&kvm->lock);
1fe779f8 2794 break;
3ddea128 2795 }
7837699f 2796 case KVM_CREATE_PIT:
c5ff41ce
JK		 2797 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2798 goto create_pit;
2799 case KVM_CREATE_PIT2:
2800 r = -EFAULT;
2801 if (copy_from_user(&u.pit_config, argp,
2802 sizeof(struct kvm_pit_config)))
2803 goto out;
2804 create_pit:
79fac95e 2805 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2806 r = -EEXIST;
2807 if (kvm->arch.vpit)
2808 goto create_pit_unlock;
7837699f 2809 r = -ENOMEM;
c5ff41ce 2810 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2811 if (kvm->arch.vpit)
2812 r = 0;
269e05e4 2813 create_pit_unlock:
79fac95e 2814 mutex_unlock(&kvm->slots_lock);
7837699f 2815 break;
4925663a 2816 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2817 case KVM_IRQ_LINE: {
2818 struct kvm_irq_level irq_event;
2819
2820 r = -EFAULT;
2821 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2822 goto out;
2823 if (irqchip_in_kernel(kvm)) {
4925663a 2824 __s32 status;
4925663a
GN		 2825 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2826 irq_event.irq, irq_event.level);
4925663a
GN		 2827 if (ioctl == KVM_IRQ_LINE_STATUS) {
2828 irq_event.status = status;
2829 if (copy_to_user(argp, &irq_event,
2830 sizeof irq_event))
2831 goto out;
2832 }
1fe779f8
CO		 2833 r = 0;
2834 }
2835 break;
2836 }
2837 case KVM_GET_IRQCHIP: {
2838 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2839 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2840
f0d66275
DH		 2841 r = -ENOMEM;
2842 if (!chip)
1fe779f8 2843 goto out;
f0d66275
DH		 2844 r = -EFAULT;
2845 if (copy_from_user(chip, argp, sizeof *chip))
2846 goto get_irqchip_out;
1fe779f8
CO		 2847 r = -ENXIO;
2848 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2849 goto get_irqchip_out;
2850 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2851 if (r)
f0d66275 2852 goto get_irqchip_out;
1fe779f8 2853 r = -EFAULT;
f0d66275
DH		 2854 if (copy_to_user(argp, chip, sizeof *chip))
2855 goto get_irqchip_out;
1fe779f8 2856 r = 0;
f0d66275
DH		 2857 get_irqchip_out:
2858 kfree(chip);
2859 if (r)
2860 goto out;
1fe779f8
CO		 2861 break;
2862 }
2863 case KVM_SET_IRQCHIP: {
2864 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2865 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2866
f0d66275
DH		 2867 r = -ENOMEM;
2868 if (!chip)
1fe779f8 2869 goto out;
f0d66275
DH		 2870 r = -EFAULT;
2871 if (copy_from_user(chip, argp, sizeof *chip))
2872 goto set_irqchip_out;
1fe779f8
CO		 2873 r = -ENXIO;
2874 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2875 goto set_irqchip_out;
2876 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2877 if (r)
f0d66275 2878 goto set_irqchip_out;
1fe779f8 2879 r = 0;
f0d66275
DH		 2880 set_irqchip_out:
2881 kfree(chip);
2882 if (r)
2883 goto out;
1fe779f8
CO		 2884 break;
2885 }
e0f63cb9 2886 case KVM_GET_PIT: {
e0f63cb9 2887 r = -EFAULT;
f0d66275 2888 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2889 goto out;
2890 r = -ENXIO;
2891 if (!kvm->arch.vpit)
2892 goto out;
f0d66275 2893 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2894 if (r)
2895 goto out;
2896 r = -EFAULT;
f0d66275 2897 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2898 goto out;
2899 r = 0;
2900 break;
2901 }
2902 case KVM_SET_PIT: {
e0f63cb9 2903 r = -EFAULT;
f0d66275 2904 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2905 goto out;
2906 r = -ENXIO;
2907 if (!kvm->arch.vpit)
2908 goto out;
f0d66275 2909 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2910 if (r)
2911 goto out;
2912 r = 0;
2913 break;
2914 }
e9f42757
BK		 2915 case KVM_GET_PIT2: {
2916 r = -ENXIO;
2917 if (!kvm->arch.vpit)
2918 goto out;
2919 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2920 if (r)
2921 goto out;
2922 r = -EFAULT;
2923 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2924 goto out;
2925 r = 0;
2926 break;
2927 }
2928 case KVM_SET_PIT2: {
2929 r = -EFAULT;
2930 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2931 goto out;
2932 r = -ENXIO;
2933 if (!kvm->arch.vpit)
2934 goto out;
2935 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2936 if (r)
2937 goto out;
2938 r = 0;
2939 break;
2940 }
52d939a0
MT		 2941 case KVM_REINJECT_CONTROL: {
2942 struct kvm_reinject_control control;
2943 r = -EFAULT;
2944 if (copy_from_user(&control, argp, sizeof(control)))
2945 goto out;
2946 r = kvm_vm_ioctl_reinject(kvm, &control);
2947 if (r)
2948 goto out;
2949 r = 0;
2950 break;
2951 }
ffde22ac
ES		 2952 case KVM_XEN_HVM_CONFIG: {
2953 r = -EFAULT;
2954 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2955 sizeof(struct kvm_xen_hvm_config)))
2956 goto out;
2957 r = -EINVAL;
2958 if (kvm->arch.xen_hvm_config.flags)
2959 goto out;
2960 r = 0;
2961 break;
2962 }
afbcf7ab
GC		 2963 case KVM_SET_CLOCK: {
2964 struct timespec now;
2965 struct kvm_clock_data user_ns;
2966 u64 now_ns;
2967 s64 delta;
2968
2969 r = -EFAULT;
2970 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2971 goto out;
2972
2973 r = -EINVAL;
2974 if (user_ns.flags)
2975 goto out;
2976
2977 r = 0;
2978 ktime_get_ts(&now);
2979 now_ns = timespec_to_ns(&now);
2980 delta = user_ns.clock - now_ns;
2981 kvm->arch.kvmclock_offset = delta;
2982 break;
2983 }
2984 case KVM_GET_CLOCK: {
2985 struct timespec now;
2986 struct kvm_clock_data user_ns;
2987 u64 now_ns;
2988
2989 ktime_get_ts(&now);
2990 now_ns = timespec_to_ns(&now);
2991 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2992 user_ns.flags = 0;
2993
2994 r = -EFAULT;
2995 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2996 goto out;
2997 r = 0;
2998 break;
2999 }
3000
1fe779f8
CO		 3001 default:
3002 ;
3003 }
3004out:
3005 return r;
3006}
3007
a16b043c 3008static void kvm_init_msr_list(void)
043405e1
CO		 3009{
3010 u32 dummy[2];
3011 unsigned i, j;
3012
e3267cbb
GC		 3013 /* skip the first msrs in the list. KVM-specific */
3014 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3015 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3016 continue;
3017 if (j < i)
3018 msrs_to_save[j] = msrs_to_save[i];
3019 j++;
3020 }
3021 num_msrs_to_save = j;
3022}
3023
bda9020e
MT		 3024static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3025 const void *v)
bbd9b64e 3026{
bda9020e
MT		 3027 if (vcpu->arch.apic &&
3028 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3029 return 0;
bbd9b64e 3030
e93f8a0f 3031 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3032}
3033
bda9020e 3034static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3035{
bda9020e
MT		 3036 if (vcpu->arch.apic &&
3037 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3038 return 0;
bbd9b64e 3039
e93f8a0f 3040 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3041}
3042
1871c602
GN		 3043gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3044{
3045 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3046 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3047}
3048
3049 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3050{
3051 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3052 access |= PFERR_FETCH_MASK;
3053 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3054}
3055
3056gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3057{
3058 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3059 access |= PFERR_WRITE_MASK;
3060 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3061}
3062
3063/* uses this to access any guest's mapped memory without checking CPL */
3064gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3065{
3066 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3067}
3068
3069static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3070 struct kvm_vcpu *vcpu, u32 access,
3071 u32 *error)
bbd9b64e
CO		 3072{
3073 void *data = val;
10589a46 3074 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3075
3076 while (bytes) {
1871c602 3077 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3078 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3079 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3080 int ret;
3081
10589a46
MT		 3082 if (gpa == UNMAPPED_GVA) {
3083 r = X86EMUL_PROPAGATE_FAULT;
3084 goto out;
3085 }
77c2002e 3086 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3087 if (ret < 0) {
3088 r = X86EMUL_UNHANDLEABLE;
3089 goto out;
3090 }
bbd9b64e 3091
77c2002e
IE		 3092 bytes -= toread;
3093 data += toread;
3094 addr += toread;
bbd9b64e 3095 }
10589a46 3096out:
10589a46 3097 return r;
bbd9b64e 3098}
77c2002e 3099
1871c602
GN		 3100/* used for instruction fetching */
3101static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3102 struct kvm_vcpu *vcpu, u32 *error)
3103{
3104 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3105 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3106 access | PFERR_FETCH_MASK, error);
3107}
3108
3109static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3110 struct kvm_vcpu *vcpu, u32 *error)
3111{
3112 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3113 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3114 error);
3115}
3116
3117static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3118 struct kvm_vcpu *vcpu, u32 *error)
3119{
3120 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3121}
3122
cded19f3 3123static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3124 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3125{
3126 void *data = val;
3127 int r = X86EMUL_CONTINUE;
3128
3129 while (bytes) {
1871c602 3130 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3131 unsigned offset = addr & (PAGE_SIZE-1);
3132 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3133 int ret;
3134
3135 if (gpa == UNMAPPED_GVA) {
3136 r = X86EMUL_PROPAGATE_FAULT;
3137 goto out;
3138 }
3139 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3140 if (ret < 0) {
3141 r = X86EMUL_UNHANDLEABLE;
3142 goto out;
3143 }
3144
3145 bytes -= towrite;
3146 data += towrite;
3147 addr += towrite;
3148 }
3149out:
3150 return r;
3151}
3152
bbd9b64e 3153
bbd9b64e
CO		 3154static int emulator_read_emulated(unsigned long addr,
3155 void *val,
3156 unsigned int bytes,
3157 struct kvm_vcpu *vcpu)
3158{
bbd9b64e 3159 gpa_t gpa;
1871c602 3160 u32 error_code;
bbd9b64e
CO		 3161
3162 if (vcpu->mmio_read_completed) {
3163 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3164 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3165 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3166 vcpu->mmio_read_completed = 0;
3167 return X86EMUL_CONTINUE;
3168 }
3169
1871c602
GN		 3170 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3171
3172 if (gpa == UNMAPPED_GVA) {
3173 kvm_inject_page_fault(vcpu, addr, error_code);
3174 return X86EMUL_PROPAGATE_FAULT;
3175 }
bbd9b64e
CO		 3176
3177 /* For APIC access vmexit */
3178 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3179 goto mmio;
3180
1871c602 3181 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3182 == X86EMUL_CONTINUE)
bbd9b64e 3183 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3184
3185mmio:
3186 /*
3187 * Is this MMIO handled locally?
3188 */
aec51dc4
AK		 3189 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3190 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3191 return X86EMUL_CONTINUE;
3192 }
aec51dc4
AK		 3193
3194 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3195
3196 vcpu->mmio_needed = 1;
3197 vcpu->mmio_phys_addr = gpa;
3198 vcpu->mmio_size = bytes;
3199 vcpu->mmio_is_write = 0;
3200
3201 return X86EMUL_UNHANDLEABLE;
3202}
3203
3200f405 3204int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3205 const void *val, int bytes)
bbd9b64e
CO		 3206{
3207 int ret;
3208
3209 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3210 if (ret < 0)
bbd9b64e 3211 return 0;
ad218f85 3212 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3213 return 1;
3214}
3215
3216static int emulator_write_emulated_onepage(unsigned long addr,
3217 const void *val,
3218 unsigned int bytes,
3219 struct kvm_vcpu *vcpu)
3220{
10589a46 3221 gpa_t gpa;
1871c602 3222 u32 error_code;
10589a46 3223
1871c602 3224 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3225
3226 if (gpa == UNMAPPED_GVA) {
1871c602 3227 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3228 return X86EMUL_PROPAGATE_FAULT;
3229 }
3230
3231 /* For APIC access vmexit */
3232 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3233 goto mmio;
3234
3235 if (emulator_write_phys(vcpu, gpa, val, bytes))
3236 return X86EMUL_CONTINUE;
3237
3238mmio:
aec51dc4 3239 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3240 /*
3241 * Is this MMIO handled locally?
3242 */
bda9020e 3243 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3244 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3245
3246 vcpu->mmio_needed = 1;
3247 vcpu->mmio_phys_addr = gpa;
3248 vcpu->mmio_size = bytes;
3249 vcpu->mmio_is_write = 1;
3250 memcpy(vcpu->mmio_data, val, bytes);
3251
3252 return X86EMUL_CONTINUE;
3253}
3254
3255int emulator_write_emulated(unsigned long addr,
3256 const void *val,
3257 unsigned int bytes,
3258 struct kvm_vcpu *vcpu)
3259{
3260 /* Crossing a page boundary? */
3261 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3262 int rc, now;
3263
3264 now = -addr & ~PAGE_MASK;
3265 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3266 if (rc != X86EMUL_CONTINUE)
3267 return rc;
3268 addr += now;
3269 val += now;
3270 bytes -= now;
3271 }
3272 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3273}
3274EXPORT_SYMBOL_GPL(emulator_write_emulated);
3275
3276static int emulator_cmpxchg_emulated(unsigned long addr,
3277 const void *old,
3278 const void *new,
3279 unsigned int bytes,
3280 struct kvm_vcpu *vcpu)
3281{
9f51e24e 3282 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3283#ifndef CONFIG_X86_64
3284 /* guests cmpxchg8b have to be emulated atomically */
3285 if (bytes == 8) {
10589a46 3286 gpa_t gpa;
2bacc55c 3287 struct page *page;
c0b49b0d 3288 char *kaddr;
2bacc55c
MT		 3289 u64 val;
3290
1871c602 3291 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
10589a46 3292
2bacc55c
MT		 3293 if (gpa == UNMAPPED_GVA ||
3294 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3295 goto emul_write;
3296
3297 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3298 goto emul_write;
3299
3300 val = *(u64 *)new;
72dc67a6 3301
2bacc55c 3302 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3303
c0b49b0d
AM		 3304 kaddr = kmap_atomic(page, KM_USER0);
3305 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3306 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3307 kvm_release_page_dirty(page);
3308 }
3200f405 3309emul_write:
2bacc55c
MT		 3310#endif
3311
bbd9b64e
CO		 3312 return emulator_write_emulated(addr, new, bytes, vcpu);
3313}
3314
3315static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3316{
3317 return kvm_x86_ops->get_segment_base(vcpu, seg);
3318}
3319
3320int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3321{
a7052897 3322 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3323 return X86EMUL_CONTINUE;
3324}
3325
3326int emulate_clts(struct kvm_vcpu *vcpu)
3327{
4d4ec087 3328 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3329 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3330 return X86EMUL_CONTINUE;
3331}
3332
3333int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3334{
c76de350 3335 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3336}
3337
3338int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3339{
3340 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3341
c76de350 3342 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3343}
3344
3345void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3346{
bbd9b64e 3347 u8 opcodes[4];
5fdbf976 3348 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3349 unsigned long rip_linear;
3350
f76c710d 3351 if (!printk_ratelimit())
bbd9b64e
CO		 3352 return;
3353
25be4608
GC		 3354 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3355
1871c602 3356 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3357
3358 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3359 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3360}
3361EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3362
14af3f3c 3363static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3364 .read_std = kvm_read_guest_virt_system,
3365 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3366 .read_emulated = emulator_read_emulated,
3367 .write_emulated = emulator_write_emulated,
3368 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3369};
3370
5fdbf976
MT		 3371static void cache_all_regs(struct kvm_vcpu *vcpu)
3372{
3373 kvm_register_read(vcpu, VCPU_REGS_RAX);
3374 kvm_register_read(vcpu, VCPU_REGS_RSP);
3375 kvm_register_read(vcpu, VCPU_REGS_RIP);
3376 vcpu->arch.regs_dirty = ~0;
3377}
3378
bbd9b64e 3379int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3380 unsigned long cr2,
3381 u16 error_code,
571008da 3382 int emulation_type)
bbd9b64e 3383{
310b5d30 3384 int r, shadow_mask;
571008da 3385 struct decode_cache *c;
851ba692 3386 struct kvm_run *run = vcpu->run;
bbd9b64e 3387
26eef70c 3388 kvm_clear_exception_queue(vcpu);
ad312c7c 3389 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3390 /*
56e82318 3391 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3392 * instead of direct ->regs accesses, can save hundred cycles
3393 * on Intel for instructions that don't read/change RSP, for
3394 * for example.
3395 */
3396 cache_all_regs(vcpu);
bbd9b64e
CO		 3397
3398 vcpu->mmio_is_write = 0;
ad312c7c 3399 vcpu->arch.pio.string = 0;
bbd9b64e 3400
571008da 3401 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3402 int cs_db, cs_l;
3403 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3404
ad312c7c 3405 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3406 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c 3407 vcpu->arch.emulate_ctxt.mode =
a0044755 3408 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3409 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3410 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3411 ? X86EMUL_MODE_PROT64 : cs_db
3412 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3413
ad312c7c 3414 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3415
0cb5762e
AP		 3416 /* Only allow emulation of specific instructions on #UD
3417 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3418 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3419 if (emulation_type & EMULTYPE_TRAP_UD) {
3420 if (!c->twobyte)
3421 return EMULATE_FAIL;
3422 switch (c->b) {
3423 case 0x01: /* VMMCALL */
3424 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3425 return EMULATE_FAIL;
3426 break;
3427 case 0x34: /* sysenter */
3428 case 0x35: /* sysexit */
3429 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3430 return EMULATE_FAIL;
3431 break;
3432 case 0x05: /* syscall */
3433 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3434 return EMULATE_FAIL;
3435 break;
3436 default:
3437 return EMULATE_FAIL;
3438 }
3439
3440 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3441 return EMULATE_FAIL;
3442 }
571008da 3443
f2b5756b 3444 ++vcpu->stat.insn_emulation;
bbd9b64e 3445 if (r) {
f2b5756b 3446 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3447 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3448 return EMULATE_DONE;
3449 return EMULATE_FAIL;
3450 }
3451 }
3452
ba8afb6b
GN		 3453 if (emulation_type & EMULTYPE_SKIP) {
3454 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3455 return EMULATE_DONE;
3456 }
3457
ad312c7c 3458 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3459 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3460
3461 if (r == 0)
3462 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3463
ad312c7c 3464 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3465 return EMULATE_DO_MMIO;
3466
3467 if ((r || vcpu->mmio_is_write) && run) {
3468 run->exit_reason = KVM_EXIT_MMIO;
3469 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3470 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3471 run->mmio.len = vcpu->mmio_size;
3472 run->mmio.is_write = vcpu->mmio_is_write;
3473 }
3474
3475 if (r) {
3476 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3477 return EMULATE_DONE;
3478 if (!vcpu->mmio_needed) {
3479 kvm_report_emulation_failure(vcpu, "mmio");
3480 return EMULATE_FAIL;
3481 }
3482 return EMULATE_DO_MMIO;
3483 }
3484
91586a3b 3485 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3486
3487 if (vcpu->mmio_is_write) {
3488 vcpu->mmio_needed = 0;
3489 return EMULATE_DO_MMIO;
3490 }
3491
3492 return EMULATE_DONE;
3493}
3494EXPORT_SYMBOL_GPL(emulate_instruction);
3495
de7d789a
CO		 3496static int pio_copy_data(struct kvm_vcpu *vcpu)
3497{
ad312c7c 3498 void *p = vcpu->arch.pio_data;
0f346074 3499 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3500 unsigned bytes;
0f346074 3501 int ret;
1871c602 3502 u32 error_code;
de7d789a 3503
ad312c7c
ZX		 3504 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3505 if (vcpu->arch.pio.in)
1871c602 3506 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3507 else
1871c602
GN		 3508 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3509
3510 if (ret == X86EMUL_PROPAGATE_FAULT)
3511 kvm_inject_page_fault(vcpu, q, error_code);
3512
0f346074 3513 return ret;
de7d789a
CO		 3514}
3515
3516int complete_pio(struct kvm_vcpu *vcpu)
3517{
ad312c7c 3518 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3519 long delta;
3520 int r;
5fdbf976 3521 unsigned long val;
de7d789a
CO		 3522
3523 if (!io->string) {
5fdbf976
MT		 3524 if (io->in) {
3525 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3526 memcpy(&val, vcpu->arch.pio_data, io->size);
3527 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3528 }
de7d789a
CO		 3529 } else {
3530 if (io->in) {
3531 r = pio_copy_data(vcpu);
5fdbf976 3532 if (r)
1871c602 3533 goto out;
de7d789a
CO		 3534 }
3535
3536 delta = 1;
3537 if (io->rep) {
3538 delta *= io->cur_count;
3539 /*
3540 * The size of the register should really depend on
3541 * current address size.
3542 */
5fdbf976
MT		 3543 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3544 val -= delta;
3545 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3546 }
3547 if (io->down)
3548 delta = -delta;
3549 delta *= io->size;
5fdbf976
MT		 3550 if (io->in) {
3551 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3552 val += delta;
3553 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3554 } else {
3555 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3556 val += delta;
3557 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3558 }
de7d789a 3559 }
1871c602 3560out:
de7d789a
CO		 3561 io->count -= io->cur_count;
3562 io->cur_count = 0;
3563
3564 return 0;
3565}
3566
bda9020e 3567static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3568{
3569 /* TODO: String I/O for in kernel device */
bda9020e 3570 int r;
de7d789a 3571
ad312c7c 3572 if (vcpu->arch.pio.in)
e93f8a0f 3573 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3574 vcpu->arch.pio.size, pd);
de7d789a 3575 else
e93f8a0f
MT		 3576 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3577 vcpu->arch.pio.port, vcpu->arch.pio.size,
3578 pd);
bda9020e 3579 return r;
de7d789a
CO		 3580}
3581
bda9020e 3582static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3583{
ad312c7c
ZX		 3584 struct kvm_pio_request *io = &vcpu->arch.pio;
3585 void *pd = vcpu->arch.pio_data;
bda9020e 3586 int i, r = 0;
de7d789a 3587
de7d789a 3588 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3589 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3590 io->port, io->size, pd)) {
3591 r = -EOPNOTSUPP;
3592 break;
3593 }
de7d789a
CO		 3594 pd += io->size;
3595 }
bda9020e 3596 return r;
de7d789a
CO		 3597}
3598
851ba692 3599int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3600{
5fdbf976 3601 unsigned long val;
de7d789a 3602
f850e2e6
GN		 3603 trace_kvm_pio(!in, port, size, 1);
3604
de7d789a
CO		 3605 vcpu->run->exit_reason = KVM_EXIT_IO;
3606 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3607 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3608 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3609 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3610 vcpu->run->io.port = vcpu->arch.pio.port = port;
3611 vcpu->arch.pio.in = in;
3612 vcpu->arch.pio.string = 0;
3613 vcpu->arch.pio.down = 0;
ad312c7c 3614 vcpu->arch.pio.rep = 0;
de7d789a 3615
1976d2d2
TY		 3616 if (!vcpu->arch.pio.in) {
3617 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3618 memcpy(vcpu->arch.pio_data, &val, 4);
3619 }
de7d789a 3620
bda9020e 3621 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3622 complete_pio(vcpu);
3623 return 1;
3624 }
3625 return 0;
3626}
3627EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3628
851ba692 3629int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3630 int size, unsigned long count, int down,
3631 gva_t address, int rep, unsigned port)
3632{
3633 unsigned now, in_page;
0f346074 3634 int ret = 0;
de7d789a 3635
f850e2e6
GN		 3636 trace_kvm_pio(!in, port, size, count);
3637
de7d789a
CO		 3638 vcpu->run->exit_reason = KVM_EXIT_IO;
3639 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3640 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3641 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3642 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3643 vcpu->run->io.port = vcpu->arch.pio.port = port;
3644 vcpu->arch.pio.in = in;
3645 vcpu->arch.pio.string = 1;
3646 vcpu->arch.pio.down = down;
ad312c7c 3647 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3648
3649 if (!count) {
3650 kvm_x86_ops->skip_emulated_instruction(vcpu);
3651 return 1;
3652 }
3653
3654 if (!down)
3655 in_page = PAGE_SIZE - offset_in_page(address);
3656 else
3657 in_page = offset_in_page(address) + size;
3658 now = min(count, (unsigned long)in_page / size);
0f346074 3659 if (!now)
de7d789a 3660 now = 1;
de7d789a
CO		 3661 if (down) {
3662 /*
3663 * String I/O in reverse. Yuck. Kill the guest, fix later.
3664 */
3665 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3666 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3667 return 1;
3668 }
3669 vcpu->run->io.count = now;
ad312c7c 3670 vcpu->arch.pio.cur_count = now;
de7d789a 3671
ad312c7c 3672 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3673 kvm_x86_ops->skip_emulated_instruction(vcpu);
3674
0f346074 3675 vcpu->arch.pio.guest_gva = address;
de7d789a 3676
ad312c7c 3677 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3678 /* string PIO write */
3679 ret = pio_copy_data(vcpu);
1871c602 3680 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3681 return 1;
bda9020e 3682 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3683 complete_pio(vcpu);
ad312c7c 3684 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3685 ret = 1;
3686 }
bda9020e
MT		 3687 }
3688 /* no string PIO read support yet */
de7d789a
CO		 3689
3690 return ret;
3691}
3692EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3693
c8076604
GH		 3694static void bounce_off(void *info)
3695{
3696 /* nothing */
3697}
3698
c8076604
GH		 3699static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3700 void *data)
3701{
3702 struct cpufreq_freqs *freq = data;
3703 struct kvm *kvm;
3704 struct kvm_vcpu *vcpu;
3705 int i, send_ipi = 0;
3706
c8076604
GH		 3707 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3708 return 0;
3709 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3710 return 0;
0cca7907 3711 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3712
3713 spin_lock(&kvm_lock);
3714 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3715 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3716 if (vcpu->cpu != freq->cpu)
3717 continue;
3718 if (!kvm_request_guest_time_update(vcpu))
3719 continue;
3720 if (vcpu->cpu != smp_processor_id())
3721 send_ipi++;
3722 }
3723 }
3724 spin_unlock(&kvm_lock);
3725
3726 if (freq->old < freq->new && send_ipi) {
3727 /*
3728 * We upscale the frequency. Must make the guest
3729 * doesn't see old kvmclock values while running with
3730 * the new frequency, otherwise we risk the guest sees
3731 * time go backwards.
3732 *
3733 * In case we update the frequency for another cpu
3734 * (which might be in guest context) send an interrupt
3735 * to kick the cpu out of guest context. Next time
3736 * guest context is entered kvmclock will be updated,
3737 * so the guest will not see stale values.
3738 */
3739 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3740 }
3741 return 0;
3742}
3743
3744static struct notifier_block kvmclock_cpufreq_notifier_block = {
3745 .notifier_call = kvmclock_cpufreq_notifier
3746};
3747
b820cc0c
ZA		 3748static void kvm_timer_init(void)
3749{
3750 int cpu;
3751
b820cc0c 3752 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3753 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3754 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3755 for_each_online_cpu(cpu) {
3756 unsigned long khz = cpufreq_get(cpu);
3757 if (!khz)
3758 khz = tsc_khz;
3759 per_cpu(cpu_tsc_khz, cpu) = khz;
3760 }
0cca7907
ZA		 3761 } else {
3762 for_each_possible_cpu(cpu)
3763 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3764 }
3765}
3766
f8c16bba 3767int kvm_arch_init(void *opaque)
043405e1 3768{
b820cc0c 3769 int r;
f8c16bba
ZX		 3770 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3771
f8c16bba
ZX		 3772 if (kvm_x86_ops) {
3773 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3774 r = -EEXIST;
3775 goto out;
f8c16bba
ZX		 3776 }
3777
3778 if (!ops->cpu_has_kvm_support()) {
3779 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3780 r = -EOPNOTSUPP;
3781 goto out;
f8c16bba
ZX		 3782 }
3783 if (ops->disabled_by_bios()) {
3784 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3785 r = -EOPNOTSUPP;
3786 goto out;
f8c16bba
ZX		 3787 }
3788
97db56ce
AK		 3789 r = kvm_mmu_module_init();
3790 if (r)
3791 goto out;
3792
3793 kvm_init_msr_list();
3794
f8c16bba 3795 kvm_x86_ops = ops;
56c6d28a 3796 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3797 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3798 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3799 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3800
b820cc0c 3801 kvm_timer_init();
c8076604 3802
f8c16bba 3803 return 0;
56c6d28a
ZX		 3804
3805out:
56c6d28a 3806 return r;
043405e1 3807}
8776e519 3808
f8c16bba
ZX		 3809void kvm_arch_exit(void)
3810{
888d256e
JK		 3811 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3812 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3813 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3814 kvm_x86_ops = NULL;
56c6d28a
ZX		 3815 kvm_mmu_module_exit();
3816}
f8c16bba 3817
8776e519
HB		 3818int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3819{
3820 ++vcpu->stat.halt_exits;
3821 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3822 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3823 return 1;
3824 } else {
3825 vcpu->run->exit_reason = KVM_EXIT_HLT;
3826 return 0;
3827 }
3828}
3829EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3830
2f333bcb
MT		 3831static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3832 unsigned long a1)
3833{
3834 if (is_long_mode(vcpu))
3835 return a0;
3836 else
3837 return a0 | ((gpa_t)a1 << 32);
3838}
3839
55cd8e5a
GN		 3840int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3841{
3842 u64 param, ingpa, outgpa, ret;
3843 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3844 bool fast, longmode;
3845 int cs_db, cs_l;
3846
3847 /*
3848 * hypercall generates UD from non zero cpl and real mode
3849 * per HYPER-V spec
3850 */
3eeb3288 3851 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3852 kvm_queue_exception(vcpu, UD_VECTOR);
3853 return 0;
3854 }
3855
3856 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3857 longmode = is_long_mode(vcpu) && cs_l == 1;
3858
3859 if (!longmode) {
ccd46936
GN		 3860 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3861 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3862 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3863 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3864 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3865 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3866 }
3867#ifdef CONFIG_X86_64
3868 else {
3869 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3870 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3871 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3872 }
3873#endif
3874
3875 code = param & 0xffff;
3876 fast = (param >> 16) & 0x1;
3877 rep_cnt = (param >> 32) & 0xfff;
3878 rep_idx = (param >> 48) & 0xfff;
3879
3880 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3881
c25bc163
GN		 3882 switch (code) {
3883 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
3884 kvm_vcpu_on_spin(vcpu);
3885 break;
3886 default:
3887 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3888 break;
3889 }
55cd8e5a
GN		 3890
3891 ret = res | (((u64)rep_done & 0xfff) << 32);
3892 if (longmode) {
3893 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3894 } else {
3895 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3896 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3897 }
3898
3899 return 1;
3900}
3901
8776e519
HB		 3902int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3903{
3904 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3905 int r = 1;
8776e519 3906
55cd8e5a
GN		 3907 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3908 return kvm_hv_hypercall(vcpu);
3909
5fdbf976
MT		 3910 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3911 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3912 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3913 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3914 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3915
229456fc 3916 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3917
8776e519
HB		 3918 if (!is_long_mode(vcpu)) {
3919 nr &= 0xFFFFFFFF;
3920 a0 &= 0xFFFFFFFF;
3921 a1 &= 0xFFFFFFFF;
3922 a2 &= 0xFFFFFFFF;
3923 a3 &= 0xFFFFFFFF;
3924 }
3925
07708c4a
JK		 3926 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3927 ret = -KVM_EPERM;
3928 goto out;
3929 }
3930
8776e519 3931 switch (nr) {
b93463aa
AK		 3932 case KVM_HC_VAPIC_POLL_IRQ:
3933 ret = 0;
3934 break;
2f333bcb
MT		 3935 case KVM_HC_MMU_OP:
3936 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3937 break;
8776e519
HB		 3938 default:
3939 ret = -KVM_ENOSYS;
3940 break;
3941 }
07708c4a 3942out:
5fdbf976 3943 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3944 ++vcpu->stat.hypercalls;
2f333bcb 3945 return r;
8776e519
HB		 3946}
3947EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3948
3949int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3950{
3951 char instruction[3];
5fdbf976 3952 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3953
8776e519
HB		 3954 /*
3955 * Blow out the MMU to ensure that no other VCPU has an active mapping
3956 * to ensure that the updated hypercall appears atomically across all
3957 * VCPUs.
3958 */
3959 kvm_mmu_zap_all(vcpu->kvm);
3960
8776e519 3961 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 3962
7edcface 3963 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 3964}
3965
3966static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3967{
3968 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3969}
3970
3971void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3972{
3973 struct descriptor_table dt = { limit, base };
3974
3975 kvm_x86_ops->set_gdt(vcpu, &dt);
3976}
3977
3978void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3979{
3980 struct descriptor_table dt = { limit, base };
3981
3982 kvm_x86_ops->set_idt(vcpu, &dt);
3983}
3984
3985void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3986 unsigned long *rflags)
3987{
2d3ad1f4 3988 kvm_lmsw(vcpu, msw);
91586a3b 3989 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3990}
3991
3992unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3993{
54e445ca
JR		 3994 unsigned long value;
3995
8776e519
HB		 3996 switch (cr) {
3997 case 0:
4d4ec087 3998 value = kvm_read_cr0(vcpu);
54e445ca 3999 break;
8776e519 4000 case 2:
54e445ca
JR		 4001 value = vcpu->arch.cr2;
4002 break;
8776e519 4003 case 3:
54e445ca
JR		 4004 value = vcpu->arch.cr3;
4005 break;
8776e519 4006 case 4:
fc78f519 4007 value = kvm_read_cr4(vcpu);
54e445ca 4008 break;
152ff9be 4009 case 8:
54e445ca
JR		 4010 value = kvm_get_cr8(vcpu);
4011 break;
8776e519 4012 default:
b8688d51 4013 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4014 return 0;
4015 }
54e445ca
JR		 4016
4017 return value;
8776e519
HB		 4018}
4019
4020void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
4021 unsigned long *rflags)
4022{
4023 switch (cr) {
4024 case 0:
4d4ec087 4025 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 4026 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4027 break;
4028 case 2:
ad312c7c 4029 vcpu->arch.cr2 = val;
8776e519
HB		 4030 break;
4031 case 3:
2d3ad1f4 4032 kvm_set_cr3(vcpu, val);
8776e519
HB		 4033 break;
4034 case 4:
fc78f519 4035 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 4036 break;
152ff9be 4037 case 8:
2d3ad1f4 4038 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 4039 break;
8776e519 4040 default:
b8688d51 4041 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4042 }
4043}
4044
07716717
DK		 4045static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4046{
ad312c7c
ZX		 4047 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4048 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4049
4050 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4051 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4052 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4053 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4054 if (ej->function == e->function) {
4055 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4056 return j;
4057 }
4058 }
4059 return 0; /* silence gcc, even though control never reaches here */
4060}
4061
4062/* find an entry with matching function, matching index (if needed), and that
4063 * should be read next (if it's stateful) */
4064static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4065 u32 function, u32 index)
4066{
4067 if (e->function != function)
4068 return 0;
4069 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4070 return 0;
4071 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4072 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4073 return 0;
4074 return 1;
4075}
4076
d8017474
AG		 4077struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4078 u32 function, u32 index)
8776e519
HB		 4079{
4080 int i;
d8017474 4081 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4082
ad312c7c 4083 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4084 struct kvm_cpuid_entry2 *e;
4085
ad312c7c 4086 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4087 if (is_matching_cpuid_entry(e, function, index)) {
4088 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4089 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4090 best = e;
4091 break;
4092 }
4093 /*
4094 * Both basic or both extended?
4095 */
4096 if (((e->function ^ function) & 0x80000000) == 0)
4097 if (!best || e->function > best->function)
4098 best = e;
4099 }
d8017474
AG		 4100 return best;
4101}
0e851880 4102EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4103
82725b20
DE		 4104int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4105{
4106 struct kvm_cpuid_entry2 *best;
4107
4108 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4109 if (best)
4110 return best->eax & 0xff;
4111 return 36;
4112}
4113
d8017474
AG		 4114void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4115{
4116 u32 function, index;
4117 struct kvm_cpuid_entry2 *best;
4118
4119 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4120 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4121 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4122 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4123 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4124 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4125 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4126 if (best) {
5fdbf976
MT		 4127 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4128 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4129 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4130 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4131 }
8776e519 4132 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4133 trace_kvm_cpuid(function,
4134 kvm_register_read(vcpu, VCPU_REGS_RAX),
4135 kvm_register_read(vcpu, VCPU_REGS_RBX),
4136 kvm_register_read(vcpu, VCPU_REGS_RCX),
4137 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4138}
4139EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4140
b6c7a5dc
HB		 4141/*
4142 * Check if userspace requested an interrupt window, and that the
4143 * interrupt window is open.
4144 *
4145 * No need to exit to userspace if we already have an interrupt queued.
4146 */
851ba692 4147static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4148{
8061823a 4149 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4150 vcpu->run->request_interrupt_window &&
5df56646 4151 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4152}
4153
851ba692 4154static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4155{
851ba692
AK		 4156 struct kvm_run *kvm_run = vcpu->run;
4157
91586a3b 4158 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4159 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4160 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4161 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4162 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4163 else
b6c7a5dc 4164 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4165 kvm_arch_interrupt_allowed(vcpu) &&
4166 !kvm_cpu_has_interrupt(vcpu) &&
4167 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4168}
4169
b93463aa
AK		 4170static void vapic_enter(struct kvm_vcpu *vcpu)
4171{
4172 struct kvm_lapic *apic = vcpu->arch.apic;
4173 struct page *page;
4174
4175 if (!apic || !apic->vapic_addr)
4176 return;
4177
4178 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4179
4180 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4181}
4182
4183static void vapic_exit(struct kvm_vcpu *vcpu)
4184{
4185 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4186 int idx;
b93463aa
AK		 4187
4188 if (!apic || !apic->vapic_addr)
4189 return;
4190
f656ce01 4191 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4192 kvm_release_page_dirty(apic->vapic_page);
4193 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4194 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4195}
4196
95ba8273
GN		 4197static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4198{
4199 int max_irr, tpr;
4200
4201 if (!kvm_x86_ops->update_cr8_intercept)
4202 return;
4203
88c808fd
AK		 4204 if (!vcpu->arch.apic)
4205 return;
4206
8db3baa2
GN		 4207 if (!vcpu->arch.apic->vapic_addr)
4208 max_irr = kvm_lapic_find_highest_irr(vcpu);
4209 else
4210 max_irr = -1;
95ba8273
GN		 4211
4212 if (max_irr != -1)
4213 max_irr >>= 4;
4214
4215 tpr = kvm_lapic_get_cr8(vcpu);
4216
4217 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4218}
4219
851ba692 4220static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4221{
4222 /* try to reinject previous events if any */
b59bb7bd
GN		 4223 if (vcpu->arch.exception.pending) {
4224 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4225 vcpu->arch.exception.has_error_code,
4226 vcpu->arch.exception.error_code);
4227 return;
4228 }
4229
95ba8273
GN		 4230 if (vcpu->arch.nmi_injected) {
4231 kvm_x86_ops->set_nmi(vcpu);
4232 return;
4233 }
4234
4235 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4236 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4237 return;
4238 }
4239
4240 /* try to inject new event if pending */
4241 if (vcpu->arch.nmi_pending) {
4242 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4243 vcpu->arch.nmi_pending = false;
4244 vcpu->arch.nmi_injected = true;
4245 kvm_x86_ops->set_nmi(vcpu);
4246 }
4247 } else if (kvm_cpu_has_interrupt(vcpu)) {
4248 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4249 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4250 false);
4251 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4252 }
4253 }
4254}
4255
851ba692 4256static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4257{
4258 int r;
6a8b1d13 4259 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4260 vcpu->run->request_interrupt_window;
b6c7a5dc 4261
2e53d63a
MT		 4262 if (vcpu->requests)
4263 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4264 kvm_mmu_unload(vcpu);
4265
b6c7a5dc
HB		 4266 r = kvm_mmu_reload(vcpu);
4267 if (unlikely(r))
4268 goto out;
4269
2f52d58c
AK		 4270 if (vcpu->requests) {
4271 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4272 __kvm_migrate_timers(vcpu);
c8076604
GH		 4273 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4274 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4275 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4276 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4277 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4278 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4279 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4280 &vcpu->requests)) {
851ba692 4281 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4282 r = 0;
4283 goto out;
4284 }
71c4dfaf 4285 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4286 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4287 r = 0;
4288 goto out;
4289 }
02daab21
AK		 4290 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4291 vcpu->fpu_active = 0;
4292 kvm_x86_ops->fpu_deactivate(vcpu);
4293 }
2f52d58c 4294 }
b93463aa 4295
b6c7a5dc
HB		 4296 preempt_disable();
4297
4298 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4299 if (vcpu->fpu_active)
4300 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4301
4302 local_irq_disable();
4303
32f88400
MT		 4304 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4305 smp_mb__after_clear_bit();
4306
d7690175 4307 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4308 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4309 local_irq_enable();
4310 preempt_enable();
4311 r = 1;
4312 goto out;
4313 }
4314
851ba692 4315 inject_pending_event(vcpu);
b6c7a5dc 4316
6a8b1d13
GN		 4317 /* enable NMI/IRQ window open exits if needed */
4318 if (vcpu->arch.nmi_pending)
4319 kvm_x86_ops->enable_nmi_window(vcpu);
4320 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4321 kvm_x86_ops->enable_irq_window(vcpu);
4322
95ba8273 4323 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4324 update_cr8_intercept(vcpu);
4325 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4326 }
b93463aa 4327
f656ce01 4328 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4329
b6c7a5dc
HB		 4330 kvm_guest_enter();
4331
42dbaa5a 4332 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4333 set_debugreg(0, 7);
4334 set_debugreg(vcpu->arch.eff_db[0], 0);
4335 set_debugreg(vcpu->arch.eff_db[1], 1);
4336 set_debugreg(vcpu->arch.eff_db[2], 2);
4337 set_debugreg(vcpu->arch.eff_db[3], 3);
4338 }
b6c7a5dc 4339
229456fc 4340 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4341 kvm_x86_ops->run(vcpu);
b6c7a5dc 4342
24f1e32c
FW		 4343 /*
4344 * If the guest has used debug registers, at least dr7
4345 * will be disabled while returning to the host.
4346 * If we don't have active breakpoints in the host, we don't
4347 * care about the messed up debug address registers. But if
4348 * we have some of them active, restore the old state.
4349 */
59d8eb53 4350 if (hw_breakpoint_active())
24f1e32c 4351 hw_breakpoint_restore();
42dbaa5a 4352
32f88400 4353 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4354 local_irq_enable();
4355
4356 ++vcpu->stat.exits;
4357
4358 /*
4359 * We must have an instruction between local_irq_enable() and
4360 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4361 * the interrupt shadow. The stat.exits increment will do nicely.
4362 * But we need to prevent reordering, hence this barrier():
4363 */
4364 barrier();
4365
4366 kvm_guest_exit();
4367
4368 preempt_enable();
4369
f656ce01 4370 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4371
b6c7a5dc
HB		 4372 /*
4373 * Profile KVM exit RIPs:
4374 */
4375 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4376 unsigned long rip = kvm_rip_read(vcpu);
4377 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4378 }
4379
298101da 4380
b93463aa
AK		 4381 kvm_lapic_sync_from_vapic(vcpu);
4382
851ba692 4383 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4384out:
4385 return r;
4386}
b6c7a5dc 4387
09cec754 4388
851ba692 4389static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4390{
4391 int r;
f656ce01 4392 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4393
4394 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4395 pr_debug("vcpu %d received sipi with vector # %x\n",
4396 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4397 kvm_lapic_reset(vcpu);
5f179287 4398 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4399 if (r)
4400 return r;
4401 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4402 }
4403
f656ce01 4404 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4405 vapic_enter(vcpu);
4406
4407 r = 1;
4408 while (r > 0) {
af2152f5 4409 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4410 r = vcpu_enter_guest(vcpu);
d7690175 4411 else {
f656ce01 4412 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4413 kvm_vcpu_block(vcpu);
f656ce01 4414 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4415 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4416 {
4417 switch(vcpu->arch.mp_state) {
4418 case KVM_MP_STATE_HALTED:
d7690175 4419 vcpu->arch.mp_state =
09cec754
GN		 4420 KVM_MP_STATE_RUNNABLE;
4421 case KVM_MP_STATE_RUNNABLE:
4422 break;
4423 case KVM_MP_STATE_SIPI_RECEIVED:
4424 default:
4425 r = -EINTR;
4426 break;
4427 }
4428 }
d7690175
MT		 4429 }
4430
09cec754
GN		 4431 if (r <= 0)
4432 break;
4433
4434 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4435 if (kvm_cpu_has_pending_timer(vcpu))
4436 kvm_inject_pending_timer_irqs(vcpu);
4437
851ba692 4438 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4439 r = -EINTR;
851ba692 4440 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4441 ++vcpu->stat.request_irq_exits;
4442 }
4443 if (signal_pending(current)) {
4444 r = -EINTR;
851ba692 4445 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4446 ++vcpu->stat.signal_exits;
4447 }
4448 if (need_resched()) {
f656ce01 4449 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4450 kvm_resched(vcpu);
f656ce01 4451 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4452 }
b6c7a5dc
HB		 4453 }
4454
f656ce01 4455 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4456 post_kvm_run_save(vcpu);
b6c7a5dc 4457
b93463aa
AK		 4458 vapic_exit(vcpu);
4459
b6c7a5dc
HB		 4460 return r;
4461}
4462
4463int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4464{
4465 int r;
4466 sigset_t sigsaved;
4467
4468 vcpu_load(vcpu);
4469
ac9f6dc0
AK		 4470 if (vcpu->sigset_active)
4471 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4472
a4535290 4473 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4474 kvm_vcpu_block(vcpu);
d7690175 4475 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4476 r = -EAGAIN;
4477 goto out;
b6c7a5dc
HB		 4478 }
4479
b6c7a5dc
HB		 4480 /* re-sync apic's tpr */
4481 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4482 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4483
ad312c7c 4484 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4485 r = complete_pio(vcpu);
4486 if (r)
4487 goto out;
4488 }
b6c7a5dc
HB		 4489 if (vcpu->mmio_needed) {
4490 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4491 vcpu->mmio_read_completed = 1;
4492 vcpu->mmio_needed = 0;
3200f405 4493
f656ce01 4494 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4495 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4496 EMULTYPE_NO_DECODE);
f656ce01 4497 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4498 if (r == EMULATE_DO_MMIO) {
4499 /*
4500 * Read-modify-write. Back to userspace.
4501 */
4502 r = 0;
4503 goto out;
4504 }
4505 }
5fdbf976
MT		 4506 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4507 kvm_register_write(vcpu, VCPU_REGS_RAX,
4508 kvm_run->hypercall.ret);
b6c7a5dc 4509
851ba692 4510 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4511
4512out:
4513 if (vcpu->sigset_active)
4514 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4515
4516 vcpu_put(vcpu);
4517 return r;
4518}
4519
4520int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4521{
4522 vcpu_load(vcpu);
4523
5fdbf976
MT		 4524 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4525 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4526 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4527 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4528 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4529 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4530 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4531 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4532#ifdef CONFIG_X86_64
5fdbf976
MT		 4533 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4534 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4535 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4536 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4537 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4538 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4539 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4540 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4541#endif
4542
5fdbf976 4543 regs->rip = kvm_rip_read(vcpu);
91586a3b 4544 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4545
4546 vcpu_put(vcpu);
4547
4548 return 0;
4549}
4550
4551int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4552{
4553 vcpu_load(vcpu);
4554
5fdbf976
MT		 4555 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4556 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4557 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4558 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4559 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4560 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4561 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4562 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4563#ifdef CONFIG_X86_64
5fdbf976
MT		 4564 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4565 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4566 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4567 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4568 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4569 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4570 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4571 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4572#endif
4573
5fdbf976 4574 kvm_rip_write(vcpu, regs->rip);
91586a3b 4575 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4576
b4f14abd
JK		 4577 vcpu->arch.exception.pending = false;
4578
b6c7a5dc
HB		 4579 vcpu_put(vcpu);
4580
4581 return 0;
4582}
4583
3e6e0aab
GT		 4584void kvm_get_segment(struct kvm_vcpu *vcpu,
4585 struct kvm_segment *var, int seg)
b6c7a5dc 4586{
14af3f3c 4587 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4588}
4589
4590void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4591{
4592 struct kvm_segment cs;
4593
3e6e0aab 4594 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4595 *db = cs.db;
4596 *l = cs.l;
4597}
4598EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4599
4600int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4601 struct kvm_sregs *sregs)
4602{
4603 struct descriptor_table dt;
b6c7a5dc
HB		 4604
4605 vcpu_load(vcpu);
4606
3e6e0aab
GT		 4607 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4608 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4609 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4610 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4611 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4612 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4613
3e6e0aab
GT		 4614 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4615 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4616
4617 kvm_x86_ops->get_idt(vcpu, &dt);
4618 sregs->idt.limit = dt.limit;
4619 sregs->idt.base = dt.base;
4620 kvm_x86_ops->get_gdt(vcpu, &dt);
4621 sregs->gdt.limit = dt.limit;
4622 sregs->gdt.base = dt.base;
4623
4d4ec087 4624 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4625 sregs->cr2 = vcpu->arch.cr2;
4626 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4627 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4628 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4629 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4630 sregs->apic_base = kvm_get_apic_base(vcpu);
4631
923c61bb 4632 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4633
36752c9b 4634 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4635 set_bit(vcpu->arch.interrupt.nr,
4636 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4637
b6c7a5dc
HB		 4638 vcpu_put(vcpu);
4639
4640 return 0;
4641}
4642
62d9f0db
MT		 4643int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4644 struct kvm_mp_state *mp_state)
4645{
4646 vcpu_load(vcpu);
4647 mp_state->mp_state = vcpu->arch.mp_state;
4648 vcpu_put(vcpu);
4649 return 0;
4650}
4651
4652int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4653 struct kvm_mp_state *mp_state)
4654{
4655 vcpu_load(vcpu);
4656 vcpu->arch.mp_state = mp_state->mp_state;
4657 vcpu_put(vcpu);
4658 return 0;
4659}
4660
3e6e0aab 4661static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4662 struct kvm_segment *var, int seg)
4663{
14af3f3c 4664 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4665}
4666
37817f29
IE		 4667static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4668 struct kvm_segment *kvm_desct)
4669{
46a359e7
AM		 4670 kvm_desct->base = get_desc_base(seg_desc);
4671 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4672 if (seg_desc->g) {
4673 kvm_desct->limit <<= 12;
4674 kvm_desct->limit |= 0xfff;
4675 }
37817f29
IE		 4676 kvm_desct->selector = selector;
4677 kvm_desct->type = seg_desc->type;
4678 kvm_desct->present = seg_desc->p;
4679 kvm_desct->dpl = seg_desc->dpl;
4680 kvm_desct->db = seg_desc->d;
4681 kvm_desct->s = seg_desc->s;
4682 kvm_desct->l = seg_desc->l;
4683 kvm_desct->g = seg_desc->g;
4684 kvm_desct->avl = seg_desc->avl;
4685 if (!selector)
4686 kvm_desct->unusable = 1;
4687 else
4688 kvm_desct->unusable = 0;
4689 kvm_desct->padding = 0;
4690}
4691
b8222ad2
AS		 4692static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4693 u16 selector,
4694 struct descriptor_table *dtable)
37817f29
IE		 4695{
4696 if (selector & 1 << 2) {
4697 struct kvm_segment kvm_seg;
4698
3e6e0aab 4699 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4700
4701 if (kvm_seg.unusable)
4702 dtable->limit = 0;
4703 else
4704 dtable->limit = kvm_seg.limit;
4705 dtable->base = kvm_seg.base;
4706 }
4707 else
4708 kvm_x86_ops->get_gdt(vcpu, dtable);
4709}
4710
4711/* allowed just for 8 bytes segments */
4712static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4713 struct desc_struct *seg_desc)
4714{
4715 struct descriptor_table dtable;
4716 u16 index = selector >> 3;
6f550484
TY		 4717 int ret;
4718 u32 err;
4719 gva_t addr;
37817f29 4720
b8222ad2 4721 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4722
4723 if (dtable.limit < index * 8 + 7) {
4724 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4725 return X86EMUL_PROPAGATE_FAULT;
37817f29 4726 }
6f550484
TY		 4727 addr = dtable.base + index * 8;
4728 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4729 vcpu, &err);
4730 if (ret == X86EMUL_PROPAGATE_FAULT)
4731 kvm_inject_page_fault(vcpu, addr, err);
4732
4733 return ret;
37817f29
IE		 4734}
4735
4736/* allowed just for 8 bytes segments */
4737static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4738 struct desc_struct *seg_desc)
4739{
4740 struct descriptor_table dtable;
4741 u16 index = selector >> 3;
4742
b8222ad2 4743 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4744
4745 if (dtable.limit < index * 8 + 7)
4746 return 1;
1871c602
GN		 4747 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
4748}
4749
4750static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4751 struct desc_struct *seg_desc)
4752{
4753 u32 base_addr = get_desc_base(seg_desc);
4754
4755 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4756}
4757
1871c602 4758static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4759 struct desc_struct *seg_desc)
4760{
46a359e7 4761 u32 base_addr = get_desc_base(seg_desc);
37817f29 4762
1871c602 4763 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4764}
4765
37817f29
IE		 4766static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4767{
4768 struct kvm_segment kvm_seg;
4769
3e6e0aab 4770 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4771 return kvm_seg.selector;
4772}
4773
2259e3a7 4774static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4775{
4776 struct kvm_segment segvar = {
4777 .base = selector << 4,
4778 .limit = 0xffff,
4779 .selector = selector,
4780 .type = 3,
4781 .present = 1,
4782 .dpl = 3,
4783 .db = 0,
4784 .s = 1,
4785 .l = 0,
4786 .g = 0,
4787 .avl = 0,
4788 .unusable = 0,
4789 };
4790 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4791 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4792}
4793
c0c7c04b
AL		 4794static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4795{
4796 return (seg != VCPU_SREG_LDTR) &&
4797 (seg != VCPU_SREG_TR) &&
91586a3b 4798 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4799}
4800
c697518a 4801int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4802{
4803 struct kvm_segment kvm_seg;
e01c2426 4804 struct desc_struct seg_desc;
c697518a
GN		 4805 u8 dpl, rpl, cpl;
4806 unsigned err_vec = GP_VECTOR;
4807 u32 err_code = 0;
4808 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4809 int ret;
37817f29 4810
3eeb3288 4811 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4812 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4813
c697518a
GN		 4814 /* NULL selector is not valid for TR, CS and SS */
4815 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4816 && null_selector)
4817 goto exception;
4818
4819 /* TR should be in GDT only */
4820 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4821 goto exception;
4822
4823 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4824 if (ret)
4825 return ret;
4826
e01c2426 4827 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4828
c697518a
GN		 4829 if (null_selector) { /* for NULL selector skip all following checks */
4830 kvm_seg.unusable = 1;
4831 goto load;
4832 }
37817f29 4833
c697518a
GN		 4834 err_code = selector & 0xfffc;
4835 err_vec = GP_VECTOR;
37817f29 4836
c697518a
GN		 4837 /* can't load system descriptor into segment selecor */
4838 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4839 goto exception;
4840
4841 if (!kvm_seg.present) {
4842 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4843 goto exception;
4844 }
4845
4846 rpl = selector & 3;
4847 dpl = kvm_seg.dpl;
4848 cpl = kvm_x86_ops->get_cpl(vcpu);
4849
4850 switch (seg) {
4851 case VCPU_SREG_SS:
4852 /*
4853 * segment is not a writable data segment or segment
4854 * selector's RPL != CPL or segment selector's RPL != CPL
4855 */
4856 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4857 goto exception;
4858 break;
4859 case VCPU_SREG_CS:
4860 if (!(kvm_seg.type & 8))
4861 goto exception;
4862
4863 if (kvm_seg.type & 4) {
4864 /* conforming */
4865 if (dpl > cpl)
4866 goto exception;
4867 } else {
4868 /* nonconforming */
4869 if (rpl > cpl || dpl != cpl)
4870 goto exception;
4871 }
4872 /* CS(RPL) <- CPL */
4873 selector = (selector & 0xfffc) | cpl;
4874 break;
4875 case VCPU_SREG_TR:
4876 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4877 goto exception;
4878 break;
4879 case VCPU_SREG_LDTR:
4880 if (kvm_seg.s || kvm_seg.type != 2)
4881 goto exception;
4882 break;
4883 default: /* DS, ES, FS, or GS */
4884 /*
4885 * segment is not a data or readable code segment or
4886 * ((segment is a data or nonconforming code segment)
4887 * and (both RPL and CPL > DPL))
4888 */
4889 if ((kvm_seg.type & 0xa) == 0x8 ||
4890 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4891 goto exception;
4892 break;
4893 }
4894
4895 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4896 /* mark segment as accessed */
c697518a 4897 kvm_seg.type |= 1;
e01c2426
GN		 4898 seg_desc.type |= 1;
4899 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4900 }
c697518a
GN		 4901load:
4902 kvm_set_segment(vcpu, &kvm_seg, seg);
4903 return X86EMUL_CONTINUE;
4904exception:
4905 kvm_queue_exception_e(vcpu, err_vec, err_code);
4906 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4907}
4908
4909static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4910 struct tss_segment_32 *tss)
4911{
4912 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4913 tss->eip = kvm_rip_read(vcpu);
91586a3b 4914 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4915 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4916 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4917 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4918 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4919 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4920 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4921 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4922 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4923 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4924 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4925 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4926 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4927 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4928 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4929 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4930}
4931
c697518a
GN		 4932static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4933{
4934 struct kvm_segment kvm_seg;
4935 kvm_get_segment(vcpu, &kvm_seg, seg);
4936 kvm_seg.selector = sel;
4937 kvm_set_segment(vcpu, &kvm_seg, seg);
4938}
4939
37817f29
IE		 4940static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4941 struct tss_segment_32 *tss)
4942{
4943 kvm_set_cr3(vcpu, tss->cr3);
4944
5fdbf976 4945 kvm_rip_write(vcpu, tss->eip);
91586a3b 4946 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4947
5fdbf976
MT		 4948 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4949 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4950 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4951 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4952 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4953 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4954 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4955 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4956
c697518a
GN		 4957 /*
4958 * SDM says that segment selectors are loaded before segment
4959 * descriptors
4960 */
4961 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
4962 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
4963 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
4964 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
4965 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
4966 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
4967 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
4968
4969 /*
4970 * Now load segment descriptors. If fault happenes at this stage
4971 * it is handled in a context of new task
4972 */
4973 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 4974 return 1;
4975
c697518a 4976 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 4977 return 1;
4978
c697518a 4979 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 4980 return 1;
4981
c697518a 4982 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 4983 return 1;
4984
c697518a 4985 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 4986 return 1;
4987
c697518a 4988 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 4989 return 1;
4990
c697518a 4991 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 4992 return 1;
4993 return 0;
4994}
4995
4996static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4997 struct tss_segment_16 *tss)
4998{
5fdbf976 4999 tss->ip = kvm_rip_read(vcpu);
91586a3b 5000 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 5001 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5002 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5003 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5004 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5005 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5006 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5007 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
5008 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 5009
5010 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
5011 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
5012 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
5013 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
5014 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 5015}
5016
5017static int load_state_from_tss16(struct kvm_vcpu *vcpu,
5018 struct tss_segment_16 *tss)
5019{
5fdbf976 5020 kvm_rip_write(vcpu, tss->ip);
91586a3b 5021 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 5022 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
5023 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5024 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5025 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5026 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5027 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5028 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5029 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5030
c697518a
GN		 5031 /*
5032 * SDM says that segment selectors are loaded before segment
5033 * descriptors
5034 */
5035 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5036 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5037 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5038 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5039 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5040
5041 /*
5042 * Now load segment descriptors. If fault happenes at this stage
5043 * it is handled in a context of new task
5044 */
5045 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5046 return 1;
5047
c697518a 5048 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5049 return 1;
5050
c697518a 5051 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5052 return 1;
5053
c697518a 5054 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5055 return 1;
5056
c697518a 5057 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5058 return 1;
5059 return 0;
5060}
5061
8b2cf73c 5062static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5063 u16 old_tss_sel, u32 old_tss_base,
5064 struct desc_struct *nseg_desc)
37817f29
IE		 5065{
5066 struct tss_segment_16 tss_segment_16;
5067 int ret = 0;
5068
34198bf8
MT		 5069 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5070 sizeof tss_segment_16))
37817f29
IE		 5071 goto out;
5072
5073 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5074
34198bf8
MT		 5075 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5076 sizeof tss_segment_16))
37817f29 5077 goto out;
34198bf8 5078
1871c602 5079 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5080 &tss_segment_16, sizeof tss_segment_16))
5081 goto out;
5082
b237ac37
GN		 5083 if (old_tss_sel != 0xffff) {
5084 tss_segment_16.prev_task_link = old_tss_sel;
5085
5086 if (kvm_write_guest(vcpu->kvm,
1871c602 5087 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5088 &tss_segment_16.prev_task_link,
5089 sizeof tss_segment_16.prev_task_link))
5090 goto out;
5091 }
5092
37817f29
IE		 5093 if (load_state_from_tss16(vcpu, &tss_segment_16))
5094 goto out;
5095
5096 ret = 1;
5097out:
5098 return ret;
5099}
5100
8b2cf73c 5101static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5102 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5103 struct desc_struct *nseg_desc)
5104{
5105 struct tss_segment_32 tss_segment_32;
5106 int ret = 0;
5107
34198bf8
MT		 5108 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5109 sizeof tss_segment_32))
37817f29
IE		 5110 goto out;
5111
5112 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5113
34198bf8
MT		 5114 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5115 sizeof tss_segment_32))
5116 goto out;
5117
1871c602 5118 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5119 &tss_segment_32, sizeof tss_segment_32))
37817f29 5120 goto out;
34198bf8 5121
b237ac37
GN		 5122 if (old_tss_sel != 0xffff) {
5123 tss_segment_32.prev_task_link = old_tss_sel;
5124
5125 if (kvm_write_guest(vcpu->kvm,
1871c602 5126 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5127 &tss_segment_32.prev_task_link,
5128 sizeof tss_segment_32.prev_task_link))
5129 goto out;
5130 }
5131
37817f29
IE		 5132 if (load_state_from_tss32(vcpu, &tss_segment_32))
5133 goto out;
5134
5135 ret = 1;
5136out:
5137 return ret;
5138}
5139
5140int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5141{
5142 struct kvm_segment tr_seg;
5143 struct desc_struct cseg_desc;
5144 struct desc_struct nseg_desc;
5145 int ret = 0;
34198bf8
MT		 5146 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5147 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 5148
1871c602 5149 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5150
34198bf8
MT		 5151 /* FIXME: Handle errors. Failure to read either TSS or their
5152 * descriptors should generate a pagefault.
5153 */
37817f29
IE		 5154 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5155 goto out;
5156
34198bf8 5157 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5158 goto out;
5159
37817f29
IE		 5160 if (reason != TASK_SWITCH_IRET) {
5161 int cpl;
5162
5163 cpl = kvm_x86_ops->get_cpl(vcpu);
5164 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5165 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5166 return 1;
5167 }
5168 }
5169
46a359e7 5170 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 5171 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5172 return 1;
5173 }
5174
5175 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5176 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5177 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5178 }
5179
5180 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5181 u32 eflags = kvm_get_rflags(vcpu);
5182 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5183 }
5184
b237ac37
GN		 5185 /* set back link to prev task only if NT bit is set in eflags
5186 note that old_tss_sel is not used afetr this point */
5187 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5188 old_tss_sel = 0xffff;
5189
37817f29 5190 if (nseg_desc.type & 8)
b237ac37
GN		 5191 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5192 old_tss_base, &nseg_desc);
37817f29 5193 else
b237ac37
GN		 5194 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5195 old_tss_base, &nseg_desc);
37817f29
IE		 5196
5197 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5198 u32 eflags = kvm_get_rflags(vcpu);
5199 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5200 }
5201
5202 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5203 nseg_desc.type |= (1 << 1);
37817f29
IE		 5204 save_guest_segment_descriptor(vcpu, tss_selector,
5205 &nseg_desc);
5206 }
5207
4d4ec087 5208 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5209 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5210 tr_seg.type = 11;
3e6e0aab 5211 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5212out:
37817f29
IE		 5213 return ret;
5214}
5215EXPORT_SYMBOL_GPL(kvm_task_switch);
5216
b6c7a5dc
HB		 5217int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5218 struct kvm_sregs *sregs)
5219{
5220 int mmu_reset_needed = 0;
923c61bb 5221 int pending_vec, max_bits;
b6c7a5dc
HB		 5222 struct descriptor_table dt;
5223
5224 vcpu_load(vcpu);
5225
5226 dt.limit = sregs->idt.limit;
5227 dt.base = sregs->idt.base;
5228 kvm_x86_ops->set_idt(vcpu, &dt);
5229 dt.limit = sregs->gdt.limit;
5230 dt.base = sregs->gdt.base;
5231 kvm_x86_ops->set_gdt(vcpu, &dt);
5232
ad312c7c
ZX		 5233 vcpu->arch.cr2 = sregs->cr2;
5234 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5235 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5236
2d3ad1f4 5237 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5238
f6801dff 5239 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5240 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5241 kvm_set_apic_base(vcpu, sregs->apic_base);
5242
4d4ec087 5243 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5244 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5245 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5246
fc78f519 5247 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5248 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5249 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5250 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5251 mmu_reset_needed = 1;
5252 }
b6c7a5dc
HB		 5253
5254 if (mmu_reset_needed)
5255 kvm_mmu_reset_context(vcpu);
5256
923c61bb
GN		 5257 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5258 pending_vec = find_first_bit(
5259 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5260 if (pending_vec < max_bits) {
66fd3f7f 5261 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5262 pr_debug("Set back pending irq %d\n", pending_vec);
5263 if (irqchip_in_kernel(vcpu->kvm))
5264 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5265 }
5266
3e6e0aab
GT		 5267 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5268 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5269 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5270 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5271 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5272 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5273
3e6e0aab
GT		 5274 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5275 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5276
5f0269f5
ME		 5277 update_cr8_intercept(vcpu);
5278
9c3e4aab 5279 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5280 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5281 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5282 !is_protmode(vcpu))
9c3e4aab
MT		 5283 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5284
b6c7a5dc
HB		 5285 vcpu_put(vcpu);
5286
5287 return 0;
5288}
5289
d0bfb940
JK		 5290int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5291 struct kvm_guest_debug *dbg)
b6c7a5dc 5292{
355be0b9 5293 unsigned long rflags;
ae675ef0 5294 int i, r;
b6c7a5dc
HB		 5295
5296 vcpu_load(vcpu);
5297
4f926bf2
JK		 5298 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5299 r = -EBUSY;
5300 if (vcpu->arch.exception.pending)
5301 goto unlock_out;
5302 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5303 kvm_queue_exception(vcpu, DB_VECTOR);
5304 else
5305 kvm_queue_exception(vcpu, BP_VECTOR);
5306 }
5307
91586a3b
JK		 5308 /*
5309 * Read rflags as long as potentially injected trace flags are still
5310 * filtered out.
5311 */
5312 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5313
5314 vcpu->guest_debug = dbg->control;
5315 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5316 vcpu->guest_debug = 0;
5317
5318 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5319 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5320 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5321 vcpu->arch.switch_db_regs =
5322 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5323 } else {
5324 for (i = 0; i < KVM_NR_DB_REGS; i++)
5325 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5326 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5327 }
5328
94fe45da
JK		 5329 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5330 vcpu->arch.singlestep_cs =
5331 get_segment_selector(vcpu, VCPU_SREG_CS);
5332 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
5333 }
5334
91586a3b
JK		 5335 /*
5336 * Trigger an rflags update that will inject or remove the trace
5337 * flags.
5338 */
5339 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5340
355be0b9 5341 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5342
4f926bf2 5343 r = 0;
d0bfb940 5344
4f926bf2 5345unlock_out:
b6c7a5dc
HB		 5346 vcpu_put(vcpu);
5347
5348 return r;
5349}
5350
d0752060
HB		 5351/*
5352 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5353 * we have asm/x86/processor.h
5354 */
5355struct fxsave {
5356 u16 cwd;
5357 u16 swd;
5358 u16 twd;
5359 u16 fop;
5360 u64 rip;
5361 u64 rdp;
5362 u32 mxcsr;
5363 u32 mxcsr_mask;
5364 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5365#ifdef CONFIG_X86_64
5366 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5367#else
5368 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5369#endif
5370};
5371
8b006791
ZX		 5372/*
5373 * Translate a guest virtual address to a guest physical address.
5374 */
5375int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5376 struct kvm_translation *tr)
5377{
5378 unsigned long vaddr = tr->linear_address;
5379 gpa_t gpa;
f656ce01 5380 int idx;
8b006791
ZX		 5381
5382 vcpu_load(vcpu);
f656ce01 5383 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5384 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5385 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5386 tr->physical_address = gpa;
5387 tr->valid = gpa != UNMAPPED_GVA;
5388 tr->writeable = 1;
5389 tr->usermode = 0;
8b006791
ZX		 5390 vcpu_put(vcpu);
5391
5392 return 0;
5393}
5394
d0752060
HB		 5395int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5396{
ad312c7c 5397 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5398
5399 vcpu_load(vcpu);
5400
5401 memcpy(fpu->fpr, fxsave->st_space, 128);
5402 fpu->fcw = fxsave->cwd;
5403 fpu->fsw = fxsave->swd;
5404 fpu->ftwx = fxsave->twd;
5405 fpu->last_opcode = fxsave->fop;
5406 fpu->last_ip = fxsave->rip;
5407 fpu->last_dp = fxsave->rdp;
5408 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5409
5410 vcpu_put(vcpu);
5411
5412 return 0;
5413}
5414
5415int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5416{
ad312c7c 5417 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5418
5419 vcpu_load(vcpu);
5420
5421 memcpy(fxsave->st_space, fpu->fpr, 128);
5422 fxsave->cwd = fpu->fcw;
5423 fxsave->swd = fpu->fsw;
5424 fxsave->twd = fpu->ftwx;
5425 fxsave->fop = fpu->last_opcode;
5426 fxsave->rip = fpu->last_ip;
5427 fxsave->rdp = fpu->last_dp;
5428 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5429
5430 vcpu_put(vcpu);
5431
5432 return 0;
5433}
5434
5435void fx_init(struct kvm_vcpu *vcpu)
5436{
5437 unsigned after_mxcsr_mask;
5438
bc1a34f1
AA		 5439 /*
5440 * Touch the fpu the first time in non atomic context as if
5441 * this is the first fpu instruction the exception handler
5442 * will fire before the instruction returns and it'll have to
5443 * allocate ram with GFP_KERNEL.
5444 */
5445 if (!used_math())
d6e88aec 5446 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5447
d0752060
HB		 5448 /* Initialize guest FPU by resetting ours and saving into guest's */
5449 preempt_disable();
d6e88aec
AK		 5450 kvm_fx_save(&vcpu->arch.host_fx_image);
5451 kvm_fx_finit();
5452 kvm_fx_save(&vcpu->arch.guest_fx_image);
5453 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5454 preempt_enable();
5455
ad312c7c 5456 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5457 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5458 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5459 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5460 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5461}
5462EXPORT_SYMBOL_GPL(fx_init);
5463
5464void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5465{
2608d7a1 5466 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5467 return;
5468
5469 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5470 kvm_fx_save(&vcpu->arch.host_fx_image);
5471 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5472 trace_kvm_fpu(1);
d0752060 5473}
d0752060
HB		 5474
5475void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5476{
5477 if (!vcpu->guest_fpu_loaded)
5478 return;
5479
5480 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5481 kvm_fx_save(&vcpu->arch.guest_fx_image);
5482 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5483 ++vcpu->stat.fpu_reload;
02daab21 5484 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5485 trace_kvm_fpu(0);
d0752060 5486}
e9b11c17
ZX		 5487
5488void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5489{
7f1ea208
JR		 5490 if (vcpu->arch.time_page) {
5491 kvm_release_page_dirty(vcpu->arch.time_page);
5492 vcpu->arch.time_page = NULL;
5493 }
5494
e9b11c17
ZX		 5495 kvm_x86_ops->vcpu_free(vcpu);
5496}
5497
5498struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5499 unsigned int id)
5500{
26e5215f
AK		 5501 return kvm_x86_ops->vcpu_create(kvm, id);
5502}
e9b11c17 5503
26e5215f
AK		 5504int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5505{
5506 int r;
e9b11c17
ZX		 5507
5508 /* We do fxsave: this must be aligned. */
ad312c7c 5509 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5510
0bed3b56 5511 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5512 vcpu_load(vcpu);
5513 r = kvm_arch_vcpu_reset(vcpu);
5514 if (r == 0)
5515 r = kvm_mmu_setup(vcpu);
5516 vcpu_put(vcpu);
5517 if (r < 0)
5518 goto free_vcpu;
5519
26e5215f 5520 return 0;
e9b11c17
ZX		 5521free_vcpu:
5522 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5523 return r;
e9b11c17
ZX		 5524}
5525
d40ccc62 5526void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5527{
5528 vcpu_load(vcpu);
5529 kvm_mmu_unload(vcpu);
5530 vcpu_put(vcpu);
5531
5532 kvm_x86_ops->vcpu_free(vcpu);
5533}
5534
5535int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5536{
448fa4a9
JK		 5537 vcpu->arch.nmi_pending = false;
5538 vcpu->arch.nmi_injected = false;
5539
42dbaa5a
JK		 5540 vcpu->arch.switch_db_regs = 0;
5541 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5542 vcpu->arch.dr6 = DR6_FIXED_1;
5543 vcpu->arch.dr7 = DR7_FIXED_1;
5544
e9b11c17
ZX		 5545 return kvm_x86_ops->vcpu_reset(vcpu);
5546}
5547
10474ae8 5548int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5549{
0cca7907
ZA		 5550 /*
5551 * Since this may be called from a hotplug notifcation,
5552 * we can't get the CPU frequency directly.
5553 */
5554 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5555 int cpu = raw_smp_processor_id();
5556 per_cpu(cpu_tsc_khz, cpu) = 0;
5557 }
18863bdd
AK		 5558
5559 kvm_shared_msr_cpu_online();
5560
10474ae8 5561 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5562}
5563
5564void kvm_arch_hardware_disable(void *garbage)
5565{
5566 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5567 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5568}
5569
5570int kvm_arch_hardware_setup(void)
5571{
5572 return kvm_x86_ops->hardware_setup();
5573}
5574
5575void kvm_arch_hardware_unsetup(void)
5576{
5577 kvm_x86_ops->hardware_unsetup();
5578}
5579
5580void kvm_arch_check_processor_compat(void *rtn)
5581{
5582 kvm_x86_ops->check_processor_compatibility(rtn);
5583}
5584
5585int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5586{
5587 struct page *page;
5588 struct kvm *kvm;
5589 int r;
5590
5591 BUG_ON(vcpu->kvm == NULL);
5592 kvm = vcpu->kvm;
5593
ad312c7c 5594 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5595 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5596 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5597 else
a4535290 5598 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5599
5600 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5601 if (!page) {
5602 r = -ENOMEM;
5603 goto fail;
5604 }
ad312c7c 5605 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5606
5607 r = kvm_mmu_create(vcpu);
5608 if (r < 0)
5609 goto fail_free_pio_data;
5610
5611 if (irqchip_in_kernel(kvm)) {
5612 r = kvm_create_lapic(vcpu);
5613 if (r < 0)
5614 goto fail_mmu_destroy;
5615 }
5616
890ca9ae
HY		 5617 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5618 GFP_KERNEL);
5619 if (!vcpu->arch.mce_banks) {
5620 r = -ENOMEM;
443c39bc 5621 goto fail_free_lapic;
890ca9ae
HY		 5622 }
5623 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5624
e9b11c17 5625 return 0;
443c39bc
WY		 5626fail_free_lapic:
5627 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5628fail_mmu_destroy:
5629 kvm_mmu_destroy(vcpu);
5630fail_free_pio_data:
ad312c7c 5631 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5632fail:
5633 return r;
5634}
5635
5636void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5637{
f656ce01
MT		 5638 int idx;
5639
36cb93fd 5640 kfree(vcpu->arch.mce_banks);
e9b11c17 5641 kvm_free_lapic(vcpu);
f656ce01 5642 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5643 kvm_mmu_destroy(vcpu);
f656ce01 5644 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5645 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5646}
d19a9cd2
ZX		 5647
5648struct kvm *kvm_arch_create_vm(void)
5649{
5650 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5651
5652 if (!kvm)
5653 return ERR_PTR(-ENOMEM);
5654
fef9cce0
MT		 5655 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5656 if (!kvm->arch.aliases) {
5657 kfree(kvm);
5658 return ERR_PTR(-ENOMEM);
5659 }
5660
f05e70ac 5661 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5662 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5663
5550af4d
SY		 5664 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5665 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5666
53f658b3
MT		 5667 rdtscll(kvm->arch.vm_init_tsc);
5668
d19a9cd2
ZX		 5669 return kvm;
5670}
5671
5672static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5673{
5674 vcpu_load(vcpu);
5675 kvm_mmu_unload(vcpu);
5676 vcpu_put(vcpu);
5677}
5678
5679static void kvm_free_vcpus(struct kvm *kvm)
5680{
5681 unsigned int i;
988a2cae 5682 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5683
5684 /*
5685 * Unpin any mmu pages first.
5686 */
988a2cae
GN		 5687 kvm_for_each_vcpu(i, vcpu, kvm)
5688 kvm_unload_vcpu_mmu(vcpu);
5689 kvm_for_each_vcpu(i, vcpu, kvm)
5690 kvm_arch_vcpu_free(vcpu);
5691
5692 mutex_lock(&kvm->lock);
5693 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5694 kvm->vcpus[i] = NULL;
d19a9cd2 5695
988a2cae
GN		 5696 atomic_set(&kvm->online_vcpus, 0);
5697 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5698}
5699
ad8ba2cd
SY		 5700void kvm_arch_sync_events(struct kvm *kvm)
5701{
ba4cef31 5702 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5703}
5704
d19a9cd2
ZX		 5705void kvm_arch_destroy_vm(struct kvm *kvm)
5706{
6eb55818 5707 kvm_iommu_unmap_guest(kvm);
7837699f 5708 kvm_free_pit(kvm);
d7deeeb0
ZX		 5709 kfree(kvm->arch.vpic);
5710 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5711 kvm_free_vcpus(kvm);
5712 kvm_free_physmem(kvm);
3d45830c
AK		 5713 if (kvm->arch.apic_access_page)
5714 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5715 if (kvm->arch.ept_identity_pagetable)
5716 put_page(kvm->arch.ept_identity_pagetable);
64749204 5717 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5718 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5719 kfree(kvm);
5720}
0de10343 5721
f7784b8e
MT		 5722int kvm_arch_prepare_memory_region(struct kvm *kvm,
5723 struct kvm_memory_slot *memslot,
0de10343 5724 struct kvm_memory_slot old,
f7784b8e 5725 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5726 int user_alloc)
5727{
f7784b8e 5728 int npages = memslot->npages;
0de10343
ZX		 5729
5730 /*To keep backward compatibility with older userspace,
5731 *x86 needs to hanlde !user_alloc case.
5732 */
5733 if (!user_alloc) {
5734 if (npages && !old.rmap) {
604b38ac
AA		 5735 unsigned long userspace_addr;
5736
72dc67a6 5737 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5738 userspace_addr = do_mmap(NULL, 0,
5739 npages * PAGE_SIZE,
5740 PROT_READ | PROT_WRITE,
acee3c04 5741 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5742 0);
72dc67a6 5743 up_write(&current->mm->mmap_sem);
0de10343 5744
604b38ac
AA		 5745 if (IS_ERR((void *)userspace_addr))
5746 return PTR_ERR((void *)userspace_addr);
5747
604b38ac 5748 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5749 }
5750 }
5751
f7784b8e
MT		 5752
5753 return 0;
5754}
5755
5756void kvm_arch_commit_memory_region(struct kvm *kvm,
5757 struct kvm_userspace_memory_region *mem,
5758 struct kvm_memory_slot old,
5759 int user_alloc)
5760{
5761
5762 int npages = mem->memory_size >> PAGE_SHIFT;
5763
5764 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5765 int ret;
5766
5767 down_write(&current->mm->mmap_sem);
5768 ret = do_munmap(current->mm, old.userspace_addr,
5769 old.npages * PAGE_SIZE);
5770 up_write(&current->mm->mmap_sem);
5771 if (ret < 0)
5772 printk(KERN_WARNING
5773 "kvm_vm_ioctl_set_memory_region: "
5774 "failed to munmap memory\n");
5775 }
5776
7c8a83b7 5777 spin_lock(&kvm->mmu_lock);
f05e70ac 5778 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5779 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5780 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5781 }
5782
5783 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5784 spin_unlock(&kvm->mmu_lock);
0de10343 5785}
1d737c8a 5786
34d4cb8f
MT		 5787void kvm_arch_flush_shadow(struct kvm *kvm)
5788{
5789 kvm_mmu_zap_all(kvm);
8986ecc0 5790 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5791}
5792
1d737c8a
ZX		 5793int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5794{
a4535290 5795 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5796 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5797 || vcpu->arch.nmi_pending ||
5798 (kvm_arch_interrupt_allowed(vcpu) &&
5799 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5800}
5736199a 5801
5736199a
ZX		 5802void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5803{
32f88400
MT		 5804 int me;
5805 int cpu = vcpu->cpu;
5736199a
ZX		 5806
5807 if (waitqueue_active(&vcpu->wq)) {
5808 wake_up_interruptible(&vcpu->wq);
5809 ++vcpu->stat.halt_wakeup;
5810 }
32f88400
MT		 5811
5812 me = get_cpu();
5813 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5814 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5815 smp_send_reschedule(cpu);
e9571ed5 5816 put_cpu();
5736199a 5817}
78646121
GN		 5818
5819int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5820{
5821 return kvm_x86_ops->interrupt_allowed(vcpu);
5822}
229456fc 5823
94fe45da
JK		 5824unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5825{
5826 unsigned long rflags;
5827
5828 rflags = kvm_x86_ops->get_rflags(vcpu);
5829 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5830 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5831 return rflags;
5832}
5833EXPORT_SYMBOL_GPL(kvm_get_rflags);
5834
5835void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5836{
5837 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5838 vcpu->arch.singlestep_cs ==
5839 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5840 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5841 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5842 kvm_x86_ops->set_rflags(vcpu, rflags);
5843}
5844EXPORT_SYMBOL_GPL(kvm_set_rflags);
5845
229456fc
MT		 5846EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5847EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5848EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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