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KVM: When switching to a vm8086 task, load segments as 16-bit
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
cb142eb7 80static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 81static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
82 struct kvm_cpuid_entry2 __user *entries);
83
97896d04 84struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 85EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 86
ed85c068
AP		 87int ignore_msrs = 0;
88module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
89
417bc304 90struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 91 { "pf_fixed", VCPU_STAT(pf_fixed) },
92 { "pf_guest", VCPU_STAT(pf_guest) },
93 { "tlb_flush", VCPU_STAT(tlb_flush) },
94 { "invlpg", VCPU_STAT(invlpg) },
95 { "exits", VCPU_STAT(exits) },
96 { "io_exits", VCPU_STAT(io_exits) },
97 { "mmio_exits", VCPU_STAT(mmio_exits) },
98 { "signal_exits", VCPU_STAT(signal_exits) },
99 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 100 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 101 { "halt_exits", VCPU_STAT(halt_exits) },
102 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 103 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 104 { "request_irq", VCPU_STAT(request_irq_exits) },
105 { "irq_exits", VCPU_STAT(irq_exits) },
106 { "host_state_reload", VCPU_STAT(host_state_reload) },
107 { "efer_reload", VCPU_STAT(efer_reload) },
108 { "fpu_reload", VCPU_STAT(fpu_reload) },
109 { "insn_emulation", VCPU_STAT(insn_emulation) },
110 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 111 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 112 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 113 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
114 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
115 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
116 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
117 { "mmu_flooded", VM_STAT(mmu_flooded) },
118 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 119 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 120 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 121 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 122 { "largepages", VM_STAT(lpages) },
417bc304
HB		 123 { NULL }
124};
125
5fb76f9b
CO		 126unsigned long segment_base(u16 selector)
127{
128 struct descriptor_table gdt;
a5f61300 129 struct desc_struct *d;
5fb76f9b
CO		 130 unsigned long table_base;
131 unsigned long v;
132
133 if (selector == 0)
134 return 0;
135
b792c344 136 kvm_get_gdt(&gdt);
5fb76f9b
CO		 137 table_base = gdt.base;
138
139 if (selector & 4) { /* from ldt */
b792c344 140 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 141
5fb76f9b
CO		 142 table_base = segment_base(ldt_selector);
143 }
a5f61300 144 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 145 v = get_desc_base(d);
5fb76f9b 146#ifdef CONFIG_X86_64
a5f61300
AK		 147 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
148 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 149#endif
150 return v;
151}
152EXPORT_SYMBOL_GPL(segment_base);
153
6866b83e
CO		 154u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
155{
156 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 157 return vcpu->arch.apic_base;
6866b83e 158 else
ad312c7c 159 return vcpu->arch.apic_base;
6866b83e
CO		 160}
161EXPORT_SYMBOL_GPL(kvm_get_apic_base);
162
163void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
164{
165 /* TODO: reserve bits check */
166 if (irqchip_in_kernel(vcpu->kvm))
167 kvm_lapic_set_base(vcpu, data);
168 else
ad312c7c 169 vcpu->arch.apic_base = data;
6866b83e
CO		 170}
171EXPORT_SYMBOL_GPL(kvm_set_apic_base);
172
298101da
AK		 173void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
174{
ad312c7c
ZX		 175 WARN_ON(vcpu->arch.exception.pending);
176 vcpu->arch.exception.pending = true;
177 vcpu->arch.exception.has_error_code = false;
178 vcpu->arch.exception.nr = nr;
298101da
AK		 179}
180EXPORT_SYMBOL_GPL(kvm_queue_exception);
181
c3c91fee
AK		 182void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
183 u32 error_code)
184{
185 ++vcpu->stat.pf_guest;
d8017474 186
71c4dfaf 187 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 188 switch(vcpu->arch.exception.nr) {
189 case DF_VECTOR:
71c4dfaf
JR		 190 /* triple fault -> shutdown */
191 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 192 return;
193 case PF_VECTOR:
194 vcpu->arch.exception.nr = DF_VECTOR;
195 vcpu->arch.exception.error_code = 0;
196 return;
197 default:
198 /* replace previous exception with a new one in a hope
199 that instruction re-execution will regenerate lost
200 exception */
201 vcpu->arch.exception.pending = false;
202 break;
71c4dfaf 203 }
c3c91fee 204 }
ad312c7c 205 vcpu->arch.cr2 = addr;
c3c91fee
AK		 206 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
207}
208
3419ffc8
SY		 209void kvm_inject_nmi(struct kvm_vcpu *vcpu)
210{
211 vcpu->arch.nmi_pending = 1;
212}
213EXPORT_SYMBOL_GPL(kvm_inject_nmi);
214
298101da
AK		 215void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
216{
ad312c7c
ZX		 217 WARN_ON(vcpu->arch.exception.pending);
218 vcpu->arch.exception.pending = true;
219 vcpu->arch.exception.has_error_code = true;
220 vcpu->arch.exception.nr = nr;
221 vcpu->arch.exception.error_code = error_code;
298101da
AK		 222}
223EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
224
a03490ed
CO		 225/*
226 * Load the pae pdptrs. Return true is they are all valid.
227 */
228int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
229{
230 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
231 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
232 int i;
233 int ret;
ad312c7c 234 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 235
a03490ed
CO		 236 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
237 offset * sizeof(u64), sizeof(pdpte));
238 if (ret < 0) {
239 ret = 0;
240 goto out;
241 }
242 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 243 if (is_present_gpte(pdpte[i]) &&
20c466b5 244 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 245 ret = 0;
246 goto out;
247 }
248 }
249 ret = 1;
250
ad312c7c 251 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 252 __set_bit(VCPU_EXREG_PDPTR,
253 (unsigned long *)&vcpu->arch.regs_avail);
254 __set_bit(VCPU_EXREG_PDPTR,
255 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 256out:
a03490ed
CO		 257
258 return ret;
259}
cc4b6871 260EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 261
d835dfec
AK		 262static bool pdptrs_changed(struct kvm_vcpu *vcpu)
263{
ad312c7c 264 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 265 bool changed = true;
266 int r;
267
268 if (is_long_mode(vcpu) || !is_pae(vcpu))
269 return false;
270
6de4f3ad
AK		 271 if (!test_bit(VCPU_EXREG_PDPTR,
272 (unsigned long *)&vcpu->arch.regs_avail))
273 return true;
274
ad312c7c 275 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 276 if (r < 0)
277 goto out;
ad312c7c 278 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 279out:
d835dfec
AK		 280
281 return changed;
282}
283
2d3ad1f4 284void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 285{
286 if (cr0 & CR0_RESERVED_BITS) {
287 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 288 cr0, vcpu->arch.cr0);
c1a5d4f9 289 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 290 return;
291 }
292
293 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
294 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 295 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 296 return;
297 }
298
299 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
300 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
301 "and a clear PE flag\n");
c1a5d4f9 302 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 303 return;
304 }
305
306 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
307#ifdef CONFIG_X86_64
ad312c7c 308 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 309 int cs_db, cs_l;
310
311 if (!is_pae(vcpu)) {
312 printk(KERN_DEBUG "set_cr0: #GP, start paging "
313 "in long mode while PAE is disabled\n");
c1a5d4f9 314 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 315 return;
316 }
317 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
318 if (cs_l) {
319 printk(KERN_DEBUG "set_cr0: #GP, start paging "
320 "in long mode while CS.L == 1\n");
c1a5d4f9 321 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 322 return;
323
324 }
325 } else
326#endif
ad312c7c 327 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 328 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
329 "reserved bits\n");
c1a5d4f9 330 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 331 return;
332 }
333
334 }
335
336 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 337 vcpu->arch.cr0 = cr0;
a03490ed 338
a03490ed 339 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 340 return;
341}
2d3ad1f4 342EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 343
2d3ad1f4 344void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 345{
2d3ad1f4 346 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 347}
2d3ad1f4 348EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 349
2d3ad1f4 350void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 351{
a2edf57f
AK		 352 unsigned long old_cr4 = vcpu->arch.cr4;
353 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
354
a03490ed
CO		 355 if (cr4 & CR4_RESERVED_BITS) {
356 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 357 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 358 return;
359 }
360
361 if (is_long_mode(vcpu)) {
362 if (!(cr4 & X86_CR4_PAE)) {
363 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
364 "in long mode\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
a2edf57f
AK		 368 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
369 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 370 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 371 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 372 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 373 return;
374 }
375
376 if (cr4 & X86_CR4_VMXE) {
377 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 378 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 379 return;
380 }
381 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 382 vcpu->arch.cr4 = cr4;
5a41accd 383 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 384 kvm_mmu_reset_context(vcpu);
a03490ed 385}
2d3ad1f4 386EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 387
2d3ad1f4 388void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 389{
ad312c7c 390 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 391 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 392 kvm_mmu_flush_tlb(vcpu);
393 return;
394 }
395
a03490ed
CO		 396 if (is_long_mode(vcpu)) {
397 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
398 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 399 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 400 return;
401 }
402 } else {
403 if (is_pae(vcpu)) {
404 if (cr3 & CR3_PAE_RESERVED_BITS) {
405 printk(KERN_DEBUG
406 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 407 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 408 return;
409 }
410 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
411 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
412 "reserved bits\n");
c1a5d4f9 413 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 414 return;
415 }
416 }
417 /*
418 * We don't check reserved bits in nonpae mode, because
419 * this isn't enforced, and VMware depends on this.
420 */
421 }
422
a03490ed
CO		 423 /*
424 * Does the new cr3 value map to physical memory? (Note, we
425 * catch an invalid cr3 even in real-mode, because it would
426 * cause trouble later on when we turn on paging anyway.)
427 *
428 * A real CPU would silently accept an invalid cr3 and would
429 * attempt to use it - with largely undefined (and often hard
430 * to debug) behavior on the guest side.
431 */
432 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 433 kvm_inject_gp(vcpu, 0);
a03490ed 434 else {
ad312c7c
ZX		 435 vcpu->arch.cr3 = cr3;
436 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 437 }
a03490ed 438}
2d3ad1f4 439EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 440
2d3ad1f4 441void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 442{
443 if (cr8 & CR8_RESERVED_BITS) {
444 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 445 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 446 return;
447 }
448 if (irqchip_in_kernel(vcpu->kvm))
449 kvm_lapic_set_tpr(vcpu, cr8);
450 else
ad312c7c 451 vcpu->arch.cr8 = cr8;
a03490ed 452}
2d3ad1f4 453EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 454
2d3ad1f4 455unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 456{
457 if (irqchip_in_kernel(vcpu->kvm))
458 return kvm_lapic_get_cr8(vcpu);
459 else
ad312c7c 460 return vcpu->arch.cr8;
a03490ed 461}
2d3ad1f4 462EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 463
d8017474
AG		 464static inline u32 bit(int bitno)
465{
466 return 1 << (bitno & 31);
467}
468
043405e1
CO		 469/*
470 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
471 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
472 *
473 * This list is modified at module load time to reflect the
474 * capabilities of the host cpu.
475 */
476static u32 msrs_to_save[] = {
477 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
478 MSR_K6_STAR,
479#ifdef CONFIG_X86_64
480 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
481#endif
af24a4e4 482 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 483 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 484};
485
486static unsigned num_msrs_to_save;
487
488static u32 emulated_msrs[] = {
489 MSR_IA32_MISC_ENABLE,
490};
491
15c4a640
CO		 492static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
493{
f2b4b7dd 494 if (efer & efer_reserved_bits) {
15c4a640
CO		 495 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
496 efer);
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 498 return;
499 }
500
501 if (is_paging(vcpu)
ad312c7c 502 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 503 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 504 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 505 return;
506 }
507
1b2fd70c
AG		 508 if (efer & EFER_FFXSR) {
509 struct kvm_cpuid_entry2 *feat;
510
511 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
512 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
513 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
514 kvm_inject_gp(vcpu, 0);
515 return;
516 }
517 }
518
d8017474
AG		 519 if (efer & EFER_SVME) {
520 struct kvm_cpuid_entry2 *feat;
521
522 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
523 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
524 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
525 kvm_inject_gp(vcpu, 0);
526 return;
527 }
528 }
529
15c4a640
CO		 530 kvm_x86_ops->set_efer(vcpu, efer);
531
532 efer &= ~EFER_LMA;
ad312c7c 533 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 534
ad312c7c 535 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 536
537 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
538 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 539}
540
f2b4b7dd
JR		 541void kvm_enable_efer_bits(u64 mask)
542{
543 efer_reserved_bits &= ~mask;
544}
545EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
546
547
15c4a640
CO		 548/*
549 * Writes msr value into into the appropriate "register".
550 * Returns 0 on success, non-0 otherwise.
551 * Assumes vcpu_load() was already called.
552 */
553int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
554{
555 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
556}
557
313a3dc7
CO		 558/*
559 * Adapt set_msr() to msr_io()'s calling convention
560 */
561static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
562{
563 return kvm_set_msr(vcpu, index, *data);
564}
565
18068523
GOC		 566static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
567{
568 static int version;
50d0a0f9
GH		 569 struct pvclock_wall_clock wc;
570 struct timespec now, sys, boot;
18068523
GOC		 571
572 if (!wall_clock)
573 return;
574
575 version++;
576
18068523
GOC		 577 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
578
50d0a0f9
GH		 579 /*
580 * The guest calculates current wall clock time by adding
581 * system time (updated by kvm_write_guest_time below) to the
582 * wall clock specified here. guest system time equals host
583 * system time for us, thus we must fill in host boot time here.
584 */
585 now = current_kernel_time();
586 ktime_get_ts(&sys);
587 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
588
589 wc.sec = boot.tv_sec;
590 wc.nsec = boot.tv_nsec;
591 wc.version = version;
18068523
GOC		 592
593 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
594
595 version++;
596 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 597}
598
50d0a0f9
GH		 599static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
600{
601 uint32_t quotient, remainder;
602
603 /* Don't try to replace with do_div(), this one calculates
604 * "(dividend << 32) / divisor" */
605 __asm__ ( "divl %4"
606 : "=a" (quotient), "=d" (remainder)
607 : "0" (0), "1" (dividend), "r" (divisor) );
608 return quotient;
609}
610
611static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
612{
613 uint64_t nsecs = 1000000000LL;
614 int32_t shift = 0;
615 uint64_t tps64;
616 uint32_t tps32;
617
618 tps64 = tsc_khz * 1000LL;
619 while (tps64 > nsecs*2) {
620 tps64 >>= 1;
621 shift--;
622 }
623
624 tps32 = (uint32_t)tps64;
625 while (tps32 <= (uint32_t)nsecs) {
626 tps32 <<= 1;
627 shift++;
628 }
629
630 hv_clock->tsc_shift = shift;
631 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
632
633 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 634 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 635 hv_clock->tsc_to_system_mul);
636}
637
c8076604
GH		 638static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
639
18068523
GOC		 640static void kvm_write_guest_time(struct kvm_vcpu *v)
641{
642 struct timespec ts;
643 unsigned long flags;
644 struct kvm_vcpu_arch *vcpu = &v->arch;
645 void *shared_kaddr;
463656c0 646 unsigned long this_tsc_khz;
18068523
GOC		 647
648 if ((!vcpu->time_page))
649 return;
650
463656c0
AK		 651 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
652 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
653 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
654 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 655 }
463656c0 656 put_cpu_var(cpu_tsc_khz);
50d0a0f9 657
18068523
GOC		 658 /* Keep irq disabled to prevent changes to the clock */
659 local_irq_save(flags);
af24a4e4 660 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 661 ktime_get_ts(&ts);
662 local_irq_restore(flags);
663
664 /* With all the info we got, fill in the values */
665
666 vcpu->hv_clock.system_time = ts.tv_nsec +
667 (NSEC_PER_SEC * (u64)ts.tv_sec);
668 /*
669 * The interface expects us to write an even number signaling that the
670 * update is finished. Since the guest won't see the intermediate
50d0a0f9 671 * state, we just increase by 2 at the end.
18068523 672 */
50d0a0f9 673 vcpu->hv_clock.version += 2;
18068523
GOC		 674
675 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
676
677 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 678 sizeof(vcpu->hv_clock));
18068523
GOC		 679
680 kunmap_atomic(shared_kaddr, KM_USER0);
681
682 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
683}
684
c8076604
GH		 685static int kvm_request_guest_time_update(struct kvm_vcpu *v)
686{
687 struct kvm_vcpu_arch *vcpu = &v->arch;
688
689 if (!vcpu->time_page)
690 return 0;
691 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
692 return 1;
693}
694
9ba075a6
AK		 695static bool msr_mtrr_valid(unsigned msr)
696{
697 switch (msr) {
698 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
699 case MSR_MTRRfix64K_00000:
700 case MSR_MTRRfix16K_80000:
701 case MSR_MTRRfix16K_A0000:
702 case MSR_MTRRfix4K_C0000:
703 case MSR_MTRRfix4K_C8000:
704 case MSR_MTRRfix4K_D0000:
705 case MSR_MTRRfix4K_D8000:
706 case MSR_MTRRfix4K_E0000:
707 case MSR_MTRRfix4K_E8000:
708 case MSR_MTRRfix4K_F0000:
709 case MSR_MTRRfix4K_F8000:
710 case MSR_MTRRdefType:
711 case MSR_IA32_CR_PAT:
712 return true;
713 case 0x2f8:
714 return true;
715 }
716 return false;
717}
718
d6289b93
MT		 719static bool valid_pat_type(unsigned t)
720{
721 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
722}
723
724static bool valid_mtrr_type(unsigned t)
725{
726 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
727}
728
729static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
730{
731 int i;
732
733 if (!msr_mtrr_valid(msr))
734 return false;
735
736 if (msr == MSR_IA32_CR_PAT) {
737 for (i = 0; i < 8; i++)
738 if (!valid_pat_type((data >> (i * 8)) & 0xff))
739 return false;
740 return true;
741 } else if (msr == MSR_MTRRdefType) {
742 if (data & ~0xcff)
743 return false;
744 return valid_mtrr_type(data & 0xff);
745 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
746 for (i = 0; i < 8 ; i++)
747 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
748 return false;
749 return true;
750 }
751
752 /* variable MTRRs */
753 return valid_mtrr_type(data & 0xff);
754}
755
9ba075a6
AK		 756static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
757{
0bed3b56
SY		 758 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
759
d6289b93 760 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 761 return 1;
762
0bed3b56
SY		 763 if (msr == MSR_MTRRdefType) {
764 vcpu->arch.mtrr_state.def_type = data;
765 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
766 } else if (msr == MSR_MTRRfix64K_00000)
767 p[0] = data;
768 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
769 p[1 + msr - MSR_MTRRfix16K_80000] = data;
770 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
771 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
772 else if (msr == MSR_IA32_CR_PAT)
773 vcpu->arch.pat = data;
774 else { /* Variable MTRRs */
775 int idx, is_mtrr_mask;
776 u64 *pt;
777
778 idx = (msr - 0x200) / 2;
779 is_mtrr_mask = msr - 0x200 - 2 * idx;
780 if (!is_mtrr_mask)
781 pt =
782 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
783 else
784 pt =
785 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
786 *pt = data;
787 }
788
789 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 790 return 0;
791}
15c4a640 792
890ca9ae 793static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 794{
890ca9ae
HY		 795 u64 mcg_cap = vcpu->arch.mcg_cap;
796 unsigned bank_num = mcg_cap & 0xff;
797
15c4a640 798 switch (msr) {
15c4a640 799 case MSR_IA32_MCG_STATUS:
890ca9ae 800 vcpu->arch.mcg_status = data;
15c4a640 801 break;
c7ac679c 802 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 803 if (!(mcg_cap & MCG_CTL_P))
804 return 1;
805 if (data != 0 && data != ~(u64)0)
806 return -1;
807 vcpu->arch.mcg_ctl = data;
808 break;
809 default:
810 if (msr >= MSR_IA32_MC0_CTL &&
811 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
812 u32 offset = msr - MSR_IA32_MC0_CTL;
813 /* only 0 or all 1s can be written to IA32_MCi_CTL */
814 if ((offset & 0x3) == 0 &&
815 data != 0 && data != ~(u64)0)
816 return -1;
817 vcpu->arch.mce_banks[offset] = data;
818 break;
819 }
820 return 1;
821 }
822 return 0;
823}
824
825int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
826{
827 switch (msr) {
828 case MSR_EFER:
829 set_efer(vcpu, data);
c7ac679c 830 break;
8f1589d9
AP		 831 case MSR_K7_HWCR:
832 data &= ~(u64)0x40; /* ignore flush filter disable */
833 if (data != 0) {
834 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
835 data);
836 return 1;
837 }
838 break;
f7c6d140
AP		 839 case MSR_FAM10H_MMIO_CONF_BASE:
840 if (data != 0) {
841 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
842 "0x%llx\n", data);
843 return 1;
844 }
845 break;
c323c0e5
AP		 846 case MSR_AMD64_NB_CFG:
847 break;
b5e2fec0
AG		 848 case MSR_IA32_DEBUGCTLMSR:
849 if (!data) {
850 /* We support the non-activated case already */
851 break;
852 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
853 /* Values other than LBR and BTF are vendor-specific,
854 thus reserved and should throw a #GP */
855 return 1;
856 }
857 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
858 __func__, data);
859 break;
15c4a640
CO		 860 case MSR_IA32_UCODE_REV:
861 case MSR_IA32_UCODE_WRITE:
61a6bd67 862 case MSR_VM_HSAVE_PA:
6098ca93 863 case MSR_AMD64_PATCH_LOADER:
15c4a640 864 break;
9ba075a6
AK		 865 case 0x200 ... 0x2ff:
866 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 867 case MSR_IA32_APICBASE:
868 kvm_set_apic_base(vcpu, data);
869 break;
0105d1a5
GN		 870 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
871 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 872 case MSR_IA32_MISC_ENABLE:
ad312c7c 873 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 874 break;
18068523
GOC		 875 case MSR_KVM_WALL_CLOCK:
876 vcpu->kvm->arch.wall_clock = data;
877 kvm_write_wall_clock(vcpu->kvm, data);
878 break;
879 case MSR_KVM_SYSTEM_TIME: {
880 if (vcpu->arch.time_page) {
881 kvm_release_page_dirty(vcpu->arch.time_page);
882 vcpu->arch.time_page = NULL;
883 }
884
885 vcpu->arch.time = data;
886
887 /* we verify if the enable bit is set... */
888 if (!(data & 1))
889 break;
890
891 /* ...but clean it before doing the actual write */
892 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
893
18068523
GOC		 894 vcpu->arch.time_page =
895 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 896
897 if (is_error_page(vcpu->arch.time_page)) {
898 kvm_release_page_clean(vcpu->arch.time_page);
899 vcpu->arch.time_page = NULL;
900 }
901
c8076604 902 kvm_request_guest_time_update(vcpu);
18068523
GOC		 903 break;
904 }
890ca9ae
HY		 905 case MSR_IA32_MCG_CTL:
906 case MSR_IA32_MCG_STATUS:
907 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
908 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 909
910 /* Performance counters are not protected by a CPUID bit,
911 * so we should check all of them in the generic path for the sake of
912 * cross vendor migration.
913 * Writing a zero into the event select MSRs disables them,
914 * which we perfectly emulate ;-). Any other value should be at least
915 * reported, some guests depend on them.
916 */
917 case MSR_P6_EVNTSEL0:
918 case MSR_P6_EVNTSEL1:
919 case MSR_K7_EVNTSEL0:
920 case MSR_K7_EVNTSEL1:
921 case MSR_K7_EVNTSEL2:
922 case MSR_K7_EVNTSEL3:
923 if (data != 0)
924 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
925 "0x%x data 0x%llx\n", msr, data);
926 break;
927 /* at least RHEL 4 unconditionally writes to the perfctr registers,
928 * so we ignore writes to make it happy.
929 */
930 case MSR_P6_PERFCTR0:
931 case MSR_P6_PERFCTR1:
932 case MSR_K7_PERFCTR0:
933 case MSR_K7_PERFCTR1:
934 case MSR_K7_PERFCTR2:
935 case MSR_K7_PERFCTR3:
936 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
937 "0x%x data 0x%llx\n", msr, data);
938 break;
15c4a640 939 default:
ed85c068
AP		 940 if (!ignore_msrs) {
941 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
942 msr, data);
943 return 1;
944 } else {
945 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
946 msr, data);
947 break;
948 }
15c4a640
CO		 949 }
950 return 0;
951}
952EXPORT_SYMBOL_GPL(kvm_set_msr_common);
953
954
955/*
956 * Reads an msr value (of 'msr_index') into 'pdata'.
957 * Returns 0 on success, non-0 otherwise.
958 * Assumes vcpu_load() was already called.
959 */
960int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
961{
962 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
963}
964
9ba075a6
AK		 965static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
966{
0bed3b56
SY		 967 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
968
9ba075a6
AK		 969 if (!msr_mtrr_valid(msr))
970 return 1;
971
0bed3b56
SY		 972 if (msr == MSR_MTRRdefType)
973 *pdata = vcpu->arch.mtrr_state.def_type +
974 (vcpu->arch.mtrr_state.enabled << 10);
975 else if (msr == MSR_MTRRfix64K_00000)
976 *pdata = p[0];
977 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
978 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
979 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
980 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
981 else if (msr == MSR_IA32_CR_PAT)
982 *pdata = vcpu->arch.pat;
983 else { /* Variable MTRRs */
984 int idx, is_mtrr_mask;
985 u64 *pt;
986
987 idx = (msr - 0x200) / 2;
988 is_mtrr_mask = msr - 0x200 - 2 * idx;
989 if (!is_mtrr_mask)
990 pt =
991 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
992 else
993 pt =
994 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
995 *pdata = *pt;
996 }
997
9ba075a6
AK		 998 return 0;
999}
1000
890ca9ae 1001static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1002{
1003 u64 data;
890ca9ae
HY		 1004 u64 mcg_cap = vcpu->arch.mcg_cap;
1005 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1006
1007 switch (msr) {
15c4a640
CO		 1008 case MSR_IA32_P5_MC_ADDR:
1009 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1010 data = 0;
1011 break;
15c4a640 1012 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1013 data = vcpu->arch.mcg_cap;
1014 break;
c7ac679c 1015 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1016 if (!(mcg_cap & MCG_CTL_P))
1017 return 1;
1018 data = vcpu->arch.mcg_ctl;
1019 break;
1020 case MSR_IA32_MCG_STATUS:
1021 data = vcpu->arch.mcg_status;
1022 break;
1023 default:
1024 if (msr >= MSR_IA32_MC0_CTL &&
1025 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1026 u32 offset = msr - MSR_IA32_MC0_CTL;
1027 data = vcpu->arch.mce_banks[offset];
1028 break;
1029 }
1030 return 1;
1031 }
1032 *pdata = data;
1033 return 0;
1034}
1035
1036int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1037{
1038 u64 data;
1039
1040 switch (msr) {
890ca9ae 1041 case MSR_IA32_PLATFORM_ID:
15c4a640 1042 case MSR_IA32_UCODE_REV:
15c4a640 1043 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1044 case MSR_IA32_DEBUGCTLMSR:
1045 case MSR_IA32_LASTBRANCHFROMIP:
1046 case MSR_IA32_LASTBRANCHTOIP:
1047 case MSR_IA32_LASTINTFROMIP:
1048 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1049 case MSR_K8_SYSCFG:
1050 case MSR_K7_HWCR:
61a6bd67 1051 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1052 case MSR_P6_PERFCTR0:
1053 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1054 case MSR_P6_EVNTSEL0:
1055 case MSR_P6_EVNTSEL1:
9e699624 1056 case MSR_K7_EVNTSEL0:
1f3ee616 1057 case MSR_K7_PERFCTR0:
1fdbd48c 1058 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1059 case MSR_AMD64_NB_CFG:
f7c6d140 1060 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1061 data = 0;
1062 break;
9ba075a6
AK		 1063 case MSR_MTRRcap:
1064 data = 0x500 | KVM_NR_VAR_MTRR;
1065 break;
1066 case 0x200 ... 0x2ff:
1067 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1068 case 0xcd: /* fsb frequency */
1069 data = 3;
1070 break;
1071 case MSR_IA32_APICBASE:
1072 data = kvm_get_apic_base(vcpu);
1073 break;
0105d1a5
GN		 1074 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1075 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1076 break;
15c4a640 1077 case MSR_IA32_MISC_ENABLE:
ad312c7c 1078 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1079 break;
847f0ad8
AG		 1080 case MSR_IA32_PERF_STATUS:
1081 /* TSC increment by tick */
1082 data = 1000ULL;
1083 /* CPU multiplier */
1084 data |= (((uint64_t)4ULL) << 40);
1085 break;
15c4a640 1086 case MSR_EFER:
ad312c7c 1087 data = vcpu->arch.shadow_efer;
15c4a640 1088 break;
18068523
GOC		 1089 case MSR_KVM_WALL_CLOCK:
1090 data = vcpu->kvm->arch.wall_clock;
1091 break;
1092 case MSR_KVM_SYSTEM_TIME:
1093 data = vcpu->arch.time;
1094 break;
890ca9ae
HY		 1095 case MSR_IA32_P5_MC_ADDR:
1096 case MSR_IA32_P5_MC_TYPE:
1097 case MSR_IA32_MCG_CAP:
1098 case MSR_IA32_MCG_CTL:
1099 case MSR_IA32_MCG_STATUS:
1100 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1101 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1102 default:
ed85c068
AP		 1103 if (!ignore_msrs) {
1104 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1105 return 1;
1106 } else {
1107 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1108 data = 0;
1109 }
1110 break;
15c4a640
CO		 1111 }
1112 *pdata = data;
1113 return 0;
1114}
1115EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1116
313a3dc7
CO		 1117/*
1118 * Read or write a bunch of msrs. All parameters are kernel addresses.
1119 *
1120 * @return number of msrs set successfully.
1121 */
1122static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1123 struct kvm_msr_entry *entries,
1124 int (*do_msr)(struct kvm_vcpu *vcpu,
1125 unsigned index, u64 *data))
1126{
1127 int i;
1128
1129 vcpu_load(vcpu);
1130
3200f405 1131 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1132 for (i = 0; i < msrs->nmsrs; ++i)
1133 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1134 break;
3200f405 1135 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1136
1137 vcpu_put(vcpu);
1138
1139 return i;
1140}
1141
1142/*
1143 * Read or write a bunch of msrs. Parameters are user addresses.
1144 *
1145 * @return number of msrs set successfully.
1146 */
1147static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1148 int (*do_msr)(struct kvm_vcpu *vcpu,
1149 unsigned index, u64 *data),
1150 int writeback)
1151{
1152 struct kvm_msrs msrs;
1153 struct kvm_msr_entry *entries;
1154 int r, n;
1155 unsigned size;
1156
1157 r = -EFAULT;
1158 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1159 goto out;
1160
1161 r = -E2BIG;
1162 if (msrs.nmsrs >= MAX_IO_MSRS)
1163 goto out;
1164
1165 r = -ENOMEM;
1166 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1167 entries = vmalloc(size);
1168 if (!entries)
1169 goto out;
1170
1171 r = -EFAULT;
1172 if (copy_from_user(entries, user_msrs->entries, size))
1173 goto out_free;
1174
1175 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1176 if (r < 0)
1177 goto out_free;
1178
1179 r = -EFAULT;
1180 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1181 goto out_free;
1182
1183 r = n;
1184
1185out_free:
1186 vfree(entries);
1187out:
1188 return r;
1189}
1190
018d00d2
ZX		 1191int kvm_dev_ioctl_check_extension(long ext)
1192{
1193 int r;
1194
1195 switch (ext) {
1196 case KVM_CAP_IRQCHIP:
1197 case KVM_CAP_HLT:
1198 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1199 case KVM_CAP_SET_TSS_ADDR:
07716717 1200 case KVM_CAP_EXT_CPUID:
c8076604 1201 case KVM_CAP_CLOCKSOURCE:
7837699f 1202 case KVM_CAP_PIT:
a28e4f5a 1203 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1204 case KVM_CAP_MP_STATE:
ed848624 1205 case KVM_CAP_SYNC_MMU:
52d939a0 1206 case KVM_CAP_REINJECT_CONTROL:
4925663a 1207 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1208 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1209 case KVM_CAP_IRQFD:
d34e6b17 1210 case KVM_CAP_IOEVENTFD:
c5ff41ce 1211 case KVM_CAP_PIT2:
e9f42757 1212 case KVM_CAP_PIT_STATE2:
b927a3ce 1213 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
018d00d2
ZX		 1214 r = 1;
1215 break;
542472b5
LV		 1216 case KVM_CAP_COALESCED_MMIO:
1217 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1218 break;
774ead3a
AK		 1219 case KVM_CAP_VAPIC:
1220 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1221 break;
f725230a
AK		 1222 case KVM_CAP_NR_VCPUS:
1223 r = KVM_MAX_VCPUS;
1224 break;
a988b910
AK		 1225 case KVM_CAP_NR_MEMSLOTS:
1226 r = KVM_MEMORY_SLOTS;
1227 break;
2f333bcb
MT		 1228 case KVM_CAP_PV_MMU:
1229 r = !tdp_enabled;
1230 break;
62c476c7 1231 case KVM_CAP_IOMMU:
19de40a8 1232 r = iommu_found();
62c476c7 1233 break;
890ca9ae
HY		 1234 case KVM_CAP_MCE:
1235 r = KVM_MAX_MCE_BANKS;
1236 break;
018d00d2
ZX		 1237 default:
1238 r = 0;
1239 break;
1240 }
1241 return r;
1242
1243}
1244
043405e1
CO		 1245long kvm_arch_dev_ioctl(struct file *filp,
1246 unsigned int ioctl, unsigned long arg)
1247{
1248 void __user *argp = (void __user *)arg;
1249 long r;
1250
1251 switch (ioctl) {
1252 case KVM_GET_MSR_INDEX_LIST: {
1253 struct kvm_msr_list __user *user_msr_list = argp;
1254 struct kvm_msr_list msr_list;
1255 unsigned n;
1256
1257 r = -EFAULT;
1258 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1259 goto out;
1260 n = msr_list.nmsrs;
1261 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1262 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1263 goto out;
1264 r = -E2BIG;
e125e7b6 1265 if (n < msr_list.nmsrs)
043405e1
CO		 1266 goto out;
1267 r = -EFAULT;
1268 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1269 num_msrs_to_save * sizeof(u32)))
1270 goto out;
e125e7b6 1271 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1272 &emulated_msrs,
1273 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1274 goto out;
1275 r = 0;
1276 break;
1277 }
674eea0f
AK		 1278 case KVM_GET_SUPPORTED_CPUID: {
1279 struct kvm_cpuid2 __user *cpuid_arg = argp;
1280 struct kvm_cpuid2 cpuid;
1281
1282 r = -EFAULT;
1283 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1284 goto out;
1285 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1286 cpuid_arg->entries);
674eea0f
AK		 1287 if (r)
1288 goto out;
1289
1290 r = -EFAULT;
1291 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1292 goto out;
1293 r = 0;
1294 break;
1295 }
890ca9ae
HY		 1296 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1297 u64 mce_cap;
1298
1299 mce_cap = KVM_MCE_CAP_SUPPORTED;
1300 r = -EFAULT;
1301 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1302 goto out;
1303 r = 0;
1304 break;
1305 }
043405e1
CO		 1306 default:
1307 r = -EINVAL;
1308 }
1309out:
1310 return r;
1311}
1312
313a3dc7
CO		 1313void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1314{
1315 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1316 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1317}
1318
1319void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1320{
1321 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1322 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1323}
1324
07716717 1325static int is_efer_nx(void)
313a3dc7 1326{
e286e86e 1327 unsigned long long efer = 0;
313a3dc7 1328
e286e86e 1329 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1330 return efer & EFER_NX;
1331}
1332
1333static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1334{
1335 int i;
1336 struct kvm_cpuid_entry2 *e, *entry;
1337
313a3dc7 1338 entry = NULL;
ad312c7c
ZX		 1339 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1340 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1341 if (e->function == 0x80000001) {
1342 entry = e;
1343 break;
1344 }
1345 }
07716717 1346 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1347 entry->edx &= ~(1 << 20);
1348 printk(KERN_INFO "kvm: guest NX capability removed\n");
1349 }
1350}
1351
07716717 1352/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1353static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1354 struct kvm_cpuid *cpuid,
1355 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1356{
1357 int r, i;
1358 struct kvm_cpuid_entry *cpuid_entries;
1359
1360 r = -E2BIG;
1361 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1362 goto out;
1363 r = -ENOMEM;
1364 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1365 if (!cpuid_entries)
1366 goto out;
1367 r = -EFAULT;
1368 if (copy_from_user(cpuid_entries, entries,
1369 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1370 goto out_free;
1371 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1372 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1373 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1374 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1375 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1376 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1377 vcpu->arch.cpuid_entries[i].index = 0;
1378 vcpu->arch.cpuid_entries[i].flags = 0;
1379 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1380 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1381 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1382 }
1383 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1384 cpuid_fix_nx_cap(vcpu);
1385 r = 0;
fc61b800 1386 kvm_apic_set_version(vcpu);
07716717
DK		 1387
1388out_free:
1389 vfree(cpuid_entries);
1390out:
1391 return r;
1392}
1393
1394static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1395 struct kvm_cpuid2 *cpuid,
1396 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1397{
1398 int r;
1399
1400 r = -E2BIG;
1401 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1402 goto out;
1403 r = -EFAULT;
ad312c7c 1404 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1405 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1406 goto out;
ad312c7c 1407 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1408 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1409 return 0;
1410
1411out:
1412 return r;
1413}
1414
07716717 1415static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1416 struct kvm_cpuid2 *cpuid,
1417 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1418{
1419 int r;
1420
1421 r = -E2BIG;
ad312c7c 1422 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1423 goto out;
1424 r = -EFAULT;
ad312c7c 1425 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1426 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1427 goto out;
1428 return 0;
1429
1430out:
ad312c7c 1431 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1432 return r;
1433}
1434
07716717 1435static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1436 u32 index)
07716717
DK		 1437{
1438 entry->function = function;
1439 entry->index = index;
1440 cpuid_count(entry->function, entry->index,
19355475 1441 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1442 entry->flags = 0;
1443}
1444
7faa4ee1
AK		 1445#define F(x) bit(X86_FEATURE_##x)
1446
07716717
DK		 1447static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1448 u32 index, int *nent, int maxnent)
1449{
7faa4ee1 1450 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
344f414f 1451 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
07716717 1452#ifdef CONFIG_X86_64
7faa4ee1
AK		 1453 unsigned f_lm = F(LM);
1454#else
1455 unsigned f_lm = 0;
07716717 1456#endif
7faa4ee1
AK		 1457
1458 /* cpuid 1.edx */
1459 const u32 kvm_supported_word0_x86_features =
1460 F(FPU) | F(VME) | F(DE) | F(PSE) |
1461 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1462 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1463 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1464 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1465 0 /* Reserved, DS, ACPI */ | F(MMX) |
1466 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1467 0 /* HTT, TM, Reserved, PBE */;
1468 /* cpuid 0x80000001.edx */
1469 const u32 kvm_supported_word1_x86_features =
1470 F(FPU) | F(VME) | F(DE) | F(PSE) |
1471 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1472 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1473 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1474 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1475 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
344f414f 1476 F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
7faa4ee1
AK		 1477 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1478 /* cpuid 1.ecx */
1479 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1480 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1481 0 /* DS-CPL, VMX, SMX, EST */ |
1482 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1483 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1484 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1485 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1486 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1487 /* cpuid 0x80000001.ecx */
07716717 1488 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1489 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1490 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1491 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1492 0 /* SKINIT */ | 0 /* WDT */;
07716717 1493
19355475 1494 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1495 get_cpu();
1496 do_cpuid_1_ent(entry, function, index);
1497 ++*nent;
1498
1499 switch (function) {
1500 case 0:
1501 entry->eax = min(entry->eax, (u32)0xb);
1502 break;
1503 case 1:
1504 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1505 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1506 /* we support x2apic emulation even if host does not support
1507 * it since we emulate x2apic in software */
1508 entry->ecx |= F(X2APIC);
07716717
DK		 1509 break;
1510 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1511 * may return different values. This forces us to get_cpu() before
1512 * issuing the first command, and also to emulate this annoying behavior
1513 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1514 case 2: {
1515 int t, times = entry->eax & 0xff;
1516
1517 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1518 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1519 for (t = 1; t < times && *nent < maxnent; ++t) {
1520 do_cpuid_1_ent(&entry[t], function, 0);
1521 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1522 ++*nent;
1523 }
1524 break;
1525 }
1526 /* function 4 and 0xb have additional index. */
1527 case 4: {
14af3f3c 1528 int i, cache_type;
07716717
DK		 1529
1530 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1531 /* read more entries until cache_type is zero */
14af3f3c
HH		 1532 for (i = 1; *nent < maxnent; ++i) {
1533 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1534 if (!cache_type)
1535 break;
14af3f3c
HH		 1536 do_cpuid_1_ent(&entry[i], function, i);
1537 entry[i].flags |=
07716717
DK		 1538 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1539 ++*nent;
1540 }
1541 break;
1542 }
1543 case 0xb: {
14af3f3c 1544 int i, level_type;
07716717
DK		 1545
1546 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1547 /* read more entries until level_type is zero */
14af3f3c 1548 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1549 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1550 if (!level_type)
1551 break;
14af3f3c
HH		 1552 do_cpuid_1_ent(&entry[i], function, i);
1553 entry[i].flags |=
07716717
DK		 1554 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1555 ++*nent;
1556 }
1557 break;
1558 }
1559 case 0x80000000:
1560 entry->eax = min(entry->eax, 0x8000001a);
1561 break;
1562 case 0x80000001:
1563 entry->edx &= kvm_supported_word1_x86_features;
1564 entry->ecx &= kvm_supported_word6_x86_features;
1565 break;
1566 }
1567 put_cpu();
1568}
1569
7faa4ee1
AK		 1570#undef F
1571
674eea0f 1572static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1573 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1574{
1575 struct kvm_cpuid_entry2 *cpuid_entries;
1576 int limit, nent = 0, r = -E2BIG;
1577 u32 func;
1578
1579 if (cpuid->nent < 1)
1580 goto out;
1581 r = -ENOMEM;
1582 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1583 if (!cpuid_entries)
1584 goto out;
1585
1586 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1587 limit = cpuid_entries[0].eax;
1588 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1589 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1590 &nent, cpuid->nent);
07716717
DK		 1591 r = -E2BIG;
1592 if (nent >= cpuid->nent)
1593 goto out_free;
1594
1595 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1596 limit = cpuid_entries[nent - 1].eax;
1597 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1598 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1599 &nent, cpuid->nent);
cb007648
MM		 1600 r = -E2BIG;
1601 if (nent >= cpuid->nent)
1602 goto out_free;
1603
07716717
DK		 1604 r = -EFAULT;
1605 if (copy_to_user(entries, cpuid_entries,
19355475 1606 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1607 goto out_free;
1608 cpuid->nent = nent;
1609 r = 0;
1610
1611out_free:
1612 vfree(cpuid_entries);
1613out:
1614 return r;
1615}
1616
313a3dc7
CO		 1617static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1618 struct kvm_lapic_state *s)
1619{
1620 vcpu_load(vcpu);
ad312c7c 1621 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1622 vcpu_put(vcpu);
1623
1624 return 0;
1625}
1626
1627static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1628 struct kvm_lapic_state *s)
1629{
1630 vcpu_load(vcpu);
ad312c7c 1631 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1632 kvm_apic_post_state_restore(vcpu);
cb142eb7 1633 update_cr8_intercept(vcpu);
313a3dc7
CO		 1634 vcpu_put(vcpu);
1635
1636 return 0;
1637}
1638
f77bc6a4
ZX		 1639static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1640 struct kvm_interrupt *irq)
1641{
1642 if (irq->irq < 0 || irq->irq >= 256)
1643 return -EINVAL;
1644 if (irqchip_in_kernel(vcpu->kvm))
1645 return -ENXIO;
1646 vcpu_load(vcpu);
1647
66fd3f7f 1648 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1649
1650 vcpu_put(vcpu);
1651
1652 return 0;
1653}
1654
c4abb7c9
JK		 1655static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1656{
1657 vcpu_load(vcpu);
1658 kvm_inject_nmi(vcpu);
1659 vcpu_put(vcpu);
1660
1661 return 0;
1662}
1663
b209749f
AK		 1664static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1665 struct kvm_tpr_access_ctl *tac)
1666{
1667 if (tac->flags)
1668 return -EINVAL;
1669 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1670 return 0;
1671}
1672
890ca9ae
HY		 1673static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1674 u64 mcg_cap)
1675{
1676 int r;
1677 unsigned bank_num = mcg_cap & 0xff, bank;
1678
1679 r = -EINVAL;
1680 if (!bank_num)
1681 goto out;
1682 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1683 goto out;
1684 r = 0;
1685 vcpu->arch.mcg_cap = mcg_cap;
1686 /* Init IA32_MCG_CTL to all 1s */
1687 if (mcg_cap & MCG_CTL_P)
1688 vcpu->arch.mcg_ctl = ~(u64)0;
1689 /* Init IA32_MCi_CTL to all 1s */
1690 for (bank = 0; bank < bank_num; bank++)
1691 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1692out:
1693 return r;
1694}
1695
1696static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1697 struct kvm_x86_mce *mce)
1698{
1699 u64 mcg_cap = vcpu->arch.mcg_cap;
1700 unsigned bank_num = mcg_cap & 0xff;
1701 u64 *banks = vcpu->arch.mce_banks;
1702
1703 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1704 return -EINVAL;
1705 /*
1706 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1707 * reporting is disabled
1708 */
1709 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1710 vcpu->arch.mcg_ctl != ~(u64)0)
1711 return 0;
1712 banks += 4 * mce->bank;
1713 /*
1714 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1715 * reporting is disabled for the bank
1716 */
1717 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1718 return 0;
1719 if (mce->status & MCI_STATUS_UC) {
1720 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1721 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1722 printk(KERN_DEBUG "kvm: set_mce: "
1723 "injects mce exception while "
1724 "previous one is in progress!\n");
1725 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1726 return 0;
1727 }
1728 if (banks[1] & MCI_STATUS_VAL)
1729 mce->status |= MCI_STATUS_OVER;
1730 banks[2] = mce->addr;
1731 banks[3] = mce->misc;
1732 vcpu->arch.mcg_status = mce->mcg_status;
1733 banks[1] = mce->status;
1734 kvm_queue_exception(vcpu, MC_VECTOR);
1735 } else if (!(banks[1] & MCI_STATUS_VAL)
1736 || !(banks[1] & MCI_STATUS_UC)) {
1737 if (banks[1] & MCI_STATUS_VAL)
1738 mce->status |= MCI_STATUS_OVER;
1739 banks[2] = mce->addr;
1740 banks[3] = mce->misc;
1741 banks[1] = mce->status;
1742 } else
1743 banks[1] |= MCI_STATUS_OVER;
1744 return 0;
1745}
1746
313a3dc7
CO		 1747long kvm_arch_vcpu_ioctl(struct file *filp,
1748 unsigned int ioctl, unsigned long arg)
1749{
1750 struct kvm_vcpu *vcpu = filp->private_data;
1751 void __user *argp = (void __user *)arg;
1752 int r;
b772ff36 1753 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1754
1755 switch (ioctl) {
1756 case KVM_GET_LAPIC: {
b772ff36 1757 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1758
b772ff36
DH		 1759 r = -ENOMEM;
1760 if (!lapic)
1761 goto out;
1762 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1763 if (r)
1764 goto out;
1765 r = -EFAULT;
b772ff36 1766 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1767 goto out;
1768 r = 0;
1769 break;
1770 }
1771 case KVM_SET_LAPIC: {
b772ff36
DH		 1772 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1773 r = -ENOMEM;
1774 if (!lapic)
1775 goto out;
313a3dc7 1776 r = -EFAULT;
b772ff36 1777 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1778 goto out;
b772ff36 1779 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1780 if (r)
1781 goto out;
1782 r = 0;
1783 break;
1784 }
f77bc6a4
ZX		 1785 case KVM_INTERRUPT: {
1786 struct kvm_interrupt irq;
1787
1788 r = -EFAULT;
1789 if (copy_from_user(&irq, argp, sizeof irq))
1790 goto out;
1791 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1792 if (r)
1793 goto out;
1794 r = 0;
1795 break;
1796 }
c4abb7c9
JK		 1797 case KVM_NMI: {
1798 r = kvm_vcpu_ioctl_nmi(vcpu);
1799 if (r)
1800 goto out;
1801 r = 0;
1802 break;
1803 }
313a3dc7
CO		 1804 case KVM_SET_CPUID: {
1805 struct kvm_cpuid __user *cpuid_arg = argp;
1806 struct kvm_cpuid cpuid;
1807
1808 r = -EFAULT;
1809 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1810 goto out;
1811 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1812 if (r)
1813 goto out;
1814 break;
1815 }
07716717
DK		 1816 case KVM_SET_CPUID2: {
1817 struct kvm_cpuid2 __user *cpuid_arg = argp;
1818 struct kvm_cpuid2 cpuid;
1819
1820 r = -EFAULT;
1821 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1822 goto out;
1823 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1824 cpuid_arg->entries);
07716717
DK		 1825 if (r)
1826 goto out;
1827 break;
1828 }
1829 case KVM_GET_CPUID2: {
1830 struct kvm_cpuid2 __user *cpuid_arg = argp;
1831 struct kvm_cpuid2 cpuid;
1832
1833 r = -EFAULT;
1834 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1835 goto out;
1836 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1837 cpuid_arg->entries);
07716717
DK		 1838 if (r)
1839 goto out;
1840 r = -EFAULT;
1841 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1842 goto out;
1843 r = 0;
1844 break;
1845 }
313a3dc7
CO		 1846 case KVM_GET_MSRS:
1847 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1848 break;
1849 case KVM_SET_MSRS:
1850 r = msr_io(vcpu, argp, do_set_msr, 0);
1851 break;
b209749f
AK		 1852 case KVM_TPR_ACCESS_REPORTING: {
1853 struct kvm_tpr_access_ctl tac;
1854
1855 r = -EFAULT;
1856 if (copy_from_user(&tac, argp, sizeof tac))
1857 goto out;
1858 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1859 if (r)
1860 goto out;
1861 r = -EFAULT;
1862 if (copy_to_user(argp, &tac, sizeof tac))
1863 goto out;
1864 r = 0;
1865 break;
1866 };
b93463aa
AK		 1867 case KVM_SET_VAPIC_ADDR: {
1868 struct kvm_vapic_addr va;
1869
1870 r = -EINVAL;
1871 if (!irqchip_in_kernel(vcpu->kvm))
1872 goto out;
1873 r = -EFAULT;
1874 if (copy_from_user(&va, argp, sizeof va))
1875 goto out;
1876 r = 0;
1877 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1878 break;
1879 }
890ca9ae
HY		 1880 case KVM_X86_SETUP_MCE: {
1881 u64 mcg_cap;
1882
1883 r = -EFAULT;
1884 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1885 goto out;
1886 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1887 break;
1888 }
1889 case KVM_X86_SET_MCE: {
1890 struct kvm_x86_mce mce;
1891
1892 r = -EFAULT;
1893 if (copy_from_user(&mce, argp, sizeof mce))
1894 goto out;
1895 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1896 break;
1897 }
313a3dc7
CO		 1898 default:
1899 r = -EINVAL;
1900 }
1901out:
7a6ce84c 1902 kfree(lapic);
313a3dc7
CO		 1903 return r;
1904}
1905
1fe779f8
CO		 1906static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1907{
1908 int ret;
1909
1910 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1911 return -1;
1912 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1913 return ret;
1914}
1915
b927a3ce
SY		 1916static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
1917 u64 ident_addr)
1918{
1919 kvm->arch.ept_identity_map_addr = ident_addr;
1920 return 0;
1921}
1922
1fe779f8
CO		 1923static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1924 u32 kvm_nr_mmu_pages)
1925{
1926 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1927 return -EINVAL;
1928
72dc67a6 1929 down_write(&kvm->slots_lock);
7c8a83b7 1930 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1931
1932 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1933 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1934
7c8a83b7 1935 spin_unlock(&kvm->mmu_lock);
72dc67a6 1936 up_write(&kvm->slots_lock);
1fe779f8
CO		 1937 return 0;
1938}
1939
1940static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1941{
f05e70ac 1942 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1943}
1944
e9f85cde
ZX		 1945gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1946{
1947 int i;
1948 struct kvm_mem_alias *alias;
1949
d69fb81f
ZX		 1950 for (i = 0; i < kvm->arch.naliases; ++i) {
1951 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1952 if (gfn >= alias->base_gfn
1953 && gfn < alias->base_gfn + alias->npages)
1954 return alias->target_gfn + gfn - alias->base_gfn;
1955 }
1956 return gfn;
1957}
1958
1fe779f8
CO		 1959/*
1960 * Set a new alias region. Aliases map a portion of physical memory into
1961 * another portion. This is useful for memory windows, for example the PC
1962 * VGA region.
1963 */
1964static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1965 struct kvm_memory_alias *alias)
1966{
1967 int r, n;
1968 struct kvm_mem_alias *p;
1969
1970 r = -EINVAL;
1971 /* General sanity checks */
1972 if (alias->memory_size & (PAGE_SIZE - 1))
1973 goto out;
1974 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1975 goto out;
1976 if (alias->slot >= KVM_ALIAS_SLOTS)
1977 goto out;
1978 if (alias->guest_phys_addr + alias->memory_size
1979 < alias->guest_phys_addr)
1980 goto out;
1981 if (alias->target_phys_addr + alias->memory_size
1982 < alias->target_phys_addr)
1983 goto out;
1984
72dc67a6 1985 down_write(&kvm->slots_lock);
a1708ce8 1986 spin_lock(&kvm->mmu_lock);
1fe779f8 1987
d69fb81f 1988 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1989 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1990 p->npages = alias->memory_size >> PAGE_SHIFT;
1991 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1992
1993 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1994 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1995 break;
d69fb81f 1996 kvm->arch.naliases = n;
1fe779f8 1997
a1708ce8 1998 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1999 kvm_mmu_zap_all(kvm);
2000
72dc67a6 2001 up_write(&kvm->slots_lock);
1fe779f8
CO		 2002
2003 return 0;
2004
2005out:
2006 return r;
2007}
2008
2009static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2010{
2011 int r;
2012
2013 r = 0;
2014 switch (chip->chip_id) {
2015 case KVM_IRQCHIP_PIC_MASTER:
2016 memcpy(&chip->chip.pic,
2017 &pic_irqchip(kvm)->pics[0],
2018 sizeof(struct kvm_pic_state));
2019 break;
2020 case KVM_IRQCHIP_PIC_SLAVE:
2021 memcpy(&chip->chip.pic,
2022 &pic_irqchip(kvm)->pics[1],
2023 sizeof(struct kvm_pic_state));
2024 break;
2025 case KVM_IRQCHIP_IOAPIC:
2026 memcpy(&chip->chip.ioapic,
2027 ioapic_irqchip(kvm),
2028 sizeof(struct kvm_ioapic_state));
2029 break;
2030 default:
2031 r = -EINVAL;
2032 break;
2033 }
2034 return r;
2035}
2036
2037static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2038{
2039 int r;
2040
2041 r = 0;
2042 switch (chip->chip_id) {
2043 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2044 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2045 memcpy(&pic_irqchip(kvm)->pics[0],
2046 &chip->chip.pic,
2047 sizeof(struct kvm_pic_state));
894a9c55 2048 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2049 break;
2050 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2051 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2052 memcpy(&pic_irqchip(kvm)->pics[1],
2053 &chip->chip.pic,
2054 sizeof(struct kvm_pic_state));
894a9c55 2055 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2056 break;
2057 case KVM_IRQCHIP_IOAPIC:
894a9c55 2058 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2059 memcpy(ioapic_irqchip(kvm),
2060 &chip->chip.ioapic,
2061 sizeof(struct kvm_ioapic_state));
894a9c55 2062 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2063 break;
2064 default:
2065 r = -EINVAL;
2066 break;
2067 }
2068 kvm_pic_update_irq(pic_irqchip(kvm));
2069 return r;
2070}
2071
e0f63cb9
SY		 2072static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2073{
2074 int r = 0;
2075
894a9c55 2076 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2077 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2078 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2079 return r;
2080}
2081
2082static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2083{
2084 int r = 0;
2085
894a9c55 2086 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2087 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2088 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2089 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2090 return r;
2091}
2092
2093static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2094{
2095 int r = 0;
2096
2097 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2098 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2099 sizeof(ps->channels));
2100 ps->flags = kvm->arch.vpit->pit_state.flags;
2101 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2102 return r;
2103}
2104
2105static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2106{
2107 int r = 0, start = 0;
2108 u32 prev_legacy, cur_legacy;
2109 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2110 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2111 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2112 if (!prev_legacy && cur_legacy)
2113 start = 1;
2114 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2115 sizeof(kvm->arch.vpit->pit_state.channels));
2116 kvm->arch.vpit->pit_state.flags = ps->flags;
2117 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2118 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2119 return r;
2120}
2121
52d939a0
MT		 2122static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2123 struct kvm_reinject_control *control)
2124{
2125 if (!kvm->arch.vpit)
2126 return -ENXIO;
894a9c55 2127 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2128 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2129 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2130 return 0;
2131}
2132
5bb064dc
ZX		 2133/*
2134 * Get (and clear) the dirty memory log for a memory slot.
2135 */
2136int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2137 struct kvm_dirty_log *log)
2138{
2139 int r;
2140 int n;
2141 struct kvm_memory_slot *memslot;
2142 int is_dirty = 0;
2143
72dc67a6 2144 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2145
2146 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2147 if (r)
2148 goto out;
2149
2150 /* If nothing is dirty, don't bother messing with page tables. */
2151 if (is_dirty) {
7c8a83b7 2152 spin_lock(&kvm->mmu_lock);
5bb064dc 2153 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2154 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2155 kvm_flush_remote_tlbs(kvm);
2156 memslot = &kvm->memslots[log->slot];
2157 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2158 memset(memslot->dirty_bitmap, 0, n);
2159 }
2160 r = 0;
2161out:
72dc67a6 2162 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2163 return r;
2164}
2165
1fe779f8
CO		 2166long kvm_arch_vm_ioctl(struct file *filp,
2167 unsigned int ioctl, unsigned long arg)
2168{
2169 struct kvm *kvm = filp->private_data;
2170 void __user *argp = (void __user *)arg;
2171 int r = -EINVAL;
f0d66275
DH		 2172 /*
2173 * This union makes it completely explicit to gcc-3.x
2174 * that these two variables' stack usage should be
2175 * combined, not added together.
2176 */
2177 union {
2178 struct kvm_pit_state ps;
e9f42757 2179 struct kvm_pit_state2 ps2;
f0d66275 2180 struct kvm_memory_alias alias;
c5ff41ce 2181 struct kvm_pit_config pit_config;
f0d66275 2182 } u;
1fe779f8
CO		 2183
2184 switch (ioctl) {
2185 case KVM_SET_TSS_ADDR:
2186 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2187 if (r < 0)
2188 goto out;
2189 break;
b927a3ce
SY		 2190 case KVM_SET_IDENTITY_MAP_ADDR: {
2191 u64 ident_addr;
2192
2193 r = -EFAULT;
2194 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2195 goto out;
2196 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2197 if (r < 0)
2198 goto out;
2199 break;
2200 }
1fe779f8
CO		 2201 case KVM_SET_MEMORY_REGION: {
2202 struct kvm_memory_region kvm_mem;
2203 struct kvm_userspace_memory_region kvm_userspace_mem;
2204
2205 r = -EFAULT;
2206 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2207 goto out;
2208 kvm_userspace_mem.slot = kvm_mem.slot;
2209 kvm_userspace_mem.flags = kvm_mem.flags;
2210 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2211 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2212 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2213 if (r)
2214 goto out;
2215 break;
2216 }
2217 case KVM_SET_NR_MMU_PAGES:
2218 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2219 if (r)
2220 goto out;
2221 break;
2222 case KVM_GET_NR_MMU_PAGES:
2223 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2224 break;
f0d66275 2225 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2226 r = -EFAULT;
f0d66275 2227 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2228 goto out;
f0d66275 2229 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2230 if (r)
2231 goto out;
2232 break;
1fe779f8
CO		 2233 case KVM_CREATE_IRQCHIP:
2234 r = -ENOMEM;
d7deeeb0
ZX		 2235 kvm->arch.vpic = kvm_create_pic(kvm);
2236 if (kvm->arch.vpic) {
1fe779f8
CO		 2237 r = kvm_ioapic_init(kvm);
2238 if (r) {
d7deeeb0
ZX		 2239 kfree(kvm->arch.vpic);
2240 kvm->arch.vpic = NULL;
1fe779f8
CO		 2241 goto out;
2242 }
2243 } else
2244 goto out;
399ec807
AK		 2245 r = kvm_setup_default_irq_routing(kvm);
2246 if (r) {
2247 kfree(kvm->arch.vpic);
2248 kfree(kvm->arch.vioapic);
2249 goto out;
2250 }
1fe779f8 2251 break;
7837699f 2252 case KVM_CREATE_PIT:
c5ff41ce
JK		 2253 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2254 goto create_pit;
2255 case KVM_CREATE_PIT2:
2256 r = -EFAULT;
2257 if (copy_from_user(&u.pit_config, argp,
2258 sizeof(struct kvm_pit_config)))
2259 goto out;
2260 create_pit:
108b5669 2261 down_write(&kvm->slots_lock);
269e05e4
AK		 2262 r = -EEXIST;
2263 if (kvm->arch.vpit)
2264 goto create_pit_unlock;
7837699f 2265 r = -ENOMEM;
c5ff41ce 2266 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2267 if (kvm->arch.vpit)
2268 r = 0;
269e05e4 2269 create_pit_unlock:
108b5669 2270 up_write(&kvm->slots_lock);
7837699f 2271 break;
4925663a 2272 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2273 case KVM_IRQ_LINE: {
2274 struct kvm_irq_level irq_event;
2275
2276 r = -EFAULT;
2277 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2278 goto out;
2279 if (irqchip_in_kernel(kvm)) {
4925663a 2280 __s32 status;
fa40a821 2281 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2282 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2283 irq_event.irq, irq_event.level);
fa40a821 2284 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2285 if (ioctl == KVM_IRQ_LINE_STATUS) {
2286 irq_event.status = status;
2287 if (copy_to_user(argp, &irq_event,
2288 sizeof irq_event))
2289 goto out;
2290 }
1fe779f8
CO		 2291 r = 0;
2292 }
2293 break;
2294 }
2295 case KVM_GET_IRQCHIP: {
2296 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2297 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2298
f0d66275
DH		 2299 r = -ENOMEM;
2300 if (!chip)
1fe779f8 2301 goto out;
f0d66275
DH		 2302 r = -EFAULT;
2303 if (copy_from_user(chip, argp, sizeof *chip))
2304 goto get_irqchip_out;
1fe779f8
CO		 2305 r = -ENXIO;
2306 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2307 goto get_irqchip_out;
2308 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2309 if (r)
f0d66275 2310 goto get_irqchip_out;
1fe779f8 2311 r = -EFAULT;
f0d66275
DH		 2312 if (copy_to_user(argp, chip, sizeof *chip))
2313 goto get_irqchip_out;
1fe779f8 2314 r = 0;
f0d66275
DH		 2315 get_irqchip_out:
2316 kfree(chip);
2317 if (r)
2318 goto out;
1fe779f8
CO		 2319 break;
2320 }
2321 case KVM_SET_IRQCHIP: {
2322 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2323 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2324
f0d66275
DH		 2325 r = -ENOMEM;
2326 if (!chip)
1fe779f8 2327 goto out;
f0d66275
DH		 2328 r = -EFAULT;
2329 if (copy_from_user(chip, argp, sizeof *chip))
2330 goto set_irqchip_out;
1fe779f8
CO		 2331 r = -ENXIO;
2332 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2333 goto set_irqchip_out;
2334 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2335 if (r)
f0d66275 2336 goto set_irqchip_out;
1fe779f8 2337 r = 0;
f0d66275
DH		 2338 set_irqchip_out:
2339 kfree(chip);
2340 if (r)
2341 goto out;
1fe779f8
CO		 2342 break;
2343 }
e0f63cb9 2344 case KVM_GET_PIT: {
e0f63cb9 2345 r = -EFAULT;
f0d66275 2346 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2347 goto out;
2348 r = -ENXIO;
2349 if (!kvm->arch.vpit)
2350 goto out;
f0d66275 2351 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2352 if (r)
2353 goto out;
2354 r = -EFAULT;
f0d66275 2355 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2356 goto out;
2357 r = 0;
2358 break;
2359 }
2360 case KVM_SET_PIT: {
e0f63cb9 2361 r = -EFAULT;
f0d66275 2362 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2363 goto out;
2364 r = -ENXIO;
2365 if (!kvm->arch.vpit)
2366 goto out;
f0d66275 2367 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2368 if (r)
2369 goto out;
2370 r = 0;
2371 break;
2372 }
e9f42757
BK		 2373 case KVM_GET_PIT2: {
2374 r = -ENXIO;
2375 if (!kvm->arch.vpit)
2376 goto out;
2377 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2378 if (r)
2379 goto out;
2380 r = -EFAULT;
2381 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2382 goto out;
2383 r = 0;
2384 break;
2385 }
2386 case KVM_SET_PIT2: {
2387 r = -EFAULT;
2388 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2389 goto out;
2390 r = -ENXIO;
2391 if (!kvm->arch.vpit)
2392 goto out;
2393 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2394 if (r)
2395 goto out;
2396 r = 0;
2397 break;
2398 }
52d939a0
MT		 2399 case KVM_REINJECT_CONTROL: {
2400 struct kvm_reinject_control control;
2401 r = -EFAULT;
2402 if (copy_from_user(&control, argp, sizeof(control)))
2403 goto out;
2404 r = kvm_vm_ioctl_reinject(kvm, &control);
2405 if (r)
2406 goto out;
2407 r = 0;
2408 break;
2409 }
1fe779f8
CO		 2410 default:
2411 ;
2412 }
2413out:
2414 return r;
2415}
2416
a16b043c 2417static void kvm_init_msr_list(void)
043405e1
CO		 2418{
2419 u32 dummy[2];
2420 unsigned i, j;
2421
2422 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2423 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2424 continue;
2425 if (j < i)
2426 msrs_to_save[j] = msrs_to_save[i];
2427 j++;
2428 }
2429 num_msrs_to_save = j;
2430}
2431
bda9020e
MT		 2432static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2433 const void *v)
bbd9b64e 2434{
bda9020e
MT		 2435 if (vcpu->arch.apic &&
2436 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2437 return 0;
bbd9b64e 2438
bda9020e 2439 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2440}
2441
bda9020e 2442static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2443{
bda9020e
MT		 2444 if (vcpu->arch.apic &&
2445 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2446 return 0;
bbd9b64e 2447
bda9020e 2448 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2449}
2450
cded19f3
HE		 2451static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2452 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2453{
2454 void *data = val;
10589a46 2455 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2456
2457 while (bytes) {
ad312c7c 2458 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2459 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2460 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2461 int ret;
2462
10589a46
MT		 2463 if (gpa == UNMAPPED_GVA) {
2464 r = X86EMUL_PROPAGATE_FAULT;
2465 goto out;
2466 }
77c2002e 2467 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2468 if (ret < 0) {
2469 r = X86EMUL_UNHANDLEABLE;
2470 goto out;
2471 }
bbd9b64e 2472
77c2002e
IE		 2473 bytes -= toread;
2474 data += toread;
2475 addr += toread;
bbd9b64e 2476 }
10589a46 2477out:
10589a46 2478 return r;
bbd9b64e 2479}
77c2002e 2480
cded19f3
HE		 2481static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2482 struct kvm_vcpu *vcpu)
77c2002e
IE		 2483{
2484 void *data = val;
2485 int r = X86EMUL_CONTINUE;
2486
2487 while (bytes) {
2488 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2489 unsigned offset = addr & (PAGE_SIZE-1);
2490 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2491 int ret;
2492
2493 if (gpa == UNMAPPED_GVA) {
2494 r = X86EMUL_PROPAGATE_FAULT;
2495 goto out;
2496 }
2497 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2498 if (ret < 0) {
2499 r = X86EMUL_UNHANDLEABLE;
2500 goto out;
2501 }
2502
2503 bytes -= towrite;
2504 data += towrite;
2505 addr += towrite;
2506 }
2507out:
2508 return r;
2509}
2510
bbd9b64e 2511
bbd9b64e
CO		 2512static int emulator_read_emulated(unsigned long addr,
2513 void *val,
2514 unsigned int bytes,
2515 struct kvm_vcpu *vcpu)
2516{
bbd9b64e
CO		 2517 gpa_t gpa;
2518
2519 if (vcpu->mmio_read_completed) {
2520 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2521 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2522 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2523 vcpu->mmio_read_completed = 0;
2524 return X86EMUL_CONTINUE;
2525 }
2526
ad312c7c 2527 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2528
2529 /* For APIC access vmexit */
2530 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2531 goto mmio;
2532
77c2002e
IE		 2533 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2534 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2535 return X86EMUL_CONTINUE;
2536 if (gpa == UNMAPPED_GVA)
2537 return X86EMUL_PROPAGATE_FAULT;
2538
2539mmio:
2540 /*
2541 * Is this MMIO handled locally?
2542 */
aec51dc4
AK		 2543 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2544 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e 2545 return X86EMUL_CONTINUE;
aec51dc4
AK		 2546 }
2547
2548 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2549
2550 vcpu->mmio_needed = 1;
2551 vcpu->mmio_phys_addr = gpa;
2552 vcpu->mmio_size = bytes;
2553 vcpu->mmio_is_write = 0;
2554
2555 return X86EMUL_UNHANDLEABLE;
2556}
2557
3200f405 2558int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2559 const void *val, int bytes)
bbd9b64e
CO		 2560{
2561 int ret;
2562
2563 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2564 if (ret < 0)
bbd9b64e 2565 return 0;
ad218f85 2566 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2567 return 1;
2568}
2569
2570static int emulator_write_emulated_onepage(unsigned long addr,
2571 const void *val,
2572 unsigned int bytes,
2573 struct kvm_vcpu *vcpu)
2574{
10589a46
MT		 2575 gpa_t gpa;
2576
10589a46 2577 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2578
2579 if (gpa == UNMAPPED_GVA) {
c3c91fee 2580 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2581 return X86EMUL_PROPAGATE_FAULT;
2582 }
2583
2584 /* For APIC access vmexit */
2585 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2586 goto mmio;
2587
2588 if (emulator_write_phys(vcpu, gpa, val, bytes))
2589 return X86EMUL_CONTINUE;
2590
2591mmio:
aec51dc4 2592 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2593 /*
2594 * Is this MMIO handled locally?
2595 */
bda9020e 2596 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2597 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2598
2599 vcpu->mmio_needed = 1;
2600 vcpu->mmio_phys_addr = gpa;
2601 vcpu->mmio_size = bytes;
2602 vcpu->mmio_is_write = 1;
2603 memcpy(vcpu->mmio_data, val, bytes);
2604
2605 return X86EMUL_CONTINUE;
2606}
2607
2608int emulator_write_emulated(unsigned long addr,
2609 const void *val,
2610 unsigned int bytes,
2611 struct kvm_vcpu *vcpu)
2612{
2613 /* Crossing a page boundary? */
2614 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2615 int rc, now;
2616
2617 now = -addr & ~PAGE_MASK;
2618 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2619 if (rc != X86EMUL_CONTINUE)
2620 return rc;
2621 addr += now;
2622 val += now;
2623 bytes -= now;
2624 }
2625 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2626}
2627EXPORT_SYMBOL_GPL(emulator_write_emulated);
2628
2629static int emulator_cmpxchg_emulated(unsigned long addr,
2630 const void *old,
2631 const void *new,
2632 unsigned int bytes,
2633 struct kvm_vcpu *vcpu)
2634{
2635 static int reported;
2636
2637 if (!reported) {
2638 reported = 1;
2639 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2640 }
2bacc55c
MT		 2641#ifndef CONFIG_X86_64
2642 /* guests cmpxchg8b have to be emulated atomically */
2643 if (bytes == 8) {
10589a46 2644 gpa_t gpa;
2bacc55c 2645 struct page *page;
c0b49b0d 2646 char *kaddr;
2bacc55c
MT		 2647 u64 val;
2648
10589a46
MT		 2649 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2650
2bacc55c
MT		 2651 if (gpa == UNMAPPED_GVA ||
2652 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2653 goto emul_write;
2654
2655 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2656 goto emul_write;
2657
2658 val = *(u64 *)new;
72dc67a6 2659
2bacc55c 2660 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2661
c0b49b0d
AM		 2662 kaddr = kmap_atomic(page, KM_USER0);
2663 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2664 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2665 kvm_release_page_dirty(page);
2666 }
3200f405 2667emul_write:
2bacc55c
MT		 2668#endif
2669
bbd9b64e
CO		 2670 return emulator_write_emulated(addr, new, bytes, vcpu);
2671}
2672
2673static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2674{
2675 return kvm_x86_ops->get_segment_base(vcpu, seg);
2676}
2677
2678int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2679{
a7052897 2680 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2681 return X86EMUL_CONTINUE;
2682}
2683
2684int emulate_clts(struct kvm_vcpu *vcpu)
2685{
ad312c7c 2686 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2687 return X86EMUL_CONTINUE;
2688}
2689
2690int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2691{
2692 struct kvm_vcpu *vcpu = ctxt->vcpu;
2693
2694 switch (dr) {
2695 case 0 ... 3:
2696 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2697 return X86EMUL_CONTINUE;
2698 default:
b8688d51 2699 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2700 return X86EMUL_UNHANDLEABLE;
2701 }
2702}
2703
2704int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2705{
2706 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2707 int exception;
2708
2709 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2710 if (exception) {
2711 /* FIXME: better handling */
2712 return X86EMUL_UNHANDLEABLE;
2713 }
2714 return X86EMUL_CONTINUE;
2715}
2716
2717void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2718{
bbd9b64e 2719 u8 opcodes[4];
5fdbf976 2720 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2721 unsigned long rip_linear;
2722
f76c710d 2723 if (!printk_ratelimit())
bbd9b64e
CO		 2724 return;
2725
25be4608
GC		 2726 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2727
77c2002e 2728 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2729
2730 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2731 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2732}
2733EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2734
14af3f3c 2735static struct x86_emulate_ops emulate_ops = {
77c2002e 2736 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2737 .read_emulated = emulator_read_emulated,
2738 .write_emulated = emulator_write_emulated,
2739 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2740};
2741
5fdbf976
MT		 2742static void cache_all_regs(struct kvm_vcpu *vcpu)
2743{
2744 kvm_register_read(vcpu, VCPU_REGS_RAX);
2745 kvm_register_read(vcpu, VCPU_REGS_RSP);
2746 kvm_register_read(vcpu, VCPU_REGS_RIP);
2747 vcpu->arch.regs_dirty = ~0;
2748}
2749
bbd9b64e
CO		 2750int emulate_instruction(struct kvm_vcpu *vcpu,
2751 struct kvm_run *run,
2752 unsigned long cr2,
2753 u16 error_code,
571008da 2754 int emulation_type)
bbd9b64e 2755{
310b5d30 2756 int r, shadow_mask;
571008da 2757 struct decode_cache *c;
bbd9b64e 2758
26eef70c 2759 kvm_clear_exception_queue(vcpu);
ad312c7c 2760 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2761 /*
2762 * TODO: fix x86_emulate.c to use guest_read/write_register
2763 * instead of direct ->regs accesses, can save hundred cycles
2764 * on Intel for instructions that don't read/change RSP, for
2765 * for example.
2766 */
2767 cache_all_regs(vcpu);
bbd9b64e
CO		 2768
2769 vcpu->mmio_is_write = 0;
ad312c7c 2770 vcpu->arch.pio.string = 0;
bbd9b64e 2771
571008da 2772 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2773 int cs_db, cs_l;
2774 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2775
ad312c7c
ZX		 2776 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2777 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2778 vcpu->arch.emulate_ctxt.mode =
2779 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2780 ? X86EMUL_MODE_REAL : cs_l
2781 ? X86EMUL_MODE_PROT64 : cs_db
2782 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2783
ad312c7c 2784 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2785
0cb5762e
AP		 2786 /* Only allow emulation of specific instructions on #UD
2787 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2788 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2789 if (emulation_type & EMULTYPE_TRAP_UD) {
2790 if (!c->twobyte)
2791 return EMULATE_FAIL;
2792 switch (c->b) {
2793 case 0x01: /* VMMCALL */
2794 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2795 return EMULATE_FAIL;
2796 break;
2797 case 0x34: /* sysenter */
2798 case 0x35: /* sysexit */
2799 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2800 return EMULATE_FAIL;
2801 break;
2802 case 0x05: /* syscall */
2803 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2804 return EMULATE_FAIL;
2805 break;
2806 default:
2807 return EMULATE_FAIL;
2808 }
2809
2810 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2811 return EMULATE_FAIL;
2812 }
571008da 2813
f2b5756b 2814 ++vcpu->stat.insn_emulation;
bbd9b64e 2815 if (r) {
f2b5756b 2816 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2817 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2818 return EMULATE_DONE;
2819 return EMULATE_FAIL;
2820 }
2821 }
2822
ba8afb6b
GN		 2823 if (emulation_type & EMULTYPE_SKIP) {
2824 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2825 return EMULATE_DONE;
2826 }
2827
ad312c7c 2828 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2829 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2830
2831 if (r == 0)
2832 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2833
ad312c7c 2834 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2835 return EMULATE_DO_MMIO;
2836
2837 if ((r || vcpu->mmio_is_write) && run) {
2838 run->exit_reason = KVM_EXIT_MMIO;
2839 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2840 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2841 run->mmio.len = vcpu->mmio_size;
2842 run->mmio.is_write = vcpu->mmio_is_write;
2843 }
2844
2845 if (r) {
2846 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2847 return EMULATE_DONE;
2848 if (!vcpu->mmio_needed) {
2849 kvm_report_emulation_failure(vcpu, "mmio");
2850 return EMULATE_FAIL;
2851 }
2852 return EMULATE_DO_MMIO;
2853 }
2854
ad312c7c 2855 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2856
2857 if (vcpu->mmio_is_write) {
2858 vcpu->mmio_needed = 0;
2859 return EMULATE_DO_MMIO;
2860 }
2861
2862 return EMULATE_DONE;
2863}
2864EXPORT_SYMBOL_GPL(emulate_instruction);
2865
de7d789a
CO		 2866static int pio_copy_data(struct kvm_vcpu *vcpu)
2867{
ad312c7c 2868 void *p = vcpu->arch.pio_data;
0f346074 2869 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2870 unsigned bytes;
0f346074 2871 int ret;
de7d789a 2872
ad312c7c
ZX		 2873 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2874 if (vcpu->arch.pio.in)
0f346074 2875 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2876 else
0f346074
IE		 2877 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2878 return ret;
de7d789a
CO		 2879}
2880
2881int complete_pio(struct kvm_vcpu *vcpu)
2882{
ad312c7c 2883 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2884 long delta;
2885 int r;
5fdbf976 2886 unsigned long val;
de7d789a
CO		 2887
2888 if (!io->string) {
5fdbf976
MT		 2889 if (io->in) {
2890 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2891 memcpy(&val, vcpu->arch.pio_data, io->size);
2892 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2893 }
de7d789a
CO		 2894 } else {
2895 if (io->in) {
2896 r = pio_copy_data(vcpu);
5fdbf976 2897 if (r)
de7d789a 2898 return r;
de7d789a
CO		 2899 }
2900
2901 delta = 1;
2902 if (io->rep) {
2903 delta *= io->cur_count;
2904 /*
2905 * The size of the register should really depend on
2906 * current address size.
2907 */
5fdbf976
MT		 2908 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2909 val -= delta;
2910 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2911 }
2912 if (io->down)
2913 delta = -delta;
2914 delta *= io->size;
5fdbf976
MT		 2915 if (io->in) {
2916 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2917 val += delta;
2918 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2919 } else {
2920 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2921 val += delta;
2922 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2923 }
de7d789a
CO		 2924 }
2925
de7d789a
CO		 2926 io->count -= io->cur_count;
2927 io->cur_count = 0;
2928
2929 return 0;
2930}
2931
bda9020e 2932static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2933{
2934 /* TODO: String I/O for in kernel device */
bda9020e 2935 int r;
de7d789a 2936
ad312c7c 2937 if (vcpu->arch.pio.in)
bda9020e
MT		 2938 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2939 vcpu->arch.pio.size, pd);
de7d789a 2940 else
bda9020e
MT		 2941 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2942 vcpu->arch.pio.size, pd);
2943 return r;
de7d789a
CO		 2944}
2945
bda9020e 2946static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2947{
ad312c7c
ZX		 2948 struct kvm_pio_request *io = &vcpu->arch.pio;
2949 void *pd = vcpu->arch.pio_data;
bda9020e 2950 int i, r = 0;
de7d789a 2951
de7d789a 2952 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2953 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2954 io->port, io->size, pd)) {
2955 r = -EOPNOTSUPP;
2956 break;
2957 }
de7d789a
CO		 2958 pd += io->size;
2959 }
bda9020e 2960 return r;
de7d789a
CO		 2961}
2962
2963int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2964 int size, unsigned port)
2965{
5fdbf976 2966 unsigned long val;
de7d789a
CO		 2967
2968 vcpu->run->exit_reason = KVM_EXIT_IO;
2969 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2970 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2971 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2972 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2973 vcpu->run->io.port = vcpu->arch.pio.port = port;
2974 vcpu->arch.pio.in = in;
2975 vcpu->arch.pio.string = 0;
2976 vcpu->arch.pio.down = 0;
ad312c7c 2977 vcpu->arch.pio.rep = 0;
de7d789a 2978
229456fc
MT		 2979 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2980 size, 1);
2714d1d3 2981
5fdbf976
MT		 2982 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2983 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2984
bda9020e 2985 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2986 complete_pio(vcpu);
2987 return 1;
2988 }
2989 return 0;
2990}
2991EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2992
2993int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2994 int size, unsigned long count, int down,
2995 gva_t address, int rep, unsigned port)
2996{
2997 unsigned now, in_page;
0f346074 2998 int ret = 0;
de7d789a
CO		 2999
3000 vcpu->run->exit_reason = KVM_EXIT_IO;
3001 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3002 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3003 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3004 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3005 vcpu->run->io.port = vcpu->arch.pio.port = port;
3006 vcpu->arch.pio.in = in;
3007 vcpu->arch.pio.string = 1;
3008 vcpu->arch.pio.down = down;
ad312c7c 3009 vcpu->arch.pio.rep = rep;
de7d789a 3010
229456fc
MT		 3011 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3012 size, count);
2714d1d3 3013
de7d789a
CO		 3014 if (!count) {
3015 kvm_x86_ops->skip_emulated_instruction(vcpu);
3016 return 1;
3017 }
3018
3019 if (!down)
3020 in_page = PAGE_SIZE - offset_in_page(address);
3021 else
3022 in_page = offset_in_page(address) + size;
3023 now = min(count, (unsigned long)in_page / size);
0f346074 3024 if (!now)
de7d789a 3025 now = 1;
de7d789a
CO		 3026 if (down) {
3027 /*
3028 * String I/O in reverse. Yuck. Kill the guest, fix later.
3029 */
3030 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3031 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3032 return 1;
3033 }
3034 vcpu->run->io.count = now;
ad312c7c 3035 vcpu->arch.pio.cur_count = now;
de7d789a 3036
ad312c7c 3037 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3038 kvm_x86_ops->skip_emulated_instruction(vcpu);
3039
0f346074 3040 vcpu->arch.pio.guest_gva = address;
de7d789a 3041
ad312c7c 3042 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3043 /* string PIO write */
3044 ret = pio_copy_data(vcpu);
0f346074
IE		 3045 if (ret == X86EMUL_PROPAGATE_FAULT) {
3046 kvm_inject_gp(vcpu, 0);
3047 return 1;
3048 }
bda9020e 3049 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3050 complete_pio(vcpu);
ad312c7c 3051 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3052 ret = 1;
3053 }
bda9020e
MT		 3054 }
3055 /* no string PIO read support yet */
de7d789a
CO		 3056
3057 return ret;
3058}
3059EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3060
c8076604
GH		 3061static void bounce_off(void *info)
3062{
3063 /* nothing */
3064}
3065
3066static unsigned int ref_freq;
3067static unsigned long tsc_khz_ref;
3068
3069static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3070 void *data)
3071{
3072 struct cpufreq_freqs *freq = data;
3073 struct kvm *kvm;
3074 struct kvm_vcpu *vcpu;
3075 int i, send_ipi = 0;
3076
3077 if (!ref_freq)
3078 ref_freq = freq->old;
3079
3080 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3081 return 0;
3082 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3083 return 0;
3084 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3085
3086 spin_lock(&kvm_lock);
3087 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3088 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3089 if (vcpu->cpu != freq->cpu)
3090 continue;
3091 if (!kvm_request_guest_time_update(vcpu))
3092 continue;
3093 if (vcpu->cpu != smp_processor_id())
3094 send_ipi++;
3095 }
3096 }
3097 spin_unlock(&kvm_lock);
3098
3099 if (freq->old < freq->new && send_ipi) {
3100 /*
3101 * We upscale the frequency. Must make the guest
3102 * doesn't see old kvmclock values while running with
3103 * the new frequency, otherwise we risk the guest sees
3104 * time go backwards.
3105 *
3106 * In case we update the frequency for another cpu
3107 * (which might be in guest context) send an interrupt
3108 * to kick the cpu out of guest context. Next time
3109 * guest context is entered kvmclock will be updated,
3110 * so the guest will not see stale values.
3111 */
3112 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3113 }
3114 return 0;
3115}
3116
3117static struct notifier_block kvmclock_cpufreq_notifier_block = {
3118 .notifier_call = kvmclock_cpufreq_notifier
3119};
3120
f8c16bba 3121int kvm_arch_init(void *opaque)
043405e1 3122{
c8076604 3123 int r, cpu;
f8c16bba
ZX		 3124 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3125
f8c16bba
ZX		 3126 if (kvm_x86_ops) {
3127 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3128 r = -EEXIST;
3129 goto out;
f8c16bba
ZX		 3130 }
3131
3132 if (!ops->cpu_has_kvm_support()) {
3133 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3134 r = -EOPNOTSUPP;
3135 goto out;
f8c16bba
ZX		 3136 }
3137 if (ops->disabled_by_bios()) {
3138 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3139 r = -EOPNOTSUPP;
3140 goto out;
f8c16bba
ZX		 3141 }
3142
97db56ce
AK		 3143 r = kvm_mmu_module_init();
3144 if (r)
3145 goto out;
3146
3147 kvm_init_msr_list();
3148
f8c16bba 3149 kvm_x86_ops = ops;
56c6d28a 3150 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3151 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3152 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3153 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3154
3155 for_each_possible_cpu(cpu)
3156 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3157 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3158 tsc_khz_ref = tsc_khz;
3159 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3160 CPUFREQ_TRANSITION_NOTIFIER);
3161 }
3162
f8c16bba 3163 return 0;
56c6d28a
ZX		 3164
3165out:
56c6d28a 3166 return r;
043405e1 3167}
8776e519 3168
f8c16bba
ZX		 3169void kvm_arch_exit(void)
3170{
888d256e
JK		 3171 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3172 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3173 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3174 kvm_x86_ops = NULL;
56c6d28a
ZX		 3175 kvm_mmu_module_exit();
3176}
f8c16bba 3177
8776e519
HB		 3178int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3179{
3180 ++vcpu->stat.halt_exits;
3181 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3182 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3183 return 1;
3184 } else {
3185 vcpu->run->exit_reason = KVM_EXIT_HLT;
3186 return 0;
3187 }
3188}
3189EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3190
2f333bcb
MT		 3191static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3192 unsigned long a1)
3193{
3194 if (is_long_mode(vcpu))
3195 return a0;
3196 else
3197 return a0 | ((gpa_t)a1 << 32);
3198}
3199
8776e519
HB		 3200int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3201{
3202 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3203 int r = 1;
8776e519 3204
5fdbf976
MT		 3205 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3206 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3207 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3208 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3209 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3210
229456fc 3211 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3212
8776e519
HB		 3213 if (!is_long_mode(vcpu)) {
3214 nr &= 0xFFFFFFFF;
3215 a0 &= 0xFFFFFFFF;
3216 a1 &= 0xFFFFFFFF;
3217 a2 &= 0xFFFFFFFF;
3218 a3 &= 0xFFFFFFFF;
3219 }
3220
07708c4a
JK		 3221 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3222 ret = -KVM_EPERM;
3223 goto out;
3224 }
3225
8776e519 3226 switch (nr) {
b93463aa
AK		 3227 case KVM_HC_VAPIC_POLL_IRQ:
3228 ret = 0;
3229 break;
2f333bcb
MT		 3230 case KVM_HC_MMU_OP:
3231 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3232 break;
8776e519
HB		 3233 default:
3234 ret = -KVM_ENOSYS;
3235 break;
3236 }
07708c4a 3237out:
5fdbf976 3238 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3239 ++vcpu->stat.hypercalls;
2f333bcb 3240 return r;
8776e519
HB		 3241}
3242EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3243
3244int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3245{
3246 char instruction[3];
3247 int ret = 0;
5fdbf976 3248 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3249
8776e519
HB		 3250
3251 /*
3252 * Blow out the MMU to ensure that no other VCPU has an active mapping
3253 * to ensure that the updated hypercall appears atomically across all
3254 * VCPUs.
3255 */
3256 kvm_mmu_zap_all(vcpu->kvm);
3257
8776e519 3258 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3259 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3260 != X86EMUL_CONTINUE)
3261 ret = -EFAULT;
3262
8776e519
HB		 3263 return ret;
3264}
3265
3266static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3267{
3268 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3269}
3270
3271void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3272{
3273 struct descriptor_table dt = { limit, base };
3274
3275 kvm_x86_ops->set_gdt(vcpu, &dt);
3276}
3277
3278void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3279{
3280 struct descriptor_table dt = { limit, base };
3281
3282 kvm_x86_ops->set_idt(vcpu, &dt);
3283}
3284
3285void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3286 unsigned long *rflags)
3287{
2d3ad1f4 3288 kvm_lmsw(vcpu, msw);
8776e519
HB		 3289 *rflags = kvm_x86_ops->get_rflags(vcpu);
3290}
3291
3292unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3293{
54e445ca
JR		 3294 unsigned long value;
3295
8776e519
HB		 3296 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3297 switch (cr) {
3298 case 0:
54e445ca
JR		 3299 value = vcpu->arch.cr0;
3300 break;
8776e519 3301 case 2:
54e445ca
JR		 3302 value = vcpu->arch.cr2;
3303 break;
8776e519 3304 case 3:
54e445ca
JR		 3305 value = vcpu->arch.cr3;
3306 break;
8776e519 3307 case 4:
54e445ca
JR		 3308 value = vcpu->arch.cr4;
3309 break;
152ff9be 3310 case 8:
54e445ca
JR		 3311 value = kvm_get_cr8(vcpu);
3312 break;
8776e519 3313 default:
b8688d51 3314 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3315 return 0;
3316 }
54e445ca
JR		 3317
3318 return value;
8776e519
HB		 3319}
3320
3321void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3322 unsigned long *rflags)
3323{
3324 switch (cr) {
3325 case 0:
2d3ad1f4 3326 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3327 *rflags = kvm_x86_ops->get_rflags(vcpu);
3328 break;
3329 case 2:
ad312c7c 3330 vcpu->arch.cr2 = val;
8776e519
HB		 3331 break;
3332 case 3:
2d3ad1f4 3333 kvm_set_cr3(vcpu, val);
8776e519
HB		 3334 break;
3335 case 4:
2d3ad1f4 3336 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3337 break;
152ff9be 3338 case 8:
2d3ad1f4 3339 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3340 break;
8776e519 3341 default:
b8688d51 3342 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3343 }
3344}
3345
07716717
DK		 3346static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3347{
ad312c7c
ZX		 3348 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3349 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3350
3351 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3352 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3353 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3354 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3355 if (ej->function == e->function) {
3356 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3357 return j;
3358 }
3359 }
3360 return 0; /* silence gcc, even though control never reaches here */
3361}
3362
3363/* find an entry with matching function, matching index (if needed), and that
3364 * should be read next (if it's stateful) */
3365static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3366 u32 function, u32 index)
3367{
3368 if (e->function != function)
3369 return 0;
3370 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3371 return 0;
3372 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3373 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3374 return 0;
3375 return 1;
3376}
3377
d8017474
AG		 3378struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3379 u32 function, u32 index)
8776e519
HB		 3380{
3381 int i;
d8017474 3382 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3383
ad312c7c 3384 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3385 struct kvm_cpuid_entry2 *e;
3386
ad312c7c 3387 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3388 if (is_matching_cpuid_entry(e, function, index)) {
3389 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3390 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3391 best = e;
3392 break;
3393 }
3394 /*
3395 * Both basic or both extended?
3396 */
3397 if (((e->function ^ function) & 0x80000000) == 0)
3398 if (!best || e->function > best->function)
3399 best = e;
3400 }
d8017474
AG		 3401 return best;
3402}
3403
82725b20
DE		 3404int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3405{
3406 struct kvm_cpuid_entry2 *best;
3407
3408 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3409 if (best)
3410 return best->eax & 0xff;
3411 return 36;
3412}
3413
d8017474
AG		 3414void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3415{
3416 u32 function, index;
3417 struct kvm_cpuid_entry2 *best;
3418
3419 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3420 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3421 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3422 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3423 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3424 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3425 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3426 if (best) {
5fdbf976
MT		 3427 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3428 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3429 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3430 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3431 }
8776e519 3432 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3433 trace_kvm_cpuid(function,
3434 kvm_register_read(vcpu, VCPU_REGS_RAX),
3435 kvm_register_read(vcpu, VCPU_REGS_RBX),
3436 kvm_register_read(vcpu, VCPU_REGS_RCX),
3437 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3438}
3439EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3440
b6c7a5dc
HB		 3441/*
3442 * Check if userspace requested an interrupt window, and that the
3443 * interrupt window is open.
3444 *
3445 * No need to exit to userspace if we already have an interrupt queued.
3446 */
3447static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3448 struct kvm_run *kvm_run)
3449{
8061823a 3450 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3451 kvm_run->request_interrupt_window &&
5df56646 3452 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3453}
3454
3455static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3456 struct kvm_run *kvm_run)
3457{
3458 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3459 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3460 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3461 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3462 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3463 else
b6c7a5dc 3464 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3465 kvm_arch_interrupt_allowed(vcpu) &&
3466 !kvm_cpu_has_interrupt(vcpu) &&
3467 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3468}
3469
b93463aa
AK		 3470static void vapic_enter(struct kvm_vcpu *vcpu)
3471{
3472 struct kvm_lapic *apic = vcpu->arch.apic;
3473 struct page *page;
3474
3475 if (!apic || !apic->vapic_addr)
3476 return;
3477
3478 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3479
3480 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3481}
3482
3483static void vapic_exit(struct kvm_vcpu *vcpu)
3484{
3485 struct kvm_lapic *apic = vcpu->arch.apic;
3486
3487 if (!apic || !apic->vapic_addr)
3488 return;
3489
f8b78fa3 3490 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3491 kvm_release_page_dirty(apic->vapic_page);
3492 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3493 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3494}
3495
95ba8273
GN		 3496static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3497{
3498 int max_irr, tpr;
3499
3500 if (!kvm_x86_ops->update_cr8_intercept)
3501 return;
3502
8db3baa2
GN		 3503 if (!vcpu->arch.apic->vapic_addr)
3504 max_irr = kvm_lapic_find_highest_irr(vcpu);
3505 else
3506 max_irr = -1;
95ba8273
GN		 3507
3508 if (max_irr != -1)
3509 max_irr >>= 4;
3510
3511 tpr = kvm_lapic_get_cr8(vcpu);
3512
3513 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3514}
3515
b59bb7bd 3516static void inject_pending_event(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3517{
3518 /* try to reinject previous events if any */
b59bb7bd
GN		 3519 if (vcpu->arch.exception.pending) {
3520 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3521 vcpu->arch.exception.has_error_code,
3522 vcpu->arch.exception.error_code);
3523 return;
3524 }
3525
95ba8273
GN		 3526 if (vcpu->arch.nmi_injected) {
3527 kvm_x86_ops->set_nmi(vcpu);
3528 return;
3529 }
3530
3531 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3532 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3533 return;
3534 }
3535
3536 /* try to inject new event if pending */
3537 if (vcpu->arch.nmi_pending) {
3538 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3539 vcpu->arch.nmi_pending = false;
3540 vcpu->arch.nmi_injected = true;
3541 kvm_x86_ops->set_nmi(vcpu);
3542 }
3543 } else if (kvm_cpu_has_interrupt(vcpu)) {
3544 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3545 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3546 false);
3547 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3548 }
3549 }
3550}
3551
d7690175 3552static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3553{
3554 int r;
6a8b1d13
GN		 3555 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3556 kvm_run->request_interrupt_window;
b6c7a5dc 3557
2e53d63a
MT		 3558 if (vcpu->requests)
3559 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3560 kvm_mmu_unload(vcpu);
3561
b6c7a5dc
HB		 3562 r = kvm_mmu_reload(vcpu);
3563 if (unlikely(r))
3564 goto out;
3565
2f52d58c
AK		 3566 if (vcpu->requests) {
3567 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3568 __kvm_migrate_timers(vcpu);
c8076604
GH		 3569 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3570 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3571 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3572 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3573 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3574 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3575 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3576 &vcpu->requests)) {
3577 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3578 r = 0;
3579 goto out;
3580 }
71c4dfaf
JR		 3581 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3582 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3583 r = 0;
3584 goto out;
3585 }
2f52d58c 3586 }
b93463aa 3587
b6c7a5dc
HB		 3588 preempt_disable();
3589
3590 kvm_x86_ops->prepare_guest_switch(vcpu);
3591 kvm_load_guest_fpu(vcpu);
3592
3593 local_irq_disable();
3594
32f88400
MT		 3595 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3596 smp_mb__after_clear_bit();
3597
d7690175 3598 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3599 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3600 local_irq_enable();
3601 preempt_enable();
3602 r = 1;
3603 goto out;
3604 }
3605
b59bb7bd 3606 inject_pending_event(vcpu, kvm_run);
b6c7a5dc 3607
6a8b1d13
GN		 3608 /* enable NMI/IRQ window open exits if needed */
3609 if (vcpu->arch.nmi_pending)
3610 kvm_x86_ops->enable_nmi_window(vcpu);
3611 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3612 kvm_x86_ops->enable_irq_window(vcpu);
3613
95ba8273 3614 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3615 update_cr8_intercept(vcpu);
3616 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3617 }
b93463aa 3618
3200f405
MT		 3619 up_read(&vcpu->kvm->slots_lock);
3620
b6c7a5dc
HB		 3621 kvm_guest_enter();
3622
42dbaa5a
JK		 3623 get_debugreg(vcpu->arch.host_dr6, 6);
3624 get_debugreg(vcpu->arch.host_dr7, 7);
3625 if (unlikely(vcpu->arch.switch_db_regs)) {
3626 get_debugreg(vcpu->arch.host_db[0], 0);
3627 get_debugreg(vcpu->arch.host_db[1], 1);
3628 get_debugreg(vcpu->arch.host_db[2], 2);
3629 get_debugreg(vcpu->arch.host_db[3], 3);
3630
3631 set_debugreg(0, 7);
3632 set_debugreg(vcpu->arch.eff_db[0], 0);
3633 set_debugreg(vcpu->arch.eff_db[1], 1);
3634 set_debugreg(vcpu->arch.eff_db[2], 2);
3635 set_debugreg(vcpu->arch.eff_db[3], 3);
3636 }
b6c7a5dc 3637
229456fc 3638 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3639 kvm_x86_ops->run(vcpu, kvm_run);
3640
42dbaa5a
JK		 3641 if (unlikely(vcpu->arch.switch_db_regs)) {
3642 set_debugreg(0, 7);
3643 set_debugreg(vcpu->arch.host_db[0], 0);
3644 set_debugreg(vcpu->arch.host_db[1], 1);
3645 set_debugreg(vcpu->arch.host_db[2], 2);
3646 set_debugreg(vcpu->arch.host_db[3], 3);
3647 }
3648 set_debugreg(vcpu->arch.host_dr6, 6);
3649 set_debugreg(vcpu->arch.host_dr7, 7);
3650
32f88400 3651 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3652 local_irq_enable();
3653
3654 ++vcpu->stat.exits;
3655
3656 /*
3657 * We must have an instruction between local_irq_enable() and
3658 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3659 * the interrupt shadow. The stat.exits increment will do nicely.
3660 * But we need to prevent reordering, hence this barrier():
3661 */
3662 barrier();
3663
3664 kvm_guest_exit();
3665
3666 preempt_enable();
3667
3200f405
MT		 3668 down_read(&vcpu->kvm->slots_lock);
3669
b6c7a5dc
HB		 3670 /*
3671 * Profile KVM exit RIPs:
3672 */
3673 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3674 unsigned long rip = kvm_rip_read(vcpu);
3675 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3676 }
3677
298101da 3678
b93463aa
AK		 3679 kvm_lapic_sync_from_vapic(vcpu);
3680
b6c7a5dc 3681 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3682out:
3683 return r;
3684}
b6c7a5dc 3685
09cec754 3686
d7690175
MT		 3687static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3688{
3689 int r;
3690
3691 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3692 pr_debug("vcpu %d received sipi with vector # %x\n",
3693 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3694 kvm_lapic_reset(vcpu);
5f179287 3695 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3696 if (r)
3697 return r;
3698 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3699 }
3700
d7690175
MT		 3701 down_read(&vcpu->kvm->slots_lock);
3702 vapic_enter(vcpu);
3703
3704 r = 1;
3705 while (r > 0) {
af2152f5 3706 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3707 r = vcpu_enter_guest(vcpu, kvm_run);
3708 else {
3709 up_read(&vcpu->kvm->slots_lock);
3710 kvm_vcpu_block(vcpu);
3711 down_read(&vcpu->kvm->slots_lock);
3712 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3713 {
3714 switch(vcpu->arch.mp_state) {
3715 case KVM_MP_STATE_HALTED:
d7690175 3716 vcpu->arch.mp_state =
09cec754
GN		 3717 KVM_MP_STATE_RUNNABLE;
3718 case KVM_MP_STATE_RUNNABLE:
3719 break;
3720 case KVM_MP_STATE_SIPI_RECEIVED:
3721 default:
3722 r = -EINTR;
3723 break;
3724 }
3725 }
d7690175
MT		 3726 }
3727
09cec754
GN		 3728 if (r <= 0)
3729 break;
3730
3731 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3732 if (kvm_cpu_has_pending_timer(vcpu))
3733 kvm_inject_pending_timer_irqs(vcpu);
3734
3735 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3736 r = -EINTR;
3737 kvm_run->exit_reason = KVM_EXIT_INTR;
3738 ++vcpu->stat.request_irq_exits;
3739 }
3740 if (signal_pending(current)) {
3741 r = -EINTR;
3742 kvm_run->exit_reason = KVM_EXIT_INTR;
3743 ++vcpu->stat.signal_exits;
3744 }
3745 if (need_resched()) {
3746 up_read(&vcpu->kvm->slots_lock);
3747 kvm_resched(vcpu);
3748 down_read(&vcpu->kvm->slots_lock);
d7690175 3749 }
b6c7a5dc
HB		 3750 }
3751
d7690175 3752 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3753 post_kvm_run_save(vcpu, kvm_run);
3754
b93463aa
AK		 3755 vapic_exit(vcpu);
3756
b6c7a5dc
HB		 3757 return r;
3758}
3759
3760int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3761{
3762 int r;
3763 sigset_t sigsaved;
3764
3765 vcpu_load(vcpu);
3766
ac9f6dc0
AK		 3767 if (vcpu->sigset_active)
3768 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3769
a4535290 3770 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3771 kvm_vcpu_block(vcpu);
d7690175 3772 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3773 r = -EAGAIN;
3774 goto out;
b6c7a5dc
HB		 3775 }
3776
b6c7a5dc
HB		 3777 /* re-sync apic's tpr */
3778 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3779 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3780
ad312c7c 3781 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3782 r = complete_pio(vcpu);
3783 if (r)
3784 goto out;
3785 }
3786#if CONFIG_HAS_IOMEM
3787 if (vcpu->mmio_needed) {
3788 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3789 vcpu->mmio_read_completed = 1;
3790 vcpu->mmio_needed = 0;
3200f405
MT		 3791
3792 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3793 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3794 vcpu->arch.mmio_fault_cr2, 0,
3795 EMULTYPE_NO_DECODE);
3200f405 3796 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3797 if (r == EMULATE_DO_MMIO) {
3798 /*
3799 * Read-modify-write. Back to userspace.
3800 */
3801 r = 0;
3802 goto out;
3803 }
3804 }
3805#endif
5fdbf976
MT		 3806 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3807 kvm_register_write(vcpu, VCPU_REGS_RAX,
3808 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3809
3810 r = __vcpu_run(vcpu, kvm_run);
3811
3812out:
3813 if (vcpu->sigset_active)
3814 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3815
3816 vcpu_put(vcpu);
3817 return r;
3818}
3819
3820int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3821{
3822 vcpu_load(vcpu);
3823
5fdbf976
MT		 3824 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3825 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3826 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3827 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3828 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3829 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3830 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3831 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3832#ifdef CONFIG_X86_64
5fdbf976
MT		 3833 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3834 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3835 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3836 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3837 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3838 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3839 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3840 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3841#endif
3842
5fdbf976 3843 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3844 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3845
3846 /*
3847 * Don't leak debug flags in case they were set for guest debugging
3848 */
d0bfb940 3849 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3850 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3851
3852 vcpu_put(vcpu);
3853
3854 return 0;
3855}
3856
3857int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3858{
3859 vcpu_load(vcpu);
3860
5fdbf976
MT		 3861 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3862 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3863 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3864 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3865 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3866 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3867 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3868 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3869#ifdef CONFIG_X86_64
5fdbf976
MT		 3870 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3871 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3872 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3873 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3874 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3875 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3876 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3877 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3878
b6c7a5dc
HB		 3879#endif
3880
5fdbf976 3881 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3882 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3883
b6c7a5dc 3884
b4f14abd
JK		 3885 vcpu->arch.exception.pending = false;
3886
b6c7a5dc
HB		 3887 vcpu_put(vcpu);
3888
3889 return 0;
3890}
3891
3e6e0aab
GT		 3892void kvm_get_segment(struct kvm_vcpu *vcpu,
3893 struct kvm_segment *var, int seg)
b6c7a5dc 3894{
14af3f3c 3895 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3896}
3897
3898void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3899{
3900 struct kvm_segment cs;
3901
3e6e0aab 3902 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3903 *db = cs.db;
3904 *l = cs.l;
3905}
3906EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3907
3908int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3909 struct kvm_sregs *sregs)
3910{
3911 struct descriptor_table dt;
b6c7a5dc
HB		 3912
3913 vcpu_load(vcpu);
3914
3e6e0aab
GT		 3915 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3916 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3917 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3918 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3919 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3920 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3921
3e6e0aab
GT		 3922 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3923 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3924
3925 kvm_x86_ops->get_idt(vcpu, &dt);
3926 sregs->idt.limit = dt.limit;
3927 sregs->idt.base = dt.base;
3928 kvm_x86_ops->get_gdt(vcpu, &dt);
3929 sregs->gdt.limit = dt.limit;
3930 sregs->gdt.base = dt.base;
3931
3932 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3933 sregs->cr0 = vcpu->arch.cr0;
3934 sregs->cr2 = vcpu->arch.cr2;
3935 sregs->cr3 = vcpu->arch.cr3;
3936 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3937 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3938 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3939 sregs->apic_base = kvm_get_apic_base(vcpu);
3940
923c61bb 3941 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3942
36752c9b 3943 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3944 set_bit(vcpu->arch.interrupt.nr,
3945 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3946
b6c7a5dc
HB		 3947 vcpu_put(vcpu);
3948
3949 return 0;
3950}
3951
62d9f0db
MT		 3952int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3953 struct kvm_mp_state *mp_state)
3954{
3955 vcpu_load(vcpu);
3956 mp_state->mp_state = vcpu->arch.mp_state;
3957 vcpu_put(vcpu);
3958 return 0;
3959}
3960
3961int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3962 struct kvm_mp_state *mp_state)
3963{
3964 vcpu_load(vcpu);
3965 vcpu->arch.mp_state = mp_state->mp_state;
3966 vcpu_put(vcpu);
3967 return 0;
3968}
3969
3e6e0aab 3970static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3971 struct kvm_segment *var, int seg)
3972{
14af3f3c 3973 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3974}
3975
37817f29
IE		 3976static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3977 struct kvm_segment *kvm_desct)
3978{
46a359e7
AM		 3979 kvm_desct->base = get_desc_base(seg_desc);
3980 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 3981 if (seg_desc->g) {
3982 kvm_desct->limit <<= 12;
3983 kvm_desct->limit |= 0xfff;
3984 }
37817f29
IE		 3985 kvm_desct->selector = selector;
3986 kvm_desct->type = seg_desc->type;
3987 kvm_desct->present = seg_desc->p;
3988 kvm_desct->dpl = seg_desc->dpl;
3989 kvm_desct->db = seg_desc->d;
3990 kvm_desct->s = seg_desc->s;
3991 kvm_desct->l = seg_desc->l;
3992 kvm_desct->g = seg_desc->g;
3993 kvm_desct->avl = seg_desc->avl;
3994 if (!selector)
3995 kvm_desct->unusable = 1;
3996 else
3997 kvm_desct->unusable = 0;
3998 kvm_desct->padding = 0;
3999}
4000
b8222ad2
AS		 4001static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4002 u16 selector,
4003 struct descriptor_table *dtable)
37817f29
IE		 4004{
4005 if (selector & 1 << 2) {
4006 struct kvm_segment kvm_seg;
4007
3e6e0aab 4008 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4009
4010 if (kvm_seg.unusable)
4011 dtable->limit = 0;
4012 else
4013 dtable->limit = kvm_seg.limit;
4014 dtable->base = kvm_seg.base;
4015 }
4016 else
4017 kvm_x86_ops->get_gdt(vcpu, dtable);
4018}
4019
4020/* allowed just for 8 bytes segments */
4021static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4022 struct desc_struct *seg_desc)
4023{
98899aa0 4024 gpa_t gpa;
37817f29
IE		 4025 struct descriptor_table dtable;
4026 u16 index = selector >> 3;
4027
b8222ad2 4028 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4029
4030 if (dtable.limit < index * 8 + 7) {
4031 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4032 return 1;
4033 }
98899aa0
MT		 4034 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4035 gpa += index * 8;
4036 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 4037}
4038
4039/* allowed just for 8 bytes segments */
4040static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4041 struct desc_struct *seg_desc)
4042{
98899aa0 4043 gpa_t gpa;
37817f29
IE		 4044 struct descriptor_table dtable;
4045 u16 index = selector >> 3;
4046
b8222ad2 4047 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4048
4049 if (dtable.limit < index * 8 + 7)
4050 return 1;
98899aa0
MT		 4051 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4052 gpa += index * 8;
4053 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 4054}
4055
4056static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
4057 struct desc_struct *seg_desc)
4058{
46a359e7 4059 u32 base_addr = get_desc_base(seg_desc);
37817f29 4060
98899aa0 4061 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4062}
4063
37817f29
IE		 4064static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4065{
4066 struct kvm_segment kvm_seg;
4067
3e6e0aab 4068 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4069 return kvm_seg.selector;
4070}
4071
4072static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4073 u16 selector,
4074 struct kvm_segment *kvm_seg)
4075{
4076 struct desc_struct seg_desc;
4077
4078 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4079 return 1;
4080 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4081 return 0;
4082}
4083
2259e3a7 4084static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4085{
4086 struct kvm_segment segvar = {
4087 .base = selector << 4,
4088 .limit = 0xffff,
4089 .selector = selector,
4090 .type = 3,
4091 .present = 1,
4092 .dpl = 3,
4093 .db = 0,
4094 .s = 1,
4095 .l = 0,
4096 .g = 0,
4097 .avl = 0,
4098 .unusable = 0,
4099 };
4100 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4101 return 0;
4102}
4103
c0c7c04b
AL		 4104static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4105{
4106 return (seg != VCPU_SREG_LDTR) &&
4107 (seg != VCPU_SREG_TR) &&
4108 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_VM);
4109}
4110
3e6e0aab
GT		 4111int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4112 int type_bits, int seg)
37817f29
IE		 4113{
4114 struct kvm_segment kvm_seg;
4115
c0c7c04b 4116 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
f4bbd9aa 4117 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4118 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4119 return 1;
4120 kvm_seg.type |= type_bits;
4121
4122 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4123 seg != VCPU_SREG_LDTR)
4124 if (!kvm_seg.s)
4125 kvm_seg.unusable = 1;
4126
3e6e0aab 4127 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4128 return 0;
4129}
4130
4131static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4132 struct tss_segment_32 *tss)
4133{
4134 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4135 tss->eip = kvm_rip_read(vcpu);
37817f29 4136 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4137 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4138 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4139 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4140 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4141 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4142 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4143 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4144 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4145 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4146 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4147 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4148 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4149 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4150 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4151 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4152}
4153
4154static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4155 struct tss_segment_32 *tss)
4156{
4157 kvm_set_cr3(vcpu, tss->cr3);
4158
5fdbf976 4159 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4160 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4161
5fdbf976
MT		 4162 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4163 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4164 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4165 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4166 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4167 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4168 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4169 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4170
3e6e0aab 4171 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4172 return 1;
4173
3e6e0aab 4174 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4175 return 1;
4176
3e6e0aab 4177 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4178 return 1;
4179
3e6e0aab 4180 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4181 return 1;
4182
3e6e0aab 4183 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4184 return 1;
4185
3e6e0aab 4186 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4187 return 1;
4188
3e6e0aab 4189 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4190 return 1;
4191 return 0;
4192}
4193
4194static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4195 struct tss_segment_16 *tss)
4196{
5fdbf976 4197 tss->ip = kvm_rip_read(vcpu);
37817f29 4198 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4199 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4200 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4201 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4202 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4203 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4204 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4205 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4206 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4207
4208 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4209 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4210 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4211 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4212 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4213 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4214}
4215
4216static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4217 struct tss_segment_16 *tss)
4218{
5fdbf976 4219 kvm_rip_write(vcpu, tss->ip);
37817f29 4220 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4221 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4222 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4223 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4224 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4225 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4226 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4227 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4228 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4229
3e6e0aab 4230 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4231 return 1;
4232
3e6e0aab 4233 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4234 return 1;
4235
3e6e0aab 4236 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4237 return 1;
4238
3e6e0aab 4239 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4240 return 1;
4241
3e6e0aab 4242 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4243 return 1;
4244 return 0;
4245}
4246
8b2cf73c 4247static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4248 u16 old_tss_sel, u32 old_tss_base,
4249 struct desc_struct *nseg_desc)
37817f29
IE		 4250{
4251 struct tss_segment_16 tss_segment_16;
4252 int ret = 0;
4253
34198bf8
MT		 4254 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4255 sizeof tss_segment_16))
37817f29
IE		 4256 goto out;
4257
4258 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4259
34198bf8
MT		 4260 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4261 sizeof tss_segment_16))
37817f29 4262 goto out;
34198bf8
MT		 4263
4264 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4265 &tss_segment_16, sizeof tss_segment_16))
4266 goto out;
4267
b237ac37
GN		 4268 if (old_tss_sel != 0xffff) {
4269 tss_segment_16.prev_task_link = old_tss_sel;
4270
4271 if (kvm_write_guest(vcpu->kvm,
4272 get_tss_base_addr(vcpu, nseg_desc),
4273 &tss_segment_16.prev_task_link,
4274 sizeof tss_segment_16.prev_task_link))
4275 goto out;
4276 }
4277
37817f29
IE		 4278 if (load_state_from_tss16(vcpu, &tss_segment_16))
4279 goto out;
4280
4281 ret = 1;
4282out:
4283 return ret;
4284}
4285
8b2cf73c 4286static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4287 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4288 struct desc_struct *nseg_desc)
4289{
4290 struct tss_segment_32 tss_segment_32;
4291 int ret = 0;
4292
34198bf8
MT		 4293 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4294 sizeof tss_segment_32))
37817f29
IE		 4295 goto out;
4296
4297 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4298
34198bf8
MT		 4299 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4300 sizeof tss_segment_32))
4301 goto out;
4302
4303 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4304 &tss_segment_32, sizeof tss_segment_32))
37817f29 4305 goto out;
34198bf8 4306
b237ac37
GN		 4307 if (old_tss_sel != 0xffff) {
4308 tss_segment_32.prev_task_link = old_tss_sel;
4309
4310 if (kvm_write_guest(vcpu->kvm,
4311 get_tss_base_addr(vcpu, nseg_desc),
4312 &tss_segment_32.prev_task_link,
4313 sizeof tss_segment_32.prev_task_link))
4314 goto out;
4315 }
4316
37817f29
IE		 4317 if (load_state_from_tss32(vcpu, &tss_segment_32))
4318 goto out;
4319
4320 ret = 1;
4321out:
4322 return ret;
4323}
4324
4325int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4326{
4327 struct kvm_segment tr_seg;
4328 struct desc_struct cseg_desc;
4329 struct desc_struct nseg_desc;
4330 int ret = 0;
34198bf8
MT		 4331 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4332 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4333
34198bf8 4334 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4335
34198bf8
MT		 4336 /* FIXME: Handle errors. Failure to read either TSS or their
4337 * descriptors should generate a pagefault.
4338 */
37817f29
IE		 4339 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4340 goto out;
4341
34198bf8 4342 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4343 goto out;
4344
37817f29
IE		 4345 if (reason != TASK_SWITCH_IRET) {
4346 int cpl;
4347
4348 cpl = kvm_x86_ops->get_cpl(vcpu);
4349 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4350 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4351 return 1;
4352 }
4353 }
4354
46a359e7 4355 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4356 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4357 return 1;
4358 }
4359
4360 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4361 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4362 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4363 }
4364
4365 if (reason == TASK_SWITCH_IRET) {
4366 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4367 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4368 }
4369
64a7ec06
GN		 4370 /* set back link to prev task only if NT bit is set in eflags
4371 note that old_tss_sel is not used afetr this point */
4372 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4373 old_tss_sel = 0xffff;
37817f29 4374
b237ac37
GN		 4375 /* set back link to prev task only if NT bit is set in eflags
4376 note that old_tss_sel is not used afetr this point */
4377 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4378 old_tss_sel = 0xffff;
4379
37817f29 4380 if (nseg_desc.type & 8)
b237ac37
GN		 4381 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4382 old_tss_base, &nseg_desc);
37817f29 4383 else
b237ac37
GN		 4384 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4385 old_tss_base, &nseg_desc);
37817f29
IE		 4386
4387 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4388 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4389 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4390 }
4391
4392 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4393 nseg_desc.type |= (1 << 1);
37817f29
IE		 4394 save_guest_segment_descriptor(vcpu, tss_selector,
4395 &nseg_desc);
4396 }
4397
4398 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4399 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4400 tr_seg.type = 11;
3e6e0aab 4401 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4402out:
37817f29
IE		 4403 return ret;
4404}
4405EXPORT_SYMBOL_GPL(kvm_task_switch);
4406
b6c7a5dc
HB		 4407int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4408 struct kvm_sregs *sregs)
4409{
4410 int mmu_reset_needed = 0;
923c61bb 4411 int pending_vec, max_bits;
b6c7a5dc
HB		 4412 struct descriptor_table dt;
4413
4414 vcpu_load(vcpu);
4415
4416 dt.limit = sregs->idt.limit;
4417 dt.base = sregs->idt.base;
4418 kvm_x86_ops->set_idt(vcpu, &dt);
4419 dt.limit = sregs->gdt.limit;
4420 dt.base = sregs->gdt.base;
4421 kvm_x86_ops->set_gdt(vcpu, &dt);
4422
ad312c7c
ZX		 4423 vcpu->arch.cr2 = sregs->cr2;
4424 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4425 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4426
2d3ad1f4 4427 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4428
ad312c7c 4429 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4430 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4431 kvm_set_apic_base(vcpu, sregs->apic_base);
4432
4433 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4434
ad312c7c 4435 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4436 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4437 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4438
ad312c7c 4439 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4440 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4441 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4442 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4443
4444 if (mmu_reset_needed)
4445 kvm_mmu_reset_context(vcpu);
4446
923c61bb
GN		 4447 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4448 pending_vec = find_first_bit(
4449 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4450 if (pending_vec < max_bits) {
66fd3f7f 4451 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4452 pr_debug("Set back pending irq %d\n", pending_vec);
4453 if (irqchip_in_kernel(vcpu->kvm))
4454 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4455 }
4456
3e6e0aab
GT		 4457 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4458 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4459 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4460 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4461 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4462 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4463
3e6e0aab
GT		 4464 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4465 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4466
5f0269f5
ME		 4467 update_cr8_intercept(vcpu);
4468
9c3e4aab 4469 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4470 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4471 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4472 !(vcpu->arch.cr0 & X86_CR0_PE))
4473 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4474
b6c7a5dc
HB		 4475 vcpu_put(vcpu);
4476
4477 return 0;
4478}
4479
d0bfb940
JK		 4480int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4481 struct kvm_guest_debug *dbg)
b6c7a5dc 4482{
ae675ef0 4483 int i, r;
b6c7a5dc
HB		 4484
4485 vcpu_load(vcpu);
4486
ae675ef0
JK		 4487 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4488 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4489 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4490 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4491 vcpu->arch.switch_db_regs =
4492 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4493 } else {
4494 for (i = 0; i < KVM_NR_DB_REGS; i++)
4495 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4496 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4497 }
4498
b6c7a5dc
HB		 4499 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4500
d0bfb940
JK		 4501 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4502 kvm_queue_exception(vcpu, DB_VECTOR);
4503 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4504 kvm_queue_exception(vcpu, BP_VECTOR);
4505
b6c7a5dc
HB		 4506 vcpu_put(vcpu);
4507
4508 return r;
4509}
4510
d0752060
HB		 4511/*
4512 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4513 * we have asm/x86/processor.h
4514 */
4515struct fxsave {
4516 u16 cwd;
4517 u16 swd;
4518 u16 twd;
4519 u16 fop;
4520 u64 rip;
4521 u64 rdp;
4522 u32 mxcsr;
4523 u32 mxcsr_mask;
4524 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4525#ifdef CONFIG_X86_64
4526 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4527#else
4528 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4529#endif
4530};
4531
8b006791
ZX		 4532/*
4533 * Translate a guest virtual address to a guest physical address.
4534 */
4535int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4536 struct kvm_translation *tr)
4537{
4538 unsigned long vaddr = tr->linear_address;
4539 gpa_t gpa;
4540
4541 vcpu_load(vcpu);
72dc67a6 4542 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4543 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4544 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4545 tr->physical_address = gpa;
4546 tr->valid = gpa != UNMAPPED_GVA;
4547 tr->writeable = 1;
4548 tr->usermode = 0;
8b006791
ZX		 4549 vcpu_put(vcpu);
4550
4551 return 0;
4552}
4553
d0752060
HB		 4554int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4555{
ad312c7c 4556 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4557
4558 vcpu_load(vcpu);
4559
4560 memcpy(fpu->fpr, fxsave->st_space, 128);
4561 fpu->fcw = fxsave->cwd;
4562 fpu->fsw = fxsave->swd;
4563 fpu->ftwx = fxsave->twd;
4564 fpu->last_opcode = fxsave->fop;
4565 fpu->last_ip = fxsave->rip;
4566 fpu->last_dp = fxsave->rdp;
4567 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4568
4569 vcpu_put(vcpu);
4570
4571 return 0;
4572}
4573
4574int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4575{
ad312c7c 4576 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4577
4578 vcpu_load(vcpu);
4579
4580 memcpy(fxsave->st_space, fpu->fpr, 128);
4581 fxsave->cwd = fpu->fcw;
4582 fxsave->swd = fpu->fsw;
4583 fxsave->twd = fpu->ftwx;
4584 fxsave->fop = fpu->last_opcode;
4585 fxsave->rip = fpu->last_ip;
4586 fxsave->rdp = fpu->last_dp;
4587 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4588
4589 vcpu_put(vcpu);
4590
4591 return 0;
4592}
4593
4594void fx_init(struct kvm_vcpu *vcpu)
4595{
4596 unsigned after_mxcsr_mask;
4597
bc1a34f1
AA		 4598 /*
4599 * Touch the fpu the first time in non atomic context as if
4600 * this is the first fpu instruction the exception handler
4601 * will fire before the instruction returns and it'll have to
4602 * allocate ram with GFP_KERNEL.
4603 */
4604 if (!used_math())
d6e88aec 4605 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4606
d0752060
HB		 4607 /* Initialize guest FPU by resetting ours and saving into guest's */
4608 preempt_disable();
d6e88aec
AK		 4609 kvm_fx_save(&vcpu->arch.host_fx_image);
4610 kvm_fx_finit();
4611 kvm_fx_save(&vcpu->arch.guest_fx_image);
4612 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4613 preempt_enable();
4614
ad312c7c 4615 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4616 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4617 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4618 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4619 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4620}
4621EXPORT_SYMBOL_GPL(fx_init);
4622
4623void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4624{
4625 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4626 return;
4627
4628 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4629 kvm_fx_save(&vcpu->arch.host_fx_image);
4630 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4631}
4632EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4633
4634void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4635{
4636 if (!vcpu->guest_fpu_loaded)
4637 return;
4638
4639 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4640 kvm_fx_save(&vcpu->arch.guest_fx_image);
4641 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4642 ++vcpu->stat.fpu_reload;
d0752060
HB		 4643}
4644EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4645
4646void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4647{
7f1ea208
JR		 4648 if (vcpu->arch.time_page) {
4649 kvm_release_page_dirty(vcpu->arch.time_page);
4650 vcpu->arch.time_page = NULL;
4651 }
4652
e9b11c17
ZX		 4653 kvm_x86_ops->vcpu_free(vcpu);
4654}
4655
4656struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4657 unsigned int id)
4658{
26e5215f
AK		 4659 return kvm_x86_ops->vcpu_create(kvm, id);
4660}
e9b11c17 4661
26e5215f
AK		 4662int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4663{
4664 int r;
e9b11c17
ZX		 4665
4666 /* We do fxsave: this must be aligned. */
ad312c7c 4667 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4668
0bed3b56 4669 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4670 vcpu_load(vcpu);
4671 r = kvm_arch_vcpu_reset(vcpu);
4672 if (r == 0)
4673 r = kvm_mmu_setup(vcpu);
4674 vcpu_put(vcpu);
4675 if (r < 0)
4676 goto free_vcpu;
4677
26e5215f 4678 return 0;
e9b11c17
ZX		 4679free_vcpu:
4680 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4681 return r;
e9b11c17
ZX		 4682}
4683
d40ccc62 4684void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4685{
4686 vcpu_load(vcpu);
4687 kvm_mmu_unload(vcpu);
4688 vcpu_put(vcpu);
4689
4690 kvm_x86_ops->vcpu_free(vcpu);
4691}
4692
4693int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4694{
448fa4a9
JK		 4695 vcpu->arch.nmi_pending = false;
4696 vcpu->arch.nmi_injected = false;
4697
42dbaa5a
JK		 4698 vcpu->arch.switch_db_regs = 0;
4699 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4700 vcpu->arch.dr6 = DR6_FIXED_1;
4701 vcpu->arch.dr7 = DR7_FIXED_1;
4702
e9b11c17
ZX		 4703 return kvm_x86_ops->vcpu_reset(vcpu);
4704}
4705
4706void kvm_arch_hardware_enable(void *garbage)
4707{
4708 kvm_x86_ops->hardware_enable(garbage);
4709}
4710
4711void kvm_arch_hardware_disable(void *garbage)
4712{
4713 kvm_x86_ops->hardware_disable(garbage);
4714}
4715
4716int kvm_arch_hardware_setup(void)
4717{
4718 return kvm_x86_ops->hardware_setup();
4719}
4720
4721void kvm_arch_hardware_unsetup(void)
4722{
4723 kvm_x86_ops->hardware_unsetup();
4724}
4725
4726void kvm_arch_check_processor_compat(void *rtn)
4727{
4728 kvm_x86_ops->check_processor_compatibility(rtn);
4729}
4730
4731int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4732{
4733 struct page *page;
4734 struct kvm *kvm;
4735 int r;
4736
4737 BUG_ON(vcpu->kvm == NULL);
4738 kvm = vcpu->kvm;
4739
ad312c7c 4740 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4741 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4742 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4743 else
a4535290 4744 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4745
4746 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4747 if (!page) {
4748 r = -ENOMEM;
4749 goto fail;
4750 }
ad312c7c 4751 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4752
4753 r = kvm_mmu_create(vcpu);
4754 if (r < 0)
4755 goto fail_free_pio_data;
4756
4757 if (irqchip_in_kernel(kvm)) {
4758 r = kvm_create_lapic(vcpu);
4759 if (r < 0)
4760 goto fail_mmu_destroy;
4761 }
4762
890ca9ae
HY		 4763 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4764 GFP_KERNEL);
4765 if (!vcpu->arch.mce_banks) {
4766 r = -ENOMEM;
4767 goto fail_mmu_destroy;
4768 }
4769 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4770
e9b11c17
ZX		 4771 return 0;
4772
4773fail_mmu_destroy:
4774 kvm_mmu_destroy(vcpu);
4775fail_free_pio_data:
ad312c7c 4776 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4777fail:
4778 return r;
4779}
4780
4781void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4782{
4783 kvm_free_lapic(vcpu);
3200f405 4784 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4785 kvm_mmu_destroy(vcpu);
3200f405 4786 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4787 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4788}
d19a9cd2
ZX		 4789
4790struct kvm *kvm_arch_create_vm(void)
4791{
4792 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4793
4794 if (!kvm)
4795 return ERR_PTR(-ENOMEM);
4796
f05e70ac 4797 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4798 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4799
5550af4d
SY		 4800 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4801 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4802
53f658b3
MT		 4803 rdtscll(kvm->arch.vm_init_tsc);
4804
d19a9cd2
ZX		 4805 return kvm;
4806}
4807
4808static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4809{
4810 vcpu_load(vcpu);
4811 kvm_mmu_unload(vcpu);
4812 vcpu_put(vcpu);
4813}
4814
4815static void kvm_free_vcpus(struct kvm *kvm)
4816{
4817 unsigned int i;
988a2cae 4818 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4819
4820 /*
4821 * Unpin any mmu pages first.
4822 */
988a2cae
GN		 4823 kvm_for_each_vcpu(i, vcpu, kvm)
4824 kvm_unload_vcpu_mmu(vcpu);
4825 kvm_for_each_vcpu(i, vcpu, kvm)
4826 kvm_arch_vcpu_free(vcpu);
4827
4828 mutex_lock(&kvm->lock);
4829 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4830 kvm->vcpus[i] = NULL;
d19a9cd2 4831
988a2cae
GN		 4832 atomic_set(&kvm->online_vcpus, 0);
4833 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4834}
4835
ad8ba2cd
SY		 4836void kvm_arch_sync_events(struct kvm *kvm)
4837{
ba4cef31 4838 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4839}
4840
d19a9cd2
ZX		 4841void kvm_arch_destroy_vm(struct kvm *kvm)
4842{
6eb55818 4843 kvm_iommu_unmap_guest(kvm);
7837699f 4844 kvm_free_pit(kvm);
d7deeeb0
ZX		 4845 kfree(kvm->arch.vpic);
4846 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4847 kvm_free_vcpus(kvm);
4848 kvm_free_physmem(kvm);
3d45830c
AK		 4849 if (kvm->arch.apic_access_page)
4850 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4851 if (kvm->arch.ept_identity_pagetable)
4852 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4853 kfree(kvm);
4854}
0de10343
ZX		 4855
4856int kvm_arch_set_memory_region(struct kvm *kvm,
4857 struct kvm_userspace_memory_region *mem,
4858 struct kvm_memory_slot old,
4859 int user_alloc)
4860{
4861 int npages = mem->memory_size >> PAGE_SHIFT;
4862 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4863
4864 /*To keep backward compatibility with older userspace,
4865 *x86 needs to hanlde !user_alloc case.
4866 */
4867 if (!user_alloc) {
4868 if (npages && !old.rmap) {
604b38ac
AA		 4869 unsigned long userspace_addr;
4870
72dc67a6 4871 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4872 userspace_addr = do_mmap(NULL, 0,
4873 npages * PAGE_SIZE,
4874 PROT_READ | PROT_WRITE,
acee3c04 4875 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4876 0);
72dc67a6 4877 up_write(&current->mm->mmap_sem);
0de10343 4878
604b38ac
AA		 4879 if (IS_ERR((void *)userspace_addr))
4880 return PTR_ERR((void *)userspace_addr);
4881
4882 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4883 spin_lock(&kvm->mmu_lock);
4884 memslot->userspace_addr = userspace_addr;
4885 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4886 } else {
4887 if (!old.user_alloc && old.rmap) {
4888 int ret;
4889
72dc67a6 4890 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4891 ret = do_munmap(current->mm, old.userspace_addr,
4892 old.npages * PAGE_SIZE);
72dc67a6 4893 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4894 if (ret < 0)
4895 printk(KERN_WARNING
4896 "kvm_vm_ioctl_set_memory_region: "
4897 "failed to munmap memory\n");
4898 }
4899 }
4900 }
4901
7c8a83b7 4902 spin_lock(&kvm->mmu_lock);
f05e70ac 4903 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4904 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4905 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4906 }
4907
4908 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4909 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4910 kvm_flush_remote_tlbs(kvm);
4911
4912 return 0;
4913}
1d737c8a 4914
34d4cb8f
MT		 4915void kvm_arch_flush_shadow(struct kvm *kvm)
4916{
4917 kvm_mmu_zap_all(kvm);
8986ecc0 4918 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4919}
4920
1d737c8a
ZX		 4921int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4922{
a4535290 4923 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 4924 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4925 || vcpu->arch.nmi_pending ||
4926 (kvm_arch_interrupt_allowed(vcpu) &&
4927 kvm_cpu_has_interrupt(vcpu));
1d737c8a 4928}
5736199a 4929
5736199a
ZX		 4930void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4931{
32f88400
MT		 4932 int me;
4933 int cpu = vcpu->cpu;
5736199a
ZX		 4934
4935 if (waitqueue_active(&vcpu->wq)) {
4936 wake_up_interruptible(&vcpu->wq);
4937 ++vcpu->stat.halt_wakeup;
4938 }
32f88400
MT		 4939
4940 me = get_cpu();
4941 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4942 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4943 smp_send_reschedule(cpu);
e9571ed5 4944 put_cpu();
5736199a 4945}
78646121
GN		 4946
4947int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4948{
4949 return kvm_x86_ops->interrupt_allowed(vcpu);
4950}
229456fc
MT		 4951
4952EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4953EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4954EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4955EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4956EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
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