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KVM: VMX: trace clts and lmsw instructions as cr accesses
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
aec51dc4
AK		 42#include <trace/events/kvm.h>
43#undef TRACE_INCLUDE_FILE
229456fc
MT		 44#define CREATE_TRACE_POINTS
45#include "trace.h"
043405e1 46
24f1e32c 47#include <asm/debugreg.h>
043405e1 48#include <asm/uaccess.h>
d825ed0a 49#include <asm/msr.h>
a5f61300 50#include <asm/desc.h>
0bed3b56 51#include <asm/mtrr.h>
890ca9ae 52#include <asm/mce.h>
043405e1 53
313a3dc7 54#define MAX_IO_MSRS 256
a03490ed
CO		 55#define CR0_RESERVED_BITS \
56 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
57 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
58 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
59#define CR4_RESERVED_BITS \
60 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
61 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
62 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
63 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
64
65#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 66
67#define KVM_MAX_MCE_BANKS 32
68#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
69
50a37eb4
JR		 70/* EFER defaults:
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
73 */
74#ifdef CONFIG_X86_64
75static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
76#else
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
18863bdd
AK		 93#define KVM_NR_SHARED_MSRS 16
94
95struct kvm_shared_msrs_global {
96 int nr;
2bf78fa7 97 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 98};
99
100struct kvm_shared_msrs {
101 struct user_return_notifier urn;
102 bool registered;
2bf78fa7
SY		 103 struct kvm_shared_msr_values {
104 u64 host;
105 u64 curr;
106 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
110static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
111
417bc304 112struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 113 { "pf_fixed", VCPU_STAT(pf_fixed) },
114 { "pf_guest", VCPU_STAT(pf_guest) },
115 { "tlb_flush", VCPU_STAT(tlb_flush) },
116 { "invlpg", VCPU_STAT(invlpg) },
117 { "exits", VCPU_STAT(exits) },
118 { "io_exits", VCPU_STAT(io_exits) },
119 { "mmio_exits", VCPU_STAT(mmio_exits) },
120 { "signal_exits", VCPU_STAT(signal_exits) },
121 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 122 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 123 { "halt_exits", VCPU_STAT(halt_exits) },
124 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 125 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 126 { "request_irq", VCPU_STAT(request_irq_exits) },
127 { "irq_exits", VCPU_STAT(irq_exits) },
128 { "host_state_reload", VCPU_STAT(host_state_reload) },
129 { "efer_reload", VCPU_STAT(efer_reload) },
130 { "fpu_reload", VCPU_STAT(fpu_reload) },
131 { "insn_emulation", VCPU_STAT(insn_emulation) },
132 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 133 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 134 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 135 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
136 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
137 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
138 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
139 { "mmu_flooded", VM_STAT(mmu_flooded) },
140 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 141 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 142 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 143 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 144 { "largepages", VM_STAT(lpages) },
417bc304
HB		 145 { NULL }
146};
147
18863bdd
AK		 148static void kvm_on_user_return(struct user_return_notifier *urn)
149{
150 unsigned slot;
18863bdd
AK		 151 struct kvm_shared_msrs *locals
152 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 153 struct kvm_shared_msr_values *values;
18863bdd
AK		 154
155 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 156 values = &locals->values[slot];
157 if (values->host != values->curr) {
158 wrmsrl(shared_msrs_global.msrs[slot], values->host);
159 values->curr = values->host;
18863bdd
AK		 160 }
161 }
162 locals->registered = false;
163 user_return_notifier_unregister(urn);
164}
165
2bf78fa7 166static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 167{
2bf78fa7 168 struct kvm_shared_msrs *smsr;
18863bdd
AK		 169 u64 value;
170
2bf78fa7
SY		 171 smsr = &__get_cpu_var(shared_msrs);
172 /* only read, and nobody should modify it at this time,
173 * so don't need lock */
174 if (slot >= shared_msrs_global.nr) {
175 printk(KERN_ERR "kvm: invalid MSR slot!");
176 return;
177 }
178 rdmsrl_safe(msr, &value);
179 smsr->values[slot].host = value;
180 smsr->values[slot].curr = value;
181}
182
183void kvm_define_shared_msr(unsigned slot, u32 msr)
184{
18863bdd
AK		 185 if (slot >= shared_msrs_global.nr)
186 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 187 shared_msrs_global.msrs[slot] = msr;
188 /* we need ensured the shared_msr_global have been updated */
189 smp_wmb();
18863bdd
AK		 190}
191EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
192
193static void kvm_shared_msr_cpu_online(void)
194{
195 unsigned i;
18863bdd
AK		 196
197 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 198 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 199}
200
d5696725 201void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 202{
203 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
204
2bf78fa7 205 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 206 return;
2bf78fa7
SY		 207 smsr->values[slot].curr = value;
208 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 209 if (!smsr->registered) {
210 smsr->urn.on_user_return = kvm_on_user_return;
211 user_return_notifier_register(&smsr->urn);
212 smsr->registered = true;
213 }
214}
215EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
216
3548bab5
AK		 217static void drop_user_return_notifiers(void *ignore)
218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
221 if (smsr->registered)
222 kvm_on_user_return(&smsr->urn);
223}
224
5fb76f9b
CO		 225unsigned long segment_base(u16 selector)
226{
227 struct descriptor_table gdt;
a5f61300 228 struct desc_struct *d;
5fb76f9b
CO		 229 unsigned long table_base;
230 unsigned long v;
231
232 if (selector == 0)
233 return 0;
234
b792c344 235 kvm_get_gdt(&gdt);
5fb76f9b
CO		 236 table_base = gdt.base;
237
238 if (selector & 4) { /* from ldt */
b792c344 239 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 240
5fb76f9b
CO		 241 table_base = segment_base(ldt_selector);
242 }
a5f61300 243 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 244 v = get_desc_base(d);
5fb76f9b 245#ifdef CONFIG_X86_64
a5f61300
AK		 246 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
247 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 248#endif
249 return v;
250}
251EXPORT_SYMBOL_GPL(segment_base);
252
6866b83e
CO		 253u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254{
255 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 256 return vcpu->arch.apic_base;
6866b83e 257 else
ad312c7c 258 return vcpu->arch.apic_base;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
262void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
263{
264 /* TODO: reserve bits check */
265 if (irqchip_in_kernel(vcpu->kvm))
266 kvm_lapic_set_base(vcpu, data);
267 else
ad312c7c 268 vcpu->arch.apic_base = data;
6866b83e
CO		 269}
270EXPORT_SYMBOL_GPL(kvm_set_apic_base);
271
3fd28fce
ED		 272#define EXCPT_BENIGN 0
273#define EXCPT_CONTRIBUTORY 1
274#define EXCPT_PF 2
275
276static int exception_class(int vector)
277{
278 switch (vector) {
279 case PF_VECTOR:
280 return EXCPT_PF;
281 case DE_VECTOR:
282 case TS_VECTOR:
283 case NP_VECTOR:
284 case SS_VECTOR:
285 case GP_VECTOR:
286 return EXCPT_CONTRIBUTORY;
287 default:
288 break;
289 }
290 return EXCPT_BENIGN;
291}
292
293static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
294 unsigned nr, bool has_error, u32 error_code)
295{
296 u32 prev_nr;
297 int class1, class2;
298
299 if (!vcpu->arch.exception.pending) {
300 queue:
301 vcpu->arch.exception.pending = true;
302 vcpu->arch.exception.has_error_code = has_error;
303 vcpu->arch.exception.nr = nr;
304 vcpu->arch.exception.error_code = error_code;
305 return;
306 }
307
308 /* to check exception */
309 prev_nr = vcpu->arch.exception.nr;
310 if (prev_nr == DF_VECTOR) {
311 /* triple fault -> shutdown */
312 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
313 return;
314 }
315 class1 = exception_class(prev_nr);
316 class2 = exception_class(nr);
317 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
318 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
319 /* generate double fault per SDM Table 5-5 */
320 vcpu->arch.exception.pending = true;
321 vcpu->arch.exception.has_error_code = true;
322 vcpu->arch.exception.nr = DF_VECTOR;
323 vcpu->arch.exception.error_code = 0;
324 } else
325 /* replace previous exception with a new one in a hope
326 that instruction re-execution will regenerate lost
327 exception */
328 goto queue;
329}
330
298101da
AK		 331void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
3fd28fce 333 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 334}
335EXPORT_SYMBOL_GPL(kvm_queue_exception);
336
c3c91fee
AK		 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
338 u32 error_code)
339{
340 ++vcpu->stat.pf_guest;
ad312c7c 341 vcpu->arch.cr2 = addr;
c3c91fee
AK		 342 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
343}
344
3419ffc8
SY		 345void kvm_inject_nmi(struct kvm_vcpu *vcpu)
346{
347 vcpu->arch.nmi_pending = 1;
348}
349EXPORT_SYMBOL_GPL(kvm_inject_nmi);
350
298101da
AK		 351void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
352{
3fd28fce 353 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 354}
355EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
356
0a79b009
AK		 357/*
358 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
359 * a #GP and return false.
360 */
361bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 362{
0a79b009
AK		 363 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
364 return true;
365 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
366 return false;
298101da 367}
0a79b009 368EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 369
a03490ed
CO		 370/*
371 * Load the pae pdptrs. Return true is they are all valid.
372 */
373int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
374{
375 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
376 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
377 int i;
378 int ret;
ad312c7c 379 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 380
a03490ed
CO		 381 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
382 offset * sizeof(u64), sizeof(pdpte));
383 if (ret < 0) {
384 ret = 0;
385 goto out;
386 }
387 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 388 if (is_present_gpte(pdpte[i]) &&
20c466b5 389 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 390 ret = 0;
391 goto out;
392 }
393 }
394 ret = 1;
395
ad312c7c 396 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 397 __set_bit(VCPU_EXREG_PDPTR,
398 (unsigned long *)&vcpu->arch.regs_avail);
399 __set_bit(VCPU_EXREG_PDPTR,
400 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 401out:
a03490ed
CO		 402
403 return ret;
404}
cc4b6871 405EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 406
d835dfec
AK		 407static bool pdptrs_changed(struct kvm_vcpu *vcpu)
408{
ad312c7c 409 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 410 bool changed = true;
411 int r;
412
413 if (is_long_mode(vcpu) || !is_pae(vcpu))
414 return false;
415
6de4f3ad
AK		 416 if (!test_bit(VCPU_EXREG_PDPTR,
417 (unsigned long *)&vcpu->arch.regs_avail))
418 return true;
419
ad312c7c 420 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 421 if (r < 0)
422 goto out;
ad312c7c 423 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 424out:
d835dfec
AK		 425
426 return changed;
427}
428
2d3ad1f4 429void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 430{
431 if (cr0 & CR0_RESERVED_BITS) {
432 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 433 cr0, vcpu->arch.cr0);
c1a5d4f9 434 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 435 return;
436 }
437
438 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
439 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 440 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 441 return;
442 }
443
444 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
445 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
446 "and a clear PE flag\n");
c1a5d4f9 447 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 448 return;
449 }
450
451 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
452#ifdef CONFIG_X86_64
ad312c7c 453 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 454 int cs_db, cs_l;
455
456 if (!is_pae(vcpu)) {
457 printk(KERN_DEBUG "set_cr0: #GP, start paging "
458 "in long mode while PAE is disabled\n");
c1a5d4f9 459 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 460 return;
461 }
462 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
463 if (cs_l) {
464 printk(KERN_DEBUG "set_cr0: #GP, start paging "
465 "in long mode while CS.L == 1\n");
c1a5d4f9 466 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 467 return;
468
469 }
470 } else
471#endif
ad312c7c 472 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 473 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
474 "reserved bits\n");
c1a5d4f9 475 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 476 return;
477 }
478
479 }
480
481 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 482 vcpu->arch.cr0 = cr0;
a03490ed 483
a03490ed 484 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 485 return;
486}
2d3ad1f4 487EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 488
2d3ad1f4 489void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 490{
2d3ad1f4 491 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 492}
2d3ad1f4 493EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 494
2d3ad1f4 495void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 496{
fc78f519 497 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 498 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
499
a03490ed
CO		 500 if (cr4 & CR4_RESERVED_BITS) {
501 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 502 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 503 return;
504 }
505
506 if (is_long_mode(vcpu)) {
507 if (!(cr4 & X86_CR4_PAE)) {
508 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
509 "in long mode\n");
c1a5d4f9 510 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 511 return;
512 }
a2edf57f
AK		 513 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
514 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 515 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 516 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 517 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 518 return;
519 }
520
521 if (cr4 & X86_CR4_VMXE) {
522 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 523 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 524 return;
525 }
526 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 527 vcpu->arch.cr4 = cr4;
5a41accd 528 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 529 kvm_mmu_reset_context(vcpu);
a03490ed 530}
2d3ad1f4 531EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 532
2d3ad1f4 533void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 534{
ad312c7c 535 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 536 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 537 kvm_mmu_flush_tlb(vcpu);
538 return;
539 }
540
a03490ed
CO		 541 if (is_long_mode(vcpu)) {
542 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
543 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 544 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 545 return;
546 }
547 } else {
548 if (is_pae(vcpu)) {
549 if (cr3 & CR3_PAE_RESERVED_BITS) {
550 printk(KERN_DEBUG
551 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 552 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 553 return;
554 }
555 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
556 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
557 "reserved bits\n");
c1a5d4f9 558 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 559 return;
560 }
561 }
562 /*
563 * We don't check reserved bits in nonpae mode, because
564 * this isn't enforced, and VMware depends on this.
565 */
566 }
567
a03490ed
CO		 568 /*
569 * Does the new cr3 value map to physical memory? (Note, we
570 * catch an invalid cr3 even in real-mode, because it would
571 * cause trouble later on when we turn on paging anyway.)
572 *
573 * A real CPU would silently accept an invalid cr3 and would
574 * attempt to use it - with largely undefined (and often hard
575 * to debug) behavior on the guest side.
576 */
577 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 578 kvm_inject_gp(vcpu, 0);
a03490ed 579 else {
ad312c7c
ZX		 580 vcpu->arch.cr3 = cr3;
581 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 582 }
a03490ed 583}
2d3ad1f4 584EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 585
2d3ad1f4 586void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 587{
588 if (cr8 & CR8_RESERVED_BITS) {
589 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 590 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 591 return;
592 }
593 if (irqchip_in_kernel(vcpu->kvm))
594 kvm_lapic_set_tpr(vcpu, cr8);
595 else
ad312c7c 596 vcpu->arch.cr8 = cr8;
a03490ed 597}
2d3ad1f4 598EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 599
2d3ad1f4 600unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 601{
602 if (irqchip_in_kernel(vcpu->kvm))
603 return kvm_lapic_get_cr8(vcpu);
604 else
ad312c7c 605 return vcpu->arch.cr8;
a03490ed 606}
2d3ad1f4 607EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 608
d8017474
AG		 609static inline u32 bit(int bitno)
610{
611 return 1 << (bitno & 31);
612}
613
043405e1
CO		 614/*
615 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
616 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
617 *
618 * This list is modified at module load time to reflect the
e3267cbb
GC		 619 * capabilities of the host cpu. This capabilities test skips MSRs that are
620 * kvm-specific. Those are put in the beginning of the list.
043405e1 621 */
e3267cbb
GC		 622
623#define KVM_SAVE_MSRS_BEGIN 2
043405e1 624static u32 msrs_to_save[] = {
e3267cbb 625 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
043405e1
CO		 626 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
627 MSR_K6_STAR,
628#ifdef CONFIG_X86_64
629 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
630#endif
e3267cbb 631 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 632};
633
634static unsigned num_msrs_to_save;
635
636static u32 emulated_msrs[] = {
637 MSR_IA32_MISC_ENABLE,
638};
639
15c4a640
CO		 640static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
641{
f2b4b7dd 642 if (efer & efer_reserved_bits) {
15c4a640
CO		 643 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
644 efer);
c1a5d4f9 645 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 646 return;
647 }
648
649 if (is_paging(vcpu)
ad312c7c 650 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 651 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 652 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 653 return;
654 }
655
1b2fd70c
AG		 656 if (efer & EFER_FFXSR) {
657 struct kvm_cpuid_entry2 *feat;
658
659 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
660 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
661 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
662 kvm_inject_gp(vcpu, 0);
663 return;
664 }
665 }
666
d8017474
AG		 667 if (efer & EFER_SVME) {
668 struct kvm_cpuid_entry2 *feat;
669
670 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
671 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
672 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
673 kvm_inject_gp(vcpu, 0);
674 return;
675 }
676 }
677
15c4a640
CO		 678 kvm_x86_ops->set_efer(vcpu, efer);
679
680 efer &= ~EFER_LMA;
ad312c7c 681 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 682
ad312c7c 683 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 684
685 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
686 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 687}
688
f2b4b7dd
JR		 689void kvm_enable_efer_bits(u64 mask)
690{
691 efer_reserved_bits &= ~mask;
692}
693EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
694
695
15c4a640
CO		 696/*
697 * Writes msr value into into the appropriate "register".
698 * Returns 0 on success, non-0 otherwise.
699 * Assumes vcpu_load() was already called.
700 */
701int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
702{
703 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
704}
705
313a3dc7
CO		 706/*
707 * Adapt set_msr() to msr_io()'s calling convention
708 */
709static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
710{
711 return kvm_set_msr(vcpu, index, *data);
712}
713
18068523
GOC		 714static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
715{
716 static int version;
50d0a0f9 717 struct pvclock_wall_clock wc;
923de3cf 718 struct timespec boot;
18068523
GOC		 719
720 if (!wall_clock)
721 return;
722
723 version++;
724
18068523
GOC		 725 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
726
50d0a0f9
GH		 727 /*
728 * The guest calculates current wall clock time by adding
729 * system time (updated by kvm_write_guest_time below) to the
730 * wall clock specified here. guest system time equals host
731 * system time for us, thus we must fill in host boot time here.
732 */
923de3cf 733 getboottime(&boot);
50d0a0f9
GH		 734
735 wc.sec = boot.tv_sec;
736 wc.nsec = boot.tv_nsec;
737 wc.version = version;
18068523
GOC		 738
739 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
740
741 version++;
742 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 743}
744
50d0a0f9
GH		 745static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
746{
747 uint32_t quotient, remainder;
748
749 /* Don't try to replace with do_div(), this one calculates
750 * "(dividend << 32) / divisor" */
751 __asm__ ( "divl %4"
752 : "=a" (quotient), "=d" (remainder)
753 : "0" (0), "1" (dividend), "r" (divisor) );
754 return quotient;
755}
756
757static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
758{
759 uint64_t nsecs = 1000000000LL;
760 int32_t shift = 0;
761 uint64_t tps64;
762 uint32_t tps32;
763
764 tps64 = tsc_khz * 1000LL;
765 while (tps64 > nsecs*2) {
766 tps64 >>= 1;
767 shift--;
768 }
769
770 tps32 = (uint32_t)tps64;
771 while (tps32 <= (uint32_t)nsecs) {
772 tps32 <<= 1;
773 shift++;
774 }
775
776 hv_clock->tsc_shift = shift;
777 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
778
779 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 780 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 781 hv_clock->tsc_to_system_mul);
782}
783
c8076604
GH		 784static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
785
18068523
GOC		 786static void kvm_write_guest_time(struct kvm_vcpu *v)
787{
788 struct timespec ts;
789 unsigned long flags;
790 struct kvm_vcpu_arch *vcpu = &v->arch;
791 void *shared_kaddr;
463656c0 792 unsigned long this_tsc_khz;
18068523
GOC		 793
794 if ((!vcpu->time_page))
795 return;
796
463656c0
AK		 797 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
798 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
799 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
800 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 801 }
463656c0 802 put_cpu_var(cpu_tsc_khz);
50d0a0f9 803
18068523
GOC		 804 /* Keep irq disabled to prevent changes to the clock */
805 local_irq_save(flags);
af24a4e4 806 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 807 ktime_get_ts(&ts);
923de3cf 808 monotonic_to_bootbased(&ts);
18068523
GOC		 809 local_irq_restore(flags);
810
811 /* With all the info we got, fill in the values */
812
813 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 814 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
815
18068523
GOC		 816 /*
817 * The interface expects us to write an even number signaling that the
818 * update is finished. Since the guest won't see the intermediate
50d0a0f9 819 * state, we just increase by 2 at the end.
18068523 820 */
50d0a0f9 821 vcpu->hv_clock.version += 2;
18068523
GOC		 822
823 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
824
825 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 826 sizeof(vcpu->hv_clock));
18068523
GOC		 827
828 kunmap_atomic(shared_kaddr, KM_USER0);
829
830 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
831}
832
c8076604
GH		 833static int kvm_request_guest_time_update(struct kvm_vcpu *v)
834{
835 struct kvm_vcpu_arch *vcpu = &v->arch;
836
837 if (!vcpu->time_page)
838 return 0;
839 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
840 return 1;
841}
842
9ba075a6
AK		 843static bool msr_mtrr_valid(unsigned msr)
844{
845 switch (msr) {
846 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
847 case MSR_MTRRfix64K_00000:
848 case MSR_MTRRfix16K_80000:
849 case MSR_MTRRfix16K_A0000:
850 case MSR_MTRRfix4K_C0000:
851 case MSR_MTRRfix4K_C8000:
852 case MSR_MTRRfix4K_D0000:
853 case MSR_MTRRfix4K_D8000:
854 case MSR_MTRRfix4K_E0000:
855 case MSR_MTRRfix4K_E8000:
856 case MSR_MTRRfix4K_F0000:
857 case MSR_MTRRfix4K_F8000:
858 case MSR_MTRRdefType:
859 case MSR_IA32_CR_PAT:
860 return true;
861 case 0x2f8:
862 return true;
863 }
864 return false;
865}
866
d6289b93
MT		 867static bool valid_pat_type(unsigned t)
868{
869 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
870}
871
872static bool valid_mtrr_type(unsigned t)
873{
874 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
875}
876
877static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
878{
879 int i;
880
881 if (!msr_mtrr_valid(msr))
882 return false;
883
884 if (msr == MSR_IA32_CR_PAT) {
885 for (i = 0; i < 8; i++)
886 if (!valid_pat_type((data >> (i * 8)) & 0xff))
887 return false;
888 return true;
889 } else if (msr == MSR_MTRRdefType) {
890 if (data & ~0xcff)
891 return false;
892 return valid_mtrr_type(data & 0xff);
893 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
894 for (i = 0; i < 8 ; i++)
895 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
896 return false;
897 return true;
898 }
899
900 /* variable MTRRs */
901 return valid_mtrr_type(data & 0xff);
902}
903
9ba075a6
AK		 904static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
905{
0bed3b56
SY		 906 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
907
d6289b93 908 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 909 return 1;
910
0bed3b56
SY		 911 if (msr == MSR_MTRRdefType) {
912 vcpu->arch.mtrr_state.def_type = data;
913 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
914 } else if (msr == MSR_MTRRfix64K_00000)
915 p[0] = data;
916 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
917 p[1 + msr - MSR_MTRRfix16K_80000] = data;
918 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
919 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
920 else if (msr == MSR_IA32_CR_PAT)
921 vcpu->arch.pat = data;
922 else { /* Variable MTRRs */
923 int idx, is_mtrr_mask;
924 u64 *pt;
925
926 idx = (msr - 0x200) / 2;
927 is_mtrr_mask = msr - 0x200 - 2 * idx;
928 if (!is_mtrr_mask)
929 pt =
930 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
931 else
932 pt =
933 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
934 *pt = data;
935 }
936
937 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 938 return 0;
939}
15c4a640 940
890ca9ae 941static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 942{
890ca9ae
HY		 943 u64 mcg_cap = vcpu->arch.mcg_cap;
944 unsigned bank_num = mcg_cap & 0xff;
945
15c4a640 946 switch (msr) {
15c4a640 947 case MSR_IA32_MCG_STATUS:
890ca9ae 948 vcpu->arch.mcg_status = data;
15c4a640 949 break;
c7ac679c 950 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 951 if (!(mcg_cap & MCG_CTL_P))
952 return 1;
953 if (data != 0 && data != ~(u64)0)
954 return -1;
955 vcpu->arch.mcg_ctl = data;
956 break;
957 default:
958 if (msr >= MSR_IA32_MC0_CTL &&
959 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
960 u32 offset = msr - MSR_IA32_MC0_CTL;
961 /* only 0 or all 1s can be written to IA32_MCi_CTL */
962 if ((offset & 0x3) == 0 &&
963 data != 0 && data != ~(u64)0)
964 return -1;
965 vcpu->arch.mce_banks[offset] = data;
966 break;
967 }
968 return 1;
969 }
970 return 0;
971}
972
ffde22ac
ES		 973static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
974{
975 struct kvm *kvm = vcpu->kvm;
976 int lm = is_long_mode(vcpu);
977 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
978 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
979 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
980 : kvm->arch.xen_hvm_config.blob_size_32;
981 u32 page_num = data & ~PAGE_MASK;
982 u64 page_addr = data & PAGE_MASK;
983 u8 *page;
984 int r;
985
986 r = -E2BIG;
987 if (page_num >= blob_size)
988 goto out;
989 r = -ENOMEM;
990 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
991 if (!page)
992 goto out;
993 r = -EFAULT;
994 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
995 goto out_free;
996 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
997 goto out_free;
998 r = 0;
999out_free:
1000 kfree(page);
1001out:
1002 return r;
1003}
1004
15c4a640
CO		 1005int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1006{
1007 switch (msr) {
15c4a640
CO		 1008 case MSR_EFER:
1009 set_efer(vcpu, data);
1010 break;
8f1589d9
AP		 1011 case MSR_K7_HWCR:
1012 data &= ~(u64)0x40; /* ignore flush filter disable */
1013 if (data != 0) {
1014 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1015 data);
1016 return 1;
1017 }
15c4a640 1018 break;
f7c6d140
AP		 1019 case MSR_FAM10H_MMIO_CONF_BASE:
1020 if (data != 0) {
1021 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1022 "0x%llx\n", data);
1023 return 1;
1024 }
15c4a640 1025 break;
c323c0e5 1026 case MSR_AMD64_NB_CFG:
c7ac679c 1027 break;
b5e2fec0
AG		 1028 case MSR_IA32_DEBUGCTLMSR:
1029 if (!data) {
1030 /* We support the non-activated case already */
1031 break;
1032 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1033 /* Values other than LBR and BTF are vendor-specific,
1034 thus reserved and should throw a #GP */
1035 return 1;
1036 }
1037 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1038 __func__, data);
1039 break;
15c4a640
CO		 1040 case MSR_IA32_UCODE_REV:
1041 case MSR_IA32_UCODE_WRITE:
61a6bd67 1042 case MSR_VM_HSAVE_PA:
6098ca93 1043 case MSR_AMD64_PATCH_LOADER:
15c4a640 1044 break;
9ba075a6
AK		 1045 case 0x200 ... 0x2ff:
1046 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1047 case MSR_IA32_APICBASE:
1048 kvm_set_apic_base(vcpu, data);
1049 break;
0105d1a5
GN		 1050 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1051 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1052 case MSR_IA32_MISC_ENABLE:
ad312c7c 1053 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1054 break;
18068523
GOC		 1055 case MSR_KVM_WALL_CLOCK:
1056 vcpu->kvm->arch.wall_clock = data;
1057 kvm_write_wall_clock(vcpu->kvm, data);
1058 break;
1059 case MSR_KVM_SYSTEM_TIME: {
1060 if (vcpu->arch.time_page) {
1061 kvm_release_page_dirty(vcpu->arch.time_page);
1062 vcpu->arch.time_page = NULL;
1063 }
1064
1065 vcpu->arch.time = data;
1066
1067 /* we verify if the enable bit is set... */
1068 if (!(data & 1))
1069 break;
1070
1071 /* ...but clean it before doing the actual write */
1072 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1073
18068523
GOC		 1074 vcpu->arch.time_page =
1075 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1076
1077 if (is_error_page(vcpu->arch.time_page)) {
1078 kvm_release_page_clean(vcpu->arch.time_page);
1079 vcpu->arch.time_page = NULL;
1080 }
1081
c8076604 1082 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1083 break;
1084 }
890ca9ae
HY		 1085 case MSR_IA32_MCG_CTL:
1086 case MSR_IA32_MCG_STATUS:
1087 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1088 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1089
1090 /* Performance counters are not protected by a CPUID bit,
1091 * so we should check all of them in the generic path for the sake of
1092 * cross vendor migration.
1093 * Writing a zero into the event select MSRs disables them,
1094 * which we perfectly emulate ;-). Any other value should be at least
1095 * reported, some guests depend on them.
1096 */
1097 case MSR_P6_EVNTSEL0:
1098 case MSR_P6_EVNTSEL1:
1099 case MSR_K7_EVNTSEL0:
1100 case MSR_K7_EVNTSEL1:
1101 case MSR_K7_EVNTSEL2:
1102 case MSR_K7_EVNTSEL3:
1103 if (data != 0)
1104 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1105 "0x%x data 0x%llx\n", msr, data);
1106 break;
1107 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1108 * so we ignore writes to make it happy.
1109 */
1110 case MSR_P6_PERFCTR0:
1111 case MSR_P6_PERFCTR1:
1112 case MSR_K7_PERFCTR0:
1113 case MSR_K7_PERFCTR1:
1114 case MSR_K7_PERFCTR2:
1115 case MSR_K7_PERFCTR3:
1116 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1117 "0x%x data 0x%llx\n", msr, data);
1118 break;
15c4a640 1119 default:
ffde22ac
ES		 1120 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1121 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1122 if (!ignore_msrs) {
1123 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1124 msr, data);
1125 return 1;
1126 } else {
1127 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1128 msr, data);
1129 break;
1130 }
15c4a640
CO		 1131 }
1132 return 0;
1133}
1134EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1135
1136
1137/*
1138 * Reads an msr value (of 'msr_index') into 'pdata'.
1139 * Returns 0 on success, non-0 otherwise.
1140 * Assumes vcpu_load() was already called.
1141 */
1142int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1143{
1144 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1145}
1146
9ba075a6
AK		 1147static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1148{
0bed3b56
SY		 1149 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1150
9ba075a6
AK		 1151 if (!msr_mtrr_valid(msr))
1152 return 1;
1153
0bed3b56
SY		 1154 if (msr == MSR_MTRRdefType)
1155 *pdata = vcpu->arch.mtrr_state.def_type +
1156 (vcpu->arch.mtrr_state.enabled << 10);
1157 else if (msr == MSR_MTRRfix64K_00000)
1158 *pdata = p[0];
1159 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1160 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1161 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1162 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1163 else if (msr == MSR_IA32_CR_PAT)
1164 *pdata = vcpu->arch.pat;
1165 else { /* Variable MTRRs */
1166 int idx, is_mtrr_mask;
1167 u64 *pt;
1168
1169 idx = (msr - 0x200) / 2;
1170 is_mtrr_mask = msr - 0x200 - 2 * idx;
1171 if (!is_mtrr_mask)
1172 pt =
1173 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1174 else
1175 pt =
1176 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1177 *pdata = *pt;
1178 }
1179
9ba075a6
AK		 1180 return 0;
1181}
1182
890ca9ae 1183static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1184{
1185 u64 data;
890ca9ae
HY		 1186 u64 mcg_cap = vcpu->arch.mcg_cap;
1187 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1188
1189 switch (msr) {
15c4a640
CO		 1190 case MSR_IA32_P5_MC_ADDR:
1191 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1192 data = 0;
1193 break;
15c4a640 1194 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1195 data = vcpu->arch.mcg_cap;
1196 break;
c7ac679c 1197 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1198 if (!(mcg_cap & MCG_CTL_P))
1199 return 1;
1200 data = vcpu->arch.mcg_ctl;
1201 break;
1202 case MSR_IA32_MCG_STATUS:
1203 data = vcpu->arch.mcg_status;
1204 break;
1205 default:
1206 if (msr >= MSR_IA32_MC0_CTL &&
1207 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1208 u32 offset = msr - MSR_IA32_MC0_CTL;
1209 data = vcpu->arch.mce_banks[offset];
1210 break;
1211 }
1212 return 1;
1213 }
1214 *pdata = data;
1215 return 0;
1216}
1217
1218int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1219{
1220 u64 data;
1221
1222 switch (msr) {
890ca9ae 1223 case MSR_IA32_PLATFORM_ID:
15c4a640 1224 case MSR_IA32_UCODE_REV:
15c4a640 1225 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1226 case MSR_IA32_DEBUGCTLMSR:
1227 case MSR_IA32_LASTBRANCHFROMIP:
1228 case MSR_IA32_LASTBRANCHTOIP:
1229 case MSR_IA32_LASTINTFROMIP:
1230 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1231 case MSR_K8_SYSCFG:
1232 case MSR_K7_HWCR:
61a6bd67 1233 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1234 case MSR_P6_PERFCTR0:
1235 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1236 case MSR_P6_EVNTSEL0:
1237 case MSR_P6_EVNTSEL1:
9e699624 1238 case MSR_K7_EVNTSEL0:
1f3ee616 1239 case MSR_K7_PERFCTR0:
1fdbd48c 1240 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1241 case MSR_AMD64_NB_CFG:
f7c6d140 1242 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1243 data = 0;
1244 break;
9ba075a6
AK		 1245 case MSR_MTRRcap:
1246 data = 0x500 | KVM_NR_VAR_MTRR;
1247 break;
1248 case 0x200 ... 0x2ff:
1249 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1250 case 0xcd: /* fsb frequency */
1251 data = 3;
1252 break;
1253 case MSR_IA32_APICBASE:
1254 data = kvm_get_apic_base(vcpu);
1255 break;
0105d1a5
GN		 1256 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1257 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1258 break;
15c4a640 1259 case MSR_IA32_MISC_ENABLE:
ad312c7c 1260 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1261 break;
847f0ad8
AG		 1262 case MSR_IA32_PERF_STATUS:
1263 /* TSC increment by tick */
1264 data = 1000ULL;
1265 /* CPU multiplier */
1266 data |= (((uint64_t)4ULL) << 40);
1267 break;
15c4a640 1268 case MSR_EFER:
ad312c7c 1269 data = vcpu->arch.shadow_efer;
15c4a640 1270 break;
18068523
GOC		 1271 case MSR_KVM_WALL_CLOCK:
1272 data = vcpu->kvm->arch.wall_clock;
1273 break;
1274 case MSR_KVM_SYSTEM_TIME:
1275 data = vcpu->arch.time;
1276 break;
890ca9ae
HY		 1277 case MSR_IA32_P5_MC_ADDR:
1278 case MSR_IA32_P5_MC_TYPE:
1279 case MSR_IA32_MCG_CAP:
1280 case MSR_IA32_MCG_CTL:
1281 case MSR_IA32_MCG_STATUS:
1282 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1283 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1284 default:
ed85c068
AP		 1285 if (!ignore_msrs) {
1286 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1287 return 1;
1288 } else {
1289 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1290 data = 0;
1291 }
1292 break;
15c4a640
CO		 1293 }
1294 *pdata = data;
1295 return 0;
1296}
1297EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1298
313a3dc7
CO		 1299/*
1300 * Read or write a bunch of msrs. All parameters are kernel addresses.
1301 *
1302 * @return number of msrs set successfully.
1303 */
1304static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1305 struct kvm_msr_entry *entries,
1306 int (*do_msr)(struct kvm_vcpu *vcpu,
1307 unsigned index, u64 *data))
1308{
f656ce01 1309 int i, idx;
313a3dc7
CO		 1310
1311 vcpu_load(vcpu);
1312
f656ce01 1313 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1314 for (i = 0; i < msrs->nmsrs; ++i)
1315 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1316 break;
f656ce01 1317 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1318
1319 vcpu_put(vcpu);
1320
1321 return i;
1322}
1323
1324/*
1325 * Read or write a bunch of msrs. Parameters are user addresses.
1326 *
1327 * @return number of msrs set successfully.
1328 */
1329static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1330 int (*do_msr)(struct kvm_vcpu *vcpu,
1331 unsigned index, u64 *data),
1332 int writeback)
1333{
1334 struct kvm_msrs msrs;
1335 struct kvm_msr_entry *entries;
1336 int r, n;
1337 unsigned size;
1338
1339 r = -EFAULT;
1340 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1341 goto out;
1342
1343 r = -E2BIG;
1344 if (msrs.nmsrs >= MAX_IO_MSRS)
1345 goto out;
1346
1347 r = -ENOMEM;
1348 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1349 entries = vmalloc(size);
1350 if (!entries)
1351 goto out;
1352
1353 r = -EFAULT;
1354 if (copy_from_user(entries, user_msrs->entries, size))
1355 goto out_free;
1356
1357 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1358 if (r < 0)
1359 goto out_free;
1360
1361 r = -EFAULT;
1362 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1363 goto out_free;
1364
1365 r = n;
1366
1367out_free:
1368 vfree(entries);
1369out:
1370 return r;
1371}
1372
018d00d2
ZX		 1373int kvm_dev_ioctl_check_extension(long ext)
1374{
1375 int r;
1376
1377 switch (ext) {
1378 case KVM_CAP_IRQCHIP:
1379 case KVM_CAP_HLT:
1380 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1381 case KVM_CAP_SET_TSS_ADDR:
07716717 1382 case KVM_CAP_EXT_CPUID:
c8076604 1383 case KVM_CAP_CLOCKSOURCE:
7837699f 1384 case KVM_CAP_PIT:
a28e4f5a 1385 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1386 case KVM_CAP_MP_STATE:
ed848624 1387 case KVM_CAP_SYNC_MMU:
52d939a0 1388 case KVM_CAP_REINJECT_CONTROL:
4925663a 1389 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1390 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1391 case KVM_CAP_IRQFD:
d34e6b17 1392 case KVM_CAP_IOEVENTFD:
c5ff41ce 1393 case KVM_CAP_PIT2:
e9f42757 1394 case KVM_CAP_PIT_STATE2:
b927a3ce 1395 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1396 case KVM_CAP_XEN_HVM:
afbcf7ab 1397 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1398 case KVM_CAP_VCPU_EVENTS:
018d00d2
ZX		 1399 r = 1;
1400 break;
542472b5
LV		 1401 case KVM_CAP_COALESCED_MMIO:
1402 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1403 break;
774ead3a
AK		 1404 case KVM_CAP_VAPIC:
1405 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1406 break;
f725230a
AK		 1407 case KVM_CAP_NR_VCPUS:
1408 r = KVM_MAX_VCPUS;
1409 break;
a988b910
AK		 1410 case KVM_CAP_NR_MEMSLOTS:
1411 r = KVM_MEMORY_SLOTS;
1412 break;
a68a6a72
MT		 1413 case KVM_CAP_PV_MMU: /* obsolete */
1414 r = 0;
2f333bcb 1415 break;
62c476c7 1416 case KVM_CAP_IOMMU:
19de40a8 1417 r = iommu_found();
62c476c7 1418 break;
890ca9ae
HY		 1419 case KVM_CAP_MCE:
1420 r = KVM_MAX_MCE_BANKS;
1421 break;
018d00d2
ZX		 1422 default:
1423 r = 0;
1424 break;
1425 }
1426 return r;
1427
1428}
1429
043405e1
CO		 1430long kvm_arch_dev_ioctl(struct file *filp,
1431 unsigned int ioctl, unsigned long arg)
1432{
1433 void __user *argp = (void __user *)arg;
1434 long r;
1435
1436 switch (ioctl) {
1437 case KVM_GET_MSR_INDEX_LIST: {
1438 struct kvm_msr_list __user *user_msr_list = argp;
1439 struct kvm_msr_list msr_list;
1440 unsigned n;
1441
1442 r = -EFAULT;
1443 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1444 goto out;
1445 n = msr_list.nmsrs;
1446 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1447 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1448 goto out;
1449 r = -E2BIG;
e125e7b6 1450 if (n < msr_list.nmsrs)
043405e1
CO		 1451 goto out;
1452 r = -EFAULT;
1453 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1454 num_msrs_to_save * sizeof(u32)))
1455 goto out;
e125e7b6 1456 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1457 &emulated_msrs,
1458 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1459 goto out;
1460 r = 0;
1461 break;
1462 }
674eea0f
AK		 1463 case KVM_GET_SUPPORTED_CPUID: {
1464 struct kvm_cpuid2 __user *cpuid_arg = argp;
1465 struct kvm_cpuid2 cpuid;
1466
1467 r = -EFAULT;
1468 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1469 goto out;
1470 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1471 cpuid_arg->entries);
674eea0f
AK		 1472 if (r)
1473 goto out;
1474
1475 r = -EFAULT;
1476 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1477 goto out;
1478 r = 0;
1479 break;
1480 }
890ca9ae
HY		 1481 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1482 u64 mce_cap;
1483
1484 mce_cap = KVM_MCE_CAP_SUPPORTED;
1485 r = -EFAULT;
1486 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1487 goto out;
1488 r = 0;
1489 break;
1490 }
043405e1
CO		 1491 default:
1492 r = -EINVAL;
1493 }
1494out:
1495 return r;
1496}
1497
313a3dc7
CO		 1498void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1499{
1500 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1501 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1502 unsigned long khz = cpufreq_quick_get(cpu);
1503 if (!khz)
1504 khz = tsc_khz;
1505 per_cpu(cpu_tsc_khz, cpu) = khz;
1506 }
c8076604 1507 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1508}
1509
1510void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1511{
1512 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1513 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1514}
1515
07716717 1516static int is_efer_nx(void)
313a3dc7 1517{
e286e86e 1518 unsigned long long efer = 0;
313a3dc7 1519
e286e86e 1520 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1521 return efer & EFER_NX;
1522}
1523
1524static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1525{
1526 int i;
1527 struct kvm_cpuid_entry2 *e, *entry;
1528
313a3dc7 1529 entry = NULL;
ad312c7c
ZX		 1530 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1531 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1532 if (e->function == 0x80000001) {
1533 entry = e;
1534 break;
1535 }
1536 }
07716717 1537 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1538 entry->edx &= ~(1 << 20);
1539 printk(KERN_INFO "kvm: guest NX capability removed\n");
1540 }
1541}
1542
07716717 1543/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1544static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1545 struct kvm_cpuid *cpuid,
1546 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1547{
1548 int r, i;
1549 struct kvm_cpuid_entry *cpuid_entries;
1550
1551 r = -E2BIG;
1552 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1553 goto out;
1554 r = -ENOMEM;
1555 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1556 if (!cpuid_entries)
1557 goto out;
1558 r = -EFAULT;
1559 if (copy_from_user(cpuid_entries, entries,
1560 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1561 goto out_free;
1562 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1563 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1564 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1565 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1566 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1567 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1568 vcpu->arch.cpuid_entries[i].index = 0;
1569 vcpu->arch.cpuid_entries[i].flags = 0;
1570 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1571 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1572 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1573 }
1574 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1575 cpuid_fix_nx_cap(vcpu);
1576 r = 0;
fc61b800 1577 kvm_apic_set_version(vcpu);
0e851880 1578 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1579
1580out_free:
1581 vfree(cpuid_entries);
1582out:
1583 return r;
1584}
1585
1586static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1587 struct kvm_cpuid2 *cpuid,
1588 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1589{
1590 int r;
1591
1592 r = -E2BIG;
1593 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1594 goto out;
1595 r = -EFAULT;
ad312c7c 1596 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1597 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1598 goto out;
ad312c7c 1599 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1600 kvm_apic_set_version(vcpu);
0e851880 1601 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1602 return 0;
1603
1604out:
1605 return r;
1606}
1607
07716717 1608static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1609 struct kvm_cpuid2 *cpuid,
1610 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1611{
1612 int r;
1613
1614 r = -E2BIG;
ad312c7c 1615 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1616 goto out;
1617 r = -EFAULT;
ad312c7c 1618 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1619 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1620 goto out;
1621 return 0;
1622
1623out:
ad312c7c 1624 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1625 return r;
1626}
1627
07716717 1628static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1629 u32 index)
07716717
DK		 1630{
1631 entry->function = function;
1632 entry->index = index;
1633 cpuid_count(entry->function, entry->index,
19355475 1634 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1635 entry->flags = 0;
1636}
1637
7faa4ee1
AK		 1638#define F(x) bit(X86_FEATURE_##x)
1639
07716717
DK		 1640static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1641 u32 index, int *nent, int maxnent)
1642{
7faa4ee1 1643 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1644#ifdef CONFIG_X86_64
17cc3935
SY		 1645 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1646 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1647 unsigned f_lm = F(LM);
1648#else
17cc3935 1649 unsigned f_gbpages = 0;
7faa4ee1 1650 unsigned f_lm = 0;
07716717 1651#endif
4e47c7a6 1652 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1653
1654 /* cpuid 1.edx */
1655 const u32 kvm_supported_word0_x86_features =
1656 F(FPU) | F(VME) | F(DE) | F(PSE) |
1657 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1658 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1659 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1660 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1661 0 /* Reserved, DS, ACPI */ | F(MMX) |
1662 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1663 0 /* HTT, TM, Reserved, PBE */;
1664 /* cpuid 0x80000001.edx */
1665 const u32 kvm_supported_word1_x86_features =
1666 F(FPU) | F(VME) | F(DE) | F(PSE) |
1667 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1668 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1669 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1670 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1671 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1672 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1673 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1674 /* cpuid 1.ecx */
1675 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1676 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1677 0 /* DS-CPL, VMX, SMX, EST */ |
1678 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1679 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1680 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1681 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1682 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1683 /* cpuid 0x80000001.ecx */
07716717 1684 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1685 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1686 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1687 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1688 0 /* SKINIT */ | 0 /* WDT */;
07716717 1689
19355475 1690 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1691 get_cpu();
1692 do_cpuid_1_ent(entry, function, index);
1693 ++*nent;
1694
1695 switch (function) {
1696 case 0:
1697 entry->eax = min(entry->eax, (u32)0xb);
1698 break;
1699 case 1:
1700 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1701 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1702 /* we support x2apic emulation even if host does not support
1703 * it since we emulate x2apic in software */
1704 entry->ecx |= F(X2APIC);
07716717
DK		 1705 break;
1706 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1707 * may return different values. This forces us to get_cpu() before
1708 * issuing the first command, and also to emulate this annoying behavior
1709 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1710 case 2: {
1711 int t, times = entry->eax & 0xff;
1712
1713 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1714 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1715 for (t = 1; t < times && *nent < maxnent; ++t) {
1716 do_cpuid_1_ent(&entry[t], function, 0);
1717 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1718 ++*nent;
1719 }
1720 break;
1721 }
1722 /* function 4 and 0xb have additional index. */
1723 case 4: {
14af3f3c 1724 int i, cache_type;
07716717
DK		 1725
1726 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1727 /* read more entries until cache_type is zero */
14af3f3c
HH		 1728 for (i = 1; *nent < maxnent; ++i) {
1729 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1730 if (!cache_type)
1731 break;
14af3f3c
HH		 1732 do_cpuid_1_ent(&entry[i], function, i);
1733 entry[i].flags |=
07716717
DK		 1734 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1735 ++*nent;
1736 }
1737 break;
1738 }
1739 case 0xb: {
14af3f3c 1740 int i, level_type;
07716717
DK		 1741
1742 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1743 /* read more entries until level_type is zero */
14af3f3c 1744 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1745 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1746 if (!level_type)
1747 break;
14af3f3c
HH		 1748 do_cpuid_1_ent(&entry[i], function, i);
1749 entry[i].flags |=
07716717
DK		 1750 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1751 ++*nent;
1752 }
1753 break;
1754 }
1755 case 0x80000000:
1756 entry->eax = min(entry->eax, 0x8000001a);
1757 break;
1758 case 0x80000001:
1759 entry->edx &= kvm_supported_word1_x86_features;
1760 entry->ecx &= kvm_supported_word6_x86_features;
1761 break;
1762 }
1763 put_cpu();
1764}
1765
7faa4ee1
AK		 1766#undef F
1767
674eea0f 1768static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1769 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1770{
1771 struct kvm_cpuid_entry2 *cpuid_entries;
1772 int limit, nent = 0, r = -E2BIG;
1773 u32 func;
1774
1775 if (cpuid->nent < 1)
1776 goto out;
6a544355
AK		 1777 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1778 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1779 r = -ENOMEM;
1780 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1781 if (!cpuid_entries)
1782 goto out;
1783
1784 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1785 limit = cpuid_entries[0].eax;
1786 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1787 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1788 &nent, cpuid->nent);
07716717
DK		 1789 r = -E2BIG;
1790 if (nent >= cpuid->nent)
1791 goto out_free;
1792
1793 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1794 limit = cpuid_entries[nent - 1].eax;
1795 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1796 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1797 &nent, cpuid->nent);
cb007648
MM		 1798 r = -E2BIG;
1799 if (nent >= cpuid->nent)
1800 goto out_free;
1801
07716717
DK		 1802 r = -EFAULT;
1803 if (copy_to_user(entries, cpuid_entries,
19355475 1804 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1805 goto out_free;
1806 cpuid->nent = nent;
1807 r = 0;
1808
1809out_free:
1810 vfree(cpuid_entries);
1811out:
1812 return r;
1813}
1814
313a3dc7
CO		 1815static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1816 struct kvm_lapic_state *s)
1817{
1818 vcpu_load(vcpu);
ad312c7c 1819 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1820 vcpu_put(vcpu);
1821
1822 return 0;
1823}
1824
1825static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1826 struct kvm_lapic_state *s)
1827{
1828 vcpu_load(vcpu);
ad312c7c 1829 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1830 kvm_apic_post_state_restore(vcpu);
cb142eb7 1831 update_cr8_intercept(vcpu);
313a3dc7
CO		 1832 vcpu_put(vcpu);
1833
1834 return 0;
1835}
1836
f77bc6a4
ZX		 1837static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1838 struct kvm_interrupt *irq)
1839{
1840 if (irq->irq < 0 || irq->irq >= 256)
1841 return -EINVAL;
1842 if (irqchip_in_kernel(vcpu->kvm))
1843 return -ENXIO;
1844 vcpu_load(vcpu);
1845
66fd3f7f 1846 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1847
1848 vcpu_put(vcpu);
1849
1850 return 0;
1851}
1852
c4abb7c9
JK		 1853static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1854{
1855 vcpu_load(vcpu);
1856 kvm_inject_nmi(vcpu);
1857 vcpu_put(vcpu);
1858
1859 return 0;
1860}
1861
b209749f
AK		 1862static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1863 struct kvm_tpr_access_ctl *tac)
1864{
1865 if (tac->flags)
1866 return -EINVAL;
1867 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1868 return 0;
1869}
1870
890ca9ae
HY		 1871static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1872 u64 mcg_cap)
1873{
1874 int r;
1875 unsigned bank_num = mcg_cap & 0xff, bank;
1876
1877 r = -EINVAL;
a9e38c3e 1878 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 1879 goto out;
1880 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1881 goto out;
1882 r = 0;
1883 vcpu->arch.mcg_cap = mcg_cap;
1884 /* Init IA32_MCG_CTL to all 1s */
1885 if (mcg_cap & MCG_CTL_P)
1886 vcpu->arch.mcg_ctl = ~(u64)0;
1887 /* Init IA32_MCi_CTL to all 1s */
1888 for (bank = 0; bank < bank_num; bank++)
1889 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1890out:
1891 return r;
1892}
1893
1894static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1895 struct kvm_x86_mce *mce)
1896{
1897 u64 mcg_cap = vcpu->arch.mcg_cap;
1898 unsigned bank_num = mcg_cap & 0xff;
1899 u64 *banks = vcpu->arch.mce_banks;
1900
1901 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1902 return -EINVAL;
1903 /*
1904 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1905 * reporting is disabled
1906 */
1907 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1908 vcpu->arch.mcg_ctl != ~(u64)0)
1909 return 0;
1910 banks += 4 * mce->bank;
1911 /*
1912 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1913 * reporting is disabled for the bank
1914 */
1915 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1916 return 0;
1917 if (mce->status & MCI_STATUS_UC) {
1918 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 1919 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 1920 printk(KERN_DEBUG "kvm: set_mce: "
1921 "injects mce exception while "
1922 "previous one is in progress!\n");
1923 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1924 return 0;
1925 }
1926 if (banks[1] & MCI_STATUS_VAL)
1927 mce->status |= MCI_STATUS_OVER;
1928 banks[2] = mce->addr;
1929 banks[3] = mce->misc;
1930 vcpu->arch.mcg_status = mce->mcg_status;
1931 banks[1] = mce->status;
1932 kvm_queue_exception(vcpu, MC_VECTOR);
1933 } else if (!(banks[1] & MCI_STATUS_VAL)
1934 || !(banks[1] & MCI_STATUS_UC)) {
1935 if (banks[1] & MCI_STATUS_VAL)
1936 mce->status |= MCI_STATUS_OVER;
1937 banks[2] = mce->addr;
1938 banks[3] = mce->misc;
1939 banks[1] = mce->status;
1940 } else
1941 banks[1] |= MCI_STATUS_OVER;
1942 return 0;
1943}
1944
3cfc3092
JK		 1945static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
1946 struct kvm_vcpu_events *events)
1947{
1948 vcpu_load(vcpu);
1949
1950 events->exception.injected = vcpu->arch.exception.pending;
1951 events->exception.nr = vcpu->arch.exception.nr;
1952 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
1953 events->exception.error_code = vcpu->arch.exception.error_code;
1954
1955 events->interrupt.injected = vcpu->arch.interrupt.pending;
1956 events->interrupt.nr = vcpu->arch.interrupt.nr;
1957 events->interrupt.soft = vcpu->arch.interrupt.soft;
1958
1959 events->nmi.injected = vcpu->arch.nmi_injected;
1960 events->nmi.pending = vcpu->arch.nmi_pending;
1961 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
1962
1963 events->sipi_vector = vcpu->arch.sipi_vector;
1964
dab4b911
JK		 1965 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
1966 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 1967
1968 vcpu_put(vcpu);
1969}
1970
1971static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
1972 struct kvm_vcpu_events *events)
1973{
dab4b911
JK		 1974 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
1975 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 1976 return -EINVAL;
1977
1978 vcpu_load(vcpu);
1979
1980 vcpu->arch.exception.pending = events->exception.injected;
1981 vcpu->arch.exception.nr = events->exception.nr;
1982 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
1983 vcpu->arch.exception.error_code = events->exception.error_code;
1984
1985 vcpu->arch.interrupt.pending = events->interrupt.injected;
1986 vcpu->arch.interrupt.nr = events->interrupt.nr;
1987 vcpu->arch.interrupt.soft = events->interrupt.soft;
1988 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
1989 kvm_pic_clear_isr_ack(vcpu->kvm);
1990
1991 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 1992 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
1993 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 1994 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
1995
dab4b911
JK		 1996 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
1997 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 1998
1999 vcpu_put(vcpu);
2000
2001 return 0;
2002}
2003
313a3dc7
CO		 2004long kvm_arch_vcpu_ioctl(struct file *filp,
2005 unsigned int ioctl, unsigned long arg)
2006{
2007 struct kvm_vcpu *vcpu = filp->private_data;
2008 void __user *argp = (void __user *)arg;
2009 int r;
b772ff36 2010 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2011
2012 switch (ioctl) {
2013 case KVM_GET_LAPIC: {
2204ae3c
MT		 2014 r = -EINVAL;
2015 if (!vcpu->arch.apic)
2016 goto out;
b772ff36 2017 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2018
b772ff36
DH		 2019 r = -ENOMEM;
2020 if (!lapic)
2021 goto out;
2022 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2023 if (r)
2024 goto out;
2025 r = -EFAULT;
b772ff36 2026 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2027 goto out;
2028 r = 0;
2029 break;
2030 }
2031 case KVM_SET_LAPIC: {
2204ae3c
MT		 2032 r = -EINVAL;
2033 if (!vcpu->arch.apic)
2034 goto out;
b772ff36
DH		 2035 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2036 r = -ENOMEM;
2037 if (!lapic)
2038 goto out;
313a3dc7 2039 r = -EFAULT;
b772ff36 2040 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2041 goto out;
b772ff36 2042 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2043 if (r)
2044 goto out;
2045 r = 0;
2046 break;
2047 }
f77bc6a4
ZX		 2048 case KVM_INTERRUPT: {
2049 struct kvm_interrupt irq;
2050
2051 r = -EFAULT;
2052 if (copy_from_user(&irq, argp, sizeof irq))
2053 goto out;
2054 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2055 if (r)
2056 goto out;
2057 r = 0;
2058 break;
2059 }
c4abb7c9
JK		 2060 case KVM_NMI: {
2061 r = kvm_vcpu_ioctl_nmi(vcpu);
2062 if (r)
2063 goto out;
2064 r = 0;
2065 break;
2066 }
313a3dc7
CO		 2067 case KVM_SET_CPUID: {
2068 struct kvm_cpuid __user *cpuid_arg = argp;
2069 struct kvm_cpuid cpuid;
2070
2071 r = -EFAULT;
2072 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2073 goto out;
2074 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2075 if (r)
2076 goto out;
2077 break;
2078 }
07716717
DK		 2079 case KVM_SET_CPUID2: {
2080 struct kvm_cpuid2 __user *cpuid_arg = argp;
2081 struct kvm_cpuid2 cpuid;
2082
2083 r = -EFAULT;
2084 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2085 goto out;
2086 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2087 cpuid_arg->entries);
07716717
DK		 2088 if (r)
2089 goto out;
2090 break;
2091 }
2092 case KVM_GET_CPUID2: {
2093 struct kvm_cpuid2 __user *cpuid_arg = argp;
2094 struct kvm_cpuid2 cpuid;
2095
2096 r = -EFAULT;
2097 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2098 goto out;
2099 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2100 cpuid_arg->entries);
07716717
DK		 2101 if (r)
2102 goto out;
2103 r = -EFAULT;
2104 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2105 goto out;
2106 r = 0;
2107 break;
2108 }
313a3dc7
CO		 2109 case KVM_GET_MSRS:
2110 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2111 break;
2112 case KVM_SET_MSRS:
2113 r = msr_io(vcpu, argp, do_set_msr, 0);
2114 break;
b209749f
AK		 2115 case KVM_TPR_ACCESS_REPORTING: {
2116 struct kvm_tpr_access_ctl tac;
2117
2118 r = -EFAULT;
2119 if (copy_from_user(&tac, argp, sizeof tac))
2120 goto out;
2121 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2122 if (r)
2123 goto out;
2124 r = -EFAULT;
2125 if (copy_to_user(argp, &tac, sizeof tac))
2126 goto out;
2127 r = 0;
2128 break;
2129 };
b93463aa
AK		 2130 case KVM_SET_VAPIC_ADDR: {
2131 struct kvm_vapic_addr va;
2132
2133 r = -EINVAL;
2134 if (!irqchip_in_kernel(vcpu->kvm))
2135 goto out;
2136 r = -EFAULT;
2137 if (copy_from_user(&va, argp, sizeof va))
2138 goto out;
2139 r = 0;
2140 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2141 break;
2142 }
890ca9ae
HY		 2143 case KVM_X86_SETUP_MCE: {
2144 u64 mcg_cap;
2145
2146 r = -EFAULT;
2147 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2148 goto out;
2149 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2150 break;
2151 }
2152 case KVM_X86_SET_MCE: {
2153 struct kvm_x86_mce mce;
2154
2155 r = -EFAULT;
2156 if (copy_from_user(&mce, argp, sizeof mce))
2157 goto out;
2158 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2159 break;
2160 }
3cfc3092
JK		 2161 case KVM_GET_VCPU_EVENTS: {
2162 struct kvm_vcpu_events events;
2163
2164 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2165
2166 r = -EFAULT;
2167 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2168 break;
2169 r = 0;
2170 break;
2171 }
2172 case KVM_SET_VCPU_EVENTS: {
2173 struct kvm_vcpu_events events;
2174
2175 r = -EFAULT;
2176 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2177 break;
2178
2179 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2180 break;
2181 }
313a3dc7
CO		 2182 default:
2183 r = -EINVAL;
2184 }
2185out:
7a6ce84c 2186 kfree(lapic);
313a3dc7
CO		 2187 return r;
2188}
2189
1fe779f8
CO		 2190static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2191{
2192 int ret;
2193
2194 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2195 return -1;
2196 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2197 return ret;
2198}
2199
b927a3ce
SY		 2200static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2201 u64 ident_addr)
2202{
2203 kvm->arch.ept_identity_map_addr = ident_addr;
2204 return 0;
2205}
2206
1fe779f8
CO		 2207static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2208 u32 kvm_nr_mmu_pages)
2209{
2210 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2211 return -EINVAL;
2212
79fac95e 2213 mutex_lock(&kvm->slots_lock);
7c8a83b7 2214 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2215
2216 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2217 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2218
7c8a83b7 2219 spin_unlock(&kvm->mmu_lock);
79fac95e 2220 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2221 return 0;
2222}
2223
2224static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2225{
f05e70ac 2226 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2227}
2228
a983fb23
MT		 2229gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2230{
2231 int i;
2232 struct kvm_mem_alias *alias;
2233 struct kvm_mem_aliases *aliases;
2234
2235 aliases = rcu_dereference(kvm->arch.aliases);
2236
2237 for (i = 0; i < aliases->naliases; ++i) {
2238 alias = &aliases->aliases[i];
2239 if (alias->flags & KVM_ALIAS_INVALID)
2240 continue;
2241 if (gfn >= alias->base_gfn
2242 && gfn < alias->base_gfn + alias->npages)
2243 return alias->target_gfn + gfn - alias->base_gfn;
2244 }
2245 return gfn;
2246}
2247
e9f85cde
ZX		 2248gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2249{
2250 int i;
2251 struct kvm_mem_alias *alias;
a983fb23
MT		 2252 struct kvm_mem_aliases *aliases;
2253
2254 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2255
fef9cce0
MT		 2256 for (i = 0; i < aliases->naliases; ++i) {
2257 alias = &aliases->aliases[i];
e9f85cde
ZX		 2258 if (gfn >= alias->base_gfn
2259 && gfn < alias->base_gfn + alias->npages)
2260 return alias->target_gfn + gfn - alias->base_gfn;
2261 }
2262 return gfn;
2263}
2264
1fe779f8
CO		 2265/*
2266 * Set a new alias region. Aliases map a portion of physical memory into
2267 * another portion. This is useful for memory windows, for example the PC
2268 * VGA region.
2269 */
2270static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2271 struct kvm_memory_alias *alias)
2272{
2273 int r, n;
2274 struct kvm_mem_alias *p;
a983fb23 2275 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2276
2277 r = -EINVAL;
2278 /* General sanity checks */
2279 if (alias->memory_size & (PAGE_SIZE - 1))
2280 goto out;
2281 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2282 goto out;
2283 if (alias->slot >= KVM_ALIAS_SLOTS)
2284 goto out;
2285 if (alias->guest_phys_addr + alias->memory_size
2286 < alias->guest_phys_addr)
2287 goto out;
2288 if (alias->target_phys_addr + alias->memory_size
2289 < alias->target_phys_addr)
2290 goto out;
2291
a983fb23
MT		 2292 r = -ENOMEM;
2293 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2294 if (!aliases)
2295 goto out;
2296
79fac95e 2297 mutex_lock(&kvm->slots_lock);
1fe779f8 2298
a983fb23
MT		 2299 /* invalidate any gfn reference in case of deletion/shrinking */
2300 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2301 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2302 old_aliases = kvm->arch.aliases;
2303 rcu_assign_pointer(kvm->arch.aliases, aliases);
2304 synchronize_srcu_expedited(&kvm->srcu);
2305 kvm_mmu_zap_all(kvm);
2306 kfree(old_aliases);
2307
2308 r = -ENOMEM;
2309 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2310 if (!aliases)
2311 goto out_unlock;
2312
2313 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2314
2315 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2316 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2317 p->npages = alias->memory_size >> PAGE_SHIFT;
2318 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2319 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2320
2321 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2322 if (aliases->aliases[n - 1].npages)
1fe779f8 2323 break;
fef9cce0 2324 aliases->naliases = n;
1fe779f8 2325
a983fb23
MT		 2326 old_aliases = kvm->arch.aliases;
2327 rcu_assign_pointer(kvm->arch.aliases, aliases);
2328 synchronize_srcu_expedited(&kvm->srcu);
2329 kfree(old_aliases);
2330 r = 0;
1fe779f8 2331
a983fb23 2332out_unlock:
79fac95e 2333 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2334out:
2335 return r;
2336}
2337
2338static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2339{
2340 int r;
2341
2342 r = 0;
2343 switch (chip->chip_id) {
2344 case KVM_IRQCHIP_PIC_MASTER:
2345 memcpy(&chip->chip.pic,
2346 &pic_irqchip(kvm)->pics[0],
2347 sizeof(struct kvm_pic_state));
2348 break;
2349 case KVM_IRQCHIP_PIC_SLAVE:
2350 memcpy(&chip->chip.pic,
2351 &pic_irqchip(kvm)->pics[1],
2352 sizeof(struct kvm_pic_state));
2353 break;
2354 case KVM_IRQCHIP_IOAPIC:
eba0226b 2355 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2356 break;
2357 default:
2358 r = -EINVAL;
2359 break;
2360 }
2361 return r;
2362}
2363
2364static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2365{
2366 int r;
2367
2368 r = 0;
2369 switch (chip->chip_id) {
2370 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2371 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2372 memcpy(&pic_irqchip(kvm)->pics[0],
2373 &chip->chip.pic,
2374 sizeof(struct kvm_pic_state));
894a9c55 2375 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2376 break;
2377 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2378 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2379 memcpy(&pic_irqchip(kvm)->pics[1],
2380 &chip->chip.pic,
2381 sizeof(struct kvm_pic_state));
894a9c55 2382 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2383 break;
2384 case KVM_IRQCHIP_IOAPIC:
eba0226b 2385 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2386 break;
2387 default:
2388 r = -EINVAL;
2389 break;
2390 }
2391 kvm_pic_update_irq(pic_irqchip(kvm));
2392 return r;
2393}
2394
e0f63cb9
SY		 2395static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2396{
2397 int r = 0;
2398
894a9c55 2399 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2400 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2401 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2402 return r;
2403}
2404
2405static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2406{
2407 int r = 0;
2408
894a9c55 2409 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2410 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2411 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2412 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2413 return r;
2414}
2415
2416static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2417{
2418 int r = 0;
2419
2420 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2421 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2422 sizeof(ps->channels));
2423 ps->flags = kvm->arch.vpit->pit_state.flags;
2424 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2425 return r;
2426}
2427
2428static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2429{
2430 int r = 0, start = 0;
2431 u32 prev_legacy, cur_legacy;
2432 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2433 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2434 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2435 if (!prev_legacy && cur_legacy)
2436 start = 1;
2437 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2438 sizeof(kvm->arch.vpit->pit_state.channels));
2439 kvm->arch.vpit->pit_state.flags = ps->flags;
2440 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2441 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2442 return r;
2443}
2444
52d939a0
MT		 2445static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2446 struct kvm_reinject_control *control)
2447{
2448 if (!kvm->arch.vpit)
2449 return -ENXIO;
894a9c55 2450 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2451 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2452 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2453 return 0;
2454}
2455
5bb064dc
ZX		 2456/*
2457 * Get (and clear) the dirty memory log for a memory slot.
2458 */
2459int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2460 struct kvm_dirty_log *log)
2461{
b050b015 2462 int r, n, i;
5bb064dc 2463 struct kvm_memory_slot *memslot;
b050b015
MT		 2464 unsigned long is_dirty = 0;
2465 unsigned long *dirty_bitmap = NULL;
5bb064dc 2466
79fac95e 2467 mutex_lock(&kvm->slots_lock);
5bb064dc 2468
b050b015
MT		 2469 r = -EINVAL;
2470 if (log->slot >= KVM_MEMORY_SLOTS)
2471 goto out;
2472
2473 memslot = &kvm->memslots->memslots[log->slot];
2474 r = -ENOENT;
2475 if (!memslot->dirty_bitmap)
2476 goto out;
2477
2478 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2479
2480 r = -ENOMEM;
2481 dirty_bitmap = vmalloc(n);
2482 if (!dirty_bitmap)
5bb064dc 2483 goto out;
b050b015
MT		 2484 memset(dirty_bitmap, 0, n);
2485
2486 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2487 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2488
2489 /* If nothing is dirty, don't bother messing with page tables. */
2490 if (is_dirty) {
b050b015
MT		 2491 struct kvm_memslots *slots, *old_slots;
2492
7c8a83b7 2493 spin_lock(&kvm->mmu_lock);
5bb064dc 2494 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2495 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2496
2497 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2498 if (!slots)
2499 goto out_free;
2500
2501 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2502 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2503
2504 old_slots = kvm->memslots;
2505 rcu_assign_pointer(kvm->memslots, slots);
2506 synchronize_srcu_expedited(&kvm->srcu);
2507 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2508 kfree(old_slots);
5bb064dc 2509 }
b050b015 2510
5bb064dc 2511 r = 0;
b050b015
MT		 2512 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2513 r = -EFAULT;
2514out_free:
2515 vfree(dirty_bitmap);
5bb064dc 2516out:
79fac95e 2517 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2518 return r;
2519}
2520
1fe779f8
CO		 2521long kvm_arch_vm_ioctl(struct file *filp,
2522 unsigned int ioctl, unsigned long arg)
2523{
2524 struct kvm *kvm = filp->private_data;
2525 void __user *argp = (void __user *)arg;
367e1319 2526 int r = -ENOTTY;
f0d66275
DH		 2527 /*
2528 * This union makes it completely explicit to gcc-3.x
2529 * that these two variables' stack usage should be
2530 * combined, not added together.
2531 */
2532 union {
2533 struct kvm_pit_state ps;
e9f42757 2534 struct kvm_pit_state2 ps2;
f0d66275 2535 struct kvm_memory_alias alias;
c5ff41ce 2536 struct kvm_pit_config pit_config;
f0d66275 2537 } u;
1fe779f8
CO		 2538
2539 switch (ioctl) {
2540 case KVM_SET_TSS_ADDR:
2541 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2542 if (r < 0)
2543 goto out;
2544 break;
b927a3ce
SY		 2545 case KVM_SET_IDENTITY_MAP_ADDR: {
2546 u64 ident_addr;
2547
2548 r = -EFAULT;
2549 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2550 goto out;
2551 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2552 if (r < 0)
2553 goto out;
2554 break;
2555 }
1fe779f8
CO		 2556 case KVM_SET_MEMORY_REGION: {
2557 struct kvm_memory_region kvm_mem;
2558 struct kvm_userspace_memory_region kvm_userspace_mem;
2559
2560 r = -EFAULT;
2561 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2562 goto out;
2563 kvm_userspace_mem.slot = kvm_mem.slot;
2564 kvm_userspace_mem.flags = kvm_mem.flags;
2565 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2566 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2567 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2568 if (r)
2569 goto out;
2570 break;
2571 }
2572 case KVM_SET_NR_MMU_PAGES:
2573 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2574 if (r)
2575 goto out;
2576 break;
2577 case KVM_GET_NR_MMU_PAGES:
2578 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2579 break;
f0d66275 2580 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2581 r = -EFAULT;
f0d66275 2582 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2583 goto out;
f0d66275 2584 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2585 if (r)
2586 goto out;
2587 break;
3ddea128
MT		 2588 case KVM_CREATE_IRQCHIP: {
2589 struct kvm_pic *vpic;
2590
2591 mutex_lock(&kvm->lock);
2592 r = -EEXIST;
2593 if (kvm->arch.vpic)
2594 goto create_irqchip_unlock;
1fe779f8 2595 r = -ENOMEM;
3ddea128
MT		 2596 vpic = kvm_create_pic(kvm);
2597 if (vpic) {
1fe779f8
CO		 2598 r = kvm_ioapic_init(kvm);
2599 if (r) {
3ddea128
MT		 2600 kfree(vpic);
2601 goto create_irqchip_unlock;
1fe779f8
CO		 2602 }
2603 } else
3ddea128
MT		 2604 goto create_irqchip_unlock;
2605 smp_wmb();
2606 kvm->arch.vpic = vpic;
2607 smp_wmb();
399ec807
AK		 2608 r = kvm_setup_default_irq_routing(kvm);
2609 if (r) {
3ddea128 2610 mutex_lock(&kvm->irq_lock);
399ec807
AK		 2611 kfree(kvm->arch.vpic);
2612 kfree(kvm->arch.vioapic);
3ddea128
MT		 2613 kvm->arch.vpic = NULL;
2614 kvm->arch.vioapic = NULL;
2615 mutex_unlock(&kvm->irq_lock);
399ec807 2616 }
3ddea128
MT		 2617 create_irqchip_unlock:
2618 mutex_unlock(&kvm->lock);
1fe779f8 2619 break;
3ddea128 2620 }
7837699f 2621 case KVM_CREATE_PIT:
c5ff41ce
JK		 2622 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2623 goto create_pit;
2624 case KVM_CREATE_PIT2:
2625 r = -EFAULT;
2626 if (copy_from_user(&u.pit_config, argp,
2627 sizeof(struct kvm_pit_config)))
2628 goto out;
2629 create_pit:
79fac95e 2630 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2631 r = -EEXIST;
2632 if (kvm->arch.vpit)
2633 goto create_pit_unlock;
7837699f 2634 r = -ENOMEM;
c5ff41ce 2635 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2636 if (kvm->arch.vpit)
2637 r = 0;
269e05e4 2638 create_pit_unlock:
79fac95e 2639 mutex_unlock(&kvm->slots_lock);
7837699f 2640 break;
4925663a 2641 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2642 case KVM_IRQ_LINE: {
2643 struct kvm_irq_level irq_event;
2644
2645 r = -EFAULT;
2646 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2647 goto out;
2648 if (irqchip_in_kernel(kvm)) {
4925663a 2649 __s32 status;
4925663a
GN		 2650 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2651 irq_event.irq, irq_event.level);
4925663a
GN		 2652 if (ioctl == KVM_IRQ_LINE_STATUS) {
2653 irq_event.status = status;
2654 if (copy_to_user(argp, &irq_event,
2655 sizeof irq_event))
2656 goto out;
2657 }
1fe779f8
CO		 2658 r = 0;
2659 }
2660 break;
2661 }
2662 case KVM_GET_IRQCHIP: {
2663 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2664 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2665
f0d66275
DH		 2666 r = -ENOMEM;
2667 if (!chip)
1fe779f8 2668 goto out;
f0d66275
DH		 2669 r = -EFAULT;
2670 if (copy_from_user(chip, argp, sizeof *chip))
2671 goto get_irqchip_out;
1fe779f8
CO		 2672 r = -ENXIO;
2673 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2674 goto get_irqchip_out;
2675 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2676 if (r)
f0d66275 2677 goto get_irqchip_out;
1fe779f8 2678 r = -EFAULT;
f0d66275
DH		 2679 if (copy_to_user(argp, chip, sizeof *chip))
2680 goto get_irqchip_out;
1fe779f8 2681 r = 0;
f0d66275
DH		 2682 get_irqchip_out:
2683 kfree(chip);
2684 if (r)
2685 goto out;
1fe779f8
CO		 2686 break;
2687 }
2688 case KVM_SET_IRQCHIP: {
2689 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2690 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2691
f0d66275
DH		 2692 r = -ENOMEM;
2693 if (!chip)
1fe779f8 2694 goto out;
f0d66275
DH		 2695 r = -EFAULT;
2696 if (copy_from_user(chip, argp, sizeof *chip))
2697 goto set_irqchip_out;
1fe779f8
CO		 2698 r = -ENXIO;
2699 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2700 goto set_irqchip_out;
2701 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2702 if (r)
f0d66275 2703 goto set_irqchip_out;
1fe779f8 2704 r = 0;
f0d66275
DH		 2705 set_irqchip_out:
2706 kfree(chip);
2707 if (r)
2708 goto out;
1fe779f8
CO		 2709 break;
2710 }
e0f63cb9 2711 case KVM_GET_PIT: {
e0f63cb9 2712 r = -EFAULT;
f0d66275 2713 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2714 goto out;
2715 r = -ENXIO;
2716 if (!kvm->arch.vpit)
2717 goto out;
f0d66275 2718 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2719 if (r)
2720 goto out;
2721 r = -EFAULT;
f0d66275 2722 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2723 goto out;
2724 r = 0;
2725 break;
2726 }
2727 case KVM_SET_PIT: {
e0f63cb9 2728 r = -EFAULT;
f0d66275 2729 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2730 goto out;
2731 r = -ENXIO;
2732 if (!kvm->arch.vpit)
2733 goto out;
f0d66275 2734 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2735 if (r)
2736 goto out;
2737 r = 0;
2738 break;
2739 }
e9f42757
BK		 2740 case KVM_GET_PIT2: {
2741 r = -ENXIO;
2742 if (!kvm->arch.vpit)
2743 goto out;
2744 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2745 if (r)
2746 goto out;
2747 r = -EFAULT;
2748 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2749 goto out;
2750 r = 0;
2751 break;
2752 }
2753 case KVM_SET_PIT2: {
2754 r = -EFAULT;
2755 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2756 goto out;
2757 r = -ENXIO;
2758 if (!kvm->arch.vpit)
2759 goto out;
2760 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2761 if (r)
2762 goto out;
2763 r = 0;
2764 break;
2765 }
52d939a0
MT		 2766 case KVM_REINJECT_CONTROL: {
2767 struct kvm_reinject_control control;
2768 r = -EFAULT;
2769 if (copy_from_user(&control, argp, sizeof(control)))
2770 goto out;
2771 r = kvm_vm_ioctl_reinject(kvm, &control);
2772 if (r)
2773 goto out;
2774 r = 0;
2775 break;
2776 }
ffde22ac
ES		 2777 case KVM_XEN_HVM_CONFIG: {
2778 r = -EFAULT;
2779 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2780 sizeof(struct kvm_xen_hvm_config)))
2781 goto out;
2782 r = -EINVAL;
2783 if (kvm->arch.xen_hvm_config.flags)
2784 goto out;
2785 r = 0;
2786 break;
2787 }
afbcf7ab
GC		 2788 case KVM_SET_CLOCK: {
2789 struct timespec now;
2790 struct kvm_clock_data user_ns;
2791 u64 now_ns;
2792 s64 delta;
2793
2794 r = -EFAULT;
2795 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2796 goto out;
2797
2798 r = -EINVAL;
2799 if (user_ns.flags)
2800 goto out;
2801
2802 r = 0;
2803 ktime_get_ts(&now);
2804 now_ns = timespec_to_ns(&now);
2805 delta = user_ns.clock - now_ns;
2806 kvm->arch.kvmclock_offset = delta;
2807 break;
2808 }
2809 case KVM_GET_CLOCK: {
2810 struct timespec now;
2811 struct kvm_clock_data user_ns;
2812 u64 now_ns;
2813
2814 ktime_get_ts(&now);
2815 now_ns = timespec_to_ns(&now);
2816 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2817 user_ns.flags = 0;
2818
2819 r = -EFAULT;
2820 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2821 goto out;
2822 r = 0;
2823 break;
2824 }
2825
1fe779f8
CO		 2826 default:
2827 ;
2828 }
2829out:
2830 return r;
2831}
2832
a16b043c 2833static void kvm_init_msr_list(void)
043405e1
CO		 2834{
2835 u32 dummy[2];
2836 unsigned i, j;
2837
e3267cbb
GC		 2838 /* skip the first msrs in the list. KVM-specific */
2839 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2840 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2841 continue;
2842 if (j < i)
2843 msrs_to_save[j] = msrs_to_save[i];
2844 j++;
2845 }
2846 num_msrs_to_save = j;
2847}
2848
bda9020e
MT		 2849static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2850 const void *v)
bbd9b64e 2851{
bda9020e
MT		 2852 if (vcpu->arch.apic &&
2853 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2854 return 0;
bbd9b64e 2855
e93f8a0f 2856 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 2857}
2858
bda9020e 2859static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2860{
bda9020e
MT		 2861 if (vcpu->arch.apic &&
2862 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2863 return 0;
bbd9b64e 2864
e93f8a0f 2865 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 2866}
2867
cded19f3
HE		 2868static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2869 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2870{
2871 void *data = val;
10589a46 2872 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2873
2874 while (bytes) {
ad312c7c 2875 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2876 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2877 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2878 int ret;
2879
10589a46
MT		 2880 if (gpa == UNMAPPED_GVA) {
2881 r = X86EMUL_PROPAGATE_FAULT;
2882 goto out;
2883 }
77c2002e 2884 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2885 if (ret < 0) {
2886 r = X86EMUL_UNHANDLEABLE;
2887 goto out;
2888 }
bbd9b64e 2889
77c2002e
IE		 2890 bytes -= toread;
2891 data += toread;
2892 addr += toread;
bbd9b64e 2893 }
10589a46 2894out:
10589a46 2895 return r;
bbd9b64e 2896}
77c2002e 2897
cded19f3
HE		 2898static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2899 struct kvm_vcpu *vcpu)
77c2002e
IE		 2900{
2901 void *data = val;
2902 int r = X86EMUL_CONTINUE;
2903
2904 while (bytes) {
2905 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2906 unsigned offset = addr & (PAGE_SIZE-1);
2907 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2908 int ret;
2909
2910 if (gpa == UNMAPPED_GVA) {
2911 r = X86EMUL_PROPAGATE_FAULT;
2912 goto out;
2913 }
2914 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2915 if (ret < 0) {
2916 r = X86EMUL_UNHANDLEABLE;
2917 goto out;
2918 }
2919
2920 bytes -= towrite;
2921 data += towrite;
2922 addr += towrite;
2923 }
2924out:
2925 return r;
2926}
2927
bbd9b64e 2928
bbd9b64e
CO		 2929static int emulator_read_emulated(unsigned long addr,
2930 void *val,
2931 unsigned int bytes,
2932 struct kvm_vcpu *vcpu)
2933{
bbd9b64e
CO		 2934 gpa_t gpa;
2935
2936 if (vcpu->mmio_read_completed) {
2937 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2938 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2939 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2940 vcpu->mmio_read_completed = 0;
2941 return X86EMUL_CONTINUE;
2942 }
2943
ad312c7c 2944 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2945
2946 /* For APIC access vmexit */
2947 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2948 goto mmio;
2949
77c2002e
IE		 2950 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2951 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2952 return X86EMUL_CONTINUE;
2953 if (gpa == UNMAPPED_GVA)
2954 return X86EMUL_PROPAGATE_FAULT;
2955
2956mmio:
2957 /*
2958 * Is this MMIO handled locally?
2959 */
aec51dc4
AK		 2960 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2961 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2962 return X86EMUL_CONTINUE;
2963 }
aec51dc4
AK		 2964
2965 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2966
2967 vcpu->mmio_needed = 1;
2968 vcpu->mmio_phys_addr = gpa;
2969 vcpu->mmio_size = bytes;
2970 vcpu->mmio_is_write = 0;
2971
2972 return X86EMUL_UNHANDLEABLE;
2973}
2974
3200f405 2975int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2976 const void *val, int bytes)
bbd9b64e
CO		 2977{
2978 int ret;
2979
2980 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2981 if (ret < 0)
bbd9b64e 2982 return 0;
ad218f85 2983 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2984 return 1;
2985}
2986
2987static int emulator_write_emulated_onepage(unsigned long addr,
2988 const void *val,
2989 unsigned int bytes,
2990 struct kvm_vcpu *vcpu)
2991{
10589a46
MT		 2992 gpa_t gpa;
2993
10589a46 2994 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2995
2996 if (gpa == UNMAPPED_GVA) {
c3c91fee 2997 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2998 return X86EMUL_PROPAGATE_FAULT;
2999 }
3000
3001 /* For APIC access vmexit */
3002 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3003 goto mmio;
3004
3005 if (emulator_write_phys(vcpu, gpa, val, bytes))
3006 return X86EMUL_CONTINUE;
3007
3008mmio:
aec51dc4 3009 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3010 /*
3011 * Is this MMIO handled locally?
3012 */
bda9020e 3013 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3014 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3015
3016 vcpu->mmio_needed = 1;
3017 vcpu->mmio_phys_addr = gpa;
3018 vcpu->mmio_size = bytes;
3019 vcpu->mmio_is_write = 1;
3020 memcpy(vcpu->mmio_data, val, bytes);
3021
3022 return X86EMUL_CONTINUE;
3023}
3024
3025int emulator_write_emulated(unsigned long addr,
3026 const void *val,
3027 unsigned int bytes,
3028 struct kvm_vcpu *vcpu)
3029{
3030 /* Crossing a page boundary? */
3031 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3032 int rc, now;
3033
3034 now = -addr & ~PAGE_MASK;
3035 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3036 if (rc != X86EMUL_CONTINUE)
3037 return rc;
3038 addr += now;
3039 val += now;
3040 bytes -= now;
3041 }
3042 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3043}
3044EXPORT_SYMBOL_GPL(emulator_write_emulated);
3045
3046static int emulator_cmpxchg_emulated(unsigned long addr,
3047 const void *old,
3048 const void *new,
3049 unsigned int bytes,
3050 struct kvm_vcpu *vcpu)
3051{
9f51e24e 3052 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3053#ifndef CONFIG_X86_64
3054 /* guests cmpxchg8b have to be emulated atomically */
3055 if (bytes == 8) {
10589a46 3056 gpa_t gpa;
2bacc55c 3057 struct page *page;
c0b49b0d 3058 char *kaddr;
2bacc55c
MT		 3059 u64 val;
3060
10589a46
MT		 3061 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
3062
2bacc55c
MT		 3063 if (gpa == UNMAPPED_GVA ||
3064 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3065 goto emul_write;
3066
3067 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3068 goto emul_write;
3069
3070 val = *(u64 *)new;
72dc67a6 3071
2bacc55c 3072 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3073
c0b49b0d
AM		 3074 kaddr = kmap_atomic(page, KM_USER0);
3075 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3076 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3077 kvm_release_page_dirty(page);
3078 }
3200f405 3079emul_write:
2bacc55c
MT		 3080#endif
3081
bbd9b64e
CO		 3082 return emulator_write_emulated(addr, new, bytes, vcpu);
3083}
3084
3085static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3086{
3087 return kvm_x86_ops->get_segment_base(vcpu, seg);
3088}
3089
3090int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3091{
a7052897 3092 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3093 return X86EMUL_CONTINUE;
3094}
3095
3096int emulate_clts(struct kvm_vcpu *vcpu)
3097{
ad312c7c 3098 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 3099 return X86EMUL_CONTINUE;
3100}
3101
3102int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3103{
3104 struct kvm_vcpu *vcpu = ctxt->vcpu;
3105
3106 switch (dr) {
3107 case 0 ... 3:
3108 *dest = kvm_x86_ops->get_dr(vcpu, dr);
3109 return X86EMUL_CONTINUE;
3110 default:
b8688d51 3111 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 3112 return X86EMUL_UNHANDLEABLE;
3113 }
3114}
3115
3116int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3117{
3118 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
3119 int exception;
3120
3121 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
3122 if (exception) {
3123 /* FIXME: better handling */
3124 return X86EMUL_UNHANDLEABLE;
3125 }
3126 return X86EMUL_CONTINUE;
3127}
3128
3129void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3130{
bbd9b64e 3131 u8 opcodes[4];
5fdbf976 3132 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3133 unsigned long rip_linear;
3134
f76c710d 3135 if (!printk_ratelimit())
bbd9b64e
CO		 3136 return;
3137
25be4608
GC		 3138 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3139
77c2002e 3140 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 3141
3142 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3143 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3144}
3145EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3146
14af3f3c 3147static struct x86_emulate_ops emulate_ops = {
77c2002e 3148 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 3149 .read_emulated = emulator_read_emulated,
3150 .write_emulated = emulator_write_emulated,
3151 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3152};
3153
5fdbf976
MT		 3154static void cache_all_regs(struct kvm_vcpu *vcpu)
3155{
3156 kvm_register_read(vcpu, VCPU_REGS_RAX);
3157 kvm_register_read(vcpu, VCPU_REGS_RSP);
3158 kvm_register_read(vcpu, VCPU_REGS_RIP);
3159 vcpu->arch.regs_dirty = ~0;
3160}
3161
bbd9b64e 3162int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3163 unsigned long cr2,
3164 u16 error_code,
571008da 3165 int emulation_type)
bbd9b64e 3166{
310b5d30 3167 int r, shadow_mask;
571008da 3168 struct decode_cache *c;
851ba692 3169 struct kvm_run *run = vcpu->run;
bbd9b64e 3170
26eef70c 3171 kvm_clear_exception_queue(vcpu);
ad312c7c 3172 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3173 /*
56e82318 3174 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3175 * instead of direct ->regs accesses, can save hundred cycles
3176 * on Intel for instructions that don't read/change RSP, for
3177 * for example.
3178 */
3179 cache_all_regs(vcpu);
bbd9b64e
CO		 3180
3181 vcpu->mmio_is_write = 0;
ad312c7c 3182 vcpu->arch.pio.string = 0;
bbd9b64e 3183
571008da 3184 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3185 int cs_db, cs_l;
3186 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3187
ad312c7c 3188 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3189 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c
ZX		 3190 vcpu->arch.emulate_ctxt.mode =
3191 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 3192 ? X86EMUL_MODE_REAL : cs_l
3193 ? X86EMUL_MODE_PROT64 : cs_db
3194 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3195
ad312c7c 3196 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3197
0cb5762e
AP		 3198 /* Only allow emulation of specific instructions on #UD
3199 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3200 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3201 if (emulation_type & EMULTYPE_TRAP_UD) {
3202 if (!c->twobyte)
3203 return EMULATE_FAIL;
3204 switch (c->b) {
3205 case 0x01: /* VMMCALL */
3206 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3207 return EMULATE_FAIL;
3208 break;
3209 case 0x34: /* sysenter */
3210 case 0x35: /* sysexit */
3211 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3212 return EMULATE_FAIL;
3213 break;
3214 case 0x05: /* syscall */
3215 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3216 return EMULATE_FAIL;
3217 break;
3218 default:
3219 return EMULATE_FAIL;
3220 }
3221
3222 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3223 return EMULATE_FAIL;
3224 }
571008da 3225
f2b5756b 3226 ++vcpu->stat.insn_emulation;
bbd9b64e 3227 if (r) {
f2b5756b 3228 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3229 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3230 return EMULATE_DONE;
3231 return EMULATE_FAIL;
3232 }
3233 }
3234
ba8afb6b
GN		 3235 if (emulation_type & EMULTYPE_SKIP) {
3236 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3237 return EMULATE_DONE;
3238 }
3239
ad312c7c 3240 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3241 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3242
3243 if (r == 0)
3244 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3245
ad312c7c 3246 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3247 return EMULATE_DO_MMIO;
3248
3249 if ((r || vcpu->mmio_is_write) && run) {
3250 run->exit_reason = KVM_EXIT_MMIO;
3251 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3252 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3253 run->mmio.len = vcpu->mmio_size;
3254 run->mmio.is_write = vcpu->mmio_is_write;
3255 }
3256
3257 if (r) {
3258 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3259 return EMULATE_DONE;
3260 if (!vcpu->mmio_needed) {
3261 kvm_report_emulation_failure(vcpu, "mmio");
3262 return EMULATE_FAIL;
3263 }
3264 return EMULATE_DO_MMIO;
3265 }
3266
91586a3b 3267 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3268
3269 if (vcpu->mmio_is_write) {
3270 vcpu->mmio_needed = 0;
3271 return EMULATE_DO_MMIO;
3272 }
3273
3274 return EMULATE_DONE;
3275}
3276EXPORT_SYMBOL_GPL(emulate_instruction);
3277
de7d789a
CO		 3278static int pio_copy_data(struct kvm_vcpu *vcpu)
3279{
ad312c7c 3280 void *p = vcpu->arch.pio_data;
0f346074 3281 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3282 unsigned bytes;
0f346074 3283 int ret;
de7d789a 3284
ad312c7c
ZX		 3285 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3286 if (vcpu->arch.pio.in)
0f346074 3287 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 3288 else
0f346074
IE		 3289 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
3290 return ret;
de7d789a
CO		 3291}
3292
3293int complete_pio(struct kvm_vcpu *vcpu)
3294{
ad312c7c 3295 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3296 long delta;
3297 int r;
5fdbf976 3298 unsigned long val;
de7d789a
CO		 3299
3300 if (!io->string) {
5fdbf976
MT		 3301 if (io->in) {
3302 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3303 memcpy(&val, vcpu->arch.pio_data, io->size);
3304 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3305 }
de7d789a
CO		 3306 } else {
3307 if (io->in) {
3308 r = pio_copy_data(vcpu);
5fdbf976 3309 if (r)
de7d789a 3310 return r;
de7d789a
CO		 3311 }
3312
3313 delta = 1;
3314 if (io->rep) {
3315 delta *= io->cur_count;
3316 /*
3317 * The size of the register should really depend on
3318 * current address size.
3319 */
5fdbf976
MT		 3320 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3321 val -= delta;
3322 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3323 }
3324 if (io->down)
3325 delta = -delta;
3326 delta *= io->size;
5fdbf976
MT		 3327 if (io->in) {
3328 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3329 val += delta;
3330 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3331 } else {
3332 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3333 val += delta;
3334 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3335 }
de7d789a
CO		 3336 }
3337
de7d789a
CO		 3338 io->count -= io->cur_count;
3339 io->cur_count = 0;
3340
3341 return 0;
3342}
3343
bda9020e 3344static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3345{
3346 /* TODO: String I/O for in kernel device */
bda9020e 3347 int r;
de7d789a 3348
ad312c7c 3349 if (vcpu->arch.pio.in)
e93f8a0f 3350 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3351 vcpu->arch.pio.size, pd);
de7d789a 3352 else
e93f8a0f
MT		 3353 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3354 vcpu->arch.pio.port, vcpu->arch.pio.size,
3355 pd);
bda9020e 3356 return r;
de7d789a
CO		 3357}
3358
bda9020e 3359static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3360{
ad312c7c
ZX		 3361 struct kvm_pio_request *io = &vcpu->arch.pio;
3362 void *pd = vcpu->arch.pio_data;
bda9020e 3363 int i, r = 0;
de7d789a 3364
de7d789a 3365 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3366 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3367 io->port, io->size, pd)) {
3368 r = -EOPNOTSUPP;
3369 break;
3370 }
de7d789a
CO		 3371 pd += io->size;
3372 }
bda9020e 3373 return r;
de7d789a
CO		 3374}
3375
851ba692 3376int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3377{
5fdbf976 3378 unsigned long val;
de7d789a
CO		 3379
3380 vcpu->run->exit_reason = KVM_EXIT_IO;
3381 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3382 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3383 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3384 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3385 vcpu->run->io.port = vcpu->arch.pio.port = port;
3386 vcpu->arch.pio.in = in;
3387 vcpu->arch.pio.string = 0;
3388 vcpu->arch.pio.down = 0;
ad312c7c 3389 vcpu->arch.pio.rep = 0;
de7d789a 3390
229456fc
MT		 3391 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3392 size, 1);
2714d1d3 3393
5fdbf976
MT		 3394 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3395 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 3396
bda9020e 3397 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3398 complete_pio(vcpu);
3399 return 1;
3400 }
3401 return 0;
3402}
3403EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3404
851ba692 3405int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3406 int size, unsigned long count, int down,
3407 gva_t address, int rep, unsigned port)
3408{
3409 unsigned now, in_page;
0f346074 3410 int ret = 0;
de7d789a
CO		 3411
3412 vcpu->run->exit_reason = KVM_EXIT_IO;
3413 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3414 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3415 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3416 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3417 vcpu->run->io.port = vcpu->arch.pio.port = port;
3418 vcpu->arch.pio.in = in;
3419 vcpu->arch.pio.string = 1;
3420 vcpu->arch.pio.down = down;
ad312c7c 3421 vcpu->arch.pio.rep = rep;
de7d789a 3422
229456fc
MT		 3423 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3424 size, count);
2714d1d3 3425
de7d789a
CO		 3426 if (!count) {
3427 kvm_x86_ops->skip_emulated_instruction(vcpu);
3428 return 1;
3429 }
3430
3431 if (!down)
3432 in_page = PAGE_SIZE - offset_in_page(address);
3433 else
3434 in_page = offset_in_page(address) + size;
3435 now = min(count, (unsigned long)in_page / size);
0f346074 3436 if (!now)
de7d789a 3437 now = 1;
de7d789a
CO		 3438 if (down) {
3439 /*
3440 * String I/O in reverse. Yuck. Kill the guest, fix later.
3441 */
3442 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3443 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3444 return 1;
3445 }
3446 vcpu->run->io.count = now;
ad312c7c 3447 vcpu->arch.pio.cur_count = now;
de7d789a 3448
ad312c7c 3449 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3450 kvm_x86_ops->skip_emulated_instruction(vcpu);
3451
0f346074 3452 vcpu->arch.pio.guest_gva = address;
de7d789a 3453
ad312c7c 3454 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3455 /* string PIO write */
3456 ret = pio_copy_data(vcpu);
0f346074
IE		 3457 if (ret == X86EMUL_PROPAGATE_FAULT) {
3458 kvm_inject_gp(vcpu, 0);
3459 return 1;
3460 }
bda9020e 3461 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3462 complete_pio(vcpu);
ad312c7c 3463 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3464 ret = 1;
3465 }
bda9020e
MT		 3466 }
3467 /* no string PIO read support yet */
de7d789a
CO		 3468
3469 return ret;
3470}
3471EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3472
c8076604
GH		 3473static void bounce_off(void *info)
3474{
3475 /* nothing */
3476}
3477
c8076604
GH		 3478static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3479 void *data)
3480{
3481 struct cpufreq_freqs *freq = data;
3482 struct kvm *kvm;
3483 struct kvm_vcpu *vcpu;
3484 int i, send_ipi = 0;
3485
c8076604
GH		 3486 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3487 return 0;
3488 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3489 return 0;
0cca7907 3490 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3491
3492 spin_lock(&kvm_lock);
3493 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3494 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3495 if (vcpu->cpu != freq->cpu)
3496 continue;
3497 if (!kvm_request_guest_time_update(vcpu))
3498 continue;
3499 if (vcpu->cpu != smp_processor_id())
3500 send_ipi++;
3501 }
3502 }
3503 spin_unlock(&kvm_lock);
3504
3505 if (freq->old < freq->new && send_ipi) {
3506 /*
3507 * We upscale the frequency. Must make the guest
3508 * doesn't see old kvmclock values while running with
3509 * the new frequency, otherwise we risk the guest sees
3510 * time go backwards.
3511 *
3512 * In case we update the frequency for another cpu
3513 * (which might be in guest context) send an interrupt
3514 * to kick the cpu out of guest context. Next time
3515 * guest context is entered kvmclock will be updated,
3516 * so the guest will not see stale values.
3517 */
3518 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3519 }
3520 return 0;
3521}
3522
3523static struct notifier_block kvmclock_cpufreq_notifier_block = {
3524 .notifier_call = kvmclock_cpufreq_notifier
3525};
3526
b820cc0c
ZA		 3527static void kvm_timer_init(void)
3528{
3529 int cpu;
3530
b820cc0c 3531 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3532 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3533 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3534 for_each_online_cpu(cpu) {
3535 unsigned long khz = cpufreq_get(cpu);
3536 if (!khz)
3537 khz = tsc_khz;
3538 per_cpu(cpu_tsc_khz, cpu) = khz;
3539 }
0cca7907
ZA		 3540 } else {
3541 for_each_possible_cpu(cpu)
3542 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3543 }
3544}
3545
f8c16bba 3546int kvm_arch_init(void *opaque)
043405e1 3547{
b820cc0c 3548 int r;
f8c16bba
ZX		 3549 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3550
f8c16bba
ZX		 3551 if (kvm_x86_ops) {
3552 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3553 r = -EEXIST;
3554 goto out;
f8c16bba
ZX		 3555 }
3556
3557 if (!ops->cpu_has_kvm_support()) {
3558 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3559 r = -EOPNOTSUPP;
3560 goto out;
f8c16bba
ZX		 3561 }
3562 if (ops->disabled_by_bios()) {
3563 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3564 r = -EOPNOTSUPP;
3565 goto out;
f8c16bba
ZX		 3566 }
3567
97db56ce
AK		 3568 r = kvm_mmu_module_init();
3569 if (r)
3570 goto out;
3571
3572 kvm_init_msr_list();
3573
f8c16bba 3574 kvm_x86_ops = ops;
56c6d28a 3575 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3576 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3577 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3578 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3579
b820cc0c 3580 kvm_timer_init();
c8076604 3581
f8c16bba 3582 return 0;
56c6d28a
ZX		 3583
3584out:
56c6d28a 3585 return r;
043405e1 3586}
8776e519 3587
f8c16bba
ZX		 3588void kvm_arch_exit(void)
3589{
888d256e
JK		 3590 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3591 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3592 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3593 kvm_x86_ops = NULL;
56c6d28a
ZX		 3594 kvm_mmu_module_exit();
3595}
f8c16bba 3596
8776e519
HB		 3597int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3598{
3599 ++vcpu->stat.halt_exits;
3600 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3601 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3602 return 1;
3603 } else {
3604 vcpu->run->exit_reason = KVM_EXIT_HLT;
3605 return 0;
3606 }
3607}
3608EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3609
2f333bcb
MT		 3610static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3611 unsigned long a1)
3612{
3613 if (is_long_mode(vcpu))
3614 return a0;
3615 else
3616 return a0 | ((gpa_t)a1 << 32);
3617}
3618
8776e519
HB		 3619int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3620{
3621 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3622 int r = 1;
8776e519 3623
5fdbf976
MT		 3624 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3625 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3626 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3627 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3628 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3629
229456fc 3630 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3631
8776e519
HB		 3632 if (!is_long_mode(vcpu)) {
3633 nr &= 0xFFFFFFFF;
3634 a0 &= 0xFFFFFFFF;
3635 a1 &= 0xFFFFFFFF;
3636 a2 &= 0xFFFFFFFF;
3637 a3 &= 0xFFFFFFFF;
3638 }
3639
07708c4a
JK		 3640 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3641 ret = -KVM_EPERM;
3642 goto out;
3643 }
3644
8776e519 3645 switch (nr) {
b93463aa
AK		 3646 case KVM_HC_VAPIC_POLL_IRQ:
3647 ret = 0;
3648 break;
2f333bcb
MT		 3649 case KVM_HC_MMU_OP:
3650 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3651 break;
8776e519
HB		 3652 default:
3653 ret = -KVM_ENOSYS;
3654 break;
3655 }
07708c4a 3656out:
5fdbf976 3657 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3658 ++vcpu->stat.hypercalls;
2f333bcb 3659 return r;
8776e519
HB		 3660}
3661EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3662
3663int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3664{
3665 char instruction[3];
3666 int ret = 0;
5fdbf976 3667 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3668
8776e519
HB		 3669
3670 /*
3671 * Blow out the MMU to ensure that no other VCPU has an active mapping
3672 * to ensure that the updated hypercall appears atomically across all
3673 * VCPUs.
3674 */
3675 kvm_mmu_zap_all(vcpu->kvm);
3676
8776e519 3677 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3678 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3679 != X86EMUL_CONTINUE)
3680 ret = -EFAULT;
3681
8776e519
HB		 3682 return ret;
3683}
3684
3685static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3686{
3687 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3688}
3689
3690void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3691{
3692 struct descriptor_table dt = { limit, base };
3693
3694 kvm_x86_ops->set_gdt(vcpu, &dt);
3695}
3696
3697void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3698{
3699 struct descriptor_table dt = { limit, base };
3700
3701 kvm_x86_ops->set_idt(vcpu, &dt);
3702}
3703
3704void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3705 unsigned long *rflags)
3706{
2d3ad1f4 3707 kvm_lmsw(vcpu, msw);
91586a3b 3708 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3709}
3710
3711unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3712{
54e445ca
JR		 3713 unsigned long value;
3714
8776e519
HB		 3715 switch (cr) {
3716 case 0:
54e445ca
JR		 3717 value = vcpu->arch.cr0;
3718 break;
8776e519 3719 case 2:
54e445ca
JR		 3720 value = vcpu->arch.cr2;
3721 break;
8776e519 3722 case 3:
54e445ca
JR		 3723 value = vcpu->arch.cr3;
3724 break;
8776e519 3725 case 4:
fc78f519 3726 value = kvm_read_cr4(vcpu);
54e445ca 3727 break;
152ff9be 3728 case 8:
54e445ca
JR		 3729 value = kvm_get_cr8(vcpu);
3730 break;
8776e519 3731 default:
b8688d51 3732 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3733 return 0;
3734 }
54e445ca
JR		 3735
3736 return value;
8776e519
HB		 3737}
3738
3739void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3740 unsigned long *rflags)
3741{
3742 switch (cr) {
3743 case 0:
2d3ad1f4 3744 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
91586a3b 3745 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3746 break;
3747 case 2:
ad312c7c 3748 vcpu->arch.cr2 = val;
8776e519
HB		 3749 break;
3750 case 3:
2d3ad1f4 3751 kvm_set_cr3(vcpu, val);
8776e519
HB		 3752 break;
3753 case 4:
fc78f519 3754 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 3755 break;
152ff9be 3756 case 8:
2d3ad1f4 3757 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3758 break;
8776e519 3759 default:
b8688d51 3760 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3761 }
3762}
3763
07716717
DK		 3764static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3765{
ad312c7c
ZX		 3766 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3767 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3768
3769 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3770 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3771 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3772 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3773 if (ej->function == e->function) {
3774 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3775 return j;
3776 }
3777 }
3778 return 0; /* silence gcc, even though control never reaches here */
3779}
3780
3781/* find an entry with matching function, matching index (if needed), and that
3782 * should be read next (if it's stateful) */
3783static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3784 u32 function, u32 index)
3785{
3786 if (e->function != function)
3787 return 0;
3788 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3789 return 0;
3790 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3791 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3792 return 0;
3793 return 1;
3794}
3795
d8017474
AG		 3796struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3797 u32 function, u32 index)
8776e519
HB		 3798{
3799 int i;
d8017474 3800 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3801
ad312c7c 3802 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3803 struct kvm_cpuid_entry2 *e;
3804
ad312c7c 3805 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3806 if (is_matching_cpuid_entry(e, function, index)) {
3807 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3808 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3809 best = e;
3810 break;
3811 }
3812 /*
3813 * Both basic or both extended?
3814 */
3815 if (((e->function ^ function) & 0x80000000) == 0)
3816 if (!best || e->function > best->function)
3817 best = e;
3818 }
d8017474
AG		 3819 return best;
3820}
0e851880 3821EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 3822
82725b20
DE		 3823int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3824{
3825 struct kvm_cpuid_entry2 *best;
3826
3827 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3828 if (best)
3829 return best->eax & 0xff;
3830 return 36;
3831}
3832
d8017474
AG		 3833void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3834{
3835 u32 function, index;
3836 struct kvm_cpuid_entry2 *best;
3837
3838 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3839 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3840 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3841 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3842 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3843 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3844 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3845 if (best) {
5fdbf976
MT		 3846 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3847 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3848 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3849 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3850 }
8776e519 3851 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3852 trace_kvm_cpuid(function,
3853 kvm_register_read(vcpu, VCPU_REGS_RAX),
3854 kvm_register_read(vcpu, VCPU_REGS_RBX),
3855 kvm_register_read(vcpu, VCPU_REGS_RCX),
3856 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3857}
3858EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3859
b6c7a5dc
HB		 3860/*
3861 * Check if userspace requested an interrupt window, and that the
3862 * interrupt window is open.
3863 *
3864 * No need to exit to userspace if we already have an interrupt queued.
3865 */
851ba692 3866static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 3867{
8061823a 3868 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 3869 vcpu->run->request_interrupt_window &&
5df56646 3870 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3871}
3872
851ba692 3873static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 3874{
851ba692
AK		 3875 struct kvm_run *kvm_run = vcpu->run;
3876
91586a3b 3877 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3878 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3879 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3880 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3881 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3882 else
b6c7a5dc 3883 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3884 kvm_arch_interrupt_allowed(vcpu) &&
3885 !kvm_cpu_has_interrupt(vcpu) &&
3886 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3887}
3888
b93463aa
AK		 3889static void vapic_enter(struct kvm_vcpu *vcpu)
3890{
3891 struct kvm_lapic *apic = vcpu->arch.apic;
3892 struct page *page;
3893
3894 if (!apic || !apic->vapic_addr)
3895 return;
3896
3897 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3898
3899 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3900}
3901
3902static void vapic_exit(struct kvm_vcpu *vcpu)
3903{
3904 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 3905 int idx;
b93463aa
AK		 3906
3907 if (!apic || !apic->vapic_addr)
3908 return;
3909
f656ce01 3910 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 3911 kvm_release_page_dirty(apic->vapic_page);
3912 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 3913 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3914}
3915
95ba8273
GN		 3916static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3917{
3918 int max_irr, tpr;
3919
3920 if (!kvm_x86_ops->update_cr8_intercept)
3921 return;
3922
88c808fd
AK		 3923 if (!vcpu->arch.apic)
3924 return;
3925
8db3baa2
GN		 3926 if (!vcpu->arch.apic->vapic_addr)
3927 max_irr = kvm_lapic_find_highest_irr(vcpu);
3928 else
3929 max_irr = -1;
95ba8273
GN		 3930
3931 if (max_irr != -1)
3932 max_irr >>= 4;
3933
3934 tpr = kvm_lapic_get_cr8(vcpu);
3935
3936 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3937}
3938
851ba692 3939static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 3940{
3941 /* try to reinject previous events if any */
b59bb7bd
GN		 3942 if (vcpu->arch.exception.pending) {
3943 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3944 vcpu->arch.exception.has_error_code,
3945 vcpu->arch.exception.error_code);
3946 return;
3947 }
3948
95ba8273
GN		 3949 if (vcpu->arch.nmi_injected) {
3950 kvm_x86_ops->set_nmi(vcpu);
3951 return;
3952 }
3953
3954 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3955 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3956 return;
3957 }
3958
3959 /* try to inject new event if pending */
3960 if (vcpu->arch.nmi_pending) {
3961 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3962 vcpu->arch.nmi_pending = false;
3963 vcpu->arch.nmi_injected = true;
3964 kvm_x86_ops->set_nmi(vcpu);
3965 }
3966 } else if (kvm_cpu_has_interrupt(vcpu)) {
3967 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3968 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3969 false);
3970 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3971 }
3972 }
3973}
3974
851ba692 3975static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 3976{
3977 int r;
6a8b1d13 3978 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 3979 vcpu->run->request_interrupt_window;
b6c7a5dc 3980
2e53d63a
MT		 3981 if (vcpu->requests)
3982 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3983 kvm_mmu_unload(vcpu);
3984
b6c7a5dc
HB		 3985 r = kvm_mmu_reload(vcpu);
3986 if (unlikely(r))
3987 goto out;
3988
2f52d58c
AK		 3989 if (vcpu->requests) {
3990 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3991 __kvm_migrate_timers(vcpu);
c8076604
GH		 3992 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3993 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3994 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3995 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3996 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3997 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3998 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3999 &vcpu->requests)) {
851ba692 4000 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4001 r = 0;
4002 goto out;
4003 }
71c4dfaf 4004 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4005 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4006 r = 0;
4007 goto out;
4008 }
2f52d58c 4009 }
b93463aa 4010
b6c7a5dc
HB		 4011 preempt_disable();
4012
4013 kvm_x86_ops->prepare_guest_switch(vcpu);
4014 kvm_load_guest_fpu(vcpu);
4015
4016 local_irq_disable();
4017
32f88400
MT		 4018 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4019 smp_mb__after_clear_bit();
4020
d7690175 4021 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4022 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4023 local_irq_enable();
4024 preempt_enable();
4025 r = 1;
4026 goto out;
4027 }
4028
851ba692 4029 inject_pending_event(vcpu);
b6c7a5dc 4030
6a8b1d13
GN		 4031 /* enable NMI/IRQ window open exits if needed */
4032 if (vcpu->arch.nmi_pending)
4033 kvm_x86_ops->enable_nmi_window(vcpu);
4034 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4035 kvm_x86_ops->enable_irq_window(vcpu);
4036
95ba8273 4037 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4038 update_cr8_intercept(vcpu);
4039 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4040 }
b93463aa 4041
f656ce01 4042 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4043
b6c7a5dc
HB		 4044 kvm_guest_enter();
4045
42dbaa5a 4046 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4047 set_debugreg(0, 7);
4048 set_debugreg(vcpu->arch.eff_db[0], 0);
4049 set_debugreg(vcpu->arch.eff_db[1], 1);
4050 set_debugreg(vcpu->arch.eff_db[2], 2);
4051 set_debugreg(vcpu->arch.eff_db[3], 3);
4052 }
b6c7a5dc 4053
229456fc 4054 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4055 kvm_x86_ops->run(vcpu);
b6c7a5dc 4056
24f1e32c
FW		 4057 /*
4058 * If the guest has used debug registers, at least dr7
4059 * will be disabled while returning to the host.
4060 * If we don't have active breakpoints in the host, we don't
4061 * care about the messed up debug address registers. But if
4062 * we have some of them active, restore the old state.
4063 */
59d8eb53 4064 if (hw_breakpoint_active())
24f1e32c 4065 hw_breakpoint_restore();
42dbaa5a 4066
32f88400 4067 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4068 local_irq_enable();
4069
4070 ++vcpu->stat.exits;
4071
4072 /*
4073 * We must have an instruction between local_irq_enable() and
4074 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4075 * the interrupt shadow. The stat.exits increment will do nicely.
4076 * But we need to prevent reordering, hence this barrier():
4077 */
4078 barrier();
4079
4080 kvm_guest_exit();
4081
4082 preempt_enable();
4083
f656ce01 4084 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4085
b6c7a5dc
HB		 4086 /*
4087 * Profile KVM exit RIPs:
4088 */
4089 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4090 unsigned long rip = kvm_rip_read(vcpu);
4091 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4092 }
4093
298101da 4094
b93463aa
AK		 4095 kvm_lapic_sync_from_vapic(vcpu);
4096
851ba692 4097 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4098out:
4099 return r;
4100}
b6c7a5dc 4101
09cec754 4102
851ba692 4103static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4104{
4105 int r;
f656ce01 4106 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4107
4108 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4109 pr_debug("vcpu %d received sipi with vector # %x\n",
4110 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4111 kvm_lapic_reset(vcpu);
5f179287 4112 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4113 if (r)
4114 return r;
4115 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4116 }
4117
f656ce01 4118 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4119 vapic_enter(vcpu);
4120
4121 r = 1;
4122 while (r > 0) {
af2152f5 4123 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4124 r = vcpu_enter_guest(vcpu);
d7690175 4125 else {
f656ce01 4126 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4127 kvm_vcpu_block(vcpu);
f656ce01 4128 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4129 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4130 {
4131 switch(vcpu->arch.mp_state) {
4132 case KVM_MP_STATE_HALTED:
d7690175 4133 vcpu->arch.mp_state =
09cec754
GN		 4134 KVM_MP_STATE_RUNNABLE;
4135 case KVM_MP_STATE_RUNNABLE:
4136 break;
4137 case KVM_MP_STATE_SIPI_RECEIVED:
4138 default:
4139 r = -EINTR;
4140 break;
4141 }
4142 }
d7690175
MT		 4143 }
4144
09cec754
GN		 4145 if (r <= 0)
4146 break;
4147
4148 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4149 if (kvm_cpu_has_pending_timer(vcpu))
4150 kvm_inject_pending_timer_irqs(vcpu);
4151
851ba692 4152 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4153 r = -EINTR;
851ba692 4154 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4155 ++vcpu->stat.request_irq_exits;
4156 }
4157 if (signal_pending(current)) {
4158 r = -EINTR;
851ba692 4159 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4160 ++vcpu->stat.signal_exits;
4161 }
4162 if (need_resched()) {
f656ce01 4163 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4164 kvm_resched(vcpu);
f656ce01 4165 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4166 }
b6c7a5dc
HB		 4167 }
4168
f656ce01 4169 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4170 post_kvm_run_save(vcpu);
b6c7a5dc 4171
b93463aa
AK		 4172 vapic_exit(vcpu);
4173
b6c7a5dc
HB		 4174 return r;
4175}
4176
4177int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4178{
4179 int r;
4180 sigset_t sigsaved;
4181
4182 vcpu_load(vcpu);
4183
ac9f6dc0
AK		 4184 if (vcpu->sigset_active)
4185 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4186
a4535290 4187 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4188 kvm_vcpu_block(vcpu);
d7690175 4189 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4190 r = -EAGAIN;
4191 goto out;
b6c7a5dc
HB		 4192 }
4193
b6c7a5dc
HB		 4194 /* re-sync apic's tpr */
4195 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4196 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4197
ad312c7c 4198 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4199 r = complete_pio(vcpu);
4200 if (r)
4201 goto out;
4202 }
b6c7a5dc
HB		 4203 if (vcpu->mmio_needed) {
4204 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4205 vcpu->mmio_read_completed = 1;
4206 vcpu->mmio_needed = 0;
3200f405 4207
f656ce01 4208 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4209 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4210 EMULTYPE_NO_DECODE);
f656ce01 4211 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4212 if (r == EMULATE_DO_MMIO) {
4213 /*
4214 * Read-modify-write. Back to userspace.
4215 */
4216 r = 0;
4217 goto out;
4218 }
4219 }
5fdbf976
MT		 4220 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4221 kvm_register_write(vcpu, VCPU_REGS_RAX,
4222 kvm_run->hypercall.ret);
b6c7a5dc 4223
851ba692 4224 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4225
4226out:
4227 if (vcpu->sigset_active)
4228 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4229
4230 vcpu_put(vcpu);
4231 return r;
4232}
4233
4234int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4235{
4236 vcpu_load(vcpu);
4237
5fdbf976
MT		 4238 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4239 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4240 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4241 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4242 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4243 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4244 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4245 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4246#ifdef CONFIG_X86_64
5fdbf976
MT		 4247 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4248 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4249 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4250 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4251 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4252 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4253 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4254 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4255#endif
4256
5fdbf976 4257 regs->rip = kvm_rip_read(vcpu);
91586a3b 4258 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4259
4260 vcpu_put(vcpu);
4261
4262 return 0;
4263}
4264
4265int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4266{
4267 vcpu_load(vcpu);
4268
5fdbf976
MT		 4269 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4270 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4271 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4272 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4273 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4274 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4275 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4276 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4277#ifdef CONFIG_X86_64
5fdbf976
MT		 4278 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4279 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4280 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4281 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4282 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4283 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4284 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4285 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4286#endif
4287
5fdbf976 4288 kvm_rip_write(vcpu, regs->rip);
91586a3b 4289 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4290
b4f14abd
JK		 4291 vcpu->arch.exception.pending = false;
4292
b6c7a5dc
HB		 4293 vcpu_put(vcpu);
4294
4295 return 0;
4296}
4297
3e6e0aab
GT		 4298void kvm_get_segment(struct kvm_vcpu *vcpu,
4299 struct kvm_segment *var, int seg)
b6c7a5dc 4300{
14af3f3c 4301 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4302}
4303
4304void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4305{
4306 struct kvm_segment cs;
4307
3e6e0aab 4308 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4309 *db = cs.db;
4310 *l = cs.l;
4311}
4312EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4313
4314int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4315 struct kvm_sregs *sregs)
4316{
4317 struct descriptor_table dt;
b6c7a5dc
HB		 4318
4319 vcpu_load(vcpu);
4320
3e6e0aab
GT		 4321 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4322 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4323 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4324 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4325 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4326 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4327
3e6e0aab
GT		 4328 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4329 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4330
4331 kvm_x86_ops->get_idt(vcpu, &dt);
4332 sregs->idt.limit = dt.limit;
4333 sregs->idt.base = dt.base;
4334 kvm_x86_ops->get_gdt(vcpu, &dt);
4335 sregs->gdt.limit = dt.limit;
4336 sregs->gdt.base = dt.base;
4337
ad312c7c
ZX		 4338 sregs->cr0 = vcpu->arch.cr0;
4339 sregs->cr2 = vcpu->arch.cr2;
4340 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4341 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4342 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 4343 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 4344 sregs->apic_base = kvm_get_apic_base(vcpu);
4345
923c61bb 4346 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4347
36752c9b 4348 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4349 set_bit(vcpu->arch.interrupt.nr,
4350 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4351
b6c7a5dc
HB		 4352 vcpu_put(vcpu);
4353
4354 return 0;
4355}
4356
62d9f0db
MT		 4357int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4358 struct kvm_mp_state *mp_state)
4359{
4360 vcpu_load(vcpu);
4361 mp_state->mp_state = vcpu->arch.mp_state;
4362 vcpu_put(vcpu);
4363 return 0;
4364}
4365
4366int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4367 struct kvm_mp_state *mp_state)
4368{
4369 vcpu_load(vcpu);
4370 vcpu->arch.mp_state = mp_state->mp_state;
4371 vcpu_put(vcpu);
4372 return 0;
4373}
4374
3e6e0aab 4375static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4376 struct kvm_segment *var, int seg)
4377{
14af3f3c 4378 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4379}
4380
37817f29
IE		 4381static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4382 struct kvm_segment *kvm_desct)
4383{
46a359e7
AM		 4384 kvm_desct->base = get_desc_base(seg_desc);
4385 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4386 if (seg_desc->g) {
4387 kvm_desct->limit <<= 12;
4388 kvm_desct->limit |= 0xfff;
4389 }
37817f29
IE		 4390 kvm_desct->selector = selector;
4391 kvm_desct->type = seg_desc->type;
4392 kvm_desct->present = seg_desc->p;
4393 kvm_desct->dpl = seg_desc->dpl;
4394 kvm_desct->db = seg_desc->d;
4395 kvm_desct->s = seg_desc->s;
4396 kvm_desct->l = seg_desc->l;
4397 kvm_desct->g = seg_desc->g;
4398 kvm_desct->avl = seg_desc->avl;
4399 if (!selector)
4400 kvm_desct->unusable = 1;
4401 else
4402 kvm_desct->unusable = 0;
4403 kvm_desct->padding = 0;
4404}
4405
b8222ad2
AS		 4406static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4407 u16 selector,
4408 struct descriptor_table *dtable)
37817f29
IE		 4409{
4410 if (selector & 1 << 2) {
4411 struct kvm_segment kvm_seg;
4412
3e6e0aab 4413 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4414
4415 if (kvm_seg.unusable)
4416 dtable->limit = 0;
4417 else
4418 dtable->limit = kvm_seg.limit;
4419 dtable->base = kvm_seg.base;
4420 }
4421 else
4422 kvm_x86_ops->get_gdt(vcpu, dtable);
4423}
4424
4425/* allowed just for 8 bytes segments */
4426static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4427 struct desc_struct *seg_desc)
4428{
4429 struct descriptor_table dtable;
4430 u16 index = selector >> 3;
4431
b8222ad2 4432 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4433
4434 if (dtable.limit < index * 8 + 7) {
4435 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4436 return 1;
4437 }
d9048d32 4438 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4439}
4440
4441/* allowed just for 8 bytes segments */
4442static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4443 struct desc_struct *seg_desc)
4444{
4445 struct descriptor_table dtable;
4446 u16 index = selector >> 3;
4447
b8222ad2 4448 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4449
4450 if (dtable.limit < index * 8 + 7)
4451 return 1;
d9048d32 4452 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4453}
4454
abb39119 4455static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
37817f29
IE		 4456 struct desc_struct *seg_desc)
4457{
46a359e7 4458 u32 base_addr = get_desc_base(seg_desc);
37817f29 4459
98899aa0 4460 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4461}
4462
37817f29
IE		 4463static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4464{
4465 struct kvm_segment kvm_seg;
4466
3e6e0aab 4467 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4468 return kvm_seg.selector;
4469}
4470
4471static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4472 u16 selector,
4473 struct kvm_segment *kvm_seg)
4474{
4475 struct desc_struct seg_desc;
4476
4477 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4478 return 1;
4479 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4480 return 0;
4481}
4482
2259e3a7 4483static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4484{
4485 struct kvm_segment segvar = {
4486 .base = selector << 4,
4487 .limit = 0xffff,
4488 .selector = selector,
4489 .type = 3,
4490 .present = 1,
4491 .dpl = 3,
4492 .db = 0,
4493 .s = 1,
4494 .l = 0,
4495 .g = 0,
4496 .avl = 0,
4497 .unusable = 0,
4498 };
4499 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4500 return 0;
4501}
4502
c0c7c04b
AL		 4503static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4504{
4505 return (seg != VCPU_SREG_LDTR) &&
4506 (seg != VCPU_SREG_TR) &&
91586a3b 4507 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4508}
4509
cb84b55f
MT		 4510static void kvm_check_segment_descriptor(struct kvm_vcpu *vcpu, int seg,
4511 u16 selector)
4512{
4513 /* NULL selector is not valid for CS and SS */
4514 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4515 if (!selector)
4516 kvm_queue_exception_e(vcpu, TS_VECTOR, selector >> 3);
4517}
4518
3e6e0aab
GT		 4519int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4520 int type_bits, int seg)
37817f29
IE		 4521{
4522 struct kvm_segment kvm_seg;
4523
c0c7c04b 4524 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
f4bbd9aa 4525 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4526 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4527 return 1;
cb84b55f
MT		 4528
4529 kvm_check_segment_descriptor(vcpu, seg, selector);
37817f29
IE		 4530 kvm_seg.type |= type_bits;
4531
4532 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4533 seg != VCPU_SREG_LDTR)
4534 if (!kvm_seg.s)
4535 kvm_seg.unusable = 1;
4536
3e6e0aab 4537 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4538 return 0;
4539}
4540
4541static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4542 struct tss_segment_32 *tss)
4543{
4544 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4545 tss->eip = kvm_rip_read(vcpu);
91586a3b 4546 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4547 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4548 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4549 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4550 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4551 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4552 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4553 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4554 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4555 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4556 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4557 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4558 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4559 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4560 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4561 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4562}
4563
4564static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4565 struct tss_segment_32 *tss)
4566{
4567 kvm_set_cr3(vcpu, tss->cr3);
4568
5fdbf976 4569 kvm_rip_write(vcpu, tss->eip);
91586a3b 4570 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4571
5fdbf976
MT		 4572 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4573 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4574 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4575 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4576 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4577 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4578 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4579 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4580
3e6e0aab 4581 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4582 return 1;
4583
3e6e0aab 4584 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4585 return 1;
4586
3e6e0aab 4587 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4588 return 1;
4589
3e6e0aab 4590 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4591 return 1;
4592
3e6e0aab 4593 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4594 return 1;
4595
3e6e0aab 4596 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4597 return 1;
4598
3e6e0aab 4599 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4600 return 1;
4601 return 0;
4602}
4603
4604static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4605 struct tss_segment_16 *tss)
4606{
5fdbf976 4607 tss->ip = kvm_rip_read(vcpu);
91586a3b 4608 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4609 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4610 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4611 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4612 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4613 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4614 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4615 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4616 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4617
4618 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4619 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4620 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4621 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4622 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4623}
4624
4625static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4626 struct tss_segment_16 *tss)
4627{
5fdbf976 4628 kvm_rip_write(vcpu, tss->ip);
91586a3b 4629 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4630 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4631 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4632 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4633 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4634 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4635 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4636 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4637 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4638
3e6e0aab 4639 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4640 return 1;
4641
3e6e0aab 4642 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4643 return 1;
4644
3e6e0aab 4645 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4646 return 1;
4647
3e6e0aab 4648 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4649 return 1;
4650
3e6e0aab 4651 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4652 return 1;
4653 return 0;
4654}
4655
8b2cf73c 4656static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4657 u16 old_tss_sel, u32 old_tss_base,
4658 struct desc_struct *nseg_desc)
37817f29
IE		 4659{
4660 struct tss_segment_16 tss_segment_16;
4661 int ret = 0;
4662
34198bf8
MT		 4663 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4664 sizeof tss_segment_16))
37817f29
IE		 4665 goto out;
4666
4667 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4668
34198bf8
MT		 4669 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4670 sizeof tss_segment_16))
37817f29 4671 goto out;
34198bf8
MT		 4672
4673 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4674 &tss_segment_16, sizeof tss_segment_16))
4675 goto out;
4676
b237ac37
GN		 4677 if (old_tss_sel != 0xffff) {
4678 tss_segment_16.prev_task_link = old_tss_sel;
4679
4680 if (kvm_write_guest(vcpu->kvm,
4681 get_tss_base_addr(vcpu, nseg_desc),
4682 &tss_segment_16.prev_task_link,
4683 sizeof tss_segment_16.prev_task_link))
4684 goto out;
4685 }
4686
37817f29
IE		 4687 if (load_state_from_tss16(vcpu, &tss_segment_16))
4688 goto out;
4689
4690 ret = 1;
4691out:
4692 return ret;
4693}
4694
8b2cf73c 4695static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4696 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4697 struct desc_struct *nseg_desc)
4698{
4699 struct tss_segment_32 tss_segment_32;
4700 int ret = 0;
4701
34198bf8
MT		 4702 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4703 sizeof tss_segment_32))
37817f29
IE		 4704 goto out;
4705
4706 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4707
34198bf8
MT		 4708 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4709 sizeof tss_segment_32))
4710 goto out;
4711
4712 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4713 &tss_segment_32, sizeof tss_segment_32))
37817f29 4714 goto out;
34198bf8 4715
b237ac37
GN		 4716 if (old_tss_sel != 0xffff) {
4717 tss_segment_32.prev_task_link = old_tss_sel;
4718
4719 if (kvm_write_guest(vcpu->kvm,
4720 get_tss_base_addr(vcpu, nseg_desc),
4721 &tss_segment_32.prev_task_link,
4722 sizeof tss_segment_32.prev_task_link))
4723 goto out;
4724 }
4725
37817f29
IE		 4726 if (load_state_from_tss32(vcpu, &tss_segment_32))
4727 goto out;
4728
4729 ret = 1;
4730out:
4731 return ret;
4732}
4733
4734int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4735{
4736 struct kvm_segment tr_seg;
4737 struct desc_struct cseg_desc;
4738 struct desc_struct nseg_desc;
4739 int ret = 0;
34198bf8
MT		 4740 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4741 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4742
34198bf8 4743 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4744
34198bf8
MT		 4745 /* FIXME: Handle errors. Failure to read either TSS or their
4746 * descriptors should generate a pagefault.
4747 */
37817f29
IE		 4748 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4749 goto out;
4750
34198bf8 4751 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4752 goto out;
4753
37817f29
IE		 4754 if (reason != TASK_SWITCH_IRET) {
4755 int cpl;
4756
4757 cpl = kvm_x86_ops->get_cpl(vcpu);
4758 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4759 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4760 return 1;
4761 }
4762 }
4763
46a359e7 4764 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4765 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4766 return 1;
4767 }
4768
4769 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4770 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4771 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4772 }
4773
4774 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 4775 u32 eflags = kvm_get_rflags(vcpu);
4776 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 4777 }
4778
b237ac37
GN		 4779 /* set back link to prev task only if NT bit is set in eflags
4780 note that old_tss_sel is not used afetr this point */
4781 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4782 old_tss_sel = 0xffff;
4783
37817f29 4784 if (nseg_desc.type & 8)
b237ac37
GN		 4785 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4786 old_tss_base, &nseg_desc);
37817f29 4787 else
b237ac37
GN		 4788 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4789 old_tss_base, &nseg_desc);
37817f29
IE		 4790
4791 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 4792 u32 eflags = kvm_get_rflags(vcpu);
4793 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 4794 }
4795
4796 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4797 nseg_desc.type |= (1 << 1);
37817f29
IE		 4798 save_guest_segment_descriptor(vcpu, tss_selector,
4799 &nseg_desc);
4800 }
4801
4802 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4803 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4804 tr_seg.type = 11;
3e6e0aab 4805 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4806out:
37817f29
IE		 4807 return ret;
4808}
4809EXPORT_SYMBOL_GPL(kvm_task_switch);
4810
b6c7a5dc
HB		 4811int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4812 struct kvm_sregs *sregs)
4813{
4814 int mmu_reset_needed = 0;
923c61bb 4815 int pending_vec, max_bits;
b6c7a5dc
HB		 4816 struct descriptor_table dt;
4817
4818 vcpu_load(vcpu);
4819
4820 dt.limit = sregs->idt.limit;
4821 dt.base = sregs->idt.base;
4822 kvm_x86_ops->set_idt(vcpu, &dt);
4823 dt.limit = sregs->gdt.limit;
4824 dt.base = sregs->gdt.base;
4825 kvm_x86_ops->set_gdt(vcpu, &dt);
4826
ad312c7c
ZX		 4827 vcpu->arch.cr2 = sregs->cr2;
4828 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4829 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4830
2d3ad1f4 4831 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4832
ad312c7c 4833 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4834 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4835 kvm_set_apic_base(vcpu, sregs->apic_base);
4836
ad312c7c 4837 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4838 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4839 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4840
fc78f519 4841 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4842 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4843 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4844 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4845 mmu_reset_needed = 1;
4846 }
b6c7a5dc
HB		 4847
4848 if (mmu_reset_needed)
4849 kvm_mmu_reset_context(vcpu);
4850
923c61bb
GN		 4851 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4852 pending_vec = find_first_bit(
4853 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4854 if (pending_vec < max_bits) {
66fd3f7f 4855 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4856 pr_debug("Set back pending irq %d\n", pending_vec);
4857 if (irqchip_in_kernel(vcpu->kvm))
4858 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4859 }
4860
3e6e0aab
GT		 4861 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4862 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4863 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4864 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4865 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4866 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4867
3e6e0aab
GT		 4868 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4869 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4870
5f0269f5
ME		 4871 update_cr8_intercept(vcpu);
4872
9c3e4aab 4873 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4874 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4875 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4876 !(vcpu->arch.cr0 & X86_CR0_PE))
4877 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4878
b6c7a5dc
HB		 4879 vcpu_put(vcpu);
4880
4881 return 0;
4882}
4883
d0bfb940
JK		 4884int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4885 struct kvm_guest_debug *dbg)
b6c7a5dc 4886{
355be0b9 4887 unsigned long rflags;
ae675ef0 4888 int i, r;
b6c7a5dc
HB		 4889
4890 vcpu_load(vcpu);
4891
4f926bf2
JK		 4892 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4893 r = -EBUSY;
4894 if (vcpu->arch.exception.pending)
4895 goto unlock_out;
4896 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4897 kvm_queue_exception(vcpu, DB_VECTOR);
4898 else
4899 kvm_queue_exception(vcpu, BP_VECTOR);
4900 }
4901
91586a3b
JK		 4902 /*
4903 * Read rflags as long as potentially injected trace flags are still
4904 * filtered out.
4905 */
4906 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4907
4908 vcpu->guest_debug = dbg->control;
4909 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4910 vcpu->guest_debug = 0;
4911
4912 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4913 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4914 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4915 vcpu->arch.switch_db_regs =
4916 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4917 } else {
4918 for (i = 0; i < KVM_NR_DB_REGS; i++)
4919 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4920 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4921 }
4922
94fe45da
JK		 4923 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4924 vcpu->arch.singlestep_cs =
4925 get_segment_selector(vcpu, VCPU_SREG_CS);
4926 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
4927 }
4928
91586a3b
JK		 4929 /*
4930 * Trigger an rflags update that will inject or remove the trace
4931 * flags.
4932 */
4933 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4934
355be0b9 4935 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 4936
4f926bf2 4937 r = 0;
d0bfb940 4938
4f926bf2 4939unlock_out:
b6c7a5dc
HB		 4940 vcpu_put(vcpu);
4941
4942 return r;
4943}
4944
d0752060
HB		 4945/*
4946 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4947 * we have asm/x86/processor.h
4948 */
4949struct fxsave {
4950 u16 cwd;
4951 u16 swd;
4952 u16 twd;
4953 u16 fop;
4954 u64 rip;
4955 u64 rdp;
4956 u32 mxcsr;
4957 u32 mxcsr_mask;
4958 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4959#ifdef CONFIG_X86_64
4960 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4961#else
4962 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4963#endif
4964};
4965
8b006791
ZX		 4966/*
4967 * Translate a guest virtual address to a guest physical address.
4968 */
4969int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4970 struct kvm_translation *tr)
4971{
4972 unsigned long vaddr = tr->linear_address;
4973 gpa_t gpa;
f656ce01 4974 int idx;
8b006791
ZX		 4975
4976 vcpu_load(vcpu);
f656ce01 4977 idx = srcu_read_lock(&vcpu->kvm->srcu);
ad312c7c 4978 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
f656ce01 4979 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 4980 tr->physical_address = gpa;
4981 tr->valid = gpa != UNMAPPED_GVA;
4982 tr->writeable = 1;
4983 tr->usermode = 0;
8b006791
ZX		 4984 vcpu_put(vcpu);
4985
4986 return 0;
4987}
4988
d0752060
HB		 4989int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4990{
ad312c7c 4991 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4992
4993 vcpu_load(vcpu);
4994
4995 memcpy(fpu->fpr, fxsave->st_space, 128);
4996 fpu->fcw = fxsave->cwd;
4997 fpu->fsw = fxsave->swd;
4998 fpu->ftwx = fxsave->twd;
4999 fpu->last_opcode = fxsave->fop;
5000 fpu->last_ip = fxsave->rip;
5001 fpu->last_dp = fxsave->rdp;
5002 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5003
5004 vcpu_put(vcpu);
5005
5006 return 0;
5007}
5008
5009int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5010{
ad312c7c 5011 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5012
5013 vcpu_load(vcpu);
5014
5015 memcpy(fxsave->st_space, fpu->fpr, 128);
5016 fxsave->cwd = fpu->fcw;
5017 fxsave->swd = fpu->fsw;
5018 fxsave->twd = fpu->ftwx;
5019 fxsave->fop = fpu->last_opcode;
5020 fxsave->rip = fpu->last_ip;
5021 fxsave->rdp = fpu->last_dp;
5022 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5023
5024 vcpu_put(vcpu);
5025
5026 return 0;
5027}
5028
5029void fx_init(struct kvm_vcpu *vcpu)
5030{
5031 unsigned after_mxcsr_mask;
5032
bc1a34f1
AA		 5033 /*
5034 * Touch the fpu the first time in non atomic context as if
5035 * this is the first fpu instruction the exception handler
5036 * will fire before the instruction returns and it'll have to
5037 * allocate ram with GFP_KERNEL.
5038 */
5039 if (!used_math())
d6e88aec 5040 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5041
d0752060
HB		 5042 /* Initialize guest FPU by resetting ours and saving into guest's */
5043 preempt_disable();
d6e88aec
AK		 5044 kvm_fx_save(&vcpu->arch.host_fx_image);
5045 kvm_fx_finit();
5046 kvm_fx_save(&vcpu->arch.guest_fx_image);
5047 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5048 preempt_enable();
5049
ad312c7c 5050 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5051 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5052 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5053 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5054 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5055}
5056EXPORT_SYMBOL_GPL(fx_init);
5057
5058void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5059{
5060 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
5061 return;
5062
5063 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5064 kvm_fx_save(&vcpu->arch.host_fx_image);
5065 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 5066}
5067EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
5068
5069void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5070{
5071 if (!vcpu->guest_fpu_loaded)
5072 return;
5073
5074 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5075 kvm_fx_save(&vcpu->arch.guest_fx_image);
5076 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5077 ++vcpu->stat.fpu_reload;
d0752060
HB		 5078}
5079EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 5080
5081void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5082{
7f1ea208
JR		 5083 if (vcpu->arch.time_page) {
5084 kvm_release_page_dirty(vcpu->arch.time_page);
5085 vcpu->arch.time_page = NULL;
5086 }
5087
e9b11c17
ZX		 5088 kvm_x86_ops->vcpu_free(vcpu);
5089}
5090
5091struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5092 unsigned int id)
5093{
26e5215f
AK		 5094 return kvm_x86_ops->vcpu_create(kvm, id);
5095}
e9b11c17 5096
26e5215f
AK		 5097int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5098{
5099 int r;
e9b11c17
ZX		 5100
5101 /* We do fxsave: this must be aligned. */
ad312c7c 5102 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5103
0bed3b56 5104 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5105 vcpu_load(vcpu);
5106 r = kvm_arch_vcpu_reset(vcpu);
5107 if (r == 0)
5108 r = kvm_mmu_setup(vcpu);
5109 vcpu_put(vcpu);
5110 if (r < 0)
5111 goto free_vcpu;
5112
26e5215f 5113 return 0;
e9b11c17
ZX		 5114free_vcpu:
5115 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5116 return r;
e9b11c17
ZX		 5117}
5118
d40ccc62 5119void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5120{
5121 vcpu_load(vcpu);
5122 kvm_mmu_unload(vcpu);
5123 vcpu_put(vcpu);
5124
5125 kvm_x86_ops->vcpu_free(vcpu);
5126}
5127
5128int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5129{
448fa4a9
JK		 5130 vcpu->arch.nmi_pending = false;
5131 vcpu->arch.nmi_injected = false;
5132
42dbaa5a
JK		 5133 vcpu->arch.switch_db_regs = 0;
5134 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5135 vcpu->arch.dr6 = DR6_FIXED_1;
5136 vcpu->arch.dr7 = DR7_FIXED_1;
5137
e9b11c17
ZX		 5138 return kvm_x86_ops->vcpu_reset(vcpu);
5139}
5140
10474ae8 5141int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5142{
0cca7907
ZA		 5143 /*
5144 * Since this may be called from a hotplug notifcation,
5145 * we can't get the CPU frequency directly.
5146 */
5147 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5148 int cpu = raw_smp_processor_id();
5149 per_cpu(cpu_tsc_khz, cpu) = 0;
5150 }
18863bdd
AK		 5151
5152 kvm_shared_msr_cpu_online();
5153
10474ae8 5154 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5155}
5156
5157void kvm_arch_hardware_disable(void *garbage)
5158{
5159 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5160 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5161}
5162
5163int kvm_arch_hardware_setup(void)
5164{
5165 return kvm_x86_ops->hardware_setup();
5166}
5167
5168void kvm_arch_hardware_unsetup(void)
5169{
5170 kvm_x86_ops->hardware_unsetup();
5171}
5172
5173void kvm_arch_check_processor_compat(void *rtn)
5174{
5175 kvm_x86_ops->check_processor_compatibility(rtn);
5176}
5177
5178int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5179{
5180 struct page *page;
5181 struct kvm *kvm;
5182 int r;
5183
5184 BUG_ON(vcpu->kvm == NULL);
5185 kvm = vcpu->kvm;
5186
ad312c7c 5187 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5188 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5189 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5190 else
a4535290 5191 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5192
5193 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5194 if (!page) {
5195 r = -ENOMEM;
5196 goto fail;
5197 }
ad312c7c 5198 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5199
5200 r = kvm_mmu_create(vcpu);
5201 if (r < 0)
5202 goto fail_free_pio_data;
5203
5204 if (irqchip_in_kernel(kvm)) {
5205 r = kvm_create_lapic(vcpu);
5206 if (r < 0)
5207 goto fail_mmu_destroy;
5208 }
5209
890ca9ae
HY		 5210 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5211 GFP_KERNEL);
5212 if (!vcpu->arch.mce_banks) {
5213 r = -ENOMEM;
443c39bc 5214 goto fail_free_lapic;
890ca9ae
HY		 5215 }
5216 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5217
e9b11c17 5218 return 0;
443c39bc
WY		 5219fail_free_lapic:
5220 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5221fail_mmu_destroy:
5222 kvm_mmu_destroy(vcpu);
5223fail_free_pio_data:
ad312c7c 5224 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5225fail:
5226 return r;
5227}
5228
5229void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5230{
f656ce01
MT		 5231 int idx;
5232
36cb93fd 5233 kfree(vcpu->arch.mce_banks);
e9b11c17 5234 kvm_free_lapic(vcpu);
f656ce01 5235 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5236 kvm_mmu_destroy(vcpu);
f656ce01 5237 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5238 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5239}
d19a9cd2
ZX		 5240
5241struct kvm *kvm_arch_create_vm(void)
5242{
5243 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5244
5245 if (!kvm)
5246 return ERR_PTR(-ENOMEM);
5247
fef9cce0
MT		 5248 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5249 if (!kvm->arch.aliases) {
5250 kfree(kvm);
5251 return ERR_PTR(-ENOMEM);
5252 }
5253
f05e70ac 5254 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5255 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5256
5550af4d
SY		 5257 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5258 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5259
53f658b3
MT		 5260 rdtscll(kvm->arch.vm_init_tsc);
5261
d19a9cd2
ZX		 5262 return kvm;
5263}
5264
5265static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5266{
5267 vcpu_load(vcpu);
5268 kvm_mmu_unload(vcpu);
5269 vcpu_put(vcpu);
5270}
5271
5272static void kvm_free_vcpus(struct kvm *kvm)
5273{
5274 unsigned int i;
988a2cae 5275 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5276
5277 /*
5278 * Unpin any mmu pages first.
5279 */
988a2cae
GN		 5280 kvm_for_each_vcpu(i, vcpu, kvm)
5281 kvm_unload_vcpu_mmu(vcpu);
5282 kvm_for_each_vcpu(i, vcpu, kvm)
5283 kvm_arch_vcpu_free(vcpu);
5284
5285 mutex_lock(&kvm->lock);
5286 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5287 kvm->vcpus[i] = NULL;
d19a9cd2 5288
988a2cae
GN		 5289 atomic_set(&kvm->online_vcpus, 0);
5290 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5291}
5292
ad8ba2cd
SY		 5293void kvm_arch_sync_events(struct kvm *kvm)
5294{
ba4cef31 5295 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5296}
5297
d19a9cd2
ZX		 5298void kvm_arch_destroy_vm(struct kvm *kvm)
5299{
6eb55818 5300 kvm_iommu_unmap_guest(kvm);
7837699f 5301 kvm_free_pit(kvm);
d7deeeb0
ZX		 5302 kfree(kvm->arch.vpic);
5303 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5304 kvm_free_vcpus(kvm);
5305 kvm_free_physmem(kvm);
3d45830c
AK		 5306 if (kvm->arch.apic_access_page)
5307 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5308 if (kvm->arch.ept_identity_pagetable)
5309 put_page(kvm->arch.ept_identity_pagetable);
fef9cce0 5310 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5311 kfree(kvm);
5312}
0de10343 5313
f7784b8e
MT		 5314int kvm_arch_prepare_memory_region(struct kvm *kvm,
5315 struct kvm_memory_slot *memslot,
0de10343 5316 struct kvm_memory_slot old,
f7784b8e 5317 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5318 int user_alloc)
5319{
f7784b8e 5320 int npages = memslot->npages;
0de10343
ZX		 5321
5322 /*To keep backward compatibility with older userspace,
5323 *x86 needs to hanlde !user_alloc case.
5324 */
5325 if (!user_alloc) {
5326 if (npages && !old.rmap) {
604b38ac
AA		 5327 unsigned long userspace_addr;
5328
72dc67a6 5329 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5330 userspace_addr = do_mmap(NULL, 0,
5331 npages * PAGE_SIZE,
5332 PROT_READ | PROT_WRITE,
acee3c04 5333 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5334 0);
72dc67a6 5335 up_write(&current->mm->mmap_sem);
0de10343 5336
604b38ac
AA		 5337 if (IS_ERR((void *)userspace_addr))
5338 return PTR_ERR((void *)userspace_addr);
5339
604b38ac 5340 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5341 }
5342 }
5343
f7784b8e
MT		 5344
5345 return 0;
5346}
5347
5348void kvm_arch_commit_memory_region(struct kvm *kvm,
5349 struct kvm_userspace_memory_region *mem,
5350 struct kvm_memory_slot old,
5351 int user_alloc)
5352{
5353
5354 int npages = mem->memory_size >> PAGE_SHIFT;
5355
5356 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5357 int ret;
5358
5359 down_write(&current->mm->mmap_sem);
5360 ret = do_munmap(current->mm, old.userspace_addr,
5361 old.npages * PAGE_SIZE);
5362 up_write(&current->mm->mmap_sem);
5363 if (ret < 0)
5364 printk(KERN_WARNING
5365 "kvm_vm_ioctl_set_memory_region: "
5366 "failed to munmap memory\n");
5367 }
5368
7c8a83b7 5369 spin_lock(&kvm->mmu_lock);
f05e70ac 5370 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5371 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5372 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5373 }
5374
5375 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5376 spin_unlock(&kvm->mmu_lock);
0de10343 5377}
1d737c8a 5378
34d4cb8f
MT		 5379void kvm_arch_flush_shadow(struct kvm *kvm)
5380{
5381 kvm_mmu_zap_all(kvm);
8986ecc0 5382 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5383}
5384
1d737c8a
ZX		 5385int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5386{
a4535290 5387 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5388 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5389 || vcpu->arch.nmi_pending ||
5390 (kvm_arch_interrupt_allowed(vcpu) &&
5391 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5392}
5736199a 5393
5736199a
ZX		 5394void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5395{
32f88400
MT		 5396 int me;
5397 int cpu = vcpu->cpu;
5736199a
ZX		 5398
5399 if (waitqueue_active(&vcpu->wq)) {
5400 wake_up_interruptible(&vcpu->wq);
5401 ++vcpu->stat.halt_wakeup;
5402 }
32f88400
MT		 5403
5404 me = get_cpu();
5405 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5406 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5407 smp_send_reschedule(cpu);
e9571ed5 5408 put_cpu();
5736199a 5409}
78646121
GN		 5410
5411int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5412{
5413 return kvm_x86_ops->interrupt_allowed(vcpu);
5414}
229456fc 5415
94fe45da
JK		 5416unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5417{
5418 unsigned long rflags;
5419
5420 rflags = kvm_x86_ops->get_rflags(vcpu);
5421 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5422 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5423 return rflags;
5424}
5425EXPORT_SYMBOL_GPL(kvm_get_rflags);
5426
5427void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5428{
5429 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5430 vcpu->arch.singlestep_cs ==
5431 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5432 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5433 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5434 kvm_x86_ops->set_rflags(vcpu, rflags);
5435}
5436EXPORT_SYMBOL_GPL(kvm_set_rflags);
5437
229456fc
MT		 5438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5441EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5442EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5443EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5444EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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