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KVM: x86: Call mask notifiers from pic
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
043405e1 58
313a3dc7 59#define MAX_IO_MSRS 256
a03490ed
CO		 60#define CR0_RESERVED_BITS \
61 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
62 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
63 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
64#define CR4_RESERVED_BITS \
65 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
66 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
67 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 68 | X86_CR4_OSXSAVE \
a03490ed
CO		 69 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
70
71#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 72
73#define KVM_MAX_MCE_BANKS 32
74#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
75
50a37eb4
JR		 76/* EFER defaults:
77 * - enable syscall per default because its emulated by KVM
78 * - enable LME and LMA per default on 64 bit KVM
79 */
80#ifdef CONFIG_X86_64
81static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
82#else
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 90static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
91 struct kvm_cpuid_entry2 __user *entries);
92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
ed85c068
AP		 96int ignore_msrs = 0;
97module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
156static inline u32 bit(int bitno)
157{
158 return 1 << (bitno & 31);
159}
160
18863bdd
AK		 161static void kvm_on_user_return(struct user_return_notifier *urn)
162{
163 unsigned slot;
18863bdd
AK		 164 struct kvm_shared_msrs *locals
165 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 166 struct kvm_shared_msr_values *values;
18863bdd
AK		 167
168 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 169 values = &locals->values[slot];
170 if (values->host != values->curr) {
171 wrmsrl(shared_msrs_global.msrs[slot], values->host);
172 values->curr = values->host;
18863bdd
AK		 173 }
174 }
175 locals->registered = false;
176 user_return_notifier_unregister(urn);
177}
178
2bf78fa7 179static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 180{
2bf78fa7 181 struct kvm_shared_msrs *smsr;
18863bdd
AK		 182 u64 value;
183
2bf78fa7
SY		 184 smsr = &__get_cpu_var(shared_msrs);
185 /* only read, and nobody should modify it at this time,
186 * so don't need lock */
187 if (slot >= shared_msrs_global.nr) {
188 printk(KERN_ERR "kvm: invalid MSR slot!");
189 return;
190 }
191 rdmsrl_safe(msr, &value);
192 smsr->values[slot].host = value;
193 smsr->values[slot].curr = value;
194}
195
196void kvm_define_shared_msr(unsigned slot, u32 msr)
197{
18863bdd
AK		 198 if (slot >= shared_msrs_global.nr)
199 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 200 shared_msrs_global.msrs[slot] = msr;
201 /* we need ensured the shared_msr_global have been updated */
202 smp_wmb();
18863bdd
AK		 203}
204EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
205
206static void kvm_shared_msr_cpu_online(void)
207{
208 unsigned i;
18863bdd
AK		 209
210 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 211 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 212}
213
d5696725 214void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 215{
216 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
217
2bf78fa7 218 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 219 return;
2bf78fa7
SY		 220 smsr->values[slot].curr = value;
221 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 222 if (!smsr->registered) {
223 smsr->urn.on_user_return = kvm_on_user_return;
224 user_return_notifier_register(&smsr->urn);
225 smsr->registered = true;
226 }
227}
228EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
229
3548bab5
AK		 230static void drop_user_return_notifiers(void *ignore)
231{
232 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
233
234 if (smsr->registered)
235 kvm_on_user_return(&smsr->urn);
236}
237
6866b83e
CO		 238u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
239{
240 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 241 return vcpu->arch.apic_base;
6866b83e 242 else
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e
CO		 244}
245EXPORT_SYMBOL_GPL(kvm_get_apic_base);
246
247void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
248{
249 /* TODO: reserve bits check */
250 if (irqchip_in_kernel(vcpu->kvm))
251 kvm_lapic_set_base(vcpu, data);
252 else
ad312c7c 253 vcpu->arch.apic_base = data;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_set_apic_base);
256
3fd28fce
ED		 257#define EXCPT_BENIGN 0
258#define EXCPT_CONTRIBUTORY 1
259#define EXCPT_PF 2
260
261static int exception_class(int vector)
262{
263 switch (vector) {
264 case PF_VECTOR:
265 return EXCPT_PF;
266 case DE_VECTOR:
267 case TS_VECTOR:
268 case NP_VECTOR:
269 case SS_VECTOR:
270 case GP_VECTOR:
271 return EXCPT_CONTRIBUTORY;
272 default:
273 break;
274 }
275 return EXCPT_BENIGN;
276}
277
278static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 279 unsigned nr, bool has_error, u32 error_code,
280 bool reinject)
3fd28fce
ED		 281{
282 u32 prev_nr;
283 int class1, class2;
284
285 if (!vcpu->arch.exception.pending) {
286 queue:
287 vcpu->arch.exception.pending = true;
288 vcpu->arch.exception.has_error_code = has_error;
289 vcpu->arch.exception.nr = nr;
290 vcpu->arch.exception.error_code = error_code;
3f0fd292 291 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 292 return;
293 }
294
295 /* to check exception */
296 prev_nr = vcpu->arch.exception.nr;
297 if (prev_nr == DF_VECTOR) {
298 /* triple fault -> shutdown */
a8eeb04a 299 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 300 return;
301 }
302 class1 = exception_class(prev_nr);
303 class2 = exception_class(nr);
304 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
305 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
306 /* generate double fault per SDM Table 5-5 */
307 vcpu->arch.exception.pending = true;
308 vcpu->arch.exception.has_error_code = true;
309 vcpu->arch.exception.nr = DF_VECTOR;
310 vcpu->arch.exception.error_code = 0;
311 } else
312 /* replace previous exception with a new one in a hope
313 that instruction re-execution will regenerate lost
314 exception */
315 goto queue;
316}
317
298101da
AK		 318void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
319{
ce7ddec4 320 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 321}
322EXPORT_SYMBOL_GPL(kvm_queue_exception);
323
ce7ddec4
JR		 324void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
326 kvm_multiple_exception(vcpu, nr, false, 0, true);
327}
328EXPORT_SYMBOL_GPL(kvm_requeue_exception);
329
c3c91fee
AK		 330void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
331 u32 error_code)
332{
333 ++vcpu->stat.pf_guest;
ad312c7c 334 vcpu->arch.cr2 = addr;
c3c91fee
AK		 335 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
336}
337
3419ffc8
SY		 338void kvm_inject_nmi(struct kvm_vcpu *vcpu)
339{
340 vcpu->arch.nmi_pending = 1;
341}
342EXPORT_SYMBOL_GPL(kvm_inject_nmi);
343
298101da
AK		 344void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
345{
ce7ddec4 346 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 347}
348EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
349
ce7ddec4
JR		 350void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
351{
352 kvm_multiple_exception(vcpu, nr, true, error_code, true);
353}
354EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
355
0a79b009
AK		 356/*
357 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
358 * a #GP and return false.
359 */
360bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 361{
0a79b009
AK		 362 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
363 return true;
364 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
365 return false;
298101da 366}
0a79b009 367EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 368
a03490ed
CO		 369/*
370 * Load the pae pdptrs. Return true is they are all valid.
371 */
372int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
373{
374 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
375 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
376 int i;
377 int ret;
ad312c7c 378 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 379
a03490ed
CO		 380 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
381 offset * sizeof(u64), sizeof(pdpte));
382 if (ret < 0) {
383 ret = 0;
384 goto out;
385 }
386 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 387 if (is_present_gpte(pdpte[i]) &&
20c466b5 388 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 389 ret = 0;
390 goto out;
391 }
392 }
393 ret = 1;
394
ad312c7c 395 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 396 __set_bit(VCPU_EXREG_PDPTR,
397 (unsigned long *)&vcpu->arch.regs_avail);
398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 400out:
a03490ed
CO		 401
402 return ret;
403}
cc4b6871 404EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 405
d835dfec
AK		 406static bool pdptrs_changed(struct kvm_vcpu *vcpu)
407{
ad312c7c 408 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 409 bool changed = true;
410 int r;
411
412 if (is_long_mode(vcpu) || !is_pae(vcpu))
413 return false;
414
6de4f3ad
AK		 415 if (!test_bit(VCPU_EXREG_PDPTR,
416 (unsigned long *)&vcpu->arch.regs_avail))
417 return true;
418
ad312c7c 419 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 420 if (r < 0)
421 goto out;
ad312c7c 422 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 423out:
d835dfec
AK		 424
425 return changed;
426}
427
49a9b07e 428int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 429{
aad82703
SY		 430 unsigned long old_cr0 = kvm_read_cr0(vcpu);
431 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
432 X86_CR0_CD | X86_CR0_NW;
433
f9a48e6a
AK		 434 cr0 |= X86_CR0_ET;
435
ab344828 436#ifdef CONFIG_X86_64
0f12244f
GN		 437 if (cr0 & 0xffffffff00000000UL)
438 return 1;
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 442
0f12244f
GN		 443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
444 return 1;
a03490ed 445
0f12244f
GN		 446 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
447 return 1;
a03490ed
CO		 448
449 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
450#ifdef CONFIG_X86_64
f6801dff 451 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 452 int cs_db, cs_l;
453
0f12244f
GN		 454 if (!is_pae(vcpu))
455 return 1;
a03490ed 456 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 457 if (cs_l)
458 return 1;
a03490ed
CO		 459 } else
460#endif
0f12244f
GN		 461 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
462 return 1;
a03490ed
CO		 463 }
464
465 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 466
aad82703
SY		 467 if ((cr0 ^ old_cr0) & update_bits)
468 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 469 return 0;
470}
2d3ad1f4 471EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 472
2d3ad1f4 473void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 474{
49a9b07e 475 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 476}
2d3ad1f4 477EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 478
2acf923e
DC		 479int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
480{
481 u64 xcr0;
482
483 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
484 if (index != XCR_XFEATURE_ENABLED_MASK)
485 return 1;
486 xcr0 = xcr;
487 if (kvm_x86_ops->get_cpl(vcpu) != 0)
488 return 1;
489 if (!(xcr0 & XSTATE_FP))
490 return 1;
491 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
492 return 1;
493 if (xcr0 & ~host_xcr0)
494 return 1;
495 vcpu->arch.xcr0 = xcr0;
496 vcpu->guest_xcr0_loaded = 0;
497 return 0;
498}
499
500int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
501{
502 if (__kvm_set_xcr(vcpu, index, xcr)) {
503 kvm_inject_gp(vcpu, 0);
504 return 1;
505 }
506 return 0;
507}
508EXPORT_SYMBOL_GPL(kvm_set_xcr);
509
510static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
511{
512 struct kvm_cpuid_entry2 *best;
513
514 best = kvm_find_cpuid_entry(vcpu, 1, 0);
515 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
516}
517
518static void update_cpuid(struct kvm_vcpu *vcpu)
519{
520 struct kvm_cpuid_entry2 *best;
521
522 best = kvm_find_cpuid_entry(vcpu, 1, 0);
523 if (!best)
524 return;
525
526 /* Update OSXSAVE bit */
527 if (cpu_has_xsave && best->function == 0x1) {
528 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
529 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
530 best->ecx |= bit(X86_FEATURE_OSXSAVE);
531 }
532}
533
a83b29c6 534int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 535{
fc78f519 536 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 537 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
538
0f12244f
GN		 539 if (cr4 & CR4_RESERVED_BITS)
540 return 1;
a03490ed 541
2acf923e
DC		 542 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
543 return 1;
544
a03490ed 545 if (is_long_mode(vcpu)) {
0f12244f
GN		 546 if (!(cr4 & X86_CR4_PAE))
547 return 1;
a2edf57f
AK		 548 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
549 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 550 && !load_pdptrs(vcpu, vcpu->arch.cr3))
551 return 1;
552
553 if (cr4 & X86_CR4_VMXE)
554 return 1;
a03490ed 555
a03490ed 556 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 557
aad82703
SY		 558 if ((cr4 ^ old_cr4) & pdptr_bits)
559 kvm_mmu_reset_context(vcpu);
0f12244f 560
2acf923e
DC		 561 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
562 update_cpuid(vcpu);
563
0f12244f
GN		 564 return 0;
565}
2d3ad1f4 566EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 567
2390218b 568int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 569{
ad312c7c 570 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 571 kvm_mmu_sync_roots(vcpu);
d835dfec 572 kvm_mmu_flush_tlb(vcpu);
0f12244f 573 return 0;
d835dfec
AK		 574 }
575
a03490ed 576 if (is_long_mode(vcpu)) {
0f12244f
GN		 577 if (cr3 & CR3_L_MODE_RESERVED_BITS)
578 return 1;
a03490ed
CO		 579 } else {
580 if (is_pae(vcpu)) {
0f12244f
GN		 581 if (cr3 & CR3_PAE_RESERVED_BITS)
582 return 1;
583 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
584 return 1;
a03490ed
CO		 585 }
586 /*
587 * We don't check reserved bits in nonpae mode, because
588 * this isn't enforced, and VMware depends on this.
589 */
590 }
591
a03490ed
CO		 592 /*
593 * Does the new cr3 value map to physical memory? (Note, we
594 * catch an invalid cr3 even in real-mode, because it would
595 * cause trouble later on when we turn on paging anyway.)
596 *
597 * A real CPU would silently accept an invalid cr3 and would
598 * attempt to use it - with largely undefined (and often hard
599 * to debug) behavior on the guest side.
600 */
601 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 602 return 1;
603 vcpu->arch.cr3 = cr3;
604 vcpu->arch.mmu.new_cr3(vcpu);
605 return 0;
606}
2d3ad1f4 607EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 608
0f12244f 609int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 610{
0f12244f
GN		 611 if (cr8 & CR8_RESERVED_BITS)
612 return 1;
a03490ed
CO		 613 if (irqchip_in_kernel(vcpu->kvm))
614 kvm_lapic_set_tpr(vcpu, cr8);
615 else
ad312c7c 616 vcpu->arch.cr8 = cr8;
0f12244f
GN		 617 return 0;
618}
619
620void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
621{
622 if (__kvm_set_cr8(vcpu, cr8))
623 kvm_inject_gp(vcpu, 0);
a03490ed 624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 626
2d3ad1f4 627unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 628{
629 if (irqchip_in_kernel(vcpu->kvm))
630 return kvm_lapic_get_cr8(vcpu);
631 else
ad312c7c 632 return vcpu->arch.cr8;
a03490ed 633}
2d3ad1f4 634EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 635
338dbc97 636static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 637{
638 switch (dr) {
639 case 0 ... 3:
640 vcpu->arch.db[dr] = val;
641 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
642 vcpu->arch.eff_db[dr] = val;
643 break;
644 case 4:
338dbc97
GN		 645 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
646 return 1; /* #UD */
020df079
GN		 647 /* fall through */
648 case 6:
338dbc97
GN		 649 if (val & 0xffffffff00000000ULL)
650 return -1; /* #GP */
020df079
GN		 651 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
652 break;
653 case 5:
338dbc97
GN		 654 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
655 return 1; /* #UD */
020df079
GN		 656 /* fall through */
657 default: /* 7 */
338dbc97
GN		 658 if (val & 0xffffffff00000000ULL)
659 return -1; /* #GP */
020df079
GN		 660 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
661 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
662 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
663 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
664 }
665 break;
666 }
667
668 return 0;
669}
338dbc97
GN		 670
671int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
672{
673 int res;
674
675 res = __kvm_set_dr(vcpu, dr, val);
676 if (res > 0)
677 kvm_queue_exception(vcpu, UD_VECTOR);
678 else if (res < 0)
679 kvm_inject_gp(vcpu, 0);
680
681 return res;
682}
020df079
GN		 683EXPORT_SYMBOL_GPL(kvm_set_dr);
684
338dbc97 685static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 686{
687 switch (dr) {
688 case 0 ... 3:
689 *val = vcpu->arch.db[dr];
690 break;
691 case 4:
338dbc97 692 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 693 return 1;
020df079
GN		 694 /* fall through */
695 case 6:
696 *val = vcpu->arch.dr6;
697 break;
698 case 5:
338dbc97 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 700 return 1;
020df079
GN		 701 /* fall through */
702 default: /* 7 */
703 *val = vcpu->arch.dr7;
704 break;
705 }
706
707 return 0;
708}
338dbc97
GN		 709
710int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
711{
712 if (_kvm_get_dr(vcpu, dr, val)) {
713 kvm_queue_exception(vcpu, UD_VECTOR);
714 return 1;
715 }
716 return 0;
717}
020df079
GN		 718EXPORT_SYMBOL_GPL(kvm_get_dr);
719
043405e1
CO		 720/*
721 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
722 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
723 *
724 * This list is modified at module load time to reflect the
e3267cbb
GC		 725 * capabilities of the host cpu. This capabilities test skips MSRs that are
726 * kvm-specific. Those are put in the beginning of the list.
043405e1 727 */
e3267cbb 728
11c6bffa 729#define KVM_SAVE_MSRS_BEGIN 7
043405e1 730static u32 msrs_to_save[] = {
e3267cbb 731 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 732 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 733 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 734 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 735 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
736 MSR_K6_STAR,
737#ifdef CONFIG_X86_64
738 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
739#endif
e3267cbb 740 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 741};
742
743static unsigned num_msrs_to_save;
744
745static u32 emulated_msrs[] = {
746 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 747 MSR_IA32_MCG_STATUS,
748 MSR_IA32_MCG_CTL,
043405e1
CO		 749};
750
b69e8cae 751static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 752{
aad82703
SY		 753 u64 old_efer = vcpu->arch.efer;
754
b69e8cae
RJ		 755 if (efer & efer_reserved_bits)
756 return 1;
15c4a640
CO		 757
758 if (is_paging(vcpu)
b69e8cae
RJ		 759 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
760 return 1;
15c4a640 761
1b2fd70c
AG		 762 if (efer & EFER_FFXSR) {
763 struct kvm_cpuid_entry2 *feat;
764
765 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 766 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
767 return 1;
1b2fd70c
AG		 768 }
769
d8017474
AG		 770 if (efer & EFER_SVME) {
771 struct kvm_cpuid_entry2 *feat;
772
773 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 774 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
775 return 1;
d8017474
AG		 776 }
777
15c4a640 778 efer &= ~EFER_LMA;
f6801dff 779 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 780
a3d204e2
SY		 781 kvm_x86_ops->set_efer(vcpu, efer);
782
9645bb56
AK		 783 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
784 kvm_mmu_reset_context(vcpu);
b69e8cae 785
aad82703
SY		 786 /* Update reserved bits */
787 if ((efer ^ old_efer) & EFER_NX)
788 kvm_mmu_reset_context(vcpu);
789
b69e8cae 790 return 0;
15c4a640
CO		 791}
792
f2b4b7dd
JR		 793void kvm_enable_efer_bits(u64 mask)
794{
795 efer_reserved_bits &= ~mask;
796}
797EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
798
799
15c4a640
CO		 800/*
801 * Writes msr value into into the appropriate "register".
802 * Returns 0 on success, non-0 otherwise.
803 * Assumes vcpu_load() was already called.
804 */
805int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
806{
807 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
808}
809
313a3dc7
CO		 810/*
811 * Adapt set_msr() to msr_io()'s calling convention
812 */
813static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
814{
815 return kvm_set_msr(vcpu, index, *data);
816}
817
18068523
GOC		 818static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
819{
9ed3c444
AK		 820 int version;
821 int r;
50d0a0f9 822 struct pvclock_wall_clock wc;
923de3cf 823 struct timespec boot;
18068523
GOC		 824
825 if (!wall_clock)
826 return;
827
9ed3c444
AK		 828 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
829 if (r)
830 return;
831
832 if (version & 1)
833 ++version; /* first time write, random junk */
834
835 ++version;
18068523 836
18068523
GOC		 837 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
838
50d0a0f9
GH		 839 /*
840 * The guest calculates current wall clock time by adding
841 * system time (updated by kvm_write_guest_time below) to the
842 * wall clock specified here. guest system time equals host
843 * system time for us, thus we must fill in host boot time here.
844 */
923de3cf 845 getboottime(&boot);
50d0a0f9
GH		 846
847 wc.sec = boot.tv_sec;
848 wc.nsec = boot.tv_nsec;
849 wc.version = version;
18068523
GOC		 850
851 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
852
853 version++;
854 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 855}
856
50d0a0f9
GH		 857static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
858{
859 uint32_t quotient, remainder;
860
861 /* Don't try to replace with do_div(), this one calculates
862 * "(dividend << 32) / divisor" */
863 __asm__ ( "divl %4"
864 : "=a" (quotient), "=d" (remainder)
865 : "0" (0), "1" (dividend), "r" (divisor) );
866 return quotient;
867}
868
869static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
870{
871 uint64_t nsecs = 1000000000LL;
872 int32_t shift = 0;
873 uint64_t tps64;
874 uint32_t tps32;
875
876 tps64 = tsc_khz * 1000LL;
877 while (tps64 > nsecs*2) {
878 tps64 >>= 1;
879 shift--;
880 }
881
882 tps32 = (uint32_t)tps64;
883 while (tps32 <= (uint32_t)nsecs) {
884 tps32 <<= 1;
885 shift++;
886 }
887
888 hv_clock->tsc_shift = shift;
889 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
890
891 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 892 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 893 hv_clock->tsc_to_system_mul);
894}
895
c8076604
GH		 896static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
897
18068523
GOC		 898static void kvm_write_guest_time(struct kvm_vcpu *v)
899{
900 struct timespec ts;
901 unsigned long flags;
902 struct kvm_vcpu_arch *vcpu = &v->arch;
903 void *shared_kaddr;
463656c0 904 unsigned long this_tsc_khz;
18068523
GOC		 905
906 if ((!vcpu->time_page))
907 return;
908
463656c0
AK		 909 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
910 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
911 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
912 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 913 }
463656c0 914 put_cpu_var(cpu_tsc_khz);
50d0a0f9 915
18068523
GOC		 916 /* Keep irq disabled to prevent changes to the clock */
917 local_irq_save(flags);
af24a4e4 918 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 919 ktime_get_ts(&ts);
923de3cf 920 monotonic_to_bootbased(&ts);
18068523
GOC		 921 local_irq_restore(flags);
922
923 /* With all the info we got, fill in the values */
924
925 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 926 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
927
371bcf64
GC		 928 vcpu->hv_clock.flags = 0;
929
18068523
GOC		 930 /*
931 * The interface expects us to write an even number signaling that the
932 * update is finished. Since the guest won't see the intermediate
50d0a0f9 933 * state, we just increase by 2 at the end.
18068523 934 */
50d0a0f9 935 vcpu->hv_clock.version += 2;
18068523
GOC		 936
937 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
938
939 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 940 sizeof(vcpu->hv_clock));
18068523
GOC		 941
942 kunmap_atomic(shared_kaddr, KM_USER0);
943
944 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
945}
946
c8076604
GH		 947static int kvm_request_guest_time_update(struct kvm_vcpu *v)
948{
949 struct kvm_vcpu_arch *vcpu = &v->arch;
950
951 if (!vcpu->time_page)
952 return 0;
a8eeb04a 953 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 954 return 1;
955}
956
9ba075a6
AK		 957static bool msr_mtrr_valid(unsigned msr)
958{
959 switch (msr) {
960 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
961 case MSR_MTRRfix64K_00000:
962 case MSR_MTRRfix16K_80000:
963 case MSR_MTRRfix16K_A0000:
964 case MSR_MTRRfix4K_C0000:
965 case MSR_MTRRfix4K_C8000:
966 case MSR_MTRRfix4K_D0000:
967 case MSR_MTRRfix4K_D8000:
968 case MSR_MTRRfix4K_E0000:
969 case MSR_MTRRfix4K_E8000:
970 case MSR_MTRRfix4K_F0000:
971 case MSR_MTRRfix4K_F8000:
972 case MSR_MTRRdefType:
973 case MSR_IA32_CR_PAT:
974 return true;
975 case 0x2f8:
976 return true;
977 }
978 return false;
979}
980
d6289b93
MT		 981static bool valid_pat_type(unsigned t)
982{
983 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
984}
985
986static bool valid_mtrr_type(unsigned t)
987{
988 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
989}
990
991static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
992{
993 int i;
994
995 if (!msr_mtrr_valid(msr))
996 return false;
997
998 if (msr == MSR_IA32_CR_PAT) {
999 for (i = 0; i < 8; i++)
1000 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1001 return false;
1002 return true;
1003 } else if (msr == MSR_MTRRdefType) {
1004 if (data & ~0xcff)
1005 return false;
1006 return valid_mtrr_type(data & 0xff);
1007 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1008 for (i = 0; i < 8 ; i++)
1009 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1010 return false;
1011 return true;
1012 }
1013
1014 /* variable MTRRs */
1015 return valid_mtrr_type(data & 0xff);
1016}
1017
9ba075a6
AK		 1018static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1019{
0bed3b56
SY		 1020 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1021
d6289b93 1022 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1023 return 1;
1024
0bed3b56
SY		 1025 if (msr == MSR_MTRRdefType) {
1026 vcpu->arch.mtrr_state.def_type = data;
1027 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1028 } else if (msr == MSR_MTRRfix64K_00000)
1029 p[0] = data;
1030 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1031 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1032 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1033 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1034 else if (msr == MSR_IA32_CR_PAT)
1035 vcpu->arch.pat = data;
1036 else { /* Variable MTRRs */
1037 int idx, is_mtrr_mask;
1038 u64 *pt;
1039
1040 idx = (msr - 0x200) / 2;
1041 is_mtrr_mask = msr - 0x200 - 2 * idx;
1042 if (!is_mtrr_mask)
1043 pt =
1044 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1045 else
1046 pt =
1047 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1048 *pt = data;
1049 }
1050
1051 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1052 return 0;
1053}
15c4a640 1054
890ca9ae 1055static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1056{
890ca9ae
HY		 1057 u64 mcg_cap = vcpu->arch.mcg_cap;
1058 unsigned bank_num = mcg_cap & 0xff;
1059
15c4a640 1060 switch (msr) {
15c4a640 1061 case MSR_IA32_MCG_STATUS:
890ca9ae 1062 vcpu->arch.mcg_status = data;
15c4a640 1063 break;
c7ac679c 1064 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1065 if (!(mcg_cap & MCG_CTL_P))
1066 return 1;
1067 if (data != 0 && data != ~(u64)0)
1068 return -1;
1069 vcpu->arch.mcg_ctl = data;
1070 break;
1071 default:
1072 if (msr >= MSR_IA32_MC0_CTL &&
1073 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1074 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1075 /* only 0 or all 1s can be written to IA32_MCi_CTL
1076 * some Linux kernels though clear bit 10 in bank 4 to
1077 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1078 * this to avoid an uncatched #GP in the guest
1079 */
890ca9ae 1080 if ((offset & 0x3) == 0 &&
114be429 1081 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1082 return -1;
1083 vcpu->arch.mce_banks[offset] = data;
1084 break;
1085 }
1086 return 1;
1087 }
1088 return 0;
1089}
1090
ffde22ac
ES		 1091static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1092{
1093 struct kvm *kvm = vcpu->kvm;
1094 int lm = is_long_mode(vcpu);
1095 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1096 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1097 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1098 : kvm->arch.xen_hvm_config.blob_size_32;
1099 u32 page_num = data & ~PAGE_MASK;
1100 u64 page_addr = data & PAGE_MASK;
1101 u8 *page;
1102 int r;
1103
1104 r = -E2BIG;
1105 if (page_num >= blob_size)
1106 goto out;
1107 r = -ENOMEM;
1108 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1109 if (!page)
1110 goto out;
1111 r = -EFAULT;
1112 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1113 goto out_free;
1114 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1115 goto out_free;
1116 r = 0;
1117out_free:
1118 kfree(page);
1119out:
1120 return r;
1121}
1122
55cd8e5a
GN		 1123static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1124{
1125 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1126}
1127
1128static bool kvm_hv_msr_partition_wide(u32 msr)
1129{
1130 bool r = false;
1131 switch (msr) {
1132 case HV_X64_MSR_GUEST_OS_ID:
1133 case HV_X64_MSR_HYPERCALL:
1134 r = true;
1135 break;
1136 }
1137
1138 return r;
1139}
1140
1141static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1142{
1143 struct kvm *kvm = vcpu->kvm;
1144
1145 switch (msr) {
1146 case HV_X64_MSR_GUEST_OS_ID:
1147 kvm->arch.hv_guest_os_id = data;
1148 /* setting guest os id to zero disables hypercall page */
1149 if (!kvm->arch.hv_guest_os_id)
1150 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1151 break;
1152 case HV_X64_MSR_HYPERCALL: {
1153 u64 gfn;
1154 unsigned long addr;
1155 u8 instructions[4];
1156
1157 /* if guest os id is not set hypercall should remain disabled */
1158 if (!kvm->arch.hv_guest_os_id)
1159 break;
1160 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1161 kvm->arch.hv_hypercall = data;
1162 break;
1163 }
1164 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1165 addr = gfn_to_hva(kvm, gfn);
1166 if (kvm_is_error_hva(addr))
1167 return 1;
1168 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1169 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1170 if (copy_to_user((void __user *)addr, instructions, 4))
1171 return 1;
1172 kvm->arch.hv_hypercall = data;
1173 break;
1174 }
1175 default:
1176 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1177 "data 0x%llx\n", msr, data);
1178 return 1;
1179 }
1180 return 0;
1181}
1182
1183static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1184{
10388a07
GN		 1185 switch (msr) {
1186 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1187 unsigned long addr;
55cd8e5a 1188
10388a07
GN		 1189 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1190 vcpu->arch.hv_vapic = data;
1191 break;
1192 }
1193 addr = gfn_to_hva(vcpu->kvm, data >>
1194 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1195 if (kvm_is_error_hva(addr))
1196 return 1;
1197 if (clear_user((void __user *)addr, PAGE_SIZE))
1198 return 1;
1199 vcpu->arch.hv_vapic = data;
1200 break;
1201 }
1202 case HV_X64_MSR_EOI:
1203 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1204 case HV_X64_MSR_ICR:
1205 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1206 case HV_X64_MSR_TPR:
1207 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1208 default:
1209 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1210 "data 0x%llx\n", msr, data);
1211 return 1;
1212 }
1213
1214 return 0;
55cd8e5a
GN		 1215}
1216
15c4a640
CO		 1217int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1218{
1219 switch (msr) {
15c4a640 1220 case MSR_EFER:
b69e8cae 1221 return set_efer(vcpu, data);
8f1589d9
AP		 1222 case MSR_K7_HWCR:
1223 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1224 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1225 if (data != 0) {
1226 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1227 data);
1228 return 1;
1229 }
15c4a640 1230 break;
f7c6d140
AP		 1231 case MSR_FAM10H_MMIO_CONF_BASE:
1232 if (data != 0) {
1233 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1234 "0x%llx\n", data);
1235 return 1;
1236 }
15c4a640 1237 break;
c323c0e5 1238 case MSR_AMD64_NB_CFG:
c7ac679c 1239 break;
b5e2fec0
AG		 1240 case MSR_IA32_DEBUGCTLMSR:
1241 if (!data) {
1242 /* We support the non-activated case already */
1243 break;
1244 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1245 /* Values other than LBR and BTF are vendor-specific,
1246 thus reserved and should throw a #GP */
1247 return 1;
1248 }
1249 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1250 __func__, data);
1251 break;
15c4a640
CO		 1252 case MSR_IA32_UCODE_REV:
1253 case MSR_IA32_UCODE_WRITE:
61a6bd67 1254 case MSR_VM_HSAVE_PA:
6098ca93 1255 case MSR_AMD64_PATCH_LOADER:
15c4a640 1256 break;
9ba075a6
AK		 1257 case 0x200 ... 0x2ff:
1258 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1259 case MSR_IA32_APICBASE:
1260 kvm_set_apic_base(vcpu, data);
1261 break;
0105d1a5
GN		 1262 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1263 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1264 case MSR_IA32_MISC_ENABLE:
ad312c7c 1265 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1266 break;
11c6bffa 1267 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1268 case MSR_KVM_WALL_CLOCK:
1269 vcpu->kvm->arch.wall_clock = data;
1270 kvm_write_wall_clock(vcpu->kvm, data);
1271 break;
11c6bffa 1272 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1273 case MSR_KVM_SYSTEM_TIME: {
1274 if (vcpu->arch.time_page) {
1275 kvm_release_page_dirty(vcpu->arch.time_page);
1276 vcpu->arch.time_page = NULL;
1277 }
1278
1279 vcpu->arch.time = data;
1280
1281 /* we verify if the enable bit is set... */
1282 if (!(data & 1))
1283 break;
1284
1285 /* ...but clean it before doing the actual write */
1286 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1287
18068523
GOC		 1288 vcpu->arch.time_page =
1289 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1290
1291 if (is_error_page(vcpu->arch.time_page)) {
1292 kvm_release_page_clean(vcpu->arch.time_page);
1293 vcpu->arch.time_page = NULL;
1294 }
1295
c8076604 1296 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1297 break;
1298 }
890ca9ae
HY		 1299 case MSR_IA32_MCG_CTL:
1300 case MSR_IA32_MCG_STATUS:
1301 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1302 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1303
1304 /* Performance counters are not protected by a CPUID bit,
1305 * so we should check all of them in the generic path for the sake of
1306 * cross vendor migration.
1307 * Writing a zero into the event select MSRs disables them,
1308 * which we perfectly emulate ;-). Any other value should be at least
1309 * reported, some guests depend on them.
1310 */
1311 case MSR_P6_EVNTSEL0:
1312 case MSR_P6_EVNTSEL1:
1313 case MSR_K7_EVNTSEL0:
1314 case MSR_K7_EVNTSEL1:
1315 case MSR_K7_EVNTSEL2:
1316 case MSR_K7_EVNTSEL3:
1317 if (data != 0)
1318 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1319 "0x%x data 0x%llx\n", msr, data);
1320 break;
1321 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1322 * so we ignore writes to make it happy.
1323 */
1324 case MSR_P6_PERFCTR0:
1325 case MSR_P6_PERFCTR1:
1326 case MSR_K7_PERFCTR0:
1327 case MSR_K7_PERFCTR1:
1328 case MSR_K7_PERFCTR2:
1329 case MSR_K7_PERFCTR3:
1330 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1331 "0x%x data 0x%llx\n", msr, data);
1332 break;
55cd8e5a
GN		 1333 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1334 if (kvm_hv_msr_partition_wide(msr)) {
1335 int r;
1336 mutex_lock(&vcpu->kvm->lock);
1337 r = set_msr_hyperv_pw(vcpu, msr, data);
1338 mutex_unlock(&vcpu->kvm->lock);
1339 return r;
1340 } else
1341 return set_msr_hyperv(vcpu, msr, data);
1342 break;
15c4a640 1343 default:
ffde22ac
ES		 1344 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1345 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1346 if (!ignore_msrs) {
1347 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1348 msr, data);
1349 return 1;
1350 } else {
1351 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1352 msr, data);
1353 break;
1354 }
15c4a640
CO		 1355 }
1356 return 0;
1357}
1358EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1359
1360
1361/*
1362 * Reads an msr value (of 'msr_index') into 'pdata'.
1363 * Returns 0 on success, non-0 otherwise.
1364 * Assumes vcpu_load() was already called.
1365 */
1366int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1367{
1368 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1369}
1370
9ba075a6
AK		 1371static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1372{
0bed3b56
SY		 1373 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1374
9ba075a6
AK		 1375 if (!msr_mtrr_valid(msr))
1376 return 1;
1377
0bed3b56
SY		 1378 if (msr == MSR_MTRRdefType)
1379 *pdata = vcpu->arch.mtrr_state.def_type +
1380 (vcpu->arch.mtrr_state.enabled << 10);
1381 else if (msr == MSR_MTRRfix64K_00000)
1382 *pdata = p[0];
1383 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1384 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1385 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1386 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1387 else if (msr == MSR_IA32_CR_PAT)
1388 *pdata = vcpu->arch.pat;
1389 else { /* Variable MTRRs */
1390 int idx, is_mtrr_mask;
1391 u64 *pt;
1392
1393 idx = (msr - 0x200) / 2;
1394 is_mtrr_mask = msr - 0x200 - 2 * idx;
1395 if (!is_mtrr_mask)
1396 pt =
1397 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1398 else
1399 pt =
1400 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1401 *pdata = *pt;
1402 }
1403
9ba075a6
AK		 1404 return 0;
1405}
1406
890ca9ae 1407static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1408{
1409 u64 data;
890ca9ae
HY		 1410 u64 mcg_cap = vcpu->arch.mcg_cap;
1411 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1412
1413 switch (msr) {
15c4a640
CO		 1414 case MSR_IA32_P5_MC_ADDR:
1415 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1416 data = 0;
1417 break;
15c4a640 1418 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1419 data = vcpu->arch.mcg_cap;
1420 break;
c7ac679c 1421 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1422 if (!(mcg_cap & MCG_CTL_P))
1423 return 1;
1424 data = vcpu->arch.mcg_ctl;
1425 break;
1426 case MSR_IA32_MCG_STATUS:
1427 data = vcpu->arch.mcg_status;
1428 break;
1429 default:
1430 if (msr >= MSR_IA32_MC0_CTL &&
1431 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1432 u32 offset = msr - MSR_IA32_MC0_CTL;
1433 data = vcpu->arch.mce_banks[offset];
1434 break;
1435 }
1436 return 1;
1437 }
1438 *pdata = data;
1439 return 0;
1440}
1441
55cd8e5a
GN		 1442static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1443{
1444 u64 data = 0;
1445 struct kvm *kvm = vcpu->kvm;
1446
1447 switch (msr) {
1448 case HV_X64_MSR_GUEST_OS_ID:
1449 data = kvm->arch.hv_guest_os_id;
1450 break;
1451 case HV_X64_MSR_HYPERCALL:
1452 data = kvm->arch.hv_hypercall;
1453 break;
1454 default:
1455 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1456 return 1;
1457 }
1458
1459 *pdata = data;
1460 return 0;
1461}
1462
1463static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1464{
1465 u64 data = 0;
1466
1467 switch (msr) {
1468 case HV_X64_MSR_VP_INDEX: {
1469 int r;
1470 struct kvm_vcpu *v;
1471 kvm_for_each_vcpu(r, v, vcpu->kvm)
1472 if (v == vcpu)
1473 data = r;
1474 break;
1475 }
10388a07
GN		 1476 case HV_X64_MSR_EOI:
1477 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1478 case HV_X64_MSR_ICR:
1479 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1480 case HV_X64_MSR_TPR:
1481 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1482 default:
1483 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1484 return 1;
1485 }
1486 *pdata = data;
1487 return 0;
1488}
1489
890ca9ae
HY		 1490int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1491{
1492 u64 data;
1493
1494 switch (msr) {
890ca9ae 1495 case MSR_IA32_PLATFORM_ID:
15c4a640 1496 case MSR_IA32_UCODE_REV:
15c4a640 1497 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1498 case MSR_IA32_DEBUGCTLMSR:
1499 case MSR_IA32_LASTBRANCHFROMIP:
1500 case MSR_IA32_LASTBRANCHTOIP:
1501 case MSR_IA32_LASTINTFROMIP:
1502 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1503 case MSR_K8_SYSCFG:
1504 case MSR_K7_HWCR:
61a6bd67 1505 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1506 case MSR_P6_PERFCTR0:
1507 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1508 case MSR_P6_EVNTSEL0:
1509 case MSR_P6_EVNTSEL1:
9e699624 1510 case MSR_K7_EVNTSEL0:
1f3ee616 1511 case MSR_K7_PERFCTR0:
1fdbd48c 1512 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1513 case MSR_AMD64_NB_CFG:
f7c6d140 1514 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1515 data = 0;
1516 break;
9ba075a6
AK		 1517 case MSR_MTRRcap:
1518 data = 0x500 | KVM_NR_VAR_MTRR;
1519 break;
1520 case 0x200 ... 0x2ff:
1521 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1522 case 0xcd: /* fsb frequency */
1523 data = 3;
1524 break;
1525 case MSR_IA32_APICBASE:
1526 data = kvm_get_apic_base(vcpu);
1527 break;
0105d1a5
GN		 1528 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1529 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1530 break;
15c4a640 1531 case MSR_IA32_MISC_ENABLE:
ad312c7c 1532 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1533 break;
847f0ad8
AG		 1534 case MSR_IA32_PERF_STATUS:
1535 /* TSC increment by tick */
1536 data = 1000ULL;
1537 /* CPU multiplier */
1538 data |= (((uint64_t)4ULL) << 40);
1539 break;
15c4a640 1540 case MSR_EFER:
f6801dff 1541 data = vcpu->arch.efer;
15c4a640 1542 break;
18068523 1543 case MSR_KVM_WALL_CLOCK:
11c6bffa 1544 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1545 data = vcpu->kvm->arch.wall_clock;
1546 break;
1547 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1548 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1549 data = vcpu->arch.time;
1550 break;
890ca9ae
HY		 1551 case MSR_IA32_P5_MC_ADDR:
1552 case MSR_IA32_P5_MC_TYPE:
1553 case MSR_IA32_MCG_CAP:
1554 case MSR_IA32_MCG_CTL:
1555 case MSR_IA32_MCG_STATUS:
1556 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1557 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1558 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1559 if (kvm_hv_msr_partition_wide(msr)) {
1560 int r;
1561 mutex_lock(&vcpu->kvm->lock);
1562 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1563 mutex_unlock(&vcpu->kvm->lock);
1564 return r;
1565 } else
1566 return get_msr_hyperv(vcpu, msr, pdata);
1567 break;
15c4a640 1568 default:
ed85c068
AP		 1569 if (!ignore_msrs) {
1570 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1571 return 1;
1572 } else {
1573 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1574 data = 0;
1575 }
1576 break;
15c4a640
CO		 1577 }
1578 *pdata = data;
1579 return 0;
1580}
1581EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1582
313a3dc7
CO		 1583/*
1584 * Read or write a bunch of msrs. All parameters are kernel addresses.
1585 *
1586 * @return number of msrs set successfully.
1587 */
1588static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1589 struct kvm_msr_entry *entries,
1590 int (*do_msr)(struct kvm_vcpu *vcpu,
1591 unsigned index, u64 *data))
1592{
f656ce01 1593 int i, idx;
313a3dc7 1594
f656ce01 1595 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1596 for (i = 0; i < msrs->nmsrs; ++i)
1597 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1598 break;
f656ce01 1599 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1600
313a3dc7
CO		 1601 return i;
1602}
1603
1604/*
1605 * Read or write a bunch of msrs. Parameters are user addresses.
1606 *
1607 * @return number of msrs set successfully.
1608 */
1609static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1610 int (*do_msr)(struct kvm_vcpu *vcpu,
1611 unsigned index, u64 *data),
1612 int writeback)
1613{
1614 struct kvm_msrs msrs;
1615 struct kvm_msr_entry *entries;
1616 int r, n;
1617 unsigned size;
1618
1619 r = -EFAULT;
1620 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1621 goto out;
1622
1623 r = -E2BIG;
1624 if (msrs.nmsrs >= MAX_IO_MSRS)
1625 goto out;
1626
1627 r = -ENOMEM;
1628 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1629 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1630 if (!entries)
1631 goto out;
1632
1633 r = -EFAULT;
1634 if (copy_from_user(entries, user_msrs->entries, size))
1635 goto out_free;
1636
1637 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1638 if (r < 0)
1639 goto out_free;
1640
1641 r = -EFAULT;
1642 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1643 goto out_free;
1644
1645 r = n;
1646
1647out_free:
7a73c028 1648 kfree(entries);
313a3dc7
CO		 1649out:
1650 return r;
1651}
1652
018d00d2
ZX		 1653int kvm_dev_ioctl_check_extension(long ext)
1654{
1655 int r;
1656
1657 switch (ext) {
1658 case KVM_CAP_IRQCHIP:
1659 case KVM_CAP_HLT:
1660 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1661 case KVM_CAP_SET_TSS_ADDR:
07716717 1662 case KVM_CAP_EXT_CPUID:
c8076604 1663 case KVM_CAP_CLOCKSOURCE:
7837699f 1664 case KVM_CAP_PIT:
a28e4f5a 1665 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1666 case KVM_CAP_MP_STATE:
ed848624 1667 case KVM_CAP_SYNC_MMU:
52d939a0 1668 case KVM_CAP_REINJECT_CONTROL:
4925663a 1669 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1670 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1671 case KVM_CAP_IRQFD:
d34e6b17 1672 case KVM_CAP_IOEVENTFD:
c5ff41ce 1673 case KVM_CAP_PIT2:
e9f42757 1674 case KVM_CAP_PIT_STATE2:
b927a3ce 1675 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1676 case KVM_CAP_XEN_HVM:
afbcf7ab 1677 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1678 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1679 case KVM_CAP_HYPERV:
10388a07 1680 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1681 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1682 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1683 case KVM_CAP_DEBUGREGS:
d2be1651 1684 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1685 case KVM_CAP_XSAVE:
018d00d2
ZX		 1686 r = 1;
1687 break;
542472b5
LV		 1688 case KVM_CAP_COALESCED_MMIO:
1689 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1690 break;
774ead3a
AK		 1691 case KVM_CAP_VAPIC:
1692 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1693 break;
f725230a
AK		 1694 case KVM_CAP_NR_VCPUS:
1695 r = KVM_MAX_VCPUS;
1696 break;
a988b910
AK		 1697 case KVM_CAP_NR_MEMSLOTS:
1698 r = KVM_MEMORY_SLOTS;
1699 break;
a68a6a72
MT		 1700 case KVM_CAP_PV_MMU: /* obsolete */
1701 r = 0;
2f333bcb 1702 break;
62c476c7 1703 case KVM_CAP_IOMMU:
19de40a8 1704 r = iommu_found();
62c476c7 1705 break;
890ca9ae
HY		 1706 case KVM_CAP_MCE:
1707 r = KVM_MAX_MCE_BANKS;
1708 break;
2d5b5a66
SY		 1709 case KVM_CAP_XCRS:
1710 r = cpu_has_xsave;
1711 break;
018d00d2
ZX		 1712 default:
1713 r = 0;
1714 break;
1715 }
1716 return r;
1717
1718}
1719
043405e1
CO		 1720long kvm_arch_dev_ioctl(struct file *filp,
1721 unsigned int ioctl, unsigned long arg)
1722{
1723 void __user *argp = (void __user *)arg;
1724 long r;
1725
1726 switch (ioctl) {
1727 case KVM_GET_MSR_INDEX_LIST: {
1728 struct kvm_msr_list __user *user_msr_list = argp;
1729 struct kvm_msr_list msr_list;
1730 unsigned n;
1731
1732 r = -EFAULT;
1733 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1734 goto out;
1735 n = msr_list.nmsrs;
1736 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1737 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1738 goto out;
1739 r = -E2BIG;
e125e7b6 1740 if (n < msr_list.nmsrs)
043405e1
CO		 1741 goto out;
1742 r = -EFAULT;
1743 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1744 num_msrs_to_save * sizeof(u32)))
1745 goto out;
e125e7b6 1746 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1747 &emulated_msrs,
1748 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1749 goto out;
1750 r = 0;
1751 break;
1752 }
674eea0f
AK		 1753 case KVM_GET_SUPPORTED_CPUID: {
1754 struct kvm_cpuid2 __user *cpuid_arg = argp;
1755 struct kvm_cpuid2 cpuid;
1756
1757 r = -EFAULT;
1758 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1759 goto out;
1760 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1761 cpuid_arg->entries);
674eea0f
AK		 1762 if (r)
1763 goto out;
1764
1765 r = -EFAULT;
1766 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1767 goto out;
1768 r = 0;
1769 break;
1770 }
890ca9ae
HY		 1771 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1772 u64 mce_cap;
1773
1774 mce_cap = KVM_MCE_CAP_SUPPORTED;
1775 r = -EFAULT;
1776 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1777 goto out;
1778 r = 0;
1779 break;
1780 }
043405e1
CO		 1781 default:
1782 r = -EINVAL;
1783 }
1784out:
1785 return r;
1786}
1787
f5f48ee1
SY		 1788static void wbinvd_ipi(void *garbage)
1789{
1790 wbinvd();
1791}
1792
1793static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
1794{
1795 return vcpu->kvm->arch.iommu_domain &&
1796 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
1797}
1798
313a3dc7
CO		 1799void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1800{
f5f48ee1
SY		 1801 /* Address WBINVD may be executed by guest */
1802 if (need_emulate_wbinvd(vcpu)) {
1803 if (kvm_x86_ops->has_wbinvd_exit())
1804 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
1805 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
1806 smp_call_function_single(vcpu->cpu,
1807 wbinvd_ipi, NULL, 1);
1808 }
1809
313a3dc7 1810 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1811 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1812 unsigned long khz = cpufreq_quick_get(cpu);
1813 if (!khz)
1814 khz = tsc_khz;
1815 per_cpu(cpu_tsc_khz, cpu) = khz;
1816 }
c8076604 1817 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1818}
1819
1820void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1821{
02daab21 1822 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1823 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1824}
1825
07716717 1826static int is_efer_nx(void)
313a3dc7 1827{
e286e86e 1828 unsigned long long efer = 0;
313a3dc7 1829
e286e86e 1830 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1831 return efer & EFER_NX;
1832}
1833
1834static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1835{
1836 int i;
1837 struct kvm_cpuid_entry2 *e, *entry;
1838
313a3dc7 1839 entry = NULL;
ad312c7c
ZX		 1840 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1841 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1842 if (e->function == 0x80000001) {
1843 entry = e;
1844 break;
1845 }
1846 }
07716717 1847 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1848 entry->edx &= ~(1 << 20);
1849 printk(KERN_INFO "kvm: guest NX capability removed\n");
1850 }
1851}
1852
07716717 1853/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1854static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1855 struct kvm_cpuid *cpuid,
1856 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1857{
1858 int r, i;
1859 struct kvm_cpuid_entry *cpuid_entries;
1860
1861 r = -E2BIG;
1862 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1863 goto out;
1864 r = -ENOMEM;
1865 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1866 if (!cpuid_entries)
1867 goto out;
1868 r = -EFAULT;
1869 if (copy_from_user(cpuid_entries, entries,
1870 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1871 goto out_free;
1872 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1873 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1874 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1875 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1876 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1877 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1878 vcpu->arch.cpuid_entries[i].index = 0;
1879 vcpu->arch.cpuid_entries[i].flags = 0;
1880 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1881 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1882 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1883 }
1884 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1885 cpuid_fix_nx_cap(vcpu);
1886 r = 0;
fc61b800 1887 kvm_apic_set_version(vcpu);
0e851880 1888 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 1889 update_cpuid(vcpu);
07716717
DK		 1890
1891out_free:
1892 vfree(cpuid_entries);
1893out:
1894 return r;
1895}
1896
1897static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1898 struct kvm_cpuid2 *cpuid,
1899 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1900{
1901 int r;
1902
1903 r = -E2BIG;
1904 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1905 goto out;
1906 r = -EFAULT;
ad312c7c 1907 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1908 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1909 goto out;
ad312c7c 1910 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1911 kvm_apic_set_version(vcpu);
0e851880 1912 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 1913 update_cpuid(vcpu);
313a3dc7
CO		 1914 return 0;
1915
1916out:
1917 return r;
1918}
1919
07716717 1920static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1921 struct kvm_cpuid2 *cpuid,
1922 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1923{
1924 int r;
1925
1926 r = -E2BIG;
ad312c7c 1927 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1928 goto out;
1929 r = -EFAULT;
ad312c7c 1930 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1931 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1932 goto out;
1933 return 0;
1934
1935out:
ad312c7c 1936 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1937 return r;
1938}
1939
07716717 1940static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1941 u32 index)
07716717
DK		 1942{
1943 entry->function = function;
1944 entry->index = index;
1945 cpuid_count(entry->function, entry->index,
19355475 1946 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1947 entry->flags = 0;
1948}
1949
7faa4ee1
AK		 1950#define F(x) bit(X86_FEATURE_##x)
1951
07716717
DK		 1952static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1953 u32 index, int *nent, int maxnent)
1954{
7faa4ee1 1955 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1956#ifdef CONFIG_X86_64
17cc3935
SY		 1957 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1958 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1959 unsigned f_lm = F(LM);
1960#else
17cc3935 1961 unsigned f_gbpages = 0;
7faa4ee1 1962 unsigned f_lm = 0;
07716717 1963#endif
4e47c7a6 1964 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1965
1966 /* cpuid 1.edx */
1967 const u32 kvm_supported_word0_x86_features =
1968 F(FPU) | F(VME) | F(DE) | F(PSE) |
1969 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1970 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1971 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1972 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1973 0 /* Reserved, DS, ACPI */ | F(MMX) |
1974 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1975 0 /* HTT, TM, Reserved, PBE */;
1976 /* cpuid 0x80000001.edx */
1977 const u32 kvm_supported_word1_x86_features =
1978 F(FPU) | F(VME) | F(DE) | F(PSE) |
1979 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1980 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1981 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1982 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1983 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1984 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1985 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1986 /* cpuid 1.ecx */
1987 const u32 kvm_supported_word4_x86_features =
6c3f6041 1988 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 1989 0 /* DS-CPL, VMX, SMX, EST */ |
1990 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1991 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1992 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1993 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 1994 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 1995 /* cpuid 0x80000001.ecx */
07716717 1996 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1997 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1998 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1999 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2000 0 /* SKINIT */ | 0 /* WDT */;
07716717 2001
19355475 2002 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2003 get_cpu();
2004 do_cpuid_1_ent(entry, function, index);
2005 ++*nent;
2006
2007 switch (function) {
2008 case 0:
2acf923e 2009 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2010 break;
2011 case 1:
2012 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2013 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2014 /* we support x2apic emulation even if host does not support
2015 * it since we emulate x2apic in software */
2016 entry->ecx |= F(X2APIC);
07716717
DK		 2017 break;
2018 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2019 * may return different values. This forces us to get_cpu() before
2020 * issuing the first command, and also to emulate this annoying behavior
2021 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2022 case 2: {
2023 int t, times = entry->eax & 0xff;
2024
2025 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2026 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2027 for (t = 1; t < times && *nent < maxnent; ++t) {
2028 do_cpuid_1_ent(&entry[t], function, 0);
2029 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2030 ++*nent;
2031 }
2032 break;
2033 }
2034 /* function 4 and 0xb have additional index. */
2035 case 4: {
14af3f3c 2036 int i, cache_type;
07716717
DK		 2037
2038 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2039 /* read more entries until cache_type is zero */
14af3f3c
HH		 2040 for (i = 1; *nent < maxnent; ++i) {
2041 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2042 if (!cache_type)
2043 break;
14af3f3c
HH		 2044 do_cpuid_1_ent(&entry[i], function, i);
2045 entry[i].flags |=
07716717
DK		 2046 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2047 ++*nent;
2048 }
2049 break;
2050 }
2051 case 0xb: {
14af3f3c 2052 int i, level_type;
07716717
DK		 2053
2054 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2055 /* read more entries until level_type is zero */
14af3f3c 2056 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2057 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2058 if (!level_type)
2059 break;
14af3f3c
HH		 2060 do_cpuid_1_ent(&entry[i], function, i);
2061 entry[i].flags |=
07716717
DK		 2062 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2063 ++*nent;
2064 }
2065 break;
2066 }
2acf923e
DC		 2067 case 0xd: {
2068 int i;
2069
2070 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2071 for (i = 1; *nent < maxnent; ++i) {
2072 if (entry[i - 1].eax == 0 && i != 2)
2073 break;
2074 do_cpuid_1_ent(&entry[i], function, i);
2075 entry[i].flags |=
2076 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2077 ++*nent;
2078 }
2079 break;
2080 }
84478c82
GC		 2081 case KVM_CPUID_SIGNATURE: {
2082 char signature[12] = "KVMKVMKVM\0\0";
2083 u32 *sigptr = (u32 *)signature;
2084 entry->eax = 0;
2085 entry->ebx = sigptr[0];
2086 entry->ecx = sigptr[1];
2087 entry->edx = sigptr[2];
2088 break;
2089 }
2090 case KVM_CPUID_FEATURES:
2091 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2092 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2093 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2094 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2095 entry->ebx = 0;
2096 entry->ecx = 0;
2097 entry->edx = 0;
2098 break;
07716717
DK		 2099 case 0x80000000:
2100 entry->eax = min(entry->eax, 0x8000001a);
2101 break;
2102 case 0x80000001:
2103 entry->edx &= kvm_supported_word1_x86_features;
2104 entry->ecx &= kvm_supported_word6_x86_features;
2105 break;
2106 }
d4330ef2
JR		 2107
2108 kvm_x86_ops->set_supported_cpuid(function, entry);
2109
07716717
DK		 2110 put_cpu();
2111}
2112
7faa4ee1
AK		 2113#undef F
2114
674eea0f 2115static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2116 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2117{
2118 struct kvm_cpuid_entry2 *cpuid_entries;
2119 int limit, nent = 0, r = -E2BIG;
2120 u32 func;
2121
2122 if (cpuid->nent < 1)
2123 goto out;
6a544355
AK		 2124 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2125 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2126 r = -ENOMEM;
2127 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2128 if (!cpuid_entries)
2129 goto out;
2130
2131 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2132 limit = cpuid_entries[0].eax;
2133 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2134 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2135 &nent, cpuid->nent);
07716717
DK		 2136 r = -E2BIG;
2137 if (nent >= cpuid->nent)
2138 goto out_free;
2139
2140 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2141 limit = cpuid_entries[nent - 1].eax;
2142 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2143 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2144 &nent, cpuid->nent);
84478c82
GC		 2145
2146
2147
2148 r = -E2BIG;
2149 if (nent >= cpuid->nent)
2150 goto out_free;
2151
2152 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2153 cpuid->nent);
2154
2155 r = -E2BIG;
2156 if (nent >= cpuid->nent)
2157 goto out_free;
2158
2159 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2160 cpuid->nent);
2161
cb007648
MM		 2162 r = -E2BIG;
2163 if (nent >= cpuid->nent)
2164 goto out_free;
2165
07716717
DK		 2166 r = -EFAULT;
2167 if (copy_to_user(entries, cpuid_entries,
19355475 2168 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2169 goto out_free;
2170 cpuid->nent = nent;
2171 r = 0;
2172
2173out_free:
2174 vfree(cpuid_entries);
2175out:
2176 return r;
2177}
2178
313a3dc7
CO		 2179static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2180 struct kvm_lapic_state *s)
2181{
ad312c7c 2182 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2183
2184 return 0;
2185}
2186
2187static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2188 struct kvm_lapic_state *s)
2189{
ad312c7c 2190 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2191 kvm_apic_post_state_restore(vcpu);
cb142eb7 2192 update_cr8_intercept(vcpu);
313a3dc7
CO		 2193
2194 return 0;
2195}
2196
f77bc6a4
ZX		 2197static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2198 struct kvm_interrupt *irq)
2199{
2200 if (irq->irq < 0 || irq->irq >= 256)
2201 return -EINVAL;
2202 if (irqchip_in_kernel(vcpu->kvm))
2203 return -ENXIO;
f77bc6a4 2204
66fd3f7f 2205 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2206
f77bc6a4
ZX		 2207 return 0;
2208}
2209
c4abb7c9
JK		 2210static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2211{
c4abb7c9 2212 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2213
2214 return 0;
2215}
2216
b209749f
AK		 2217static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2218 struct kvm_tpr_access_ctl *tac)
2219{
2220 if (tac->flags)
2221 return -EINVAL;
2222 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2223 return 0;
2224}
2225
890ca9ae
HY		 2226static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2227 u64 mcg_cap)
2228{
2229 int r;
2230 unsigned bank_num = mcg_cap & 0xff, bank;
2231
2232 r = -EINVAL;
a9e38c3e 2233 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2234 goto out;
2235 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2236 goto out;
2237 r = 0;
2238 vcpu->arch.mcg_cap = mcg_cap;
2239 /* Init IA32_MCG_CTL to all 1s */
2240 if (mcg_cap & MCG_CTL_P)
2241 vcpu->arch.mcg_ctl = ~(u64)0;
2242 /* Init IA32_MCi_CTL to all 1s */
2243 for (bank = 0; bank < bank_num; bank++)
2244 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2245out:
2246 return r;
2247}
2248
2249static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2250 struct kvm_x86_mce *mce)
2251{
2252 u64 mcg_cap = vcpu->arch.mcg_cap;
2253 unsigned bank_num = mcg_cap & 0xff;
2254 u64 *banks = vcpu->arch.mce_banks;
2255
2256 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2257 return -EINVAL;
2258 /*
2259 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2260 * reporting is disabled
2261 */
2262 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2263 vcpu->arch.mcg_ctl != ~(u64)0)
2264 return 0;
2265 banks += 4 * mce->bank;
2266 /*
2267 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2268 * reporting is disabled for the bank
2269 */
2270 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2271 return 0;
2272 if (mce->status & MCI_STATUS_UC) {
2273 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2274 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2275 printk(KERN_DEBUG "kvm: set_mce: "
2276 "injects mce exception while "
2277 "previous one is in progress!\n");
a8eeb04a 2278 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2279 return 0;
2280 }
2281 if (banks[1] & MCI_STATUS_VAL)
2282 mce->status |= MCI_STATUS_OVER;
2283 banks[2] = mce->addr;
2284 banks[3] = mce->misc;
2285 vcpu->arch.mcg_status = mce->mcg_status;
2286 banks[1] = mce->status;
2287 kvm_queue_exception(vcpu, MC_VECTOR);
2288 } else if (!(banks[1] & MCI_STATUS_VAL)
2289 || !(banks[1] & MCI_STATUS_UC)) {
2290 if (banks[1] & MCI_STATUS_VAL)
2291 mce->status |= MCI_STATUS_OVER;
2292 banks[2] = mce->addr;
2293 banks[3] = mce->misc;
2294 banks[1] = mce->status;
2295 } else
2296 banks[1] |= MCI_STATUS_OVER;
2297 return 0;
2298}
2299
3cfc3092
JK		 2300static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2301 struct kvm_vcpu_events *events)
2302{
03b82a30
JK		 2303 events->exception.injected =
2304 vcpu->arch.exception.pending &&
2305 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2306 events->exception.nr = vcpu->arch.exception.nr;
2307 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2308 events->exception.error_code = vcpu->arch.exception.error_code;
2309
03b82a30
JK		 2310 events->interrupt.injected =
2311 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2312 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2313 events->interrupt.soft = 0;
48005f64
JK		 2314 events->interrupt.shadow =
2315 kvm_x86_ops->get_interrupt_shadow(vcpu,
2316 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2317
2318 events->nmi.injected = vcpu->arch.nmi_injected;
2319 events->nmi.pending = vcpu->arch.nmi_pending;
2320 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2321
2322 events->sipi_vector = vcpu->arch.sipi_vector;
2323
dab4b911 2324 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2325 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2326 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2327}
2328
2329static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2330 struct kvm_vcpu_events *events)
2331{
dab4b911 2332 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2333 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2334 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2335 return -EINVAL;
2336
3cfc3092
JK		 2337 vcpu->arch.exception.pending = events->exception.injected;
2338 vcpu->arch.exception.nr = events->exception.nr;
2339 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2340 vcpu->arch.exception.error_code = events->exception.error_code;
2341
2342 vcpu->arch.interrupt.pending = events->interrupt.injected;
2343 vcpu->arch.interrupt.nr = events->interrupt.nr;
2344 vcpu->arch.interrupt.soft = events->interrupt.soft;
2345 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2346 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2347 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2348 kvm_x86_ops->set_interrupt_shadow(vcpu,
2349 events->interrupt.shadow);
3cfc3092
JK		 2350
2351 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2352 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2353 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2354 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2355
dab4b911
JK		 2356 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2357 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2358
3cfc3092
JK		 2359 return 0;
2360}
2361
a1efbe77
JK		 2362static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2363 struct kvm_debugregs *dbgregs)
2364{
a1efbe77
JK		 2365 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2366 dbgregs->dr6 = vcpu->arch.dr6;
2367 dbgregs->dr7 = vcpu->arch.dr7;
2368 dbgregs->flags = 0;
a1efbe77
JK		 2369}
2370
2371static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2372 struct kvm_debugregs *dbgregs)
2373{
2374 if (dbgregs->flags)
2375 return -EINVAL;
2376
a1efbe77
JK		 2377 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2378 vcpu->arch.dr6 = dbgregs->dr6;
2379 vcpu->arch.dr7 = dbgregs->dr7;
2380
a1efbe77
JK		 2381 return 0;
2382}
2383
2d5b5a66
SY		 2384static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2385 struct kvm_xsave *guest_xsave)
2386{
2387 if (cpu_has_xsave)
2388 memcpy(guest_xsave->region,
2389 &vcpu->arch.guest_fpu.state->xsave,
2390 sizeof(struct xsave_struct));
2391 else {
2392 memcpy(guest_xsave->region,
2393 &vcpu->arch.guest_fpu.state->fxsave,
2394 sizeof(struct i387_fxsave_struct));
2395 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2396 XSTATE_FPSSE;
2397 }
2398}
2399
2400static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2401 struct kvm_xsave *guest_xsave)
2402{
2403 u64 xstate_bv =
2404 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2405
2406 if (cpu_has_xsave)
2407 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2408 guest_xsave->region, sizeof(struct xsave_struct));
2409 else {
2410 if (xstate_bv & ~XSTATE_FPSSE)
2411 return -EINVAL;
2412 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2413 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2414 }
2415 return 0;
2416}
2417
2418static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2419 struct kvm_xcrs *guest_xcrs)
2420{
2421 if (!cpu_has_xsave) {
2422 guest_xcrs->nr_xcrs = 0;
2423 return;
2424 }
2425
2426 guest_xcrs->nr_xcrs = 1;
2427 guest_xcrs->flags = 0;
2428 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2429 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2430}
2431
2432static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2433 struct kvm_xcrs *guest_xcrs)
2434{
2435 int i, r = 0;
2436
2437 if (!cpu_has_xsave)
2438 return -EINVAL;
2439
2440 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2441 return -EINVAL;
2442
2443 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2444 /* Only support XCR0 currently */
2445 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2446 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2447 guest_xcrs->xcrs[0].value);
2448 break;
2449 }
2450 if (r)
2451 r = -EINVAL;
2452 return r;
2453}
2454
313a3dc7
CO		 2455long kvm_arch_vcpu_ioctl(struct file *filp,
2456 unsigned int ioctl, unsigned long arg)
2457{
2458 struct kvm_vcpu *vcpu = filp->private_data;
2459 void __user *argp = (void __user *)arg;
2460 int r;
d1ac91d8
AK		 2461 union {
2462 struct kvm_lapic_state *lapic;
2463 struct kvm_xsave *xsave;
2464 struct kvm_xcrs *xcrs;
2465 void *buffer;
2466 } u;
2467
2468 u.buffer = NULL;
313a3dc7
CO		 2469 switch (ioctl) {
2470 case KVM_GET_LAPIC: {
2204ae3c
MT		 2471 r = -EINVAL;
2472 if (!vcpu->arch.apic)
2473 goto out;
d1ac91d8 2474 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2475
b772ff36 2476 r = -ENOMEM;
d1ac91d8 2477 if (!u.lapic)
b772ff36 2478 goto out;
d1ac91d8 2479 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2480 if (r)
2481 goto out;
2482 r = -EFAULT;
d1ac91d8 2483 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2484 goto out;
2485 r = 0;
2486 break;
2487 }
2488 case KVM_SET_LAPIC: {
2204ae3c
MT		 2489 r = -EINVAL;
2490 if (!vcpu->arch.apic)
2491 goto out;
d1ac91d8 2492 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2493 r = -ENOMEM;
d1ac91d8 2494 if (!u.lapic)
b772ff36 2495 goto out;
313a3dc7 2496 r = -EFAULT;
d1ac91d8 2497 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2498 goto out;
d1ac91d8 2499 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2500 if (r)
2501 goto out;
2502 r = 0;
2503 break;
2504 }
f77bc6a4
ZX		 2505 case KVM_INTERRUPT: {
2506 struct kvm_interrupt irq;
2507
2508 r = -EFAULT;
2509 if (copy_from_user(&irq, argp, sizeof irq))
2510 goto out;
2511 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2512 if (r)
2513 goto out;
2514 r = 0;
2515 break;
2516 }
c4abb7c9
JK		 2517 case KVM_NMI: {
2518 r = kvm_vcpu_ioctl_nmi(vcpu);
2519 if (r)
2520 goto out;
2521 r = 0;
2522 break;
2523 }
313a3dc7
CO		 2524 case KVM_SET_CPUID: {
2525 struct kvm_cpuid __user *cpuid_arg = argp;
2526 struct kvm_cpuid cpuid;
2527
2528 r = -EFAULT;
2529 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2530 goto out;
2531 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2532 if (r)
2533 goto out;
2534 break;
2535 }
07716717
DK		 2536 case KVM_SET_CPUID2: {
2537 struct kvm_cpuid2 __user *cpuid_arg = argp;
2538 struct kvm_cpuid2 cpuid;
2539
2540 r = -EFAULT;
2541 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2542 goto out;
2543 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2544 cpuid_arg->entries);
07716717
DK		 2545 if (r)
2546 goto out;
2547 break;
2548 }
2549 case KVM_GET_CPUID2: {
2550 struct kvm_cpuid2 __user *cpuid_arg = argp;
2551 struct kvm_cpuid2 cpuid;
2552
2553 r = -EFAULT;
2554 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2555 goto out;
2556 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2557 cpuid_arg->entries);
07716717
DK		 2558 if (r)
2559 goto out;
2560 r = -EFAULT;
2561 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2562 goto out;
2563 r = 0;
2564 break;
2565 }
313a3dc7
CO		 2566 case KVM_GET_MSRS:
2567 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2568 break;
2569 case KVM_SET_MSRS:
2570 r = msr_io(vcpu, argp, do_set_msr, 0);
2571 break;
b209749f
AK		 2572 case KVM_TPR_ACCESS_REPORTING: {
2573 struct kvm_tpr_access_ctl tac;
2574
2575 r = -EFAULT;
2576 if (copy_from_user(&tac, argp, sizeof tac))
2577 goto out;
2578 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2579 if (r)
2580 goto out;
2581 r = -EFAULT;
2582 if (copy_to_user(argp, &tac, sizeof tac))
2583 goto out;
2584 r = 0;
2585 break;
2586 };
b93463aa
AK		 2587 case KVM_SET_VAPIC_ADDR: {
2588 struct kvm_vapic_addr va;
2589
2590 r = -EINVAL;
2591 if (!irqchip_in_kernel(vcpu->kvm))
2592 goto out;
2593 r = -EFAULT;
2594 if (copy_from_user(&va, argp, sizeof va))
2595 goto out;
2596 r = 0;
2597 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2598 break;
2599 }
890ca9ae
HY		 2600 case KVM_X86_SETUP_MCE: {
2601 u64 mcg_cap;
2602
2603 r = -EFAULT;
2604 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2605 goto out;
2606 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2607 break;
2608 }
2609 case KVM_X86_SET_MCE: {
2610 struct kvm_x86_mce mce;
2611
2612 r = -EFAULT;
2613 if (copy_from_user(&mce, argp, sizeof mce))
2614 goto out;
2615 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2616 break;
2617 }
3cfc3092
JK		 2618 case KVM_GET_VCPU_EVENTS: {
2619 struct kvm_vcpu_events events;
2620
2621 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2622
2623 r = -EFAULT;
2624 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2625 break;
2626 r = 0;
2627 break;
2628 }
2629 case KVM_SET_VCPU_EVENTS: {
2630 struct kvm_vcpu_events events;
2631
2632 r = -EFAULT;
2633 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2634 break;
2635
2636 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2637 break;
2638 }
a1efbe77
JK		 2639 case KVM_GET_DEBUGREGS: {
2640 struct kvm_debugregs dbgregs;
2641
2642 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2643
2644 r = -EFAULT;
2645 if (copy_to_user(argp, &dbgregs,
2646 sizeof(struct kvm_debugregs)))
2647 break;
2648 r = 0;
2649 break;
2650 }
2651 case KVM_SET_DEBUGREGS: {
2652 struct kvm_debugregs dbgregs;
2653
2654 r = -EFAULT;
2655 if (copy_from_user(&dbgregs, argp,
2656 sizeof(struct kvm_debugregs)))
2657 break;
2658
2659 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2660 break;
2661 }
2d5b5a66 2662 case KVM_GET_XSAVE: {
d1ac91d8 2663 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2664 r = -ENOMEM;
d1ac91d8 2665 if (!u.xsave)
2d5b5a66
SY		 2666 break;
2667
d1ac91d8 2668 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2669
2670 r = -EFAULT;
d1ac91d8 2671 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2672 break;
2673 r = 0;
2674 break;
2675 }
2676 case KVM_SET_XSAVE: {
d1ac91d8 2677 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2678 r = -ENOMEM;
d1ac91d8 2679 if (!u.xsave)
2d5b5a66
SY		 2680 break;
2681
2682 r = -EFAULT;
d1ac91d8 2683 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2684 break;
2685
d1ac91d8 2686 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2687 break;
2688 }
2689 case KVM_GET_XCRS: {
d1ac91d8 2690 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2691 r = -ENOMEM;
d1ac91d8 2692 if (!u.xcrs)
2d5b5a66
SY		 2693 break;
2694
d1ac91d8 2695 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2696
2697 r = -EFAULT;
d1ac91d8 2698 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2699 sizeof(struct kvm_xcrs)))
2700 break;
2701 r = 0;
2702 break;
2703 }
2704 case KVM_SET_XCRS: {
d1ac91d8 2705 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2706 r = -ENOMEM;
d1ac91d8 2707 if (!u.xcrs)
2d5b5a66
SY		 2708 break;
2709
2710 r = -EFAULT;
d1ac91d8 2711 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2712 sizeof(struct kvm_xcrs)))
2713 break;
2714
d1ac91d8 2715 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2716 break;
2717 }
313a3dc7
CO		 2718 default:
2719 r = -EINVAL;
2720 }
2721out:
d1ac91d8 2722 kfree(u.buffer);
313a3dc7
CO		 2723 return r;
2724}
2725
1fe779f8
CO		 2726static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2727{
2728 int ret;
2729
2730 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2731 return -1;
2732 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2733 return ret;
2734}
2735
b927a3ce
SY		 2736static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2737 u64 ident_addr)
2738{
2739 kvm->arch.ept_identity_map_addr = ident_addr;
2740 return 0;
2741}
2742
1fe779f8
CO		 2743static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2744 u32 kvm_nr_mmu_pages)
2745{
2746 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2747 return -EINVAL;
2748
79fac95e 2749 mutex_lock(&kvm->slots_lock);
7c8a83b7 2750 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2751
2752 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2753 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2754
7c8a83b7 2755 spin_unlock(&kvm->mmu_lock);
79fac95e 2756 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2757 return 0;
2758}
2759
2760static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2761{
f05e70ac 2762 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2763}
2764
1fe779f8
CO		 2765static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2766{
2767 int r;
2768
2769 r = 0;
2770 switch (chip->chip_id) {
2771 case KVM_IRQCHIP_PIC_MASTER:
2772 memcpy(&chip->chip.pic,
2773 &pic_irqchip(kvm)->pics[0],
2774 sizeof(struct kvm_pic_state));
2775 break;
2776 case KVM_IRQCHIP_PIC_SLAVE:
2777 memcpy(&chip->chip.pic,
2778 &pic_irqchip(kvm)->pics[1],
2779 sizeof(struct kvm_pic_state));
2780 break;
2781 case KVM_IRQCHIP_IOAPIC:
eba0226b 2782 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2783 break;
2784 default:
2785 r = -EINVAL;
2786 break;
2787 }
2788 return r;
2789}
2790
2791static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2792{
2793 int r;
2794
2795 r = 0;
2796 switch (chip->chip_id) {
2797 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2798 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2799 memcpy(&pic_irqchip(kvm)->pics[0],
2800 &chip->chip.pic,
2801 sizeof(struct kvm_pic_state));
fa8273e9 2802 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2803 break;
2804 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2805 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2806 memcpy(&pic_irqchip(kvm)->pics[1],
2807 &chip->chip.pic,
2808 sizeof(struct kvm_pic_state));
fa8273e9 2809 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2810 break;
2811 case KVM_IRQCHIP_IOAPIC:
eba0226b 2812 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2813 break;
2814 default:
2815 r = -EINVAL;
2816 break;
2817 }
2818 kvm_pic_update_irq(pic_irqchip(kvm));
2819 return r;
2820}
2821
e0f63cb9
SY		 2822static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2823{
2824 int r = 0;
2825
894a9c55 2826 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2827 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2828 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2829 return r;
2830}
2831
2832static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2833{
2834 int r = 0;
2835
894a9c55 2836 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2837 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2838 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2839 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2840 return r;
2841}
2842
2843static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2844{
2845 int r = 0;
2846
2847 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2848 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2849 sizeof(ps->channels));
2850 ps->flags = kvm->arch.vpit->pit_state.flags;
2851 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2852 return r;
2853}
2854
2855static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2856{
2857 int r = 0, start = 0;
2858 u32 prev_legacy, cur_legacy;
2859 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2860 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2861 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2862 if (!prev_legacy && cur_legacy)
2863 start = 1;
2864 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2865 sizeof(kvm->arch.vpit->pit_state.channels));
2866 kvm->arch.vpit->pit_state.flags = ps->flags;
2867 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2868 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2869 return r;
2870}
2871
52d939a0
MT		 2872static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2873 struct kvm_reinject_control *control)
2874{
2875 if (!kvm->arch.vpit)
2876 return -ENXIO;
894a9c55 2877 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2878 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2879 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2880 return 0;
2881}
2882
5bb064dc
ZX		 2883/*
2884 * Get (and clear) the dirty memory log for a memory slot.
2885 */
2886int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2887 struct kvm_dirty_log *log)
2888{
87bf6e7d 2889 int r, i;
5bb064dc 2890 struct kvm_memory_slot *memslot;
87bf6e7d 2891 unsigned long n;
b050b015 2892 unsigned long is_dirty = 0;
5bb064dc 2893
79fac95e 2894 mutex_lock(&kvm->slots_lock);
5bb064dc 2895
b050b015
MT		 2896 r = -EINVAL;
2897 if (log->slot >= KVM_MEMORY_SLOTS)
2898 goto out;
2899
2900 memslot = &kvm->memslots->memslots[log->slot];
2901 r = -ENOENT;
2902 if (!memslot->dirty_bitmap)
2903 goto out;
2904
87bf6e7d 2905 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2906
b050b015
MT		 2907 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2908 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2909
2910 /* If nothing is dirty, don't bother messing with page tables. */
2911 if (is_dirty) {
b050b015 2912 struct kvm_memslots *slots, *old_slots;
914ebccd 2913 unsigned long *dirty_bitmap;
b050b015 2914
7c8a83b7 2915 spin_lock(&kvm->mmu_lock);
5bb064dc 2916 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2917 spin_unlock(&kvm->mmu_lock);
b050b015 2918
914ebccd
TY		 2919 r = -ENOMEM;
2920 dirty_bitmap = vmalloc(n);
2921 if (!dirty_bitmap)
2922 goto out;
2923 memset(dirty_bitmap, 0, n);
b050b015 2924
914ebccd
TY		 2925 r = -ENOMEM;
2926 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2927 if (!slots) {
2928 vfree(dirty_bitmap);
2929 goto out;
2930 }
b050b015
MT		 2931 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2932 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2933
2934 old_slots = kvm->memslots;
2935 rcu_assign_pointer(kvm->memslots, slots);
2936 synchronize_srcu_expedited(&kvm->srcu);
2937 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2938 kfree(old_slots);
914ebccd
TY		 2939
2940 r = -EFAULT;
2941 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2942 vfree(dirty_bitmap);
2943 goto out;
2944 }
2945 vfree(dirty_bitmap);
2946 } else {
2947 r = -EFAULT;
2948 if (clear_user(log->dirty_bitmap, n))
2949 goto out;
5bb064dc 2950 }
b050b015 2951
5bb064dc
ZX		 2952 r = 0;
2953out:
79fac95e 2954 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2955 return r;
2956}
2957
1fe779f8
CO		 2958long kvm_arch_vm_ioctl(struct file *filp,
2959 unsigned int ioctl, unsigned long arg)
2960{
2961 struct kvm *kvm = filp->private_data;
2962 void __user *argp = (void __user *)arg;
367e1319 2963 int r = -ENOTTY;
f0d66275
DH		 2964 /*
2965 * This union makes it completely explicit to gcc-3.x
2966 * that these two variables' stack usage should be
2967 * combined, not added together.
2968 */
2969 union {
2970 struct kvm_pit_state ps;
e9f42757 2971 struct kvm_pit_state2 ps2;
c5ff41ce 2972 struct kvm_pit_config pit_config;
f0d66275 2973 } u;
1fe779f8
CO		 2974
2975 switch (ioctl) {
2976 case KVM_SET_TSS_ADDR:
2977 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2978 if (r < 0)
2979 goto out;
2980 break;
b927a3ce
SY		 2981 case KVM_SET_IDENTITY_MAP_ADDR: {
2982 u64 ident_addr;
2983
2984 r = -EFAULT;
2985 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2986 goto out;
2987 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2988 if (r < 0)
2989 goto out;
2990 break;
2991 }
1fe779f8
CO		 2992 case KVM_SET_NR_MMU_PAGES:
2993 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2994 if (r)
2995 goto out;
2996 break;
2997 case KVM_GET_NR_MMU_PAGES:
2998 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2999 break;
3ddea128
MT		 3000 case KVM_CREATE_IRQCHIP: {
3001 struct kvm_pic *vpic;
3002
3003 mutex_lock(&kvm->lock);
3004 r = -EEXIST;
3005 if (kvm->arch.vpic)
3006 goto create_irqchip_unlock;
1fe779f8 3007 r = -ENOMEM;
3ddea128
MT		 3008 vpic = kvm_create_pic(kvm);
3009 if (vpic) {
1fe779f8
CO		 3010 r = kvm_ioapic_init(kvm);
3011 if (r) {
72bb2fcd
WY		 3012 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3013 &vpic->dev);
3ddea128
MT		 3014 kfree(vpic);
3015 goto create_irqchip_unlock;
1fe779f8
CO		 3016 }
3017 } else
3ddea128
MT		 3018 goto create_irqchip_unlock;
3019 smp_wmb();
3020 kvm->arch.vpic = vpic;
3021 smp_wmb();
399ec807
AK		 3022 r = kvm_setup_default_irq_routing(kvm);
3023 if (r) {
3ddea128 3024 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3025 kvm_ioapic_destroy(kvm);
3026 kvm_destroy_pic(kvm);
3ddea128 3027 mutex_unlock(&kvm->irq_lock);
399ec807 3028 }
3ddea128
MT		 3029 create_irqchip_unlock:
3030 mutex_unlock(&kvm->lock);
1fe779f8 3031 break;
3ddea128 3032 }
7837699f 3033 case KVM_CREATE_PIT:
c5ff41ce
JK		 3034 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3035 goto create_pit;
3036 case KVM_CREATE_PIT2:
3037 r = -EFAULT;
3038 if (copy_from_user(&u.pit_config, argp,
3039 sizeof(struct kvm_pit_config)))
3040 goto out;
3041 create_pit:
79fac95e 3042 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3043 r = -EEXIST;
3044 if (kvm->arch.vpit)
3045 goto create_pit_unlock;
7837699f 3046 r = -ENOMEM;
c5ff41ce 3047 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3048 if (kvm->arch.vpit)
3049 r = 0;
269e05e4 3050 create_pit_unlock:
79fac95e 3051 mutex_unlock(&kvm->slots_lock);
7837699f 3052 break;
4925663a 3053 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3054 case KVM_IRQ_LINE: {
3055 struct kvm_irq_level irq_event;
3056
3057 r = -EFAULT;
3058 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3059 goto out;
160d2f6c 3060 r = -ENXIO;
1fe779f8 3061 if (irqchip_in_kernel(kvm)) {
4925663a 3062 __s32 status;
4925663a
GN		 3063 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3064 irq_event.irq, irq_event.level);
4925663a 3065 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3066 r = -EFAULT;
4925663a
GN		 3067 irq_event.status = status;
3068 if (copy_to_user(argp, &irq_event,
3069 sizeof irq_event))
3070 goto out;
3071 }
1fe779f8
CO		 3072 r = 0;
3073 }
3074 break;
3075 }
3076 case KVM_GET_IRQCHIP: {
3077 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3078 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3079
f0d66275
DH		 3080 r = -ENOMEM;
3081 if (!chip)
1fe779f8 3082 goto out;
f0d66275
DH		 3083 r = -EFAULT;
3084 if (copy_from_user(chip, argp, sizeof *chip))
3085 goto get_irqchip_out;
1fe779f8
CO		 3086 r = -ENXIO;
3087 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3088 goto get_irqchip_out;
3089 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3090 if (r)
f0d66275 3091 goto get_irqchip_out;
1fe779f8 3092 r = -EFAULT;
f0d66275
DH		 3093 if (copy_to_user(argp, chip, sizeof *chip))
3094 goto get_irqchip_out;
1fe779f8 3095 r = 0;
f0d66275
DH		 3096 get_irqchip_out:
3097 kfree(chip);
3098 if (r)
3099 goto out;
1fe779f8
CO		 3100 break;
3101 }
3102 case KVM_SET_IRQCHIP: {
3103 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3104 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3105
f0d66275
DH		 3106 r = -ENOMEM;
3107 if (!chip)
1fe779f8 3108 goto out;
f0d66275
DH		 3109 r = -EFAULT;
3110 if (copy_from_user(chip, argp, sizeof *chip))
3111 goto set_irqchip_out;
1fe779f8
CO		 3112 r = -ENXIO;
3113 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3114 goto set_irqchip_out;
3115 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3116 if (r)
f0d66275 3117 goto set_irqchip_out;
1fe779f8 3118 r = 0;
f0d66275
DH		 3119 set_irqchip_out:
3120 kfree(chip);
3121 if (r)
3122 goto out;
1fe779f8
CO		 3123 break;
3124 }
e0f63cb9 3125 case KVM_GET_PIT: {
e0f63cb9 3126 r = -EFAULT;
f0d66275 3127 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3128 goto out;
3129 r = -ENXIO;
3130 if (!kvm->arch.vpit)
3131 goto out;
f0d66275 3132 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3133 if (r)
3134 goto out;
3135 r = -EFAULT;
f0d66275 3136 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3137 goto out;
3138 r = 0;
3139 break;
3140 }
3141 case KVM_SET_PIT: {
e0f63cb9 3142 r = -EFAULT;
f0d66275 3143 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3144 goto out;
3145 r = -ENXIO;
3146 if (!kvm->arch.vpit)
3147 goto out;
f0d66275 3148 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3149 if (r)
3150 goto out;
3151 r = 0;
3152 break;
3153 }
e9f42757
BK		 3154 case KVM_GET_PIT2: {
3155 r = -ENXIO;
3156 if (!kvm->arch.vpit)
3157 goto out;
3158 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3159 if (r)
3160 goto out;
3161 r = -EFAULT;
3162 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3163 goto out;
3164 r = 0;
3165 break;
3166 }
3167 case KVM_SET_PIT2: {
3168 r = -EFAULT;
3169 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3170 goto out;
3171 r = -ENXIO;
3172 if (!kvm->arch.vpit)
3173 goto out;
3174 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3175 if (r)
3176 goto out;
3177 r = 0;
3178 break;
3179 }
52d939a0
MT		 3180 case KVM_REINJECT_CONTROL: {
3181 struct kvm_reinject_control control;
3182 r = -EFAULT;
3183 if (copy_from_user(&control, argp, sizeof(control)))
3184 goto out;
3185 r = kvm_vm_ioctl_reinject(kvm, &control);
3186 if (r)
3187 goto out;
3188 r = 0;
3189 break;
3190 }
ffde22ac
ES		 3191 case KVM_XEN_HVM_CONFIG: {
3192 r = -EFAULT;
3193 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3194 sizeof(struct kvm_xen_hvm_config)))
3195 goto out;
3196 r = -EINVAL;
3197 if (kvm->arch.xen_hvm_config.flags)
3198 goto out;
3199 r = 0;
3200 break;
3201 }
afbcf7ab
GC		 3202 case KVM_SET_CLOCK: {
3203 struct timespec now;
3204 struct kvm_clock_data user_ns;
3205 u64 now_ns;
3206 s64 delta;
3207
3208 r = -EFAULT;
3209 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3210 goto out;
3211
3212 r = -EINVAL;
3213 if (user_ns.flags)
3214 goto out;
3215
3216 r = 0;
3217 ktime_get_ts(&now);
3218 now_ns = timespec_to_ns(&now);
3219 delta = user_ns.clock - now_ns;
3220 kvm->arch.kvmclock_offset = delta;
3221 break;
3222 }
3223 case KVM_GET_CLOCK: {
3224 struct timespec now;
3225 struct kvm_clock_data user_ns;
3226 u64 now_ns;
3227
3228 ktime_get_ts(&now);
3229 now_ns = timespec_to_ns(&now);
3230 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3231 user_ns.flags = 0;
3232
3233 r = -EFAULT;
3234 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3235 goto out;
3236 r = 0;
3237 break;
3238 }
3239
1fe779f8
CO		 3240 default:
3241 ;
3242 }
3243out:
3244 return r;
3245}
3246
a16b043c 3247static void kvm_init_msr_list(void)
043405e1
CO		 3248{
3249 u32 dummy[2];
3250 unsigned i, j;
3251
e3267cbb
GC		 3252 /* skip the first msrs in the list. KVM-specific */
3253 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3254 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3255 continue;
3256 if (j < i)
3257 msrs_to_save[j] = msrs_to_save[i];
3258 j++;
3259 }
3260 num_msrs_to_save = j;
3261}
3262
bda9020e
MT		 3263static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3264 const void *v)
bbd9b64e 3265{
bda9020e
MT		 3266 if (vcpu->arch.apic &&
3267 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3268 return 0;
bbd9b64e 3269
e93f8a0f 3270 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3271}
3272
bda9020e 3273static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3274{
bda9020e
MT		 3275 if (vcpu->arch.apic &&
3276 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3277 return 0;
bbd9b64e 3278
e93f8a0f 3279 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3280}
3281
2dafc6c2
GN		 3282static void kvm_set_segment(struct kvm_vcpu *vcpu,
3283 struct kvm_segment *var, int seg)
3284{
3285 kvm_x86_ops->set_segment(vcpu, var, seg);
3286}
3287
3288void kvm_get_segment(struct kvm_vcpu *vcpu,
3289 struct kvm_segment *var, int seg)
3290{
3291 kvm_x86_ops->get_segment(vcpu, var, seg);
3292}
3293
1871c602
GN		 3294gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3295{
3296 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3297 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3298}
3299
3300 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3301{
3302 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3303 access |= PFERR_FETCH_MASK;
3304 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3305}
3306
3307gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3308{
3309 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3310 access |= PFERR_WRITE_MASK;
3311 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3312}
3313
3314/* uses this to access any guest's mapped memory without checking CPL */
3315gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3316{
3317 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3318}
3319
3320static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3321 struct kvm_vcpu *vcpu, u32 access,
3322 u32 *error)
bbd9b64e
CO		 3323{
3324 void *data = val;
10589a46 3325 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3326
3327 while (bytes) {
1871c602 3328 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3329 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3330 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3331 int ret;
3332
10589a46
MT		 3333 if (gpa == UNMAPPED_GVA) {
3334 r = X86EMUL_PROPAGATE_FAULT;
3335 goto out;
3336 }
77c2002e 3337 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3338 if (ret < 0) {
c3cd7ffa 3339 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3340 goto out;
3341 }
bbd9b64e 3342
77c2002e
IE		 3343 bytes -= toread;
3344 data += toread;
3345 addr += toread;
bbd9b64e 3346 }
10589a46 3347out:
10589a46 3348 return r;
bbd9b64e 3349}
77c2002e 3350
1871c602
GN		 3351/* used for instruction fetching */
3352static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3353 struct kvm_vcpu *vcpu, u32 *error)
3354{
3355 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3356 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3357 access | PFERR_FETCH_MASK, error);
3358}
3359
3360static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3361 struct kvm_vcpu *vcpu, u32 *error)
3362{
3363 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3364 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3365 error);
3366}
3367
3368static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3369 struct kvm_vcpu *vcpu, u32 *error)
3370{
3371 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3372}
3373
7972995b 3374static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3375 unsigned int bytes,
7972995b 3376 struct kvm_vcpu *vcpu,
2dafc6c2 3377 u32 *error)
77c2002e
IE		 3378{
3379 void *data = val;
3380 int r = X86EMUL_CONTINUE;
3381
3382 while (bytes) {
7972995b
GN		 3383 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3384 PFERR_WRITE_MASK, error);
77c2002e
IE		 3385 unsigned offset = addr & (PAGE_SIZE-1);
3386 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3387 int ret;
3388
3389 if (gpa == UNMAPPED_GVA) {
3390 r = X86EMUL_PROPAGATE_FAULT;
3391 goto out;
3392 }
3393 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3394 if (ret < 0) {
c3cd7ffa 3395 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3396 goto out;
3397 }
3398
3399 bytes -= towrite;
3400 data += towrite;
3401 addr += towrite;
3402 }
3403out:
3404 return r;
3405}
3406
bbd9b64e
CO		 3407static int emulator_read_emulated(unsigned long addr,
3408 void *val,
3409 unsigned int bytes,
8fe681e9 3410 unsigned int *error_code,
bbd9b64e
CO		 3411 struct kvm_vcpu *vcpu)
3412{
bbd9b64e
CO		 3413 gpa_t gpa;
3414
3415 if (vcpu->mmio_read_completed) {
3416 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3417 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3418 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3419 vcpu->mmio_read_completed = 0;
3420 return X86EMUL_CONTINUE;
3421 }
3422
8fe681e9 3423 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3424
8fe681e9 3425 if (gpa == UNMAPPED_GVA)
1871c602 3426 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3427
3428 /* For APIC access vmexit */
3429 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3430 goto mmio;
3431
1871c602 3432 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3433 == X86EMUL_CONTINUE)
bbd9b64e 3434 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3435
3436mmio:
3437 /*
3438 * Is this MMIO handled locally?
3439 */
aec51dc4
AK		 3440 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3441 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3442 return X86EMUL_CONTINUE;
3443 }
aec51dc4
AK		 3444
3445 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3446
3447 vcpu->mmio_needed = 1;
411c35b7
GN		 3448 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3449 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3450 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3451 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3452
c3cd7ffa 3453 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3454}
3455
3200f405 3456int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3457 const void *val, int bytes)
bbd9b64e
CO		 3458{
3459 int ret;
3460
3461 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3462 if (ret < 0)
bbd9b64e 3463 return 0;
ad218f85 3464 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3465 return 1;
3466}
3467
3468static int emulator_write_emulated_onepage(unsigned long addr,
3469 const void *val,
3470 unsigned int bytes,
8fe681e9 3471 unsigned int *error_code,
bbd9b64e
CO		 3472 struct kvm_vcpu *vcpu)
3473{
10589a46
MT		 3474 gpa_t gpa;
3475
8fe681e9 3476 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3477
8fe681e9 3478 if (gpa == UNMAPPED_GVA)
bbd9b64e 3479 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3480
3481 /* For APIC access vmexit */
3482 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3483 goto mmio;
3484
3485 if (emulator_write_phys(vcpu, gpa, val, bytes))
3486 return X86EMUL_CONTINUE;
3487
3488mmio:
aec51dc4 3489 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3490 /*
3491 * Is this MMIO handled locally?
3492 */
bda9020e 3493 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3494 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3495
3496 vcpu->mmio_needed = 1;
411c35b7
GN		 3497 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3498 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3499 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3500 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3501 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3502
3503 return X86EMUL_CONTINUE;
3504}
3505
3506int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3507 const void *val,
3508 unsigned int bytes,
8fe681e9 3509 unsigned int *error_code,
8f6abd06 3510 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3511{
3512 /* Crossing a page boundary? */
3513 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3514 int rc, now;
3515
3516 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3517 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3518 vcpu);
bbd9b64e
CO		 3519 if (rc != X86EMUL_CONTINUE)
3520 return rc;
3521 addr += now;
3522 val += now;
3523 bytes -= now;
3524 }
8fe681e9
GN		 3525 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3526 vcpu);
bbd9b64e 3527}
bbd9b64e 3528
daea3e73
AK		 3529#define CMPXCHG_TYPE(t, ptr, old, new) \
3530 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3531
3532#ifdef CONFIG_X86_64
3533# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3534#else
3535# define CMPXCHG64(ptr, old, new) \
9749a6c0 3536 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3537#endif
3538
bbd9b64e
CO		 3539static int emulator_cmpxchg_emulated(unsigned long addr,
3540 const void *old,
3541 const void *new,
3542 unsigned int bytes,
8fe681e9 3543 unsigned int *error_code,
bbd9b64e
CO		 3544 struct kvm_vcpu *vcpu)
3545{
daea3e73
AK		 3546 gpa_t gpa;
3547 struct page *page;
3548 char *kaddr;
3549 bool exchanged;
2bacc55c 3550
daea3e73
AK		 3551 /* guests cmpxchg8b have to be emulated atomically */
3552 if (bytes > 8 || (bytes & (bytes - 1)))
3553 goto emul_write;
10589a46 3554
daea3e73 3555 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3556
daea3e73
AK		 3557 if (gpa == UNMAPPED_GVA ||
3558 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3559 goto emul_write;
2bacc55c 3560
daea3e73
AK		 3561 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3562 goto emul_write;
72dc67a6 3563
daea3e73 3564 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3565
daea3e73
AK		 3566 kaddr = kmap_atomic(page, KM_USER0);
3567 kaddr += offset_in_page(gpa);
3568 switch (bytes) {
3569 case 1:
3570 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3571 break;
3572 case 2:
3573 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3574 break;
3575 case 4:
3576 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3577 break;
3578 case 8:
3579 exchanged = CMPXCHG64(kaddr, old, new);
3580 break;
3581 default:
3582 BUG();
2bacc55c 3583 }
daea3e73
AK		 3584 kunmap_atomic(kaddr, KM_USER0);
3585 kvm_release_page_dirty(page);
3586
3587 if (!exchanged)
3588 return X86EMUL_CMPXCHG_FAILED;
3589
8f6abd06
GN		 3590 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3591
3592 return X86EMUL_CONTINUE;
4a5f48f6 3593
3200f405 3594emul_write:
daea3e73 3595 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3596
8fe681e9 3597 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3598}
3599
cf8f70bf
GN		 3600static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3601{
3602 /* TODO: String I/O for in kernel device */
3603 int r;
3604
3605 if (vcpu->arch.pio.in)
3606 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3607 vcpu->arch.pio.size, pd);
3608 else
3609 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3610 vcpu->arch.pio.port, vcpu->arch.pio.size,
3611 pd);
3612 return r;
3613}
3614
3615
3616static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3617 unsigned int count, struct kvm_vcpu *vcpu)
3618{
7972995b 3619 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3620 goto data_avail;
3621
3622 trace_kvm_pio(1, port, size, 1);
3623
3624 vcpu->arch.pio.port = port;
3625 vcpu->arch.pio.in = 1;
7972995b 3626 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3627 vcpu->arch.pio.size = size;
3628
3629 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3630 data_avail:
3631 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3632 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3633 return 1;
3634 }
3635
3636 vcpu->run->exit_reason = KVM_EXIT_IO;
3637 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3638 vcpu->run->io.size = size;
3639 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3640 vcpu->run->io.count = count;
3641 vcpu->run->io.port = port;
3642
3643 return 0;
3644}
3645
3646static int emulator_pio_out_emulated(int size, unsigned short port,
3647 const void *val, unsigned int count,
3648 struct kvm_vcpu *vcpu)
3649{
3650 trace_kvm_pio(0, port, size, 1);
3651
3652 vcpu->arch.pio.port = port;
3653 vcpu->arch.pio.in = 0;
7972995b 3654 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3655 vcpu->arch.pio.size = size;
3656
3657 memcpy(vcpu->arch.pio_data, val, size * count);
3658
3659 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3660 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3661 return 1;
3662 }
3663
3664 vcpu->run->exit_reason = KVM_EXIT_IO;
3665 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3666 vcpu->run->io.size = size;
3667 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3668 vcpu->run->io.count = count;
3669 vcpu->run->io.port = port;
3670
3671 return 0;
3672}
3673
bbd9b64e
CO		 3674static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3675{
3676 return kvm_x86_ops->get_segment_base(vcpu, seg);
3677}
3678
3679int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3680{
a7052897 3681 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3682 return X86EMUL_CONTINUE;
3683}
3684
f5f48ee1
SY		 3685int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3686{
3687 if (!need_emulate_wbinvd(vcpu))
3688 return X86EMUL_CONTINUE;
3689
3690 if (kvm_x86_ops->has_wbinvd_exit()) {
3691 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3692 wbinvd_ipi, NULL, 1);
3693 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3694 }
3695 wbinvd();
3696 return X86EMUL_CONTINUE;
3697}
3698EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3699
bbd9b64e
CO		 3700int emulate_clts(struct kvm_vcpu *vcpu)
3701{
4d4ec087 3702 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3703 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3704 return X86EMUL_CONTINUE;
3705}
3706
35aa5375 3707int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3708{
338dbc97 3709 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3710}
3711
35aa5375 3712int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3713{
338dbc97
GN		 3714
3715 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3716}
3717
52a46617 3718static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3719{
52a46617 3720 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3721}
3722
52a46617 3723static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3724{
52a46617
GN		 3725 unsigned long value;
3726
3727 switch (cr) {
3728 case 0:
3729 value = kvm_read_cr0(vcpu);
3730 break;
3731 case 2:
3732 value = vcpu->arch.cr2;
3733 break;
3734 case 3:
3735 value = vcpu->arch.cr3;
3736 break;
3737 case 4:
3738 value = kvm_read_cr4(vcpu);
3739 break;
3740 case 8:
3741 value = kvm_get_cr8(vcpu);
3742 break;
3743 default:
3744 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3745 return 0;
3746 }
3747
3748 return value;
3749}
3750
0f12244f 3751static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3752{
0f12244f
GN		 3753 int res = 0;
3754
52a46617
GN		 3755 switch (cr) {
3756 case 0:
49a9b07e 3757 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3758 break;
3759 case 2:
3760 vcpu->arch.cr2 = val;
3761 break;
3762 case 3:
2390218b 3763 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3764 break;
3765 case 4:
a83b29c6 3766 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3767 break;
3768 case 8:
0f12244f 3769 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3770 break;
3771 default:
3772 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3773 res = -1;
52a46617 3774 }
0f12244f
GN		 3775
3776 return res;
52a46617
GN		 3777}
3778
9c537244
GN		 3779static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3780{
3781 return kvm_x86_ops->get_cpl(vcpu);
3782}
3783
2dafc6c2
GN		 3784static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3785{
3786 kvm_x86_ops->get_gdt(vcpu, dt);
3787}
3788
5951c442
GN		 3789static unsigned long emulator_get_cached_segment_base(int seg,
3790 struct kvm_vcpu *vcpu)
3791{
3792 return get_segment_base(vcpu, seg);
3793}
3794
2dafc6c2
GN		 3795static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3796 struct kvm_vcpu *vcpu)
3797{
3798 struct kvm_segment var;
3799
3800 kvm_get_segment(vcpu, &var, seg);
3801
3802 if (var.unusable)
3803 return false;
3804
3805 if (var.g)
3806 var.limit >>= 12;
3807 set_desc_limit(desc, var.limit);
3808 set_desc_base(desc, (unsigned long)var.base);
3809 desc->type = var.type;
3810 desc->s = var.s;
3811 desc->dpl = var.dpl;
3812 desc->p = var.present;
3813 desc->avl = var.avl;
3814 desc->l = var.l;
3815 desc->d = var.db;
3816 desc->g = var.g;
3817
3818 return true;
3819}
3820
3821static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3822 struct kvm_vcpu *vcpu)
3823{
3824 struct kvm_segment var;
3825
3826 /* needed to preserve selector */
3827 kvm_get_segment(vcpu, &var, seg);
3828
3829 var.base = get_desc_base(desc);
3830 var.limit = get_desc_limit(desc);
3831 if (desc->g)
3832 var.limit = (var.limit << 12) | 0xfff;
3833 var.type = desc->type;
3834 var.present = desc->p;
3835 var.dpl = desc->dpl;
3836 var.db = desc->d;
3837 var.s = desc->s;
3838 var.l = desc->l;
3839 var.g = desc->g;
3840 var.avl = desc->avl;
3841 var.present = desc->p;
3842 var.unusable = !var.present;
3843 var.padding = 0;
3844
3845 kvm_set_segment(vcpu, &var, seg);
3846 return;
3847}
3848
3849static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3850{
3851 struct kvm_segment kvm_seg;
3852
3853 kvm_get_segment(vcpu, &kvm_seg, seg);
3854 return kvm_seg.selector;
3855}
3856
3857static void emulator_set_segment_selector(u16 sel, int seg,
3858 struct kvm_vcpu *vcpu)
3859{
3860 struct kvm_segment kvm_seg;
3861
3862 kvm_get_segment(vcpu, &kvm_seg, seg);
3863 kvm_seg.selector = sel;
3864 kvm_set_segment(vcpu, &kvm_seg, seg);
3865}
3866
14af3f3c 3867static struct x86_emulate_ops emulate_ops = {
1871c602 3868 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3869 .write_std = kvm_write_guest_virt_system,
1871c602 3870 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3871 .read_emulated = emulator_read_emulated,
3872 .write_emulated = emulator_write_emulated,
3873 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3874 .pio_in_emulated = emulator_pio_in_emulated,
3875 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3876 .get_cached_descriptor = emulator_get_cached_descriptor,
3877 .set_cached_descriptor = emulator_set_cached_descriptor,
3878 .get_segment_selector = emulator_get_segment_selector,
3879 .set_segment_selector = emulator_set_segment_selector,
5951c442 3880 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3881 .get_gdt = emulator_get_gdt,
52a46617
GN		 3882 .get_cr = emulator_get_cr,
3883 .set_cr = emulator_set_cr,
9c537244 3884 .cpl = emulator_get_cpl,
35aa5375
GN		 3885 .get_dr = emulator_get_dr,
3886 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3887 .set_msr = kvm_set_msr,
3888 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3889};
3890
5fdbf976
MT		 3891static void cache_all_regs(struct kvm_vcpu *vcpu)
3892{
3893 kvm_register_read(vcpu, VCPU_REGS_RAX);
3894 kvm_register_read(vcpu, VCPU_REGS_RSP);
3895 kvm_register_read(vcpu, VCPU_REGS_RIP);
3896 vcpu->arch.regs_dirty = ~0;
3897}
3898
95cb2295
GN		 3899static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
3900{
3901 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
3902 /*
3903 * an sti; sti; sequence only disable interrupts for the first
3904 * instruction. So, if the last instruction, be it emulated or
3905 * not, left the system with the INT_STI flag enabled, it
3906 * means that the last instruction is an sti. We should not
3907 * leave the flag on in this case. The same goes for mov ss
3908 */
3909 if (!(int_shadow & mask))
3910 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
3911}
3912
54b8486f
GN		 3913static void inject_emulated_exception(struct kvm_vcpu *vcpu)
3914{
3915 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3916 if (ctxt->exception == PF_VECTOR)
3917 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
3918 else if (ctxt->error_code_valid)
3919 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
3920 else
3921 kvm_queue_exception(vcpu, ctxt->exception);
3922}
3923
6d77dbfc
GN		 3924static int handle_emulation_failure(struct kvm_vcpu *vcpu)
3925{
6d77dbfc
GN		 3926 ++vcpu->stat.insn_emulation_fail;
3927 trace_kvm_emulate_insn_failed(vcpu);
3928 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3929 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3930 vcpu->run->internal.ndata = 0;
3931 kvm_queue_exception(vcpu, UD_VECTOR);
3932 return EMULATE_FAIL;
3933}
3934
a6f177ef
GN		 3935static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
3936{
3937 gpa_t gpa;
3938
68be0803
GN		 3939 if (tdp_enabled)
3940 return false;
3941
a6f177ef
GN		 3942 /*
3943 * if emulation was due to access to shadowed page table
3944 * and it failed try to unshadow page and re-entetr the
3945 * guest to let CPU execute the instruction.
3946 */
3947 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
3948 return true;
3949
3950 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
3951
3952 if (gpa == UNMAPPED_GVA)
3953 return true; /* let cpu generate fault */
3954
3955 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
3956 return true;
3957
3958 return false;
3959}
3960
bbd9b64e 3961int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3962 unsigned long cr2,
3963 u16 error_code,
571008da 3964 int emulation_type)
bbd9b64e 3965{
95cb2295 3966 int r;
4d2179e1 3967 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 3968
26eef70c 3969 kvm_clear_exception_queue(vcpu);
ad312c7c 3970 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3971 /*
56e82318 3972 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3973 * instead of direct ->regs accesses, can save hundred cycles
3974 * on Intel for instructions that don't read/change RSP, for
3975 * for example.
3976 */
3977 cache_all_regs(vcpu);
bbd9b64e 3978
571008da 3979 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3980 int cs_db, cs_l;
3981 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3982
ad312c7c 3983 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3984 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3985 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3986 vcpu->arch.emulate_ctxt.mode =
a0044755 3987 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3988 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3989 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3990 ? X86EMUL_MODE_PROT64 : cs_db
3991 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 3992 memset(c, 0, sizeof(struct decode_cache));
3993 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
95cb2295 3994 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 3995 vcpu->arch.emulate_ctxt.exception = -1;
bbd9b64e 3996
ad312c7c 3997 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3998 trace_kvm_emulate_insn_start(vcpu);
571008da 3999
0cb5762e
AP		 4000 /* Only allow emulation of specific instructions on #UD
4001 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4002 if (emulation_type & EMULTYPE_TRAP_UD) {
4003 if (!c->twobyte)
4004 return EMULATE_FAIL;
4005 switch (c->b) {
4006 case 0x01: /* VMMCALL */
4007 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4008 return EMULATE_FAIL;
4009 break;
4010 case 0x34: /* sysenter */
4011 case 0x35: /* sysexit */
4012 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4013 return EMULATE_FAIL;
4014 break;
4015 case 0x05: /* syscall */
4016 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4017 return EMULATE_FAIL;
4018 break;
4019 default:
4020 return EMULATE_FAIL;
4021 }
4022
4023 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4024 return EMULATE_FAIL;
4025 }
571008da 4026
f2b5756b 4027 ++vcpu->stat.insn_emulation;
bbd9b64e 4028 if (r) {
a6f177ef 4029 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4030 return EMULATE_DONE;
6d77dbfc
GN		 4031 if (emulation_type & EMULTYPE_SKIP)
4032 return EMULATE_FAIL;
4033 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4034 }
4035 }
4036
ba8afb6b
GN		 4037 if (emulation_type & EMULTYPE_SKIP) {
4038 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4039 return EMULATE_DONE;
4040 }
4041
4d2179e1
GN		 4042 /* this is needed for vmware backdor interface to work since it
4043 changes registers values during IO operation */
4044 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4045
5cd21917 4046restart:
ad312c7c 4047 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 4048
c3cd7ffa 4049 if (r) { /* emulation failed */
a6f177ef 4050 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4051 return EMULATE_DONE;
4052
6d77dbfc 4053 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4054 }
4055
95cb2295 4056 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
ef050dc0 4057 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4d2179e1 4058 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 4059 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
3457e419 4060
54b8486f
GN		 4061 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4062 inject_emulated_exception(vcpu);
4063 return EMULATE_DONE;
4064 }
4065
3457e419
GN		 4066 if (vcpu->arch.pio.count) {
4067 if (!vcpu->arch.pio.in)
4068 vcpu->arch.pio.count = 0;
4069 return EMULATE_DO_MMIO;
4070 }
4071
4072 if (vcpu->mmio_needed) {
4073 if (vcpu->mmio_is_write)
4074 vcpu->mmio_needed = 0;
4075 return EMULATE_DO_MMIO;
4076 }
4077
5cd21917
GN		 4078 if (vcpu->arch.emulate_ctxt.restart)
4079 goto restart;
f850e2e6 4080
bbd9b64e 4081 return EMULATE_DONE;
de7d789a 4082}
bbd9b64e 4083EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4084
cf8f70bf 4085int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4086{
cf8f70bf
GN		 4087 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4088 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4089 /* do not return to emulator after return from userspace */
7972995b 4090 vcpu->arch.pio.count = 0;
de7d789a
CO		 4091 return ret;
4092}
cf8f70bf 4093EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4094
c8076604
GH		 4095static void bounce_off(void *info)
4096{
4097 /* nothing */
4098}
4099
c8076604
GH		 4100static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4101 void *data)
4102{
4103 struct cpufreq_freqs *freq = data;
4104 struct kvm *kvm;
4105 struct kvm_vcpu *vcpu;
4106 int i, send_ipi = 0;
4107
c8076604
GH		 4108 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4109 return 0;
4110 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4111 return 0;
0cca7907 4112 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 4113
4114 spin_lock(&kvm_lock);
4115 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4116 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4117 if (vcpu->cpu != freq->cpu)
4118 continue;
4119 if (!kvm_request_guest_time_update(vcpu))
4120 continue;
4121 if (vcpu->cpu != smp_processor_id())
4122 send_ipi++;
4123 }
4124 }
4125 spin_unlock(&kvm_lock);
4126
4127 if (freq->old < freq->new && send_ipi) {
4128 /*
4129 * We upscale the frequency. Must make the guest
4130 * doesn't see old kvmclock values while running with
4131 * the new frequency, otherwise we risk the guest sees
4132 * time go backwards.
4133 *
4134 * In case we update the frequency for another cpu
4135 * (which might be in guest context) send an interrupt
4136 * to kick the cpu out of guest context. Next time
4137 * guest context is entered kvmclock will be updated,
4138 * so the guest will not see stale values.
4139 */
4140 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4141 }
4142 return 0;
4143}
4144
4145static struct notifier_block kvmclock_cpufreq_notifier_block = {
4146 .notifier_call = kvmclock_cpufreq_notifier
4147};
4148
b820cc0c
ZA		 4149static void kvm_timer_init(void)
4150{
4151 int cpu;
4152
b820cc0c 4153 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4154 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4155 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4156 for_each_online_cpu(cpu) {
4157 unsigned long khz = cpufreq_get(cpu);
4158 if (!khz)
4159 khz = tsc_khz;
4160 per_cpu(cpu_tsc_khz, cpu) = khz;
4161 }
0cca7907
ZA		 4162 } else {
4163 for_each_possible_cpu(cpu)
4164 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4165 }
4166}
4167
ff9d07a0
ZY		 4168static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4169
4170static int kvm_is_in_guest(void)
4171{
4172 return percpu_read(current_vcpu) != NULL;
4173}
4174
4175static int kvm_is_user_mode(void)
4176{
4177 int user_mode = 3;
dcf46b94 4178
ff9d07a0
ZY		 4179 if (percpu_read(current_vcpu))
4180 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4181
ff9d07a0
ZY		 4182 return user_mode != 0;
4183}
4184
4185static unsigned long kvm_get_guest_ip(void)
4186{
4187 unsigned long ip = 0;
dcf46b94 4188
ff9d07a0
ZY		 4189 if (percpu_read(current_vcpu))
4190 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4191
ff9d07a0
ZY		 4192 return ip;
4193}
4194
4195static struct perf_guest_info_callbacks kvm_guest_cbs = {
4196 .is_in_guest = kvm_is_in_guest,
4197 .is_user_mode = kvm_is_user_mode,
4198 .get_guest_ip = kvm_get_guest_ip,
4199};
4200
4201void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4202{
4203 percpu_write(current_vcpu, vcpu);
4204}
4205EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4206
4207void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4208{
4209 percpu_write(current_vcpu, NULL);
4210}
4211EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4212
f8c16bba 4213int kvm_arch_init(void *opaque)
043405e1 4214{
b820cc0c 4215 int r;
f8c16bba
ZX		 4216 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4217
f8c16bba
ZX		 4218 if (kvm_x86_ops) {
4219 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4220 r = -EEXIST;
4221 goto out;
f8c16bba
ZX		 4222 }
4223
4224 if (!ops->cpu_has_kvm_support()) {
4225 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4226 r = -EOPNOTSUPP;
4227 goto out;
f8c16bba
ZX		 4228 }
4229 if (ops->disabled_by_bios()) {
4230 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4231 r = -EOPNOTSUPP;
4232 goto out;
f8c16bba
ZX		 4233 }
4234
97db56ce
AK		 4235 r = kvm_mmu_module_init();
4236 if (r)
4237 goto out;
4238
4239 kvm_init_msr_list();
4240
f8c16bba 4241 kvm_x86_ops = ops;
56c6d28a 4242 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4243 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4244 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4245 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4246
b820cc0c 4247 kvm_timer_init();
c8076604 4248
ff9d07a0
ZY		 4249 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4250
2acf923e
DC		 4251 if (cpu_has_xsave)
4252 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4253
f8c16bba 4254 return 0;
56c6d28a
ZX		 4255
4256out:
56c6d28a 4257 return r;
043405e1 4258}
8776e519 4259
f8c16bba
ZX		 4260void kvm_arch_exit(void)
4261{
ff9d07a0
ZY		 4262 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4263
888d256e
JK		 4264 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4265 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4266 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4267 kvm_x86_ops = NULL;
56c6d28a
ZX		 4268 kvm_mmu_module_exit();
4269}
f8c16bba 4270
8776e519
HB		 4271int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4272{
4273 ++vcpu->stat.halt_exits;
4274 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4275 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4276 return 1;
4277 } else {
4278 vcpu->run->exit_reason = KVM_EXIT_HLT;
4279 return 0;
4280 }
4281}
4282EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4283
2f333bcb
MT		 4284static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4285 unsigned long a1)
4286{
4287 if (is_long_mode(vcpu))
4288 return a0;
4289 else
4290 return a0 | ((gpa_t)a1 << 32);
4291}
4292
55cd8e5a
GN		 4293int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4294{
4295 u64 param, ingpa, outgpa, ret;
4296 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4297 bool fast, longmode;
4298 int cs_db, cs_l;
4299
4300 /*
4301 * hypercall generates UD from non zero cpl and real mode
4302 * per HYPER-V spec
4303 */
3eeb3288 4304 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4305 kvm_queue_exception(vcpu, UD_VECTOR);
4306 return 0;
4307 }
4308
4309 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4310 longmode = is_long_mode(vcpu) && cs_l == 1;
4311
4312 if (!longmode) {
ccd46936
GN		 4313 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4314 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4315 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4316 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4317 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4318 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4319 }
4320#ifdef CONFIG_X86_64
4321 else {
4322 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4323 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4324 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4325 }
4326#endif
4327
4328 code = param & 0xffff;
4329 fast = (param >> 16) & 0x1;
4330 rep_cnt = (param >> 32) & 0xfff;
4331 rep_idx = (param >> 48) & 0xfff;
4332
4333 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4334
c25bc163
GN		 4335 switch (code) {
4336 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4337 kvm_vcpu_on_spin(vcpu);
4338 break;
4339 default:
4340 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4341 break;
4342 }
55cd8e5a
GN		 4343
4344 ret = res | (((u64)rep_done & 0xfff) << 32);
4345 if (longmode) {
4346 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4347 } else {
4348 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4349 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4350 }
4351
4352 return 1;
4353}
4354
8776e519
HB		 4355int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4356{
4357 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4358 int r = 1;
8776e519 4359
55cd8e5a
GN		 4360 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4361 return kvm_hv_hypercall(vcpu);
4362
5fdbf976
MT		 4363 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4364 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4365 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4366 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4367 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4368
229456fc 4369 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4370
8776e519
HB		 4371 if (!is_long_mode(vcpu)) {
4372 nr &= 0xFFFFFFFF;
4373 a0 &= 0xFFFFFFFF;
4374 a1 &= 0xFFFFFFFF;
4375 a2 &= 0xFFFFFFFF;
4376 a3 &= 0xFFFFFFFF;
4377 }
4378
07708c4a
JK		 4379 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4380 ret = -KVM_EPERM;
4381 goto out;
4382 }
4383
8776e519 4384 switch (nr) {
b93463aa
AK		 4385 case KVM_HC_VAPIC_POLL_IRQ:
4386 ret = 0;
4387 break;
2f333bcb
MT		 4388 case KVM_HC_MMU_OP:
4389 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4390 break;
8776e519
HB		 4391 default:
4392 ret = -KVM_ENOSYS;
4393 break;
4394 }
07708c4a 4395out:
5fdbf976 4396 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4397 ++vcpu->stat.hypercalls;
2f333bcb 4398 return r;
8776e519
HB		 4399}
4400EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4401
4402int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4403{
4404 char instruction[3];
5fdbf976 4405 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4406
8776e519
HB		 4407 /*
4408 * Blow out the MMU to ensure that no other VCPU has an active mapping
4409 * to ensure that the updated hypercall appears atomically across all
4410 * VCPUs.
4411 */
4412 kvm_mmu_zap_all(vcpu->kvm);
4413
8776e519 4414 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4415
8fe681e9 4416 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4417}
4418
8776e519
HB		 4419void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4420{
89a27f4d 4421 struct desc_ptr dt = { limit, base };
8776e519
HB		 4422
4423 kvm_x86_ops->set_gdt(vcpu, &dt);
4424}
4425
4426void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4427{
89a27f4d 4428 struct desc_ptr dt = { limit, base };
8776e519
HB		 4429
4430 kvm_x86_ops->set_idt(vcpu, &dt);
4431}
4432
07716717
DK		 4433static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4434{
ad312c7c
ZX		 4435 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4436 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4437
4438 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4439 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4440 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4441 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4442 if (ej->function == e->function) {
4443 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4444 return j;
4445 }
4446 }
4447 return 0; /* silence gcc, even though control never reaches here */
4448}
4449
4450/* find an entry with matching function, matching index (if needed), and that
4451 * should be read next (if it's stateful) */
4452static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4453 u32 function, u32 index)
4454{
4455 if (e->function != function)
4456 return 0;
4457 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4458 return 0;
4459 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4460 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4461 return 0;
4462 return 1;
4463}
4464
d8017474
AG		 4465struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4466 u32 function, u32 index)
8776e519
HB		 4467{
4468 int i;
d8017474 4469 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4470
ad312c7c 4471 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4472 struct kvm_cpuid_entry2 *e;
4473
ad312c7c 4474 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4475 if (is_matching_cpuid_entry(e, function, index)) {
4476 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4477 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4478 best = e;
4479 break;
4480 }
4481 /*
4482 * Both basic or both extended?
4483 */
4484 if (((e->function ^ function) & 0x80000000) == 0)
4485 if (!best || e->function > best->function)
4486 best = e;
4487 }
d8017474
AG		 4488 return best;
4489}
0e851880 4490EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4491
82725b20
DE		 4492int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4493{
4494 struct kvm_cpuid_entry2 *best;
4495
f7a71197
AK		 4496 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4497 if (!best || best->eax < 0x80000008)
4498 goto not_found;
82725b20
DE		 4499 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4500 if (best)
4501 return best->eax & 0xff;
f7a71197 4502not_found:
82725b20
DE		 4503 return 36;
4504}
4505
d8017474
AG		 4506void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4507{
4508 u32 function, index;
4509 struct kvm_cpuid_entry2 *best;
4510
4511 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4512 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4513 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4514 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4515 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4516 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4517 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4518 if (best) {
5fdbf976
MT		 4519 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4520 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4521 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4522 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4523 }
8776e519 4524 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4525 trace_kvm_cpuid(function,
4526 kvm_register_read(vcpu, VCPU_REGS_RAX),
4527 kvm_register_read(vcpu, VCPU_REGS_RBX),
4528 kvm_register_read(vcpu, VCPU_REGS_RCX),
4529 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4530}
4531EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4532
b6c7a5dc
HB		 4533/*
4534 * Check if userspace requested an interrupt window, and that the
4535 * interrupt window is open.
4536 *
4537 * No need to exit to userspace if we already have an interrupt queued.
4538 */
851ba692 4539static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4540{
8061823a 4541 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4542 vcpu->run->request_interrupt_window &&
5df56646 4543 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4544}
4545
851ba692 4546static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4547{
851ba692
AK		 4548 struct kvm_run *kvm_run = vcpu->run;
4549
91586a3b 4550 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4551 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4552 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4553 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4554 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4555 else
b6c7a5dc 4556 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4557 kvm_arch_interrupt_allowed(vcpu) &&
4558 !kvm_cpu_has_interrupt(vcpu) &&
4559 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4560}
4561
b93463aa
AK		 4562static void vapic_enter(struct kvm_vcpu *vcpu)
4563{
4564 struct kvm_lapic *apic = vcpu->arch.apic;
4565 struct page *page;
4566
4567 if (!apic || !apic->vapic_addr)
4568 return;
4569
4570 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4571
4572 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4573}
4574
4575static void vapic_exit(struct kvm_vcpu *vcpu)
4576{
4577 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4578 int idx;
b93463aa
AK		 4579
4580 if (!apic || !apic->vapic_addr)
4581 return;
4582
f656ce01 4583 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4584 kvm_release_page_dirty(apic->vapic_page);
4585 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4586 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4587}
4588
95ba8273
GN		 4589static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4590{
4591 int max_irr, tpr;
4592
4593 if (!kvm_x86_ops->update_cr8_intercept)
4594 return;
4595
88c808fd
AK		 4596 if (!vcpu->arch.apic)
4597 return;
4598
8db3baa2
GN		 4599 if (!vcpu->arch.apic->vapic_addr)
4600 max_irr = kvm_lapic_find_highest_irr(vcpu);
4601 else
4602 max_irr = -1;
95ba8273
GN		 4603
4604 if (max_irr != -1)
4605 max_irr >>= 4;
4606
4607 tpr = kvm_lapic_get_cr8(vcpu);
4608
4609 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4610}
4611
851ba692 4612static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4613{
4614 /* try to reinject previous events if any */
b59bb7bd 4615 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4616 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4617 vcpu->arch.exception.has_error_code,
4618 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4619 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4620 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4621 vcpu->arch.exception.error_code,
4622 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4623 return;
4624 }
4625
95ba8273
GN		 4626 if (vcpu->arch.nmi_injected) {
4627 kvm_x86_ops->set_nmi(vcpu);
4628 return;
4629 }
4630
4631 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4632 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4633 return;
4634 }
4635
4636 /* try to inject new event if pending */
4637 if (vcpu->arch.nmi_pending) {
4638 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4639 vcpu->arch.nmi_pending = false;
4640 vcpu->arch.nmi_injected = true;
4641 kvm_x86_ops->set_nmi(vcpu);
4642 }
4643 } else if (kvm_cpu_has_interrupt(vcpu)) {
4644 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4645 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4646 false);
4647 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4648 }
4649 }
4650}
4651
2acf923e
DC		 4652static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4653{
4654 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4655 !vcpu->guest_xcr0_loaded) {
4656 /* kvm_set_xcr() also depends on this */
4657 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4658 vcpu->guest_xcr0_loaded = 1;
4659 }
4660}
4661
4662static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4663{
4664 if (vcpu->guest_xcr0_loaded) {
4665 if (vcpu->arch.xcr0 != host_xcr0)
4666 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4667 vcpu->guest_xcr0_loaded = 0;
4668 }
4669}
4670
851ba692 4671static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4672{
4673 int r;
6a8b1d13 4674 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4675 vcpu->run->request_interrupt_window;
b6c7a5dc 4676
3e007509 4677 if (vcpu->requests) {
a8eeb04a 4678 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4679 kvm_mmu_unload(vcpu);
a8eeb04a 4680 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4681 __kvm_migrate_timers(vcpu);
a8eeb04a 4682 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu))
c8076604 4683 kvm_write_guest_time(vcpu);
a8eeb04a 4684 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4685 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4686 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4687 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4688 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4689 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4690 r = 0;
4691 goto out;
4692 }
a8eeb04a 4693 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 4694 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4695 r = 0;
4696 goto out;
4697 }
a8eeb04a 4698 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 4699 vcpu->fpu_active = 0;
4700 kvm_x86_ops->fpu_deactivate(vcpu);
4701 }
2f52d58c 4702 }
b93463aa 4703
3e007509
AK		 4704 r = kvm_mmu_reload(vcpu);
4705 if (unlikely(r))
4706 goto out;
4707
b6c7a5dc
HB		 4708 preempt_disable();
4709
4710 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4711 if (vcpu->fpu_active)
4712 kvm_load_guest_fpu(vcpu);
2acf923e 4713 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4714
d94e1dc9
AK		 4715 atomic_set(&vcpu->guest_mode, 1);
4716 smp_wmb();
b6c7a5dc 4717
d94e1dc9 4718 local_irq_disable();
32f88400 4719
d94e1dc9
AK		 4720 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4721 || need_resched() || signal_pending(current)) {
4722 atomic_set(&vcpu->guest_mode, 0);
4723 smp_wmb();
6c142801
AK		 4724 local_irq_enable();
4725 preempt_enable();
4726 r = 1;
4727 goto out;
4728 }
4729
851ba692 4730 inject_pending_event(vcpu);
b6c7a5dc 4731
6a8b1d13
GN		 4732 /* enable NMI/IRQ window open exits if needed */
4733 if (vcpu->arch.nmi_pending)
4734 kvm_x86_ops->enable_nmi_window(vcpu);
4735 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4736 kvm_x86_ops->enable_irq_window(vcpu);
4737
95ba8273 4738 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4739 update_cr8_intercept(vcpu);
4740 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4741 }
b93463aa 4742
f656ce01 4743 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4744
b6c7a5dc
HB		 4745 kvm_guest_enter();
4746
42dbaa5a 4747 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4748 set_debugreg(0, 7);
4749 set_debugreg(vcpu->arch.eff_db[0], 0);
4750 set_debugreg(vcpu->arch.eff_db[1], 1);
4751 set_debugreg(vcpu->arch.eff_db[2], 2);
4752 set_debugreg(vcpu->arch.eff_db[3], 3);
4753 }
b6c7a5dc 4754
229456fc 4755 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4756 kvm_x86_ops->run(vcpu);
b6c7a5dc 4757
24f1e32c
FW		 4758 /*
4759 * If the guest has used debug registers, at least dr7
4760 * will be disabled while returning to the host.
4761 * If we don't have active breakpoints in the host, we don't
4762 * care about the messed up debug address registers. But if
4763 * we have some of them active, restore the old state.
4764 */
59d8eb53 4765 if (hw_breakpoint_active())
24f1e32c 4766 hw_breakpoint_restore();
42dbaa5a 4767
d94e1dc9
AK		 4768 atomic_set(&vcpu->guest_mode, 0);
4769 smp_wmb();
b6c7a5dc
HB		 4770 local_irq_enable();
4771
4772 ++vcpu->stat.exits;
4773
4774 /*
4775 * We must have an instruction between local_irq_enable() and
4776 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4777 * the interrupt shadow. The stat.exits increment will do nicely.
4778 * But we need to prevent reordering, hence this barrier():
4779 */
4780 barrier();
4781
4782 kvm_guest_exit();
4783
4784 preempt_enable();
4785
f656ce01 4786 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4787
b6c7a5dc
HB		 4788 /*
4789 * Profile KVM exit RIPs:
4790 */
4791 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4792 unsigned long rip = kvm_rip_read(vcpu);
4793 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4794 }
4795
298101da 4796
b93463aa
AK		 4797 kvm_lapic_sync_from_vapic(vcpu);
4798
851ba692 4799 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4800out:
4801 return r;
4802}
b6c7a5dc 4803
09cec754 4804
851ba692 4805static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4806{
4807 int r;
f656ce01 4808 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4809
4810 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4811 pr_debug("vcpu %d received sipi with vector # %x\n",
4812 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4813 kvm_lapic_reset(vcpu);
5f179287 4814 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4815 if (r)
4816 return r;
4817 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4818 }
4819
f656ce01 4820 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4821 vapic_enter(vcpu);
4822
4823 r = 1;
4824 while (r > 0) {
af2152f5 4825 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4826 r = vcpu_enter_guest(vcpu);
d7690175 4827 else {
f656ce01 4828 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4829 kvm_vcpu_block(vcpu);
f656ce01 4830 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 4831 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 4832 {
4833 switch(vcpu->arch.mp_state) {
4834 case KVM_MP_STATE_HALTED:
d7690175 4835 vcpu->arch.mp_state =
09cec754
GN		 4836 KVM_MP_STATE_RUNNABLE;
4837 case KVM_MP_STATE_RUNNABLE:
4838 break;
4839 case KVM_MP_STATE_SIPI_RECEIVED:
4840 default:
4841 r = -EINTR;
4842 break;
4843 }
4844 }
d7690175
MT		 4845 }
4846
09cec754
GN		 4847 if (r <= 0)
4848 break;
4849
4850 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4851 if (kvm_cpu_has_pending_timer(vcpu))
4852 kvm_inject_pending_timer_irqs(vcpu);
4853
851ba692 4854 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4855 r = -EINTR;
851ba692 4856 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4857 ++vcpu->stat.request_irq_exits;
4858 }
4859 if (signal_pending(current)) {
4860 r = -EINTR;
851ba692 4861 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4862 ++vcpu->stat.signal_exits;
4863 }
4864 if (need_resched()) {
f656ce01 4865 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4866 kvm_resched(vcpu);
f656ce01 4867 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4868 }
b6c7a5dc
HB		 4869 }
4870
f656ce01 4871 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4872
b93463aa
AK		 4873 vapic_exit(vcpu);
4874
b6c7a5dc
HB		 4875 return r;
4876}
4877
4878int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4879{
4880 int r;
4881 sigset_t sigsaved;
4882
ac9f6dc0
AK		 4883 if (vcpu->sigset_active)
4884 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4885
a4535290 4886 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4887 kvm_vcpu_block(vcpu);
d7690175 4888 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4889 r = -EAGAIN;
4890 goto out;
b6c7a5dc
HB		 4891 }
4892
b6c7a5dc
HB		 4893 /* re-sync apic's tpr */
4894 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4895 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4896
92bf9748
GN		 4897 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4898 vcpu->arch.emulate_ctxt.restart) {
4899 if (vcpu->mmio_needed) {
4900 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4901 vcpu->mmio_read_completed = 1;
4902 vcpu->mmio_needed = 0;
b6c7a5dc 4903 }
f656ce01 4904 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4905 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4906 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 4907 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 4908 r = 0;
4909 goto out;
4910 }
4911 }
5fdbf976
MT		 4912 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4913 kvm_register_write(vcpu, VCPU_REGS_RAX,
4914 kvm_run->hypercall.ret);
b6c7a5dc 4915
851ba692 4916 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4917
4918out:
f1d86e46 4919 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4920 if (vcpu->sigset_active)
4921 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4922
b6c7a5dc
HB		 4923 return r;
4924}
4925
4926int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4927{
5fdbf976
MT		 4928 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4929 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4930 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4931 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4932 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4933 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4934 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4935 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4936#ifdef CONFIG_X86_64
5fdbf976
MT		 4937 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4938 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4939 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4940 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4941 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4942 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4943 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4944 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4945#endif
4946
5fdbf976 4947 regs->rip = kvm_rip_read(vcpu);
91586a3b 4948 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 4949
b6c7a5dc
HB		 4950 return 0;
4951}
4952
4953int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4954{
5fdbf976
MT		 4955 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4956 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4957 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4958 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4959 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4960 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4961 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4962 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4963#ifdef CONFIG_X86_64
5fdbf976
MT		 4964 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4965 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4966 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4967 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4968 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4969 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4970 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4971 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4972#endif
4973
5fdbf976 4974 kvm_rip_write(vcpu, regs->rip);
91586a3b 4975 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4976
b4f14abd
JK		 4977 vcpu->arch.exception.pending = false;
4978
b6c7a5dc
HB		 4979 return 0;
4980}
4981
b6c7a5dc
HB		 4982void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4983{
4984 struct kvm_segment cs;
4985
3e6e0aab 4986 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4987 *db = cs.db;
4988 *l = cs.l;
4989}
4990EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4991
4992int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4993 struct kvm_sregs *sregs)
4994{
89a27f4d 4995 struct desc_ptr dt;
b6c7a5dc 4996
3e6e0aab
GT		 4997 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4998 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4999 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5000 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5001 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5002 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5003
3e6e0aab
GT		 5004 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5005 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5006
5007 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5008 sregs->idt.limit = dt.size;
5009 sregs->idt.base = dt.address;
b6c7a5dc 5010 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5011 sregs->gdt.limit = dt.size;
5012 sregs->gdt.base = dt.address;
b6c7a5dc 5013
4d4ec087 5014 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5015 sregs->cr2 = vcpu->arch.cr2;
5016 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5017 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5018 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5019 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5020 sregs->apic_base = kvm_get_apic_base(vcpu);
5021
923c61bb 5022 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5023
36752c9b 5024 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5025 set_bit(vcpu->arch.interrupt.nr,
5026 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5027
b6c7a5dc
HB		 5028 return 0;
5029}
5030
62d9f0db
MT		 5031int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5032 struct kvm_mp_state *mp_state)
5033{
62d9f0db 5034 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5035 return 0;
5036}
5037
5038int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5039 struct kvm_mp_state *mp_state)
5040{
62d9f0db 5041 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5042 return 0;
5043}
5044
e269fb21
JK		 5045int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5046 bool has_error_code, u32 error_code)
b6c7a5dc 5047{
4d2179e1 5048 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
ceffb459
GN		 5049 int cs_db, cs_l, ret;
5050 cache_all_regs(vcpu);
37817f29 5051
ceffb459 5052 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 5053
ceffb459
GN		 5054 vcpu->arch.emulate_ctxt.vcpu = vcpu;
5055 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
5056 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
5057 vcpu->arch.emulate_ctxt.mode =
5058 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5059 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
5060 ? X86EMUL_MODE_VM86 : cs_l
5061 ? X86EMUL_MODE_PROT64 : cs_db
5062 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 5063 memset(c, 0, sizeof(struct decode_cache));
5064 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
c697518a 5065
ceffb459 5066 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 5067 tss_selector, reason, has_error_code,
5068 error_code);
c697518a 5069
c697518a 5070 if (ret)
19d04437 5071 return EMULATE_FAIL;
37817f29 5072
4d2179e1 5073 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5074 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5075 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5076 return EMULATE_DONE;
37817f29
IE		 5077}
5078EXPORT_SYMBOL_GPL(kvm_task_switch);
5079
b6c7a5dc
HB		 5080int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5081 struct kvm_sregs *sregs)
5082{
5083 int mmu_reset_needed = 0;
923c61bb 5084 int pending_vec, max_bits;
89a27f4d 5085 struct desc_ptr dt;
b6c7a5dc 5086
89a27f4d
GN		 5087 dt.size = sregs->idt.limit;
5088 dt.address = sregs->idt.base;
b6c7a5dc 5089 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5090 dt.size = sregs->gdt.limit;
5091 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5092 kvm_x86_ops->set_gdt(vcpu, &dt);
5093
ad312c7c
ZX		 5094 vcpu->arch.cr2 = sregs->cr2;
5095 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5096 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5097
2d3ad1f4 5098 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5099
f6801dff 5100 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5101 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5102 kvm_set_apic_base(vcpu, sregs->apic_base);
5103
4d4ec087 5104 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5105 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5106 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5107
fc78f519 5108 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5109 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5110 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5111 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5112 mmu_reset_needed = 1;
5113 }
b6c7a5dc
HB		 5114
5115 if (mmu_reset_needed)
5116 kvm_mmu_reset_context(vcpu);
5117
923c61bb
GN		 5118 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5119 pending_vec = find_first_bit(
5120 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5121 if (pending_vec < max_bits) {
66fd3f7f 5122 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5123 pr_debug("Set back pending irq %d\n", pending_vec);
5124 if (irqchip_in_kernel(vcpu->kvm))
5125 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5126 }
5127
3e6e0aab
GT		 5128 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5129 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5130 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5131 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5132 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5133 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5134
3e6e0aab
GT		 5135 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5136 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5137
5f0269f5
ME		 5138 update_cr8_intercept(vcpu);
5139
9c3e4aab 5140 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5141 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5142 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5143 !is_protmode(vcpu))
9c3e4aab
MT		 5144 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5145
b6c7a5dc
HB		 5146 return 0;
5147}
5148
d0bfb940
JK		 5149int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5150 struct kvm_guest_debug *dbg)
b6c7a5dc 5151{
355be0b9 5152 unsigned long rflags;
ae675ef0 5153 int i, r;
b6c7a5dc 5154
4f926bf2
JK		 5155 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5156 r = -EBUSY;
5157 if (vcpu->arch.exception.pending)
2122ff5e 5158 goto out;
4f926bf2
JK		 5159 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5160 kvm_queue_exception(vcpu, DB_VECTOR);
5161 else
5162 kvm_queue_exception(vcpu, BP_VECTOR);
5163 }
5164
91586a3b
JK		 5165 /*
5166 * Read rflags as long as potentially injected trace flags are still
5167 * filtered out.
5168 */
5169 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5170
5171 vcpu->guest_debug = dbg->control;
5172 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5173 vcpu->guest_debug = 0;
5174
5175 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5176 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5177 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5178 vcpu->arch.switch_db_regs =
5179 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5180 } else {
5181 for (i = 0; i < KVM_NR_DB_REGS; i++)
5182 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5183 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5184 }
5185
f92653ee
JK		 5186 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5187 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5188 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5189
91586a3b
JK		 5190 /*
5191 * Trigger an rflags update that will inject or remove the trace
5192 * flags.
5193 */
5194 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5195
355be0b9 5196 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5197
4f926bf2 5198 r = 0;
d0bfb940 5199
2122ff5e 5200out:
b6c7a5dc
HB		 5201
5202 return r;
5203}
5204
8b006791
ZX		 5205/*
5206 * Translate a guest virtual address to a guest physical address.
5207 */
5208int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5209 struct kvm_translation *tr)
5210{
5211 unsigned long vaddr = tr->linear_address;
5212 gpa_t gpa;
f656ce01 5213 int idx;
8b006791 5214
f656ce01 5215 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5216 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5217 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5218 tr->physical_address = gpa;
5219 tr->valid = gpa != UNMAPPED_GVA;
5220 tr->writeable = 1;
5221 tr->usermode = 0;
8b006791
ZX		 5222
5223 return 0;
5224}
5225
d0752060
HB		 5226int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5227{
98918833
SY		 5228 struct i387_fxsave_struct *fxsave =
5229 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5230
d0752060
HB		 5231 memcpy(fpu->fpr, fxsave->st_space, 128);
5232 fpu->fcw = fxsave->cwd;
5233 fpu->fsw = fxsave->swd;
5234 fpu->ftwx = fxsave->twd;
5235 fpu->last_opcode = fxsave->fop;
5236 fpu->last_ip = fxsave->rip;
5237 fpu->last_dp = fxsave->rdp;
5238 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5239
d0752060
HB		 5240 return 0;
5241}
5242
5243int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5244{
98918833
SY		 5245 struct i387_fxsave_struct *fxsave =
5246 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5247
d0752060
HB		 5248 memcpy(fxsave->st_space, fpu->fpr, 128);
5249 fxsave->cwd = fpu->fcw;
5250 fxsave->swd = fpu->fsw;
5251 fxsave->twd = fpu->ftwx;
5252 fxsave->fop = fpu->last_opcode;
5253 fxsave->rip = fpu->last_ip;
5254 fxsave->rdp = fpu->last_dp;
5255 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5256
d0752060
HB		 5257 return 0;
5258}
5259
10ab25cd 5260int fx_init(struct kvm_vcpu *vcpu)
d0752060 5261{
10ab25cd
JK		 5262 int err;
5263
5264 err = fpu_alloc(&vcpu->arch.guest_fpu);
5265 if (err)
5266 return err;
5267
98918833 5268 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5269
2acf923e
DC		 5270 /*
5271 * Ensure guest xcr0 is valid for loading
5272 */
5273 vcpu->arch.xcr0 = XSTATE_FP;
5274
ad312c7c 5275 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5276
5277 return 0;
d0752060
HB		 5278}
5279EXPORT_SYMBOL_GPL(fx_init);
5280
98918833
SY		 5281static void fx_free(struct kvm_vcpu *vcpu)
5282{
5283 fpu_free(&vcpu->arch.guest_fpu);
5284}
5285
d0752060
HB		 5286void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5287{
2608d7a1 5288 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5289 return;
5290
2acf923e
DC		 5291 /*
5292 * Restore all possible states in the guest,
5293 * and assume host would use all available bits.
5294 * Guest xcr0 would be loaded later.
5295 */
5296 kvm_put_guest_xcr0(vcpu);
d0752060 5297 vcpu->guest_fpu_loaded = 1;
7cf30855 5298 unlazy_fpu(current);
98918833 5299 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5300 trace_kvm_fpu(1);
d0752060 5301}
d0752060
HB		 5302
5303void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5304{
2acf923e
DC		 5305 kvm_put_guest_xcr0(vcpu);
5306
d0752060
HB		 5307 if (!vcpu->guest_fpu_loaded)
5308 return;
5309
5310 vcpu->guest_fpu_loaded = 0;
98918833 5311 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5312 ++vcpu->stat.fpu_reload;
a8eeb04a 5313 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5314 trace_kvm_fpu(0);
d0752060 5315}
e9b11c17
ZX		 5316
5317void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5318{
7f1ea208
JR		 5319 if (vcpu->arch.time_page) {
5320 kvm_release_page_dirty(vcpu->arch.time_page);
5321 vcpu->arch.time_page = NULL;
5322 }
5323
f5f48ee1 5324 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5325 fx_free(vcpu);
e9b11c17
ZX		 5326 kvm_x86_ops->vcpu_free(vcpu);
5327}
5328
5329struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5330 unsigned int id)
5331{
26e5215f
AK		 5332 return kvm_x86_ops->vcpu_create(kvm, id);
5333}
e9b11c17 5334
26e5215f
AK		 5335int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5336{
5337 int r;
e9b11c17 5338
0bed3b56 5339 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5340 vcpu_load(vcpu);
5341 r = kvm_arch_vcpu_reset(vcpu);
5342 if (r == 0)
5343 r = kvm_mmu_setup(vcpu);
5344 vcpu_put(vcpu);
5345 if (r < 0)
5346 goto free_vcpu;
5347
26e5215f 5348 return 0;
e9b11c17
ZX		 5349free_vcpu:
5350 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5351 return r;
e9b11c17
ZX		 5352}
5353
d40ccc62 5354void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5355{
5356 vcpu_load(vcpu);
5357 kvm_mmu_unload(vcpu);
5358 vcpu_put(vcpu);
5359
98918833 5360 fx_free(vcpu);
e9b11c17
ZX		 5361 kvm_x86_ops->vcpu_free(vcpu);
5362}
5363
5364int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5365{
448fa4a9
JK		 5366 vcpu->arch.nmi_pending = false;
5367 vcpu->arch.nmi_injected = false;
5368
42dbaa5a
JK		 5369 vcpu->arch.switch_db_regs = 0;
5370 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5371 vcpu->arch.dr6 = DR6_FIXED_1;
5372 vcpu->arch.dr7 = DR7_FIXED_1;
5373
e9b11c17
ZX		 5374 return kvm_x86_ops->vcpu_reset(vcpu);
5375}
5376
10474ae8 5377int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5378{
0cca7907
ZA		 5379 /*
5380 * Since this may be called from a hotplug notifcation,
5381 * we can't get the CPU frequency directly.
5382 */
5383 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5384 int cpu = raw_smp_processor_id();
5385 per_cpu(cpu_tsc_khz, cpu) = 0;
5386 }
18863bdd
AK		 5387
5388 kvm_shared_msr_cpu_online();
5389
10474ae8 5390 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5391}
5392
5393void kvm_arch_hardware_disable(void *garbage)
5394{
5395 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5396 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5397}
5398
5399int kvm_arch_hardware_setup(void)
5400{
5401 return kvm_x86_ops->hardware_setup();
5402}
5403
5404void kvm_arch_hardware_unsetup(void)
5405{
5406 kvm_x86_ops->hardware_unsetup();
5407}
5408
5409void kvm_arch_check_processor_compat(void *rtn)
5410{
5411 kvm_x86_ops->check_processor_compatibility(rtn);
5412}
5413
5414int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5415{
5416 struct page *page;
5417 struct kvm *kvm;
5418 int r;
5419
5420 BUG_ON(vcpu->kvm == NULL);
5421 kvm = vcpu->kvm;
5422
ad312c7c 5423 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5424 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5425 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5426 else
a4535290 5427 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5428
5429 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5430 if (!page) {
5431 r = -ENOMEM;
5432 goto fail;
5433 }
ad312c7c 5434 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5435
5436 r = kvm_mmu_create(vcpu);
5437 if (r < 0)
5438 goto fail_free_pio_data;
5439
5440 if (irqchip_in_kernel(kvm)) {
5441 r = kvm_create_lapic(vcpu);
5442 if (r < 0)
5443 goto fail_mmu_destroy;
5444 }
5445
890ca9ae
HY		 5446 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5447 GFP_KERNEL);
5448 if (!vcpu->arch.mce_banks) {
5449 r = -ENOMEM;
443c39bc 5450 goto fail_free_lapic;
890ca9ae
HY		 5451 }
5452 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5453
f5f48ee1
SY		 5454 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5455 goto fail_free_mce_banks;
5456
e9b11c17 5457 return 0;
f5f48ee1
SY		 5458fail_free_mce_banks:
5459 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5460fail_free_lapic:
5461 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5462fail_mmu_destroy:
5463 kvm_mmu_destroy(vcpu);
5464fail_free_pio_data:
ad312c7c 5465 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5466fail:
5467 return r;
5468}
5469
5470void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5471{
f656ce01
MT		 5472 int idx;
5473
36cb93fd 5474 kfree(vcpu->arch.mce_banks);
e9b11c17 5475 kvm_free_lapic(vcpu);
f656ce01 5476 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5477 kvm_mmu_destroy(vcpu);
f656ce01 5478 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5479 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5480}
d19a9cd2
ZX		 5481
5482struct kvm *kvm_arch_create_vm(void)
5483{
5484 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5485
5486 if (!kvm)
5487 return ERR_PTR(-ENOMEM);
5488
f05e70ac 5489 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5490 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5491
5550af4d
SY		 5492 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5493 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5494
53f658b3
MT		 5495 rdtscll(kvm->arch.vm_init_tsc);
5496
d19a9cd2
ZX		 5497 return kvm;
5498}
5499
5500static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5501{
5502 vcpu_load(vcpu);
5503 kvm_mmu_unload(vcpu);
5504 vcpu_put(vcpu);
5505}
5506
5507static void kvm_free_vcpus(struct kvm *kvm)
5508{
5509 unsigned int i;
988a2cae 5510 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5511
5512 /*
5513 * Unpin any mmu pages first.
5514 */
988a2cae
GN		 5515 kvm_for_each_vcpu(i, vcpu, kvm)
5516 kvm_unload_vcpu_mmu(vcpu);
5517 kvm_for_each_vcpu(i, vcpu, kvm)
5518 kvm_arch_vcpu_free(vcpu);
5519
5520 mutex_lock(&kvm->lock);
5521 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5522 kvm->vcpus[i] = NULL;
d19a9cd2 5523
988a2cae
GN		 5524 atomic_set(&kvm->online_vcpus, 0);
5525 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5526}
5527
ad8ba2cd
SY		 5528void kvm_arch_sync_events(struct kvm *kvm)
5529{
ba4cef31 5530 kvm_free_all_assigned_devices(kvm);
aea924f6 5531 kvm_free_pit(kvm);
ad8ba2cd
SY		 5532}
5533
d19a9cd2
ZX		 5534void kvm_arch_destroy_vm(struct kvm *kvm)
5535{
6eb55818 5536 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5537 kfree(kvm->arch.vpic);
5538 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5539 kvm_free_vcpus(kvm);
5540 kvm_free_physmem(kvm);
3d45830c
AK		 5541 if (kvm->arch.apic_access_page)
5542 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5543 if (kvm->arch.ept_identity_pagetable)
5544 put_page(kvm->arch.ept_identity_pagetable);
64749204 5545 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5546 kfree(kvm);
5547}
0de10343 5548
f7784b8e
MT		 5549int kvm_arch_prepare_memory_region(struct kvm *kvm,
5550 struct kvm_memory_slot *memslot,
0de10343 5551 struct kvm_memory_slot old,
f7784b8e 5552 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5553 int user_alloc)
5554{
f7784b8e 5555 int npages = memslot->npages;
7ac77099
AK		 5556 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5557
5558 /* Prevent internal slot pages from being moved by fork()/COW. */
5559 if (memslot->id >= KVM_MEMORY_SLOTS)
5560 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5561
5562 /*To keep backward compatibility with older userspace,
5563 *x86 needs to hanlde !user_alloc case.
5564 */
5565 if (!user_alloc) {
5566 if (npages && !old.rmap) {
604b38ac
AA		 5567 unsigned long userspace_addr;
5568
72dc67a6 5569 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5570 userspace_addr = do_mmap(NULL, 0,
5571 npages * PAGE_SIZE,
5572 PROT_READ | PROT_WRITE,
7ac77099 5573 map_flags,
604b38ac 5574 0);
72dc67a6 5575 up_write(&current->mm->mmap_sem);
0de10343 5576
604b38ac
AA		 5577 if (IS_ERR((void *)userspace_addr))
5578 return PTR_ERR((void *)userspace_addr);
5579
604b38ac 5580 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5581 }
5582 }
5583
f7784b8e
MT		 5584
5585 return 0;
5586}
5587
5588void kvm_arch_commit_memory_region(struct kvm *kvm,
5589 struct kvm_userspace_memory_region *mem,
5590 struct kvm_memory_slot old,
5591 int user_alloc)
5592{
5593
5594 int npages = mem->memory_size >> PAGE_SHIFT;
5595
5596 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5597 int ret;
5598
5599 down_write(&current->mm->mmap_sem);
5600 ret = do_munmap(current->mm, old.userspace_addr,
5601 old.npages * PAGE_SIZE);
5602 up_write(&current->mm->mmap_sem);
5603 if (ret < 0)
5604 printk(KERN_WARNING
5605 "kvm_vm_ioctl_set_memory_region: "
5606 "failed to munmap memory\n");
5607 }
5608
7c8a83b7 5609 spin_lock(&kvm->mmu_lock);
f05e70ac 5610 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5611 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5612 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5613 }
5614
5615 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5616 spin_unlock(&kvm->mmu_lock);
0de10343 5617}
1d737c8a 5618
34d4cb8f
MT		 5619void kvm_arch_flush_shadow(struct kvm *kvm)
5620{
5621 kvm_mmu_zap_all(kvm);
8986ecc0 5622 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5623}
5624
1d737c8a
ZX		 5625int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5626{
a4535290 5627 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5628 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5629 || vcpu->arch.nmi_pending ||
5630 (kvm_arch_interrupt_allowed(vcpu) &&
5631 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5632}
5736199a 5633
5736199a
ZX		 5634void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5635{
32f88400
MT		 5636 int me;
5637 int cpu = vcpu->cpu;
5736199a
ZX		 5638
5639 if (waitqueue_active(&vcpu->wq)) {
5640 wake_up_interruptible(&vcpu->wq);
5641 ++vcpu->stat.halt_wakeup;
5642 }
32f88400
MT		 5643
5644 me = get_cpu();
5645 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5646 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5647 smp_send_reschedule(cpu);
e9571ed5 5648 put_cpu();
5736199a 5649}
78646121
GN		 5650
5651int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5652{
5653 return kvm_x86_ops->interrupt_allowed(vcpu);
5654}
229456fc 5655
f92653ee
JK		 5656bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5657{
5658 unsigned long current_rip = kvm_rip_read(vcpu) +
5659 get_segment_base(vcpu, VCPU_SREG_CS);
5660
5661 return current_rip == linear_rip;
5662}
5663EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5664
94fe45da
JK		 5665unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5666{
5667 unsigned long rflags;
5668
5669 rflags = kvm_x86_ops->get_rflags(vcpu);
5670 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5671 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5672 return rflags;
5673}
5674EXPORT_SYMBOL_GPL(kvm_get_rflags);
5675
5676void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5677{
5678 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5679 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5680 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5681 kvm_x86_ops->set_rflags(vcpu, rflags);
5682}
5683EXPORT_SYMBOL_GPL(kvm_set_rflags);
5684
229456fc
MT		 5685EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5686EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5692EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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