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KVM: SVM: Fix wrong interrupt injection in enable_irq_windows
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
aec51dc4
AK		 43#include <trace/events/kvm.h>
44#undef TRACE_INCLUDE_FILE
229456fc
MT		 45#define CREATE_TRACE_POINTS
46#include "trace.h"
043405e1 47
24f1e32c 48#include <asm/debugreg.h>
043405e1 49#include <asm/uaccess.h>
d825ed0a 50#include <asm/msr.h>
a5f61300 51#include <asm/desc.h>
0bed3b56 52#include <asm/mtrr.h>
890ca9ae 53#include <asm/mce.h>
043405e1 54
313a3dc7 55#define MAX_IO_MSRS 256
a03490ed
CO		 56#define CR0_RESERVED_BITS \
57 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
58 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
59 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
60#define CR4_RESERVED_BITS \
61 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
62 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
63 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
64 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
65
66#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 67
68#define KVM_MAX_MCE_BANKS 32
69#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
77#else
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
18863bdd
AK		 94#define KVM_NR_SHARED_MSRS 16
95
96struct kvm_shared_msrs_global {
97 int nr;
2bf78fa7 98 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
2bf78fa7
SY		 104 struct kvm_shared_msr_values {
105 u64 host;
106 u64 curr;
107 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
111static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
112
417bc304 113struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 114 { "pf_fixed", VCPU_STAT(pf_fixed) },
115 { "pf_guest", VCPU_STAT(pf_guest) },
116 { "tlb_flush", VCPU_STAT(tlb_flush) },
117 { "invlpg", VCPU_STAT(invlpg) },
118 { "exits", VCPU_STAT(exits) },
119 { "io_exits", VCPU_STAT(io_exits) },
120 { "mmio_exits", VCPU_STAT(mmio_exits) },
121 { "signal_exits", VCPU_STAT(signal_exits) },
122 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 123 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 124 { "halt_exits", VCPU_STAT(halt_exits) },
125 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 126 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 127 { "request_irq", VCPU_STAT(request_irq_exits) },
128 { "irq_exits", VCPU_STAT(irq_exits) },
129 { "host_state_reload", VCPU_STAT(host_state_reload) },
130 { "efer_reload", VCPU_STAT(efer_reload) },
131 { "fpu_reload", VCPU_STAT(fpu_reload) },
132 { "insn_emulation", VCPU_STAT(insn_emulation) },
133 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 134 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 135 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 136 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
137 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
138 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
139 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
140 { "mmu_flooded", VM_STAT(mmu_flooded) },
141 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 142 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 143 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 144 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 145 { "largepages", VM_STAT(lpages) },
417bc304
HB		 146 { NULL }
147};
148
18863bdd
AK		 149static void kvm_on_user_return(struct user_return_notifier *urn)
150{
151 unsigned slot;
18863bdd
AK		 152 struct kvm_shared_msrs *locals
153 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 154 struct kvm_shared_msr_values *values;
18863bdd
AK		 155
156 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 157 values = &locals->values[slot];
158 if (values->host != values->curr) {
159 wrmsrl(shared_msrs_global.msrs[slot], values->host);
160 values->curr = values->host;
18863bdd
AK		 161 }
162 }
163 locals->registered = false;
164 user_return_notifier_unregister(urn);
165}
166
2bf78fa7 167static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 168{
2bf78fa7 169 struct kvm_shared_msrs *smsr;
18863bdd
AK		 170 u64 value;
171
2bf78fa7
SY		 172 smsr = &__get_cpu_var(shared_msrs);
173 /* only read, and nobody should modify it at this time,
174 * so don't need lock */
175 if (slot >= shared_msrs_global.nr) {
176 printk(KERN_ERR "kvm: invalid MSR slot!");
177 return;
178 }
179 rdmsrl_safe(msr, &value);
180 smsr->values[slot].host = value;
181 smsr->values[slot].curr = value;
182}
183
184void kvm_define_shared_msr(unsigned slot, u32 msr)
185{
18863bdd
AK		 186 if (slot >= shared_msrs_global.nr)
187 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 188 shared_msrs_global.msrs[slot] = msr;
189 /* we need ensured the shared_msr_global have been updated */
190 smp_wmb();
18863bdd
AK		 191}
192EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
193
194static void kvm_shared_msr_cpu_online(void)
195{
196 unsigned i;
18863bdd
AK		 197
198 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 199 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 200}
201
d5696725 202void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 203{
204 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
205
2bf78fa7 206 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 207 return;
2bf78fa7
SY		 208 smsr->values[slot].curr = value;
209 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 210 if (!smsr->registered) {
211 smsr->urn.on_user_return = kvm_on_user_return;
212 user_return_notifier_register(&smsr->urn);
213 smsr->registered = true;
214 }
215}
216EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
217
3548bab5
AK		 218static void drop_user_return_notifiers(void *ignore)
219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
222 if (smsr->registered)
223 kvm_on_user_return(&smsr->urn);
224}
225
5fb76f9b
CO		 226unsigned long segment_base(u16 selector)
227{
89a27f4d 228 struct desc_ptr gdt;
a5f61300 229 struct desc_struct *d;
5fb76f9b
CO		 230 unsigned long table_base;
231 unsigned long v;
232
233 if (selector == 0)
234 return 0;
235
b792c344 236 kvm_get_gdt(&gdt);
89a27f4d 237 table_base = gdt.address;
5fb76f9b
CO		 238
239 if (selector & 4) { /* from ldt */
b792c344 240 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 241
5fb76f9b
CO		 242 table_base = segment_base(ldt_selector);
243 }
a5f61300 244 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 245 v = get_desc_base(d);
5fb76f9b 246#ifdef CONFIG_X86_64
a5f61300
AK		 247 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
248 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 249#endif
250 return v;
251}
252EXPORT_SYMBOL_GPL(segment_base);
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
256 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 257 return vcpu->arch.apic_base;
6866b83e 258 else
ad312c7c 259 return vcpu->arch.apic_base;
6866b83e
CO		 260}
261EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262
263void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
264{
265 /* TODO: reserve bits check */
266 if (irqchip_in_kernel(vcpu->kvm))
267 kvm_lapic_set_base(vcpu, data);
268 else
ad312c7c 269 vcpu->arch.apic_base = data;
6866b83e
CO		 270}
271EXPORT_SYMBOL_GPL(kvm_set_apic_base);
272
3fd28fce
ED		 273#define EXCPT_BENIGN 0
274#define EXCPT_CONTRIBUTORY 1
275#define EXCPT_PF 2
276
277static int exception_class(int vector)
278{
279 switch (vector) {
280 case PF_VECTOR:
281 return EXCPT_PF;
282 case DE_VECTOR:
283 case TS_VECTOR:
284 case NP_VECTOR:
285 case SS_VECTOR:
286 case GP_VECTOR:
287 return EXCPT_CONTRIBUTORY;
288 default:
289 break;
290 }
291 return EXCPT_BENIGN;
292}
293
294static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
295 unsigned nr, bool has_error, u32 error_code)
296{
297 u32 prev_nr;
298 int class1, class2;
299
300 if (!vcpu->arch.exception.pending) {
301 queue:
302 vcpu->arch.exception.pending = true;
303 vcpu->arch.exception.has_error_code = has_error;
304 vcpu->arch.exception.nr = nr;
305 vcpu->arch.exception.error_code = error_code;
306 return;
307 }
308
309 /* to check exception */
310 prev_nr = vcpu->arch.exception.nr;
311 if (prev_nr == DF_VECTOR) {
312 /* triple fault -> shutdown */
313 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
314 return;
315 }
316 class1 = exception_class(prev_nr);
317 class2 = exception_class(nr);
318 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
319 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
320 /* generate double fault per SDM Table 5-5 */
321 vcpu->arch.exception.pending = true;
322 vcpu->arch.exception.has_error_code = true;
323 vcpu->arch.exception.nr = DF_VECTOR;
324 vcpu->arch.exception.error_code = 0;
325 } else
326 /* replace previous exception with a new one in a hope
327 that instruction re-execution will regenerate lost
328 exception */
329 goto queue;
330}
331
298101da
AK		 332void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
333{
3fd28fce 334 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 335}
336EXPORT_SYMBOL_GPL(kvm_queue_exception);
337
c3c91fee
AK		 338void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
339 u32 error_code)
340{
341 ++vcpu->stat.pf_guest;
ad312c7c 342 vcpu->arch.cr2 = addr;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
3419ffc8
SY		 346void kvm_inject_nmi(struct kvm_vcpu *vcpu)
347{
348 vcpu->arch.nmi_pending = 1;
349}
350EXPORT_SYMBOL_GPL(kvm_inject_nmi);
351
298101da
AK		 352void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
353{
3fd28fce 354 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 355}
356EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
357
0a79b009
AK		 358/*
359 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
360 * a #GP and return false.
361 */
362bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 363{
0a79b009
AK		 364 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
365 return true;
366 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
367 return false;
298101da 368}
0a79b009 369EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 370
a03490ed
CO		 371/*
372 * Load the pae pdptrs. Return true is they are all valid.
373 */
374int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
375{
376 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
377 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
378 int i;
379 int ret;
ad312c7c 380 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 381
a03490ed
CO		 382 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
383 offset * sizeof(u64), sizeof(pdpte));
384 if (ret < 0) {
385 ret = 0;
386 goto out;
387 }
388 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 389 if (is_present_gpte(pdpte[i]) &&
20c466b5 390 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 391 ret = 0;
392 goto out;
393 }
394 }
395 ret = 1;
396
ad312c7c 397 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_avail);
400 __set_bit(VCPU_EXREG_PDPTR,
401 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 402out:
a03490ed
CO		 403
404 return ret;
405}
cc4b6871 406EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 407
d835dfec
AK		 408static bool pdptrs_changed(struct kvm_vcpu *vcpu)
409{
ad312c7c 410 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 411 bool changed = true;
412 int r;
413
414 if (is_long_mode(vcpu) || !is_pae(vcpu))
415 return false;
416
6de4f3ad
AK		 417 if (!test_bit(VCPU_EXREG_PDPTR,
418 (unsigned long *)&vcpu->arch.regs_avail))
419 return true;
420
ad312c7c 421 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 422 if (r < 0)
423 goto out;
ad312c7c 424 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 425out:
d835dfec
AK		 426
427 return changed;
428}
429
2d3ad1f4 430void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 431{
f9a48e6a
AK		 432 cr0 |= X86_CR0_ET;
433
ab344828
GN		 434#ifdef CONFIG_X86_64
435 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 442
443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 444 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 445 return;
446 }
447
448 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 449 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 450 return;
451 }
452
453 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
454#ifdef CONFIG_X86_64
f6801dff 455 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 456 int cs_db, cs_l;
457
458 if (!is_pae(vcpu)) {
c1a5d4f9 459 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 460 return;
461 }
462 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
463 if (cs_l) {
c1a5d4f9 464 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 465 return;
466
467 }
468 } else
469#endif
ad312c7c 470 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 471 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 472 return;
473 }
474
475 }
476
477 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 478 vcpu->arch.cr0 = cr0;
a03490ed 479
a03490ed 480 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 481 return;
482}
2d3ad1f4 483EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 484
2d3ad1f4 485void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 486{
4d4ec087 487 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 488}
2d3ad1f4 489EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 490
2d3ad1f4 491void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 492{
fc78f519 493 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 494 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
495
a03490ed 496 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 498 return;
499 }
500
501 if (is_long_mode(vcpu)) {
502 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 504 return;
505 }
a2edf57f
AK		 506 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
507 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 508 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 510 return;
511 }
512
513 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 514 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 515 return;
516 }
517 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 518 vcpu->arch.cr4 = cr4;
5a41accd 519 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 520 kvm_mmu_reset_context(vcpu);
a03490ed 521}
2d3ad1f4 522EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 523
2d3ad1f4 524void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 525{
ad312c7c 526 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 527 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 528 kvm_mmu_flush_tlb(vcpu);
529 return;
530 }
531
a03490ed
CO		 532 if (is_long_mode(vcpu)) {
533 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 534 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 535 return;
536 }
537 } else {
538 if (is_pae(vcpu)) {
539 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 540 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 541 return;
542 }
543 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 544 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 545 return;
546 }
547 }
548 /*
549 * We don't check reserved bits in nonpae mode, because
550 * this isn't enforced, and VMware depends on this.
551 */
552 }
553
a03490ed
CO		 554 /*
555 * Does the new cr3 value map to physical memory? (Note, we
556 * catch an invalid cr3 even in real-mode, because it would
557 * cause trouble later on when we turn on paging anyway.)
558 *
559 * A real CPU would silently accept an invalid cr3 and would
560 * attempt to use it - with largely undefined (and often hard
561 * to debug) behavior on the guest side.
562 */
563 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 564 kvm_inject_gp(vcpu, 0);
a03490ed 565 else {
ad312c7c
ZX		 566 vcpu->arch.cr3 = cr3;
567 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 568 }
a03490ed 569}
2d3ad1f4 570EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 571
2d3ad1f4 572void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 573{
574 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 575 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 576 return;
577 }
578 if (irqchip_in_kernel(vcpu->kvm))
579 kvm_lapic_set_tpr(vcpu, cr8);
580 else
ad312c7c 581 vcpu->arch.cr8 = cr8;
a03490ed 582}
2d3ad1f4 583EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 584
2d3ad1f4 585unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 586{
587 if (irqchip_in_kernel(vcpu->kvm))
588 return kvm_lapic_get_cr8(vcpu);
589 else
ad312c7c 590 return vcpu->arch.cr8;
a03490ed 591}
2d3ad1f4 592EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 593
d8017474
AG		 594static inline u32 bit(int bitno)
595{
596 return 1 << (bitno & 31);
597}
598
043405e1
CO		 599/*
600 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
601 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
602 *
603 * This list is modified at module load time to reflect the
e3267cbb
GC		 604 * capabilities of the host cpu. This capabilities test skips MSRs that are
605 * kvm-specific. Those are put in the beginning of the list.
043405e1 606 */
e3267cbb 607
10388a07 608#define KVM_SAVE_MSRS_BEGIN 5
043405e1 609static u32 msrs_to_save[] = {
e3267cbb 610 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 611 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 612 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 613 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
614 MSR_K6_STAR,
615#ifdef CONFIG_X86_64
616 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
617#endif
e3267cbb 618 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 619};
620
621static unsigned num_msrs_to_save;
622
623static u32 emulated_msrs[] = {
624 MSR_IA32_MISC_ENABLE,
625};
626
15c4a640
CO		 627static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
628{
f2b4b7dd 629 if (efer & efer_reserved_bits) {
c1a5d4f9 630 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 631 return;
632 }
633
634 if (is_paging(vcpu)
f6801dff 635 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 636 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 637 return;
638 }
639
1b2fd70c
AG		 640 if (efer & EFER_FFXSR) {
641 struct kvm_cpuid_entry2 *feat;
642
643 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
644 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 645 kvm_inject_gp(vcpu, 0);
646 return;
647 }
648 }
649
d8017474
AG		 650 if (efer & EFER_SVME) {
651 struct kvm_cpuid_entry2 *feat;
652
653 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
654 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 655 kvm_inject_gp(vcpu, 0);
656 return;
657 }
658 }
659
15c4a640
CO		 660 kvm_x86_ops->set_efer(vcpu, efer);
661
662 efer &= ~EFER_LMA;
f6801dff 663 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 664
f6801dff 665 vcpu->arch.efer = efer;
9645bb56
AK		 666
667 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
668 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 669}
670
f2b4b7dd
JR		 671void kvm_enable_efer_bits(u64 mask)
672{
673 efer_reserved_bits &= ~mask;
674}
675EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
676
677
15c4a640
CO		 678/*
679 * Writes msr value into into the appropriate "register".
680 * Returns 0 on success, non-0 otherwise.
681 * Assumes vcpu_load() was already called.
682 */
683int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
684{
685 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
686}
687
313a3dc7
CO		 688/*
689 * Adapt set_msr() to msr_io()'s calling convention
690 */
691static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
692{
693 return kvm_set_msr(vcpu, index, *data);
694}
695
18068523
GOC		 696static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
697{
698 static int version;
50d0a0f9 699 struct pvclock_wall_clock wc;
923de3cf 700 struct timespec boot;
18068523
GOC		 701
702 if (!wall_clock)
703 return;
704
705 version++;
706
18068523
GOC		 707 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
708
50d0a0f9
GH		 709 /*
710 * The guest calculates current wall clock time by adding
711 * system time (updated by kvm_write_guest_time below) to the
712 * wall clock specified here. guest system time equals host
713 * system time for us, thus we must fill in host boot time here.
714 */
923de3cf 715 getboottime(&boot);
50d0a0f9
GH		 716
717 wc.sec = boot.tv_sec;
718 wc.nsec = boot.tv_nsec;
719 wc.version = version;
18068523
GOC		 720
721 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
722
723 version++;
724 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 725}
726
50d0a0f9
GH		 727static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
728{
729 uint32_t quotient, remainder;
730
731 /* Don't try to replace with do_div(), this one calculates
732 * "(dividend << 32) / divisor" */
733 __asm__ ( "divl %4"
734 : "=a" (quotient), "=d" (remainder)
735 : "0" (0), "1" (dividend), "r" (divisor) );
736 return quotient;
737}
738
739static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
740{
741 uint64_t nsecs = 1000000000LL;
742 int32_t shift = 0;
743 uint64_t tps64;
744 uint32_t tps32;
745
746 tps64 = tsc_khz * 1000LL;
747 while (tps64 > nsecs*2) {
748 tps64 >>= 1;
749 shift--;
750 }
751
752 tps32 = (uint32_t)tps64;
753 while (tps32 <= (uint32_t)nsecs) {
754 tps32 <<= 1;
755 shift++;
756 }
757
758 hv_clock->tsc_shift = shift;
759 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
760
761 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 762 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 763 hv_clock->tsc_to_system_mul);
764}
765
c8076604
GH		 766static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
767
18068523
GOC		 768static void kvm_write_guest_time(struct kvm_vcpu *v)
769{
770 struct timespec ts;
771 unsigned long flags;
772 struct kvm_vcpu_arch *vcpu = &v->arch;
773 void *shared_kaddr;
463656c0 774 unsigned long this_tsc_khz;
18068523
GOC		 775
776 if ((!vcpu->time_page))
777 return;
778
463656c0
AK		 779 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
780 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
781 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
782 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 783 }
463656c0 784 put_cpu_var(cpu_tsc_khz);
50d0a0f9 785
18068523
GOC		 786 /* Keep irq disabled to prevent changes to the clock */
787 local_irq_save(flags);
af24a4e4 788 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 789 ktime_get_ts(&ts);
923de3cf 790 monotonic_to_bootbased(&ts);
18068523
GOC		 791 local_irq_restore(flags);
792
793 /* With all the info we got, fill in the values */
794
795 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 796 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
797
18068523
GOC		 798 /*
799 * The interface expects us to write an even number signaling that the
800 * update is finished. Since the guest won't see the intermediate
50d0a0f9 801 * state, we just increase by 2 at the end.
18068523 802 */
50d0a0f9 803 vcpu->hv_clock.version += 2;
18068523
GOC		 804
805 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
806
807 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 808 sizeof(vcpu->hv_clock));
18068523
GOC		 809
810 kunmap_atomic(shared_kaddr, KM_USER0);
811
812 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
813}
814
c8076604
GH		 815static int kvm_request_guest_time_update(struct kvm_vcpu *v)
816{
817 struct kvm_vcpu_arch *vcpu = &v->arch;
818
819 if (!vcpu->time_page)
820 return 0;
821 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
822 return 1;
823}
824
9ba075a6
AK		 825static bool msr_mtrr_valid(unsigned msr)
826{
827 switch (msr) {
828 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
829 case MSR_MTRRfix64K_00000:
830 case MSR_MTRRfix16K_80000:
831 case MSR_MTRRfix16K_A0000:
832 case MSR_MTRRfix4K_C0000:
833 case MSR_MTRRfix4K_C8000:
834 case MSR_MTRRfix4K_D0000:
835 case MSR_MTRRfix4K_D8000:
836 case MSR_MTRRfix4K_E0000:
837 case MSR_MTRRfix4K_E8000:
838 case MSR_MTRRfix4K_F0000:
839 case MSR_MTRRfix4K_F8000:
840 case MSR_MTRRdefType:
841 case MSR_IA32_CR_PAT:
842 return true;
843 case 0x2f8:
844 return true;
845 }
846 return false;
847}
848
d6289b93
MT		 849static bool valid_pat_type(unsigned t)
850{
851 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
852}
853
854static bool valid_mtrr_type(unsigned t)
855{
856 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
857}
858
859static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
860{
861 int i;
862
863 if (!msr_mtrr_valid(msr))
864 return false;
865
866 if (msr == MSR_IA32_CR_PAT) {
867 for (i = 0; i < 8; i++)
868 if (!valid_pat_type((data >> (i * 8)) & 0xff))
869 return false;
870 return true;
871 } else if (msr == MSR_MTRRdefType) {
872 if (data & ~0xcff)
873 return false;
874 return valid_mtrr_type(data & 0xff);
875 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
876 for (i = 0; i < 8 ; i++)
877 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
878 return false;
879 return true;
880 }
881
882 /* variable MTRRs */
883 return valid_mtrr_type(data & 0xff);
884}
885
9ba075a6
AK		 886static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
887{
0bed3b56
SY		 888 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
889
d6289b93 890 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 891 return 1;
892
0bed3b56
SY		 893 if (msr == MSR_MTRRdefType) {
894 vcpu->arch.mtrr_state.def_type = data;
895 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
896 } else if (msr == MSR_MTRRfix64K_00000)
897 p[0] = data;
898 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
899 p[1 + msr - MSR_MTRRfix16K_80000] = data;
900 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
901 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
902 else if (msr == MSR_IA32_CR_PAT)
903 vcpu->arch.pat = data;
904 else { /* Variable MTRRs */
905 int idx, is_mtrr_mask;
906 u64 *pt;
907
908 idx = (msr - 0x200) / 2;
909 is_mtrr_mask = msr - 0x200 - 2 * idx;
910 if (!is_mtrr_mask)
911 pt =
912 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
913 else
914 pt =
915 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
916 *pt = data;
917 }
918
919 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 920 return 0;
921}
15c4a640 922
890ca9ae 923static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 924{
890ca9ae
HY		 925 u64 mcg_cap = vcpu->arch.mcg_cap;
926 unsigned bank_num = mcg_cap & 0xff;
927
15c4a640 928 switch (msr) {
15c4a640 929 case MSR_IA32_MCG_STATUS:
890ca9ae 930 vcpu->arch.mcg_status = data;
15c4a640 931 break;
c7ac679c 932 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 933 if (!(mcg_cap & MCG_CTL_P))
934 return 1;
935 if (data != 0 && data != ~(u64)0)
936 return -1;
937 vcpu->arch.mcg_ctl = data;
938 break;
939 default:
940 if (msr >= MSR_IA32_MC0_CTL &&
941 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
942 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 943 /* only 0 or all 1s can be written to IA32_MCi_CTL
944 * some Linux kernels though clear bit 10 in bank 4 to
945 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
946 * this to avoid an uncatched #GP in the guest
947 */
890ca9ae 948 if ((offset & 0x3) == 0 &&
114be429 949 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 950 return -1;
951 vcpu->arch.mce_banks[offset] = data;
952 break;
953 }
954 return 1;
955 }
956 return 0;
957}
958
ffde22ac
ES		 959static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
960{
961 struct kvm *kvm = vcpu->kvm;
962 int lm = is_long_mode(vcpu);
963 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
964 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
965 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
966 : kvm->arch.xen_hvm_config.blob_size_32;
967 u32 page_num = data & ~PAGE_MASK;
968 u64 page_addr = data & PAGE_MASK;
969 u8 *page;
970 int r;
971
972 r = -E2BIG;
973 if (page_num >= blob_size)
974 goto out;
975 r = -ENOMEM;
976 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
977 if (!page)
978 goto out;
979 r = -EFAULT;
980 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
981 goto out_free;
982 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
983 goto out_free;
984 r = 0;
985out_free:
986 kfree(page);
987out:
988 return r;
989}
990
55cd8e5a
GN		 991static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
992{
993 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
994}
995
996static bool kvm_hv_msr_partition_wide(u32 msr)
997{
998 bool r = false;
999 switch (msr) {
1000 case HV_X64_MSR_GUEST_OS_ID:
1001 case HV_X64_MSR_HYPERCALL:
1002 r = true;
1003 break;
1004 }
1005
1006 return r;
1007}
1008
1009static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1010{
1011 struct kvm *kvm = vcpu->kvm;
1012
1013 switch (msr) {
1014 case HV_X64_MSR_GUEST_OS_ID:
1015 kvm->arch.hv_guest_os_id = data;
1016 /* setting guest os id to zero disables hypercall page */
1017 if (!kvm->arch.hv_guest_os_id)
1018 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1019 break;
1020 case HV_X64_MSR_HYPERCALL: {
1021 u64 gfn;
1022 unsigned long addr;
1023 u8 instructions[4];
1024
1025 /* if guest os id is not set hypercall should remain disabled */
1026 if (!kvm->arch.hv_guest_os_id)
1027 break;
1028 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1029 kvm->arch.hv_hypercall = data;
1030 break;
1031 }
1032 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1033 addr = gfn_to_hva(kvm, gfn);
1034 if (kvm_is_error_hva(addr))
1035 return 1;
1036 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1037 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1038 if (copy_to_user((void __user *)addr, instructions, 4))
1039 return 1;
1040 kvm->arch.hv_hypercall = data;
1041 break;
1042 }
1043 default:
1044 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1045 "data 0x%llx\n", msr, data);
1046 return 1;
1047 }
1048 return 0;
1049}
1050
1051static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1052{
10388a07
GN		 1053 switch (msr) {
1054 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1055 unsigned long addr;
55cd8e5a 1056
10388a07
GN		 1057 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1058 vcpu->arch.hv_vapic = data;
1059 break;
1060 }
1061 addr = gfn_to_hva(vcpu->kvm, data >>
1062 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1063 if (kvm_is_error_hva(addr))
1064 return 1;
1065 if (clear_user((void __user *)addr, PAGE_SIZE))
1066 return 1;
1067 vcpu->arch.hv_vapic = data;
1068 break;
1069 }
1070 case HV_X64_MSR_EOI:
1071 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1072 case HV_X64_MSR_ICR:
1073 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1074 case HV_X64_MSR_TPR:
1075 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1076 default:
1077 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1078 "data 0x%llx\n", msr, data);
1079 return 1;
1080 }
1081
1082 return 0;
55cd8e5a
GN		 1083}
1084
15c4a640
CO		 1085int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1086{
1087 switch (msr) {
15c4a640
CO		 1088 case MSR_EFER:
1089 set_efer(vcpu, data);
1090 break;
8f1589d9
AP		 1091 case MSR_K7_HWCR:
1092 data &= ~(u64)0x40; /* ignore flush filter disable */
1093 if (data != 0) {
1094 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1095 data);
1096 return 1;
1097 }
15c4a640 1098 break;
f7c6d140
AP		 1099 case MSR_FAM10H_MMIO_CONF_BASE:
1100 if (data != 0) {
1101 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1102 "0x%llx\n", data);
1103 return 1;
1104 }
15c4a640 1105 break;
c323c0e5 1106 case MSR_AMD64_NB_CFG:
c7ac679c 1107 break;
b5e2fec0
AG		 1108 case MSR_IA32_DEBUGCTLMSR:
1109 if (!data) {
1110 /* We support the non-activated case already */
1111 break;
1112 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1113 /* Values other than LBR and BTF are vendor-specific,
1114 thus reserved and should throw a #GP */
1115 return 1;
1116 }
1117 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1118 __func__, data);
1119 break;
15c4a640
CO		 1120 case MSR_IA32_UCODE_REV:
1121 case MSR_IA32_UCODE_WRITE:
61a6bd67 1122 case MSR_VM_HSAVE_PA:
6098ca93 1123 case MSR_AMD64_PATCH_LOADER:
15c4a640 1124 break;
9ba075a6
AK		 1125 case 0x200 ... 0x2ff:
1126 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1127 case MSR_IA32_APICBASE:
1128 kvm_set_apic_base(vcpu, data);
1129 break;
0105d1a5
GN		 1130 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1131 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1132 case MSR_IA32_MISC_ENABLE:
ad312c7c 1133 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1134 break;
18068523
GOC		 1135 case MSR_KVM_WALL_CLOCK:
1136 vcpu->kvm->arch.wall_clock = data;
1137 kvm_write_wall_clock(vcpu->kvm, data);
1138 break;
1139 case MSR_KVM_SYSTEM_TIME: {
1140 if (vcpu->arch.time_page) {
1141 kvm_release_page_dirty(vcpu->arch.time_page);
1142 vcpu->arch.time_page = NULL;
1143 }
1144
1145 vcpu->arch.time = data;
1146
1147 /* we verify if the enable bit is set... */
1148 if (!(data & 1))
1149 break;
1150
1151 /* ...but clean it before doing the actual write */
1152 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1153
18068523
GOC		 1154 vcpu->arch.time_page =
1155 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1156
1157 if (is_error_page(vcpu->arch.time_page)) {
1158 kvm_release_page_clean(vcpu->arch.time_page);
1159 vcpu->arch.time_page = NULL;
1160 }
1161
c8076604 1162 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1163 break;
1164 }
890ca9ae
HY		 1165 case MSR_IA32_MCG_CTL:
1166 case MSR_IA32_MCG_STATUS:
1167 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1168 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1169
1170 /* Performance counters are not protected by a CPUID bit,
1171 * so we should check all of them in the generic path for the sake of
1172 * cross vendor migration.
1173 * Writing a zero into the event select MSRs disables them,
1174 * which we perfectly emulate ;-). Any other value should be at least
1175 * reported, some guests depend on them.
1176 */
1177 case MSR_P6_EVNTSEL0:
1178 case MSR_P6_EVNTSEL1:
1179 case MSR_K7_EVNTSEL0:
1180 case MSR_K7_EVNTSEL1:
1181 case MSR_K7_EVNTSEL2:
1182 case MSR_K7_EVNTSEL3:
1183 if (data != 0)
1184 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1185 "0x%x data 0x%llx\n", msr, data);
1186 break;
1187 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1188 * so we ignore writes to make it happy.
1189 */
1190 case MSR_P6_PERFCTR0:
1191 case MSR_P6_PERFCTR1:
1192 case MSR_K7_PERFCTR0:
1193 case MSR_K7_PERFCTR1:
1194 case MSR_K7_PERFCTR2:
1195 case MSR_K7_PERFCTR3:
1196 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1197 "0x%x data 0x%llx\n", msr, data);
1198 break;
55cd8e5a
GN		 1199 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1200 if (kvm_hv_msr_partition_wide(msr)) {
1201 int r;
1202 mutex_lock(&vcpu->kvm->lock);
1203 r = set_msr_hyperv_pw(vcpu, msr, data);
1204 mutex_unlock(&vcpu->kvm->lock);
1205 return r;
1206 } else
1207 return set_msr_hyperv(vcpu, msr, data);
1208 break;
15c4a640 1209 default:
ffde22ac
ES		 1210 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1211 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1212 if (!ignore_msrs) {
1213 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1214 msr, data);
1215 return 1;
1216 } else {
1217 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1218 msr, data);
1219 break;
1220 }
15c4a640
CO		 1221 }
1222 return 0;
1223}
1224EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1225
1226
1227/*
1228 * Reads an msr value (of 'msr_index') into 'pdata'.
1229 * Returns 0 on success, non-0 otherwise.
1230 * Assumes vcpu_load() was already called.
1231 */
1232int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1233{
1234 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1235}
1236
9ba075a6
AK		 1237static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1238{
0bed3b56
SY		 1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
9ba075a6
AK		 1241 if (!msr_mtrr_valid(msr))
1242 return 1;
1243
0bed3b56
SY		 1244 if (msr == MSR_MTRRdefType)
1245 *pdata = vcpu->arch.mtrr_state.def_type +
1246 (vcpu->arch.mtrr_state.enabled << 10);
1247 else if (msr == MSR_MTRRfix64K_00000)
1248 *pdata = p[0];
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1253 else if (msr == MSR_IA32_CR_PAT)
1254 *pdata = vcpu->arch.pat;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pdata = *pt;
1268 }
1269
9ba075a6
AK		 1270 return 0;
1271}
1272
890ca9ae 1273static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1274{
1275 u64 data;
890ca9ae
HY		 1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1278
1279 switch (msr) {
15c4a640
CO		 1280 case MSR_IA32_P5_MC_ADDR:
1281 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1282 data = 0;
1283 break;
15c4a640 1284 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1285 data = vcpu->arch.mcg_cap;
1286 break;
c7ac679c 1287 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1288 if (!(mcg_cap & MCG_CTL_P))
1289 return 1;
1290 data = vcpu->arch.mcg_ctl;
1291 break;
1292 case MSR_IA32_MCG_STATUS:
1293 data = vcpu->arch.mcg_status;
1294 break;
1295 default:
1296 if (msr >= MSR_IA32_MC0_CTL &&
1297 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1298 u32 offset = msr - MSR_IA32_MC0_CTL;
1299 data = vcpu->arch.mce_banks[offset];
1300 break;
1301 }
1302 return 1;
1303 }
1304 *pdata = data;
1305 return 0;
1306}
1307
55cd8e5a
GN		 1308static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1309{
1310 u64 data = 0;
1311 struct kvm *kvm = vcpu->kvm;
1312
1313 switch (msr) {
1314 case HV_X64_MSR_GUEST_OS_ID:
1315 data = kvm->arch.hv_guest_os_id;
1316 break;
1317 case HV_X64_MSR_HYPERCALL:
1318 data = kvm->arch.hv_hypercall;
1319 break;
1320 default:
1321 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1322 return 1;
1323 }
1324
1325 *pdata = data;
1326 return 0;
1327}
1328
1329static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1330{
1331 u64 data = 0;
1332
1333 switch (msr) {
1334 case HV_X64_MSR_VP_INDEX: {
1335 int r;
1336 struct kvm_vcpu *v;
1337 kvm_for_each_vcpu(r, v, vcpu->kvm)
1338 if (v == vcpu)
1339 data = r;
1340 break;
1341 }
10388a07
GN		 1342 case HV_X64_MSR_EOI:
1343 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1344 case HV_X64_MSR_ICR:
1345 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1346 case HV_X64_MSR_TPR:
1347 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1348 default:
1349 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1350 return 1;
1351 }
1352 *pdata = data;
1353 return 0;
1354}
1355
890ca9ae
HY		 1356int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1357{
1358 u64 data;
1359
1360 switch (msr) {
890ca9ae 1361 case MSR_IA32_PLATFORM_ID:
15c4a640 1362 case MSR_IA32_UCODE_REV:
15c4a640 1363 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1364 case MSR_IA32_DEBUGCTLMSR:
1365 case MSR_IA32_LASTBRANCHFROMIP:
1366 case MSR_IA32_LASTBRANCHTOIP:
1367 case MSR_IA32_LASTINTFROMIP:
1368 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1369 case MSR_K8_SYSCFG:
1370 case MSR_K7_HWCR:
61a6bd67 1371 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1372 case MSR_P6_PERFCTR0:
1373 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1374 case MSR_P6_EVNTSEL0:
1375 case MSR_P6_EVNTSEL1:
9e699624 1376 case MSR_K7_EVNTSEL0:
1f3ee616 1377 case MSR_K7_PERFCTR0:
1fdbd48c 1378 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1379 case MSR_AMD64_NB_CFG:
f7c6d140 1380 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1381 data = 0;
1382 break;
9ba075a6
AK		 1383 case MSR_MTRRcap:
1384 data = 0x500 | KVM_NR_VAR_MTRR;
1385 break;
1386 case 0x200 ... 0x2ff:
1387 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1388 case 0xcd: /* fsb frequency */
1389 data = 3;
1390 break;
1391 case MSR_IA32_APICBASE:
1392 data = kvm_get_apic_base(vcpu);
1393 break;
0105d1a5
GN		 1394 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1395 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1396 break;
15c4a640 1397 case MSR_IA32_MISC_ENABLE:
ad312c7c 1398 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1399 break;
847f0ad8
AG		 1400 case MSR_IA32_PERF_STATUS:
1401 /* TSC increment by tick */
1402 data = 1000ULL;
1403 /* CPU multiplier */
1404 data |= (((uint64_t)4ULL) << 40);
1405 break;
15c4a640 1406 case MSR_EFER:
f6801dff 1407 data = vcpu->arch.efer;
15c4a640 1408 break;
18068523
GOC		 1409 case MSR_KVM_WALL_CLOCK:
1410 data = vcpu->kvm->arch.wall_clock;
1411 break;
1412 case MSR_KVM_SYSTEM_TIME:
1413 data = vcpu->arch.time;
1414 break;
890ca9ae
HY		 1415 case MSR_IA32_P5_MC_ADDR:
1416 case MSR_IA32_P5_MC_TYPE:
1417 case MSR_IA32_MCG_CAP:
1418 case MSR_IA32_MCG_CTL:
1419 case MSR_IA32_MCG_STATUS:
1420 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1421 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1422 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1423 if (kvm_hv_msr_partition_wide(msr)) {
1424 int r;
1425 mutex_lock(&vcpu->kvm->lock);
1426 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1427 mutex_unlock(&vcpu->kvm->lock);
1428 return r;
1429 } else
1430 return get_msr_hyperv(vcpu, msr, pdata);
1431 break;
15c4a640 1432 default:
ed85c068
AP		 1433 if (!ignore_msrs) {
1434 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1435 return 1;
1436 } else {
1437 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1438 data = 0;
1439 }
1440 break;
15c4a640
CO		 1441 }
1442 *pdata = data;
1443 return 0;
1444}
1445EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1446
313a3dc7
CO		 1447/*
1448 * Read or write a bunch of msrs. All parameters are kernel addresses.
1449 *
1450 * @return number of msrs set successfully.
1451 */
1452static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1453 struct kvm_msr_entry *entries,
1454 int (*do_msr)(struct kvm_vcpu *vcpu,
1455 unsigned index, u64 *data))
1456{
f656ce01 1457 int i, idx;
313a3dc7
CO		 1458
1459 vcpu_load(vcpu);
1460
f656ce01 1461 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1462 for (i = 0; i < msrs->nmsrs; ++i)
1463 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1464 break;
f656ce01 1465 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1466
1467 vcpu_put(vcpu);
1468
1469 return i;
1470}
1471
1472/*
1473 * Read or write a bunch of msrs. Parameters are user addresses.
1474 *
1475 * @return number of msrs set successfully.
1476 */
1477static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1478 int (*do_msr)(struct kvm_vcpu *vcpu,
1479 unsigned index, u64 *data),
1480 int writeback)
1481{
1482 struct kvm_msrs msrs;
1483 struct kvm_msr_entry *entries;
1484 int r, n;
1485 unsigned size;
1486
1487 r = -EFAULT;
1488 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1489 goto out;
1490
1491 r = -E2BIG;
1492 if (msrs.nmsrs >= MAX_IO_MSRS)
1493 goto out;
1494
1495 r = -ENOMEM;
1496 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1497 entries = vmalloc(size);
1498 if (!entries)
1499 goto out;
1500
1501 r = -EFAULT;
1502 if (copy_from_user(entries, user_msrs->entries, size))
1503 goto out_free;
1504
1505 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1506 if (r < 0)
1507 goto out_free;
1508
1509 r = -EFAULT;
1510 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1511 goto out_free;
1512
1513 r = n;
1514
1515out_free:
1516 vfree(entries);
1517out:
1518 return r;
1519}
1520
018d00d2
ZX		 1521int kvm_dev_ioctl_check_extension(long ext)
1522{
1523 int r;
1524
1525 switch (ext) {
1526 case KVM_CAP_IRQCHIP:
1527 case KVM_CAP_HLT:
1528 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1529 case KVM_CAP_SET_TSS_ADDR:
07716717 1530 case KVM_CAP_EXT_CPUID:
c8076604 1531 case KVM_CAP_CLOCKSOURCE:
7837699f 1532 case KVM_CAP_PIT:
a28e4f5a 1533 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1534 case KVM_CAP_MP_STATE:
ed848624 1535 case KVM_CAP_SYNC_MMU:
52d939a0 1536 case KVM_CAP_REINJECT_CONTROL:
4925663a 1537 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1538 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1539 case KVM_CAP_IRQFD:
d34e6b17 1540 case KVM_CAP_IOEVENTFD:
c5ff41ce 1541 case KVM_CAP_PIT2:
e9f42757 1542 case KVM_CAP_PIT_STATE2:
b927a3ce 1543 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1544 case KVM_CAP_XEN_HVM:
afbcf7ab 1545 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1546 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1547 case KVM_CAP_HYPERV:
10388a07 1548 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1549 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1550 case KVM_CAP_PCI_SEGMENT:
d2be1651 1551 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1552 r = 1;
1553 break;
542472b5
LV		 1554 case KVM_CAP_COALESCED_MMIO:
1555 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1556 break;
774ead3a
AK		 1557 case KVM_CAP_VAPIC:
1558 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1559 break;
f725230a
AK		 1560 case KVM_CAP_NR_VCPUS:
1561 r = KVM_MAX_VCPUS;
1562 break;
a988b910
AK		 1563 case KVM_CAP_NR_MEMSLOTS:
1564 r = KVM_MEMORY_SLOTS;
1565 break;
a68a6a72
MT		 1566 case KVM_CAP_PV_MMU: /* obsolete */
1567 r = 0;
2f333bcb 1568 break;
62c476c7 1569 case KVM_CAP_IOMMU:
19de40a8 1570 r = iommu_found();
62c476c7 1571 break;
890ca9ae
HY		 1572 case KVM_CAP_MCE:
1573 r = KVM_MAX_MCE_BANKS;
1574 break;
018d00d2
ZX		 1575 default:
1576 r = 0;
1577 break;
1578 }
1579 return r;
1580
1581}
1582
043405e1
CO		 1583long kvm_arch_dev_ioctl(struct file *filp,
1584 unsigned int ioctl, unsigned long arg)
1585{
1586 void __user *argp = (void __user *)arg;
1587 long r;
1588
1589 switch (ioctl) {
1590 case KVM_GET_MSR_INDEX_LIST: {
1591 struct kvm_msr_list __user *user_msr_list = argp;
1592 struct kvm_msr_list msr_list;
1593 unsigned n;
1594
1595 r = -EFAULT;
1596 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1597 goto out;
1598 n = msr_list.nmsrs;
1599 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1600 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1601 goto out;
1602 r = -E2BIG;
e125e7b6 1603 if (n < msr_list.nmsrs)
043405e1
CO		 1604 goto out;
1605 r = -EFAULT;
1606 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1607 num_msrs_to_save * sizeof(u32)))
1608 goto out;
e125e7b6 1609 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1610 &emulated_msrs,
1611 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1612 goto out;
1613 r = 0;
1614 break;
1615 }
674eea0f
AK		 1616 case KVM_GET_SUPPORTED_CPUID: {
1617 struct kvm_cpuid2 __user *cpuid_arg = argp;
1618 struct kvm_cpuid2 cpuid;
1619
1620 r = -EFAULT;
1621 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1622 goto out;
1623 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1624 cpuid_arg->entries);
674eea0f
AK		 1625 if (r)
1626 goto out;
1627
1628 r = -EFAULT;
1629 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1630 goto out;
1631 r = 0;
1632 break;
1633 }
890ca9ae
HY		 1634 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1635 u64 mce_cap;
1636
1637 mce_cap = KVM_MCE_CAP_SUPPORTED;
1638 r = -EFAULT;
1639 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1640 goto out;
1641 r = 0;
1642 break;
1643 }
043405e1
CO		 1644 default:
1645 r = -EINVAL;
1646 }
1647out:
1648 return r;
1649}
1650
313a3dc7
CO		 1651void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1652{
1653 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1654 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1655 unsigned long khz = cpufreq_quick_get(cpu);
1656 if (!khz)
1657 khz = tsc_khz;
1658 per_cpu(cpu_tsc_khz, cpu) = khz;
1659 }
c8076604 1660 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1661}
1662
1663void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1664{
9327fd11 1665 kvm_put_guest_fpu(vcpu);
02daab21 1666 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1667}
1668
07716717 1669static int is_efer_nx(void)
313a3dc7 1670{
e286e86e 1671 unsigned long long efer = 0;
313a3dc7 1672
e286e86e 1673 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1674 return efer & EFER_NX;
1675}
1676
1677static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1678{
1679 int i;
1680 struct kvm_cpuid_entry2 *e, *entry;
1681
313a3dc7 1682 entry = NULL;
ad312c7c
ZX		 1683 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1684 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1685 if (e->function == 0x80000001) {
1686 entry = e;
1687 break;
1688 }
1689 }
07716717 1690 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1691 entry->edx &= ~(1 << 20);
1692 printk(KERN_INFO "kvm: guest NX capability removed\n");
1693 }
1694}
1695
07716717 1696/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1697static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1698 struct kvm_cpuid *cpuid,
1699 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1700{
1701 int r, i;
1702 struct kvm_cpuid_entry *cpuid_entries;
1703
1704 r = -E2BIG;
1705 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1706 goto out;
1707 r = -ENOMEM;
1708 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1709 if (!cpuid_entries)
1710 goto out;
1711 r = -EFAULT;
1712 if (copy_from_user(cpuid_entries, entries,
1713 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1714 goto out_free;
1715 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1716 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1717 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1718 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1719 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1720 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1721 vcpu->arch.cpuid_entries[i].index = 0;
1722 vcpu->arch.cpuid_entries[i].flags = 0;
1723 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1724 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1725 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1726 }
1727 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1728 cpuid_fix_nx_cap(vcpu);
1729 r = 0;
fc61b800 1730 kvm_apic_set_version(vcpu);
0e851880 1731 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1732
1733out_free:
1734 vfree(cpuid_entries);
1735out:
1736 return r;
1737}
1738
1739static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1740 struct kvm_cpuid2 *cpuid,
1741 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1742{
1743 int r;
1744
1745 r = -E2BIG;
1746 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1747 goto out;
1748 r = -EFAULT;
ad312c7c 1749 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1750 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1751 goto out;
ad312c7c 1752 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1753 kvm_apic_set_version(vcpu);
0e851880 1754 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1755 return 0;
1756
1757out:
1758 return r;
1759}
1760
07716717 1761static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1762 struct kvm_cpuid2 *cpuid,
1763 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1764{
1765 int r;
1766
1767 r = -E2BIG;
ad312c7c 1768 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1769 goto out;
1770 r = -EFAULT;
ad312c7c 1771 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1772 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1773 goto out;
1774 return 0;
1775
1776out:
ad312c7c 1777 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1778 return r;
1779}
1780
07716717 1781static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1782 u32 index)
07716717
DK		 1783{
1784 entry->function = function;
1785 entry->index = index;
1786 cpuid_count(entry->function, entry->index,
19355475 1787 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1788 entry->flags = 0;
1789}
1790
7faa4ee1
AK		 1791#define F(x) bit(X86_FEATURE_##x)
1792
07716717
DK		 1793static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1794 u32 index, int *nent, int maxnent)
1795{
7faa4ee1 1796 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1797#ifdef CONFIG_X86_64
17cc3935
SY		 1798 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1799 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1800 unsigned f_lm = F(LM);
1801#else
17cc3935 1802 unsigned f_gbpages = 0;
7faa4ee1 1803 unsigned f_lm = 0;
07716717 1804#endif
4e47c7a6 1805 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1806
1807 /* cpuid 1.edx */
1808 const u32 kvm_supported_word0_x86_features =
1809 F(FPU) | F(VME) | F(DE) | F(PSE) |
1810 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1811 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1812 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1813 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1814 0 /* Reserved, DS, ACPI */ | F(MMX) |
1815 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1816 0 /* HTT, TM, Reserved, PBE */;
1817 /* cpuid 0x80000001.edx */
1818 const u32 kvm_supported_word1_x86_features =
1819 F(FPU) | F(VME) | F(DE) | F(PSE) |
1820 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1821 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1822 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1823 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1824 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1825 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1826 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1827 /* cpuid 1.ecx */
1828 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1829 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1830 0 /* DS-CPL, VMX, SMX, EST */ |
1831 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1832 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1833 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1834 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1835 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1836 /* cpuid 0x80000001.ecx */
07716717 1837 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1838 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1839 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1840 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1841 0 /* SKINIT */ | 0 /* WDT */;
07716717 1842
19355475 1843 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1844 get_cpu();
1845 do_cpuid_1_ent(entry, function, index);
1846 ++*nent;
1847
1848 switch (function) {
1849 case 0:
1850 entry->eax = min(entry->eax, (u32)0xb);
1851 break;
1852 case 1:
1853 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1854 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1855 /* we support x2apic emulation even if host does not support
1856 * it since we emulate x2apic in software */
1857 entry->ecx |= F(X2APIC);
07716717
DK		 1858 break;
1859 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1860 * may return different values. This forces us to get_cpu() before
1861 * issuing the first command, and also to emulate this annoying behavior
1862 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1863 case 2: {
1864 int t, times = entry->eax & 0xff;
1865
1866 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1867 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1868 for (t = 1; t < times && *nent < maxnent; ++t) {
1869 do_cpuid_1_ent(&entry[t], function, 0);
1870 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1871 ++*nent;
1872 }
1873 break;
1874 }
1875 /* function 4 and 0xb have additional index. */
1876 case 4: {
14af3f3c 1877 int i, cache_type;
07716717
DK		 1878
1879 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1880 /* read more entries until cache_type is zero */
14af3f3c
HH		 1881 for (i = 1; *nent < maxnent; ++i) {
1882 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1883 if (!cache_type)
1884 break;
14af3f3c
HH		 1885 do_cpuid_1_ent(&entry[i], function, i);
1886 entry[i].flags |=
07716717
DK		 1887 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1888 ++*nent;
1889 }
1890 break;
1891 }
1892 case 0xb: {
14af3f3c 1893 int i, level_type;
07716717
DK		 1894
1895 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1896 /* read more entries until level_type is zero */
14af3f3c 1897 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1898 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1899 if (!level_type)
1900 break;
14af3f3c
HH		 1901 do_cpuid_1_ent(&entry[i], function, i);
1902 entry[i].flags |=
07716717
DK		 1903 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1904 ++*nent;
1905 }
1906 break;
1907 }
1908 case 0x80000000:
1909 entry->eax = min(entry->eax, 0x8000001a);
1910 break;
1911 case 0x80000001:
1912 entry->edx &= kvm_supported_word1_x86_features;
1913 entry->ecx &= kvm_supported_word6_x86_features;
1914 break;
1915 }
1916 put_cpu();
1917}
1918
7faa4ee1
AK		 1919#undef F
1920
674eea0f 1921static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1922 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1923{
1924 struct kvm_cpuid_entry2 *cpuid_entries;
1925 int limit, nent = 0, r = -E2BIG;
1926 u32 func;
1927
1928 if (cpuid->nent < 1)
1929 goto out;
6a544355
AK		 1930 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1931 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1932 r = -ENOMEM;
1933 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1934 if (!cpuid_entries)
1935 goto out;
1936
1937 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1938 limit = cpuid_entries[0].eax;
1939 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1940 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1941 &nent, cpuid->nent);
07716717
DK		 1942 r = -E2BIG;
1943 if (nent >= cpuid->nent)
1944 goto out_free;
1945
1946 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1947 limit = cpuid_entries[nent - 1].eax;
1948 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1949 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1950 &nent, cpuid->nent);
cb007648
MM		 1951 r = -E2BIG;
1952 if (nent >= cpuid->nent)
1953 goto out_free;
1954
07716717
DK		 1955 r = -EFAULT;
1956 if (copy_to_user(entries, cpuid_entries,
19355475 1957 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1958 goto out_free;
1959 cpuid->nent = nent;
1960 r = 0;
1961
1962out_free:
1963 vfree(cpuid_entries);
1964out:
1965 return r;
1966}
1967
313a3dc7
CO		 1968static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1969 struct kvm_lapic_state *s)
1970{
1971 vcpu_load(vcpu);
ad312c7c 1972 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1973 vcpu_put(vcpu);
1974
1975 return 0;
1976}
1977
1978static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1979 struct kvm_lapic_state *s)
1980{
1981 vcpu_load(vcpu);
ad312c7c 1982 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1983 kvm_apic_post_state_restore(vcpu);
cb142eb7 1984 update_cr8_intercept(vcpu);
313a3dc7
CO		 1985 vcpu_put(vcpu);
1986
1987 return 0;
1988}
1989
f77bc6a4
ZX		 1990static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1991 struct kvm_interrupt *irq)
1992{
1993 if (irq->irq < 0 || irq->irq >= 256)
1994 return -EINVAL;
1995 if (irqchip_in_kernel(vcpu->kvm))
1996 return -ENXIO;
1997 vcpu_load(vcpu);
1998
66fd3f7f 1999 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2000
2001 vcpu_put(vcpu);
2002
2003 return 0;
2004}
2005
c4abb7c9
JK		 2006static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2007{
2008 vcpu_load(vcpu);
2009 kvm_inject_nmi(vcpu);
2010 vcpu_put(vcpu);
2011
2012 return 0;
2013}
2014
b209749f
AK		 2015static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2016 struct kvm_tpr_access_ctl *tac)
2017{
2018 if (tac->flags)
2019 return -EINVAL;
2020 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2021 return 0;
2022}
2023
890ca9ae
HY		 2024static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2025 u64 mcg_cap)
2026{
2027 int r;
2028 unsigned bank_num = mcg_cap & 0xff, bank;
2029
2030 r = -EINVAL;
a9e38c3e 2031 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2032 goto out;
2033 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2034 goto out;
2035 r = 0;
2036 vcpu->arch.mcg_cap = mcg_cap;
2037 /* Init IA32_MCG_CTL to all 1s */
2038 if (mcg_cap & MCG_CTL_P)
2039 vcpu->arch.mcg_ctl = ~(u64)0;
2040 /* Init IA32_MCi_CTL to all 1s */
2041 for (bank = 0; bank < bank_num; bank++)
2042 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2043out:
2044 return r;
2045}
2046
2047static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2048 struct kvm_x86_mce *mce)
2049{
2050 u64 mcg_cap = vcpu->arch.mcg_cap;
2051 unsigned bank_num = mcg_cap & 0xff;
2052 u64 *banks = vcpu->arch.mce_banks;
2053
2054 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2055 return -EINVAL;
2056 /*
2057 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2058 * reporting is disabled
2059 */
2060 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2061 vcpu->arch.mcg_ctl != ~(u64)0)
2062 return 0;
2063 banks += 4 * mce->bank;
2064 /*
2065 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2066 * reporting is disabled for the bank
2067 */
2068 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2069 return 0;
2070 if (mce->status & MCI_STATUS_UC) {
2071 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2072 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2073 printk(KERN_DEBUG "kvm: set_mce: "
2074 "injects mce exception while "
2075 "previous one is in progress!\n");
2076 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2077 return 0;
2078 }
2079 if (banks[1] & MCI_STATUS_VAL)
2080 mce->status |= MCI_STATUS_OVER;
2081 banks[2] = mce->addr;
2082 banks[3] = mce->misc;
2083 vcpu->arch.mcg_status = mce->mcg_status;
2084 banks[1] = mce->status;
2085 kvm_queue_exception(vcpu, MC_VECTOR);
2086 } else if (!(banks[1] & MCI_STATUS_VAL)
2087 || !(banks[1] & MCI_STATUS_UC)) {
2088 if (banks[1] & MCI_STATUS_VAL)
2089 mce->status |= MCI_STATUS_OVER;
2090 banks[2] = mce->addr;
2091 banks[3] = mce->misc;
2092 banks[1] = mce->status;
2093 } else
2094 banks[1] |= MCI_STATUS_OVER;
2095 return 0;
2096}
2097
3cfc3092
JK		 2098static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2099 struct kvm_vcpu_events *events)
2100{
2101 vcpu_load(vcpu);
2102
2103 events->exception.injected = vcpu->arch.exception.pending;
2104 events->exception.nr = vcpu->arch.exception.nr;
2105 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2106 events->exception.error_code = vcpu->arch.exception.error_code;
2107
2108 events->interrupt.injected = vcpu->arch.interrupt.pending;
2109 events->interrupt.nr = vcpu->arch.interrupt.nr;
2110 events->interrupt.soft = vcpu->arch.interrupt.soft;
2111
2112 events->nmi.injected = vcpu->arch.nmi_injected;
2113 events->nmi.pending = vcpu->arch.nmi_pending;
2114 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2115
2116 events->sipi_vector = vcpu->arch.sipi_vector;
2117
dab4b911
JK		 2118 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2119 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 2120
2121 vcpu_put(vcpu);
2122}
2123
2124static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2125 struct kvm_vcpu_events *events)
2126{
dab4b911
JK		 2127 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2128 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 2129 return -EINVAL;
2130
2131 vcpu_load(vcpu);
2132
2133 vcpu->arch.exception.pending = events->exception.injected;
2134 vcpu->arch.exception.nr = events->exception.nr;
2135 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2136 vcpu->arch.exception.error_code = events->exception.error_code;
2137
2138 vcpu->arch.interrupt.pending = events->interrupt.injected;
2139 vcpu->arch.interrupt.nr = events->interrupt.nr;
2140 vcpu->arch.interrupt.soft = events->interrupt.soft;
2141 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2142 kvm_pic_clear_isr_ack(vcpu->kvm);
2143
2144 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2145 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2146 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2147 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2148
dab4b911
JK		 2149 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2150 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2151
2152 vcpu_put(vcpu);
2153
2154 return 0;
2155}
2156
313a3dc7
CO		 2157long kvm_arch_vcpu_ioctl(struct file *filp,
2158 unsigned int ioctl, unsigned long arg)
2159{
2160 struct kvm_vcpu *vcpu = filp->private_data;
2161 void __user *argp = (void __user *)arg;
2162 int r;
b772ff36 2163 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2164
2165 switch (ioctl) {
2166 case KVM_GET_LAPIC: {
2204ae3c
MT		 2167 r = -EINVAL;
2168 if (!vcpu->arch.apic)
2169 goto out;
b772ff36 2170 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2171
b772ff36
DH		 2172 r = -ENOMEM;
2173 if (!lapic)
2174 goto out;
2175 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2176 if (r)
2177 goto out;
2178 r = -EFAULT;
b772ff36 2179 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2180 goto out;
2181 r = 0;
2182 break;
2183 }
2184 case KVM_SET_LAPIC: {
2204ae3c
MT		 2185 r = -EINVAL;
2186 if (!vcpu->arch.apic)
2187 goto out;
b772ff36
DH		 2188 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2189 r = -ENOMEM;
2190 if (!lapic)
2191 goto out;
313a3dc7 2192 r = -EFAULT;
b772ff36 2193 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2194 goto out;
b772ff36 2195 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2196 if (r)
2197 goto out;
2198 r = 0;
2199 break;
2200 }
f77bc6a4
ZX		 2201 case KVM_INTERRUPT: {
2202 struct kvm_interrupt irq;
2203
2204 r = -EFAULT;
2205 if (copy_from_user(&irq, argp, sizeof irq))
2206 goto out;
2207 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2208 if (r)
2209 goto out;
2210 r = 0;
2211 break;
2212 }
c4abb7c9
JK		 2213 case KVM_NMI: {
2214 r = kvm_vcpu_ioctl_nmi(vcpu);
2215 if (r)
2216 goto out;
2217 r = 0;
2218 break;
2219 }
313a3dc7
CO		 2220 case KVM_SET_CPUID: {
2221 struct kvm_cpuid __user *cpuid_arg = argp;
2222 struct kvm_cpuid cpuid;
2223
2224 r = -EFAULT;
2225 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2226 goto out;
2227 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2228 if (r)
2229 goto out;
2230 break;
2231 }
07716717
DK		 2232 case KVM_SET_CPUID2: {
2233 struct kvm_cpuid2 __user *cpuid_arg = argp;
2234 struct kvm_cpuid2 cpuid;
2235
2236 r = -EFAULT;
2237 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2238 goto out;
2239 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2240 cpuid_arg->entries);
07716717
DK		 2241 if (r)
2242 goto out;
2243 break;
2244 }
2245 case KVM_GET_CPUID2: {
2246 struct kvm_cpuid2 __user *cpuid_arg = argp;
2247 struct kvm_cpuid2 cpuid;
2248
2249 r = -EFAULT;
2250 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2251 goto out;
2252 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2253 cpuid_arg->entries);
07716717
DK		 2254 if (r)
2255 goto out;
2256 r = -EFAULT;
2257 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2258 goto out;
2259 r = 0;
2260 break;
2261 }
313a3dc7
CO		 2262 case KVM_GET_MSRS:
2263 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2264 break;
2265 case KVM_SET_MSRS:
2266 r = msr_io(vcpu, argp, do_set_msr, 0);
2267 break;
b209749f
AK		 2268 case KVM_TPR_ACCESS_REPORTING: {
2269 struct kvm_tpr_access_ctl tac;
2270
2271 r = -EFAULT;
2272 if (copy_from_user(&tac, argp, sizeof tac))
2273 goto out;
2274 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2275 if (r)
2276 goto out;
2277 r = -EFAULT;
2278 if (copy_to_user(argp, &tac, sizeof tac))
2279 goto out;
2280 r = 0;
2281 break;
2282 };
b93463aa
AK		 2283 case KVM_SET_VAPIC_ADDR: {
2284 struct kvm_vapic_addr va;
2285
2286 r = -EINVAL;
2287 if (!irqchip_in_kernel(vcpu->kvm))
2288 goto out;
2289 r = -EFAULT;
2290 if (copy_from_user(&va, argp, sizeof va))
2291 goto out;
2292 r = 0;
2293 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2294 break;
2295 }
890ca9ae
HY		 2296 case KVM_X86_SETUP_MCE: {
2297 u64 mcg_cap;
2298
2299 r = -EFAULT;
2300 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2301 goto out;
2302 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2303 break;
2304 }
2305 case KVM_X86_SET_MCE: {
2306 struct kvm_x86_mce mce;
2307
2308 r = -EFAULT;
2309 if (copy_from_user(&mce, argp, sizeof mce))
2310 goto out;
2311 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2312 break;
2313 }
3cfc3092
JK		 2314 case KVM_GET_VCPU_EVENTS: {
2315 struct kvm_vcpu_events events;
2316
2317 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2318
2319 r = -EFAULT;
2320 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2321 break;
2322 r = 0;
2323 break;
2324 }
2325 case KVM_SET_VCPU_EVENTS: {
2326 struct kvm_vcpu_events events;
2327
2328 r = -EFAULT;
2329 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2330 break;
2331
2332 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2333 break;
2334 }
313a3dc7
CO		 2335 default:
2336 r = -EINVAL;
2337 }
2338out:
7a6ce84c 2339 kfree(lapic);
313a3dc7
CO		 2340 return r;
2341}
2342
1fe779f8
CO		 2343static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2344{
2345 int ret;
2346
2347 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2348 return -1;
2349 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2350 return ret;
2351}
2352
b927a3ce
SY		 2353static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2354 u64 ident_addr)
2355{
2356 kvm->arch.ept_identity_map_addr = ident_addr;
2357 return 0;
2358}
2359
1fe779f8
CO		 2360static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2361 u32 kvm_nr_mmu_pages)
2362{
2363 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2364 return -EINVAL;
2365
79fac95e 2366 mutex_lock(&kvm->slots_lock);
7c8a83b7 2367 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2368
2369 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2370 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2371
7c8a83b7 2372 spin_unlock(&kvm->mmu_lock);
79fac95e 2373 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2374 return 0;
2375}
2376
2377static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2378{
f05e70ac 2379 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2380}
2381
a983fb23
MT		 2382gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2383{
2384 int i;
2385 struct kvm_mem_alias *alias;
2386 struct kvm_mem_aliases *aliases;
2387
2388 aliases = rcu_dereference(kvm->arch.aliases);
2389
2390 for (i = 0; i < aliases->naliases; ++i) {
2391 alias = &aliases->aliases[i];
2392 if (alias->flags & KVM_ALIAS_INVALID)
2393 continue;
2394 if (gfn >= alias->base_gfn
2395 && gfn < alias->base_gfn + alias->npages)
2396 return alias->target_gfn + gfn - alias->base_gfn;
2397 }
2398 return gfn;
2399}
2400
e9f85cde
ZX		 2401gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2402{
2403 int i;
2404 struct kvm_mem_alias *alias;
a983fb23
MT		 2405 struct kvm_mem_aliases *aliases;
2406
2407 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2408
fef9cce0
MT		 2409 for (i = 0; i < aliases->naliases; ++i) {
2410 alias = &aliases->aliases[i];
e9f85cde
ZX		 2411 if (gfn >= alias->base_gfn
2412 && gfn < alias->base_gfn + alias->npages)
2413 return alias->target_gfn + gfn - alias->base_gfn;
2414 }
2415 return gfn;
2416}
2417
1fe779f8
CO		 2418/*
2419 * Set a new alias region. Aliases map a portion of physical memory into
2420 * another portion. This is useful for memory windows, for example the PC
2421 * VGA region.
2422 */
2423static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2424 struct kvm_memory_alias *alias)
2425{
2426 int r, n;
2427 struct kvm_mem_alias *p;
a983fb23 2428 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2429
2430 r = -EINVAL;
2431 /* General sanity checks */
2432 if (alias->memory_size & (PAGE_SIZE - 1))
2433 goto out;
2434 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2435 goto out;
2436 if (alias->slot >= KVM_ALIAS_SLOTS)
2437 goto out;
2438 if (alias->guest_phys_addr + alias->memory_size
2439 < alias->guest_phys_addr)
2440 goto out;
2441 if (alias->target_phys_addr + alias->memory_size
2442 < alias->target_phys_addr)
2443 goto out;
2444
a983fb23
MT		 2445 r = -ENOMEM;
2446 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2447 if (!aliases)
2448 goto out;
2449
79fac95e 2450 mutex_lock(&kvm->slots_lock);
1fe779f8 2451
a983fb23
MT		 2452 /* invalidate any gfn reference in case of deletion/shrinking */
2453 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2454 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2455 old_aliases = kvm->arch.aliases;
2456 rcu_assign_pointer(kvm->arch.aliases, aliases);
2457 synchronize_srcu_expedited(&kvm->srcu);
2458 kvm_mmu_zap_all(kvm);
2459 kfree(old_aliases);
2460
2461 r = -ENOMEM;
2462 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2463 if (!aliases)
2464 goto out_unlock;
2465
2466 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2467
2468 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2469 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2470 p->npages = alias->memory_size >> PAGE_SHIFT;
2471 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2472 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2473
2474 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2475 if (aliases->aliases[n - 1].npages)
1fe779f8 2476 break;
fef9cce0 2477 aliases->naliases = n;
1fe779f8 2478
a983fb23
MT		 2479 old_aliases = kvm->arch.aliases;
2480 rcu_assign_pointer(kvm->arch.aliases, aliases);
2481 synchronize_srcu_expedited(&kvm->srcu);
2482 kfree(old_aliases);
2483 r = 0;
1fe779f8 2484
a983fb23 2485out_unlock:
79fac95e 2486 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2487out:
2488 return r;
2489}
2490
2491static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2492{
2493 int r;
2494
2495 r = 0;
2496 switch (chip->chip_id) {
2497 case KVM_IRQCHIP_PIC_MASTER:
2498 memcpy(&chip->chip.pic,
2499 &pic_irqchip(kvm)->pics[0],
2500 sizeof(struct kvm_pic_state));
2501 break;
2502 case KVM_IRQCHIP_PIC_SLAVE:
2503 memcpy(&chip->chip.pic,
2504 &pic_irqchip(kvm)->pics[1],
2505 sizeof(struct kvm_pic_state));
2506 break;
2507 case KVM_IRQCHIP_IOAPIC:
eba0226b 2508 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2509 break;
2510 default:
2511 r = -EINVAL;
2512 break;
2513 }
2514 return r;
2515}
2516
2517static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2518{
2519 int r;
2520
2521 r = 0;
2522 switch (chip->chip_id) {
2523 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2524 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2525 memcpy(&pic_irqchip(kvm)->pics[0],
2526 &chip->chip.pic,
2527 sizeof(struct kvm_pic_state));
fa8273e9 2528 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2529 break;
2530 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2531 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2532 memcpy(&pic_irqchip(kvm)->pics[1],
2533 &chip->chip.pic,
2534 sizeof(struct kvm_pic_state));
fa8273e9 2535 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2536 break;
2537 case KVM_IRQCHIP_IOAPIC:
eba0226b 2538 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2539 break;
2540 default:
2541 r = -EINVAL;
2542 break;
2543 }
2544 kvm_pic_update_irq(pic_irqchip(kvm));
2545 return r;
2546}
2547
e0f63cb9
SY		 2548static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2549{
2550 int r = 0;
2551
894a9c55 2552 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2553 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2554 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2555 return r;
2556}
2557
2558static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2559{
2560 int r = 0;
2561
894a9c55 2562 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2563 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2564 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2565 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2566 return r;
2567}
2568
2569static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2570{
2571 int r = 0;
2572
2573 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2574 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2575 sizeof(ps->channels));
2576 ps->flags = kvm->arch.vpit->pit_state.flags;
2577 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2578 return r;
2579}
2580
2581static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2582{
2583 int r = 0, start = 0;
2584 u32 prev_legacy, cur_legacy;
2585 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2586 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2587 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2588 if (!prev_legacy && cur_legacy)
2589 start = 1;
2590 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2591 sizeof(kvm->arch.vpit->pit_state.channels));
2592 kvm->arch.vpit->pit_state.flags = ps->flags;
2593 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2594 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2595 return r;
2596}
2597
52d939a0
MT		 2598static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2599 struct kvm_reinject_control *control)
2600{
2601 if (!kvm->arch.vpit)
2602 return -ENXIO;
894a9c55 2603 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2604 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2605 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2606 return 0;
2607}
2608
5bb064dc
ZX		 2609/*
2610 * Get (and clear) the dirty memory log for a memory slot.
2611 */
2612int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2613 struct kvm_dirty_log *log)
2614{
87bf6e7d 2615 int r, i;
5bb064dc 2616 struct kvm_memory_slot *memslot;
87bf6e7d 2617 unsigned long n;
b050b015
MT		 2618 unsigned long is_dirty = 0;
2619 unsigned long *dirty_bitmap = NULL;
5bb064dc 2620
79fac95e 2621 mutex_lock(&kvm->slots_lock);
5bb064dc 2622
b050b015
MT		 2623 r = -EINVAL;
2624 if (log->slot >= KVM_MEMORY_SLOTS)
2625 goto out;
2626
2627 memslot = &kvm->memslots->memslots[log->slot];
2628 r = -ENOENT;
2629 if (!memslot->dirty_bitmap)
2630 goto out;
2631
87bf6e7d 2632 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2633
2634 r = -ENOMEM;
2635 dirty_bitmap = vmalloc(n);
2636 if (!dirty_bitmap)
5bb064dc 2637 goto out;
b050b015
MT		 2638 memset(dirty_bitmap, 0, n);
2639
2640 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2641 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2642
2643 /* If nothing is dirty, don't bother messing with page tables. */
2644 if (is_dirty) {
b050b015
MT		 2645 struct kvm_memslots *slots, *old_slots;
2646
7c8a83b7 2647 spin_lock(&kvm->mmu_lock);
5bb064dc 2648 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2649 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2650
2651 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2652 if (!slots)
2653 goto out_free;
2654
2655 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2656 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2657
2658 old_slots = kvm->memslots;
2659 rcu_assign_pointer(kvm->memslots, slots);
2660 synchronize_srcu_expedited(&kvm->srcu);
2661 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2662 kfree(old_slots);
5bb064dc 2663 }
b050b015 2664
5bb064dc 2665 r = 0;
b050b015
MT		 2666 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2667 r = -EFAULT;
2668out_free:
2669 vfree(dirty_bitmap);
5bb064dc 2670out:
79fac95e 2671 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2672 return r;
2673}
2674
1fe779f8
CO		 2675long kvm_arch_vm_ioctl(struct file *filp,
2676 unsigned int ioctl, unsigned long arg)
2677{
2678 struct kvm *kvm = filp->private_data;
2679 void __user *argp = (void __user *)arg;
367e1319 2680 int r = -ENOTTY;
f0d66275
DH		 2681 /*
2682 * This union makes it completely explicit to gcc-3.x
2683 * that these two variables' stack usage should be
2684 * combined, not added together.
2685 */
2686 union {
2687 struct kvm_pit_state ps;
e9f42757 2688 struct kvm_pit_state2 ps2;
f0d66275 2689 struct kvm_memory_alias alias;
c5ff41ce 2690 struct kvm_pit_config pit_config;
f0d66275 2691 } u;
1fe779f8
CO		 2692
2693 switch (ioctl) {
2694 case KVM_SET_TSS_ADDR:
2695 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2696 if (r < 0)
2697 goto out;
2698 break;
b927a3ce
SY		 2699 case KVM_SET_IDENTITY_MAP_ADDR: {
2700 u64 ident_addr;
2701
2702 r = -EFAULT;
2703 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2704 goto out;
2705 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2706 if (r < 0)
2707 goto out;
2708 break;
2709 }
1fe779f8
CO		 2710 case KVM_SET_MEMORY_REGION: {
2711 struct kvm_memory_region kvm_mem;
2712 struct kvm_userspace_memory_region kvm_userspace_mem;
2713
2714 r = -EFAULT;
2715 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2716 goto out;
2717 kvm_userspace_mem.slot = kvm_mem.slot;
2718 kvm_userspace_mem.flags = kvm_mem.flags;
2719 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2720 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2721 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2722 if (r)
2723 goto out;
2724 break;
2725 }
2726 case KVM_SET_NR_MMU_PAGES:
2727 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2728 if (r)
2729 goto out;
2730 break;
2731 case KVM_GET_NR_MMU_PAGES:
2732 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2733 break;
f0d66275 2734 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2735 r = -EFAULT;
f0d66275 2736 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2737 goto out;
f0d66275 2738 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2739 if (r)
2740 goto out;
2741 break;
3ddea128
MT		 2742 case KVM_CREATE_IRQCHIP: {
2743 struct kvm_pic *vpic;
2744
2745 mutex_lock(&kvm->lock);
2746 r = -EEXIST;
2747 if (kvm->arch.vpic)
2748 goto create_irqchip_unlock;
1fe779f8 2749 r = -ENOMEM;
3ddea128
MT		 2750 vpic = kvm_create_pic(kvm);
2751 if (vpic) {
1fe779f8
CO		 2752 r = kvm_ioapic_init(kvm);
2753 if (r) {
72bb2fcd
WY		 2754 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2755 &vpic->dev);
3ddea128
MT		 2756 kfree(vpic);
2757 goto create_irqchip_unlock;
1fe779f8
CO		 2758 }
2759 } else
3ddea128
MT		 2760 goto create_irqchip_unlock;
2761 smp_wmb();
2762 kvm->arch.vpic = vpic;
2763 smp_wmb();
399ec807
AK		 2764 r = kvm_setup_default_irq_routing(kvm);
2765 if (r) {
3ddea128 2766 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2767 kvm_ioapic_destroy(kvm);
2768 kvm_destroy_pic(kvm);
3ddea128 2769 mutex_unlock(&kvm->irq_lock);
399ec807 2770 }
3ddea128
MT		 2771 create_irqchip_unlock:
2772 mutex_unlock(&kvm->lock);
1fe779f8 2773 break;
3ddea128 2774 }
7837699f 2775 case KVM_CREATE_PIT:
c5ff41ce
JK		 2776 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2777 goto create_pit;
2778 case KVM_CREATE_PIT2:
2779 r = -EFAULT;
2780 if (copy_from_user(&u.pit_config, argp,
2781 sizeof(struct kvm_pit_config)))
2782 goto out;
2783 create_pit:
79fac95e 2784 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2785 r = -EEXIST;
2786 if (kvm->arch.vpit)
2787 goto create_pit_unlock;
7837699f 2788 r = -ENOMEM;
c5ff41ce 2789 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2790 if (kvm->arch.vpit)
2791 r = 0;
269e05e4 2792 create_pit_unlock:
79fac95e 2793 mutex_unlock(&kvm->slots_lock);
7837699f 2794 break;
4925663a 2795 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2796 case KVM_IRQ_LINE: {
2797 struct kvm_irq_level irq_event;
2798
2799 r = -EFAULT;
2800 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2801 goto out;
2802 if (irqchip_in_kernel(kvm)) {
4925663a 2803 __s32 status;
4925663a
GN		 2804 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2805 irq_event.irq, irq_event.level);
4925663a
GN		 2806 if (ioctl == KVM_IRQ_LINE_STATUS) {
2807 irq_event.status = status;
2808 if (copy_to_user(argp, &irq_event,
2809 sizeof irq_event))
2810 goto out;
2811 }
1fe779f8
CO		 2812 r = 0;
2813 }
2814 break;
2815 }
2816 case KVM_GET_IRQCHIP: {
2817 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2818 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2819
f0d66275
DH		 2820 r = -ENOMEM;
2821 if (!chip)
1fe779f8 2822 goto out;
f0d66275
DH		 2823 r = -EFAULT;
2824 if (copy_from_user(chip, argp, sizeof *chip))
2825 goto get_irqchip_out;
1fe779f8
CO		 2826 r = -ENXIO;
2827 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2828 goto get_irqchip_out;
2829 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2830 if (r)
f0d66275 2831 goto get_irqchip_out;
1fe779f8 2832 r = -EFAULT;
f0d66275
DH		 2833 if (copy_to_user(argp, chip, sizeof *chip))
2834 goto get_irqchip_out;
1fe779f8 2835 r = 0;
f0d66275
DH		 2836 get_irqchip_out:
2837 kfree(chip);
2838 if (r)
2839 goto out;
1fe779f8
CO		 2840 break;
2841 }
2842 case KVM_SET_IRQCHIP: {
2843 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2844 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2845
f0d66275
DH		 2846 r = -ENOMEM;
2847 if (!chip)
1fe779f8 2848 goto out;
f0d66275
DH		 2849 r = -EFAULT;
2850 if (copy_from_user(chip, argp, sizeof *chip))
2851 goto set_irqchip_out;
1fe779f8
CO		 2852 r = -ENXIO;
2853 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2854 goto set_irqchip_out;
2855 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2856 if (r)
f0d66275 2857 goto set_irqchip_out;
1fe779f8 2858 r = 0;
f0d66275
DH		 2859 set_irqchip_out:
2860 kfree(chip);
2861 if (r)
2862 goto out;
1fe779f8
CO		 2863 break;
2864 }
e0f63cb9 2865 case KVM_GET_PIT: {
e0f63cb9 2866 r = -EFAULT;
f0d66275 2867 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2868 goto out;
2869 r = -ENXIO;
2870 if (!kvm->arch.vpit)
2871 goto out;
f0d66275 2872 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2873 if (r)
2874 goto out;
2875 r = -EFAULT;
f0d66275 2876 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2877 goto out;
2878 r = 0;
2879 break;
2880 }
2881 case KVM_SET_PIT: {
e0f63cb9 2882 r = -EFAULT;
f0d66275 2883 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2884 goto out;
2885 r = -ENXIO;
2886 if (!kvm->arch.vpit)
2887 goto out;
f0d66275 2888 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2889 if (r)
2890 goto out;
2891 r = 0;
2892 break;
2893 }
e9f42757
BK		 2894 case KVM_GET_PIT2: {
2895 r = -ENXIO;
2896 if (!kvm->arch.vpit)
2897 goto out;
2898 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2899 if (r)
2900 goto out;
2901 r = -EFAULT;
2902 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2903 goto out;
2904 r = 0;
2905 break;
2906 }
2907 case KVM_SET_PIT2: {
2908 r = -EFAULT;
2909 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2910 goto out;
2911 r = -ENXIO;
2912 if (!kvm->arch.vpit)
2913 goto out;
2914 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2915 if (r)
2916 goto out;
2917 r = 0;
2918 break;
2919 }
52d939a0
MT		 2920 case KVM_REINJECT_CONTROL: {
2921 struct kvm_reinject_control control;
2922 r = -EFAULT;
2923 if (copy_from_user(&control, argp, sizeof(control)))
2924 goto out;
2925 r = kvm_vm_ioctl_reinject(kvm, &control);
2926 if (r)
2927 goto out;
2928 r = 0;
2929 break;
2930 }
ffde22ac
ES		 2931 case KVM_XEN_HVM_CONFIG: {
2932 r = -EFAULT;
2933 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2934 sizeof(struct kvm_xen_hvm_config)))
2935 goto out;
2936 r = -EINVAL;
2937 if (kvm->arch.xen_hvm_config.flags)
2938 goto out;
2939 r = 0;
2940 break;
2941 }
afbcf7ab
GC		 2942 case KVM_SET_CLOCK: {
2943 struct timespec now;
2944 struct kvm_clock_data user_ns;
2945 u64 now_ns;
2946 s64 delta;
2947
2948 r = -EFAULT;
2949 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2950 goto out;
2951
2952 r = -EINVAL;
2953 if (user_ns.flags)
2954 goto out;
2955
2956 r = 0;
2957 ktime_get_ts(&now);
2958 now_ns = timespec_to_ns(&now);
2959 delta = user_ns.clock - now_ns;
2960 kvm->arch.kvmclock_offset = delta;
2961 break;
2962 }
2963 case KVM_GET_CLOCK: {
2964 struct timespec now;
2965 struct kvm_clock_data user_ns;
2966 u64 now_ns;
2967
2968 ktime_get_ts(&now);
2969 now_ns = timespec_to_ns(&now);
2970 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2971 user_ns.flags = 0;
2972
2973 r = -EFAULT;
2974 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2975 goto out;
2976 r = 0;
2977 break;
2978 }
2979
1fe779f8
CO		 2980 default:
2981 ;
2982 }
2983out:
2984 return r;
2985}
2986
a16b043c 2987static void kvm_init_msr_list(void)
043405e1
CO		 2988{
2989 u32 dummy[2];
2990 unsigned i, j;
2991
e3267cbb
GC		 2992 /* skip the first msrs in the list. KVM-specific */
2993 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2994 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2995 continue;
2996 if (j < i)
2997 msrs_to_save[j] = msrs_to_save[i];
2998 j++;
2999 }
3000 num_msrs_to_save = j;
3001}
3002
bda9020e
MT		 3003static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3004 const void *v)
bbd9b64e 3005{
bda9020e
MT		 3006 if (vcpu->arch.apic &&
3007 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3008 return 0;
bbd9b64e 3009
e93f8a0f 3010 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3011}
3012
bda9020e 3013static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3014{
bda9020e
MT		 3015 if (vcpu->arch.apic &&
3016 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3017 return 0;
bbd9b64e 3018
e93f8a0f 3019 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3020}
3021
1871c602
GN		 3022gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3023{
3024 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3025 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3026}
3027
3028 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3029{
3030 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3031 access |= PFERR_FETCH_MASK;
3032 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3033}
3034
3035gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3036{
3037 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3038 access |= PFERR_WRITE_MASK;
3039 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3040}
3041
3042/* uses this to access any guest's mapped memory without checking CPL */
3043gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3044{
3045 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3046}
3047
3048static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3049 struct kvm_vcpu *vcpu, u32 access,
3050 u32 *error)
bbd9b64e
CO		 3051{
3052 void *data = val;
10589a46 3053 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3054
3055 while (bytes) {
1871c602 3056 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3057 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3058 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3059 int ret;
3060
10589a46
MT		 3061 if (gpa == UNMAPPED_GVA) {
3062 r = X86EMUL_PROPAGATE_FAULT;
3063 goto out;
3064 }
77c2002e 3065 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3066 if (ret < 0) {
3067 r = X86EMUL_UNHANDLEABLE;
3068 goto out;
3069 }
bbd9b64e 3070
77c2002e
IE		 3071 bytes -= toread;
3072 data += toread;
3073 addr += toread;
bbd9b64e 3074 }
10589a46 3075out:
10589a46 3076 return r;
bbd9b64e 3077}
77c2002e 3078
1871c602
GN		 3079/* used for instruction fetching */
3080static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3081 struct kvm_vcpu *vcpu, u32 *error)
3082{
3083 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3084 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3085 access | PFERR_FETCH_MASK, error);
3086}
3087
3088static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3089 struct kvm_vcpu *vcpu, u32 *error)
3090{
3091 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3092 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3093 error);
3094}
3095
3096static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3097 struct kvm_vcpu *vcpu, u32 *error)
3098{
3099 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3100}
3101
cded19f3 3102static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3103 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3104{
3105 void *data = val;
3106 int r = X86EMUL_CONTINUE;
3107
3108 while (bytes) {
1871c602 3109 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3110 unsigned offset = addr & (PAGE_SIZE-1);
3111 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3112 int ret;
3113
3114 if (gpa == UNMAPPED_GVA) {
3115 r = X86EMUL_PROPAGATE_FAULT;
3116 goto out;
3117 }
3118 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3119 if (ret < 0) {
3120 r = X86EMUL_UNHANDLEABLE;
3121 goto out;
3122 }
3123
3124 bytes -= towrite;
3125 data += towrite;
3126 addr += towrite;
3127 }
3128out:
3129 return r;
3130}
3131
bbd9b64e 3132
bbd9b64e
CO		 3133static int emulator_read_emulated(unsigned long addr,
3134 void *val,
3135 unsigned int bytes,
3136 struct kvm_vcpu *vcpu)
3137{
bbd9b64e 3138 gpa_t gpa;
1871c602 3139 u32 error_code;
bbd9b64e
CO		 3140
3141 if (vcpu->mmio_read_completed) {
3142 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3143 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3144 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3145 vcpu->mmio_read_completed = 0;
3146 return X86EMUL_CONTINUE;
3147 }
3148
1871c602
GN		 3149 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3150
3151 if (gpa == UNMAPPED_GVA) {
3152 kvm_inject_page_fault(vcpu, addr, error_code);
3153 return X86EMUL_PROPAGATE_FAULT;
3154 }
bbd9b64e
CO		 3155
3156 /* For APIC access vmexit */
3157 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3158 goto mmio;
3159
1871c602 3160 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3161 == X86EMUL_CONTINUE)
bbd9b64e 3162 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3163
3164mmio:
3165 /*
3166 * Is this MMIO handled locally?
3167 */
aec51dc4
AK		 3168 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3169 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3170 return X86EMUL_CONTINUE;
3171 }
aec51dc4
AK		 3172
3173 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3174
3175 vcpu->mmio_needed = 1;
3176 vcpu->mmio_phys_addr = gpa;
3177 vcpu->mmio_size = bytes;
3178 vcpu->mmio_is_write = 0;
3179
3180 return X86EMUL_UNHANDLEABLE;
3181}
3182
3200f405 3183int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3184 const void *val, int bytes)
bbd9b64e
CO		 3185{
3186 int ret;
3187
3188 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3189 if (ret < 0)
bbd9b64e 3190 return 0;
ad218f85 3191 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3192 return 1;
3193}
3194
3195static int emulator_write_emulated_onepage(unsigned long addr,
3196 const void *val,
3197 unsigned int bytes,
3198 struct kvm_vcpu *vcpu)
3199{
10589a46 3200 gpa_t gpa;
1871c602 3201 u32 error_code;
10589a46 3202
1871c602 3203 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3204
3205 if (gpa == UNMAPPED_GVA) {
1871c602 3206 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3207 return X86EMUL_PROPAGATE_FAULT;
3208 }
3209
3210 /* For APIC access vmexit */
3211 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3212 goto mmio;
3213
3214 if (emulator_write_phys(vcpu, gpa, val, bytes))
3215 return X86EMUL_CONTINUE;
3216
3217mmio:
aec51dc4 3218 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3219 /*
3220 * Is this MMIO handled locally?
3221 */
bda9020e 3222 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3223 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3224
3225 vcpu->mmio_needed = 1;
3226 vcpu->mmio_phys_addr = gpa;
3227 vcpu->mmio_size = bytes;
3228 vcpu->mmio_is_write = 1;
3229 memcpy(vcpu->mmio_data, val, bytes);
3230
3231 return X86EMUL_CONTINUE;
3232}
3233
3234int emulator_write_emulated(unsigned long addr,
3235 const void *val,
3236 unsigned int bytes,
3237 struct kvm_vcpu *vcpu)
3238{
3239 /* Crossing a page boundary? */
3240 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3241 int rc, now;
3242
3243 now = -addr & ~PAGE_MASK;
3244 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3245 if (rc != X86EMUL_CONTINUE)
3246 return rc;
3247 addr += now;
3248 val += now;
3249 bytes -= now;
3250 }
3251 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3252}
3253EXPORT_SYMBOL_GPL(emulator_write_emulated);
3254
3255static int emulator_cmpxchg_emulated(unsigned long addr,
3256 const void *old,
3257 const void *new,
3258 unsigned int bytes,
3259 struct kvm_vcpu *vcpu)
3260{
9f51e24e 3261 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3262#ifndef CONFIG_X86_64
3263 /* guests cmpxchg8b have to be emulated atomically */
3264 if (bytes == 8) {
10589a46 3265 gpa_t gpa;
2bacc55c 3266 struct page *page;
c0b49b0d 3267 char *kaddr;
2bacc55c
MT		 3268 u64 val;
3269
1871c602 3270 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
10589a46 3271
2bacc55c
MT		 3272 if (gpa == UNMAPPED_GVA ||
3273 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3274 goto emul_write;
3275
3276 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3277 goto emul_write;
3278
3279 val = *(u64 *)new;
72dc67a6 3280
2bacc55c 3281 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3282
c0b49b0d
AM		 3283 kaddr = kmap_atomic(page, KM_USER0);
3284 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3285 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3286 kvm_release_page_dirty(page);
3287 }
3200f405 3288emul_write:
2bacc55c
MT		 3289#endif
3290
bbd9b64e
CO		 3291 return emulator_write_emulated(addr, new, bytes, vcpu);
3292}
3293
3294static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3295{
3296 return kvm_x86_ops->get_segment_base(vcpu, seg);
3297}
3298
3299int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3300{
a7052897 3301 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3302 return X86EMUL_CONTINUE;
3303}
3304
3305int emulate_clts(struct kvm_vcpu *vcpu)
3306{
4d4ec087 3307 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3308 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3309 return X86EMUL_CONTINUE;
3310}
3311
3312int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3313{
c76de350 3314 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3315}
3316
3317int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3318{
3319 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3320
c76de350 3321 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3322}
3323
3324void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3325{
bbd9b64e 3326 u8 opcodes[4];
5fdbf976 3327 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3328 unsigned long rip_linear;
3329
f76c710d 3330 if (!printk_ratelimit())
bbd9b64e
CO		 3331 return;
3332
25be4608
GC		 3333 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3334
1871c602 3335 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3336
3337 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3338 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3339}
3340EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3341
14af3f3c 3342static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3343 .read_std = kvm_read_guest_virt_system,
3344 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3345 .read_emulated = emulator_read_emulated,
3346 .write_emulated = emulator_write_emulated,
3347 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3348};
3349
5fdbf976
MT		 3350static void cache_all_regs(struct kvm_vcpu *vcpu)
3351{
3352 kvm_register_read(vcpu, VCPU_REGS_RAX);
3353 kvm_register_read(vcpu, VCPU_REGS_RSP);
3354 kvm_register_read(vcpu, VCPU_REGS_RIP);
3355 vcpu->arch.regs_dirty = ~0;
3356}
3357
bbd9b64e 3358int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3359 unsigned long cr2,
3360 u16 error_code,
571008da 3361 int emulation_type)
bbd9b64e 3362{
310b5d30 3363 int r, shadow_mask;
571008da 3364 struct decode_cache *c;
851ba692 3365 struct kvm_run *run = vcpu->run;
bbd9b64e 3366
26eef70c 3367 kvm_clear_exception_queue(vcpu);
ad312c7c 3368 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3369 /*
56e82318 3370 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3371 * instead of direct ->regs accesses, can save hundred cycles
3372 * on Intel for instructions that don't read/change RSP, for
3373 * for example.
3374 */
3375 cache_all_regs(vcpu);
bbd9b64e
CO		 3376
3377 vcpu->mmio_is_write = 0;
ad312c7c 3378 vcpu->arch.pio.string = 0;
bbd9b64e 3379
571008da 3380 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3381 int cs_db, cs_l;
3382 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3383
ad312c7c 3384 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3385 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c 3386 vcpu->arch.emulate_ctxt.mode =
a0044755 3387 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3388 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3389 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3390 ? X86EMUL_MODE_PROT64 : cs_db
3391 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3392
ad312c7c 3393 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3394
0cb5762e
AP		 3395 /* Only allow emulation of specific instructions on #UD
3396 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3397 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3398 if (emulation_type & EMULTYPE_TRAP_UD) {
3399 if (!c->twobyte)
3400 return EMULATE_FAIL;
3401 switch (c->b) {
3402 case 0x01: /* VMMCALL */
3403 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3404 return EMULATE_FAIL;
3405 break;
3406 case 0x34: /* sysenter */
3407 case 0x35: /* sysexit */
3408 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3409 return EMULATE_FAIL;
3410 break;
3411 case 0x05: /* syscall */
3412 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3413 return EMULATE_FAIL;
3414 break;
3415 default:
3416 return EMULATE_FAIL;
3417 }
3418
3419 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3420 return EMULATE_FAIL;
3421 }
571008da 3422
f2b5756b 3423 ++vcpu->stat.insn_emulation;
bbd9b64e 3424 if (r) {
f2b5756b 3425 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3426 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3427 return EMULATE_DONE;
3428 return EMULATE_FAIL;
3429 }
3430 }
3431
ba8afb6b
GN		 3432 if (emulation_type & EMULTYPE_SKIP) {
3433 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3434 return EMULATE_DONE;
3435 }
3436
ad312c7c 3437 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3438 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3439
3440 if (r == 0)
3441 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3442
ad312c7c 3443 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3444 return EMULATE_DO_MMIO;
3445
112592da 3446 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3447 run->exit_reason = KVM_EXIT_MMIO;
3448 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3449 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3450 run->mmio.len = vcpu->mmio_size;
3451 run->mmio.is_write = vcpu->mmio_is_write;
3452 }
3453
3454 if (r) {
3455 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3456 return EMULATE_DONE;
3457 if (!vcpu->mmio_needed) {
3458 kvm_report_emulation_failure(vcpu, "mmio");
3459 return EMULATE_FAIL;
3460 }
3461 return EMULATE_DO_MMIO;
3462 }
3463
91586a3b 3464 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3465
3466 if (vcpu->mmio_is_write) {
3467 vcpu->mmio_needed = 0;
3468 return EMULATE_DO_MMIO;
3469 }
3470
3471 return EMULATE_DONE;
3472}
3473EXPORT_SYMBOL_GPL(emulate_instruction);
3474
de7d789a
CO		 3475static int pio_copy_data(struct kvm_vcpu *vcpu)
3476{
ad312c7c 3477 void *p = vcpu->arch.pio_data;
0f346074 3478 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3479 unsigned bytes;
0f346074 3480 int ret;
1871c602 3481 u32 error_code;
de7d789a 3482
ad312c7c
ZX		 3483 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3484 if (vcpu->arch.pio.in)
1871c602 3485 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3486 else
1871c602
GN		 3487 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3488
3489 if (ret == X86EMUL_PROPAGATE_FAULT)
3490 kvm_inject_page_fault(vcpu, q, error_code);
3491
0f346074 3492 return ret;
de7d789a
CO		 3493}
3494
3495int complete_pio(struct kvm_vcpu *vcpu)
3496{
ad312c7c 3497 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3498 long delta;
3499 int r;
5fdbf976 3500 unsigned long val;
de7d789a
CO		 3501
3502 if (!io->string) {
5fdbf976
MT		 3503 if (io->in) {
3504 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3505 memcpy(&val, vcpu->arch.pio_data, io->size);
3506 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3507 }
de7d789a
CO		 3508 } else {
3509 if (io->in) {
3510 r = pio_copy_data(vcpu);
5fdbf976 3511 if (r)
1871c602 3512 goto out;
de7d789a
CO		 3513 }
3514
3515 delta = 1;
3516 if (io->rep) {
3517 delta *= io->cur_count;
3518 /*
3519 * The size of the register should really depend on
3520 * current address size.
3521 */
5fdbf976
MT		 3522 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3523 val -= delta;
3524 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3525 }
3526 if (io->down)
3527 delta = -delta;
3528 delta *= io->size;
5fdbf976
MT		 3529 if (io->in) {
3530 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3531 val += delta;
3532 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3533 } else {
3534 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3535 val += delta;
3536 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3537 }
de7d789a 3538 }
1871c602 3539out:
de7d789a
CO		 3540 io->count -= io->cur_count;
3541 io->cur_count = 0;
3542
3543 return 0;
3544}
3545
bda9020e 3546static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3547{
3548 /* TODO: String I/O for in kernel device */
bda9020e 3549 int r;
de7d789a 3550
ad312c7c 3551 if (vcpu->arch.pio.in)
e93f8a0f 3552 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3553 vcpu->arch.pio.size, pd);
de7d789a 3554 else
e93f8a0f
MT		 3555 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3556 vcpu->arch.pio.port, vcpu->arch.pio.size,
3557 pd);
bda9020e 3558 return r;
de7d789a
CO		 3559}
3560
bda9020e 3561static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3562{
ad312c7c
ZX		 3563 struct kvm_pio_request *io = &vcpu->arch.pio;
3564 void *pd = vcpu->arch.pio_data;
bda9020e 3565 int i, r = 0;
de7d789a 3566
de7d789a 3567 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3568 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3569 io->port, io->size, pd)) {
3570 r = -EOPNOTSUPP;
3571 break;
3572 }
de7d789a
CO		 3573 pd += io->size;
3574 }
bda9020e 3575 return r;
de7d789a
CO		 3576}
3577
851ba692 3578int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3579{
5fdbf976 3580 unsigned long val;
de7d789a 3581
f850e2e6
GN		 3582 trace_kvm_pio(!in, port, size, 1);
3583
de7d789a
CO		 3584 vcpu->run->exit_reason = KVM_EXIT_IO;
3585 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3586 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3587 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3588 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3589 vcpu->run->io.port = vcpu->arch.pio.port = port;
3590 vcpu->arch.pio.in = in;
3591 vcpu->arch.pio.string = 0;
3592 vcpu->arch.pio.down = 0;
ad312c7c 3593 vcpu->arch.pio.rep = 0;
de7d789a 3594
1976d2d2
TY		 3595 if (!vcpu->arch.pio.in) {
3596 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3597 memcpy(vcpu->arch.pio_data, &val, 4);
3598 }
de7d789a 3599
bda9020e 3600 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3601 complete_pio(vcpu);
3602 return 1;
3603 }
3604 return 0;
3605}
3606EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3607
851ba692 3608int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3609 int size, unsigned long count, int down,
3610 gva_t address, int rep, unsigned port)
3611{
3612 unsigned now, in_page;
0f346074 3613 int ret = 0;
de7d789a 3614
f850e2e6
GN		 3615 trace_kvm_pio(!in, port, size, count);
3616
de7d789a
CO		 3617 vcpu->run->exit_reason = KVM_EXIT_IO;
3618 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3619 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3620 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3621 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3622 vcpu->run->io.port = vcpu->arch.pio.port = port;
3623 vcpu->arch.pio.in = in;
3624 vcpu->arch.pio.string = 1;
3625 vcpu->arch.pio.down = down;
ad312c7c 3626 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3627
3628 if (!count) {
3629 kvm_x86_ops->skip_emulated_instruction(vcpu);
3630 return 1;
3631 }
3632
3633 if (!down)
3634 in_page = PAGE_SIZE - offset_in_page(address);
3635 else
3636 in_page = offset_in_page(address) + size;
3637 now = min(count, (unsigned long)in_page / size);
0f346074 3638 if (!now)
de7d789a 3639 now = 1;
de7d789a
CO		 3640 if (down) {
3641 /*
3642 * String I/O in reverse. Yuck. Kill the guest, fix later.
3643 */
3644 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3645 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3646 return 1;
3647 }
3648 vcpu->run->io.count = now;
ad312c7c 3649 vcpu->arch.pio.cur_count = now;
de7d789a 3650
ad312c7c 3651 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3652 kvm_x86_ops->skip_emulated_instruction(vcpu);
3653
0f346074 3654 vcpu->arch.pio.guest_gva = address;
de7d789a 3655
ad312c7c 3656 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3657 /* string PIO write */
3658 ret = pio_copy_data(vcpu);
1871c602 3659 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3660 return 1;
bda9020e 3661 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3662 complete_pio(vcpu);
ad312c7c 3663 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3664 ret = 1;
3665 }
bda9020e
MT		 3666 }
3667 /* no string PIO read support yet */
de7d789a
CO		 3668
3669 return ret;
3670}
3671EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3672
c8076604
GH		 3673static void bounce_off(void *info)
3674{
3675 /* nothing */
3676}
3677
c8076604
GH		 3678static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3679 void *data)
3680{
3681 struct cpufreq_freqs *freq = data;
3682 struct kvm *kvm;
3683 struct kvm_vcpu *vcpu;
3684 int i, send_ipi = 0;
3685
c8076604
GH		 3686 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3687 return 0;
3688 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3689 return 0;
0cca7907 3690 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3691
3692 spin_lock(&kvm_lock);
3693 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3694 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3695 if (vcpu->cpu != freq->cpu)
3696 continue;
3697 if (!kvm_request_guest_time_update(vcpu))
3698 continue;
3699 if (vcpu->cpu != smp_processor_id())
3700 send_ipi++;
3701 }
3702 }
3703 spin_unlock(&kvm_lock);
3704
3705 if (freq->old < freq->new && send_ipi) {
3706 /*
3707 * We upscale the frequency. Must make the guest
3708 * doesn't see old kvmclock values while running with
3709 * the new frequency, otherwise we risk the guest sees
3710 * time go backwards.
3711 *
3712 * In case we update the frequency for another cpu
3713 * (which might be in guest context) send an interrupt
3714 * to kick the cpu out of guest context. Next time
3715 * guest context is entered kvmclock will be updated,
3716 * so the guest will not see stale values.
3717 */
3718 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3719 }
3720 return 0;
3721}
3722
3723static struct notifier_block kvmclock_cpufreq_notifier_block = {
3724 .notifier_call = kvmclock_cpufreq_notifier
3725};
3726
b820cc0c
ZA		 3727static void kvm_timer_init(void)
3728{
3729 int cpu;
3730
b820cc0c 3731 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3732 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3733 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3734 for_each_online_cpu(cpu) {
3735 unsigned long khz = cpufreq_get(cpu);
3736 if (!khz)
3737 khz = tsc_khz;
3738 per_cpu(cpu_tsc_khz, cpu) = khz;
3739 }
0cca7907
ZA		 3740 } else {
3741 for_each_possible_cpu(cpu)
3742 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3743 }
3744}
3745
f8c16bba 3746int kvm_arch_init(void *opaque)
043405e1 3747{
b820cc0c 3748 int r;
f8c16bba
ZX		 3749 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3750
f8c16bba
ZX		 3751 if (kvm_x86_ops) {
3752 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3753 r = -EEXIST;
3754 goto out;
f8c16bba
ZX		 3755 }
3756
3757 if (!ops->cpu_has_kvm_support()) {
3758 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3759 r = -EOPNOTSUPP;
3760 goto out;
f8c16bba
ZX		 3761 }
3762 if (ops->disabled_by_bios()) {
3763 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3764 r = -EOPNOTSUPP;
3765 goto out;
f8c16bba
ZX		 3766 }
3767
97db56ce
AK		 3768 r = kvm_mmu_module_init();
3769 if (r)
3770 goto out;
3771
3772 kvm_init_msr_list();
3773
f8c16bba 3774 kvm_x86_ops = ops;
56c6d28a 3775 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3776 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3777 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3778 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3779
b820cc0c 3780 kvm_timer_init();
c8076604 3781
f8c16bba 3782 return 0;
56c6d28a
ZX		 3783
3784out:
56c6d28a 3785 return r;
043405e1 3786}
8776e519 3787
f8c16bba
ZX		 3788void kvm_arch_exit(void)
3789{
888d256e
JK		 3790 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3791 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3792 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3793 kvm_x86_ops = NULL;
56c6d28a
ZX		 3794 kvm_mmu_module_exit();
3795}
f8c16bba 3796
8776e519
HB		 3797int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3798{
3799 ++vcpu->stat.halt_exits;
3800 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3801 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3802 return 1;
3803 } else {
3804 vcpu->run->exit_reason = KVM_EXIT_HLT;
3805 return 0;
3806 }
3807}
3808EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3809
2f333bcb
MT		 3810static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3811 unsigned long a1)
3812{
3813 if (is_long_mode(vcpu))
3814 return a0;
3815 else
3816 return a0 | ((gpa_t)a1 << 32);
3817}
3818
55cd8e5a
GN		 3819int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3820{
3821 u64 param, ingpa, outgpa, ret;
3822 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3823 bool fast, longmode;
3824 int cs_db, cs_l;
3825
3826 /*
3827 * hypercall generates UD from non zero cpl and real mode
3828 * per HYPER-V spec
3829 */
3eeb3288 3830 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3831 kvm_queue_exception(vcpu, UD_VECTOR);
3832 return 0;
3833 }
3834
3835 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3836 longmode = is_long_mode(vcpu) && cs_l == 1;
3837
3838 if (!longmode) {
ccd46936
GN		 3839 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3840 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3841 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3842 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3843 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3844 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3845 }
3846#ifdef CONFIG_X86_64
3847 else {
3848 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3849 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3850 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3851 }
3852#endif
3853
3854 code = param & 0xffff;
3855 fast = (param >> 16) & 0x1;
3856 rep_cnt = (param >> 32) & 0xfff;
3857 rep_idx = (param >> 48) & 0xfff;
3858
3859 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3860
c25bc163
GN		 3861 switch (code) {
3862 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
3863 kvm_vcpu_on_spin(vcpu);
3864 break;
3865 default:
3866 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3867 break;
3868 }
55cd8e5a
GN		 3869
3870 ret = res | (((u64)rep_done & 0xfff) << 32);
3871 if (longmode) {
3872 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3873 } else {
3874 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3875 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3876 }
3877
3878 return 1;
3879}
3880
8776e519
HB		 3881int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3882{
3883 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3884 int r = 1;
8776e519 3885
55cd8e5a
GN		 3886 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3887 return kvm_hv_hypercall(vcpu);
3888
5fdbf976
MT		 3889 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3890 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3891 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3892 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3893 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3894
229456fc 3895 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3896
8776e519
HB		 3897 if (!is_long_mode(vcpu)) {
3898 nr &= 0xFFFFFFFF;
3899 a0 &= 0xFFFFFFFF;
3900 a1 &= 0xFFFFFFFF;
3901 a2 &= 0xFFFFFFFF;
3902 a3 &= 0xFFFFFFFF;
3903 }
3904
07708c4a
JK		 3905 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3906 ret = -KVM_EPERM;
3907 goto out;
3908 }
3909
8776e519 3910 switch (nr) {
b93463aa
AK		 3911 case KVM_HC_VAPIC_POLL_IRQ:
3912 ret = 0;
3913 break;
2f333bcb
MT		 3914 case KVM_HC_MMU_OP:
3915 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3916 break;
8776e519
HB		 3917 default:
3918 ret = -KVM_ENOSYS;
3919 break;
3920 }
07708c4a 3921out:
5fdbf976 3922 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3923 ++vcpu->stat.hypercalls;
2f333bcb 3924 return r;
8776e519
HB		 3925}
3926EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3927
3928int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3929{
3930 char instruction[3];
5fdbf976 3931 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3932
8776e519
HB		 3933 /*
3934 * Blow out the MMU to ensure that no other VCPU has an active mapping
3935 * to ensure that the updated hypercall appears atomically across all
3936 * VCPUs.
3937 */
3938 kvm_mmu_zap_all(vcpu->kvm);
3939
8776e519 3940 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 3941
7edcface 3942 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 3943}
3944
3945static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3946{
3947 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3948}
3949
3950void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3951{
89a27f4d 3952 struct desc_ptr dt = { limit, base };
8776e519
HB		 3953
3954 kvm_x86_ops->set_gdt(vcpu, &dt);
3955}
3956
3957void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3958{
89a27f4d 3959 struct desc_ptr dt = { limit, base };
8776e519
HB		 3960
3961 kvm_x86_ops->set_idt(vcpu, &dt);
3962}
3963
3964void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3965 unsigned long *rflags)
3966{
2d3ad1f4 3967 kvm_lmsw(vcpu, msw);
91586a3b 3968 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3969}
3970
3971unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3972{
54e445ca
JR		 3973 unsigned long value;
3974
8776e519
HB		 3975 switch (cr) {
3976 case 0:
4d4ec087 3977 value = kvm_read_cr0(vcpu);
54e445ca 3978 break;
8776e519 3979 case 2:
54e445ca
JR		 3980 value = vcpu->arch.cr2;
3981 break;
8776e519 3982 case 3:
54e445ca
JR		 3983 value = vcpu->arch.cr3;
3984 break;
8776e519 3985 case 4:
fc78f519 3986 value = kvm_read_cr4(vcpu);
54e445ca 3987 break;
152ff9be 3988 case 8:
54e445ca
JR		 3989 value = kvm_get_cr8(vcpu);
3990 break;
8776e519 3991 default:
b8688d51 3992 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3993 return 0;
3994 }
54e445ca
JR		 3995
3996 return value;
8776e519
HB		 3997}
3998
3999void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
4000 unsigned long *rflags)
4001{
4002 switch (cr) {
4003 case 0:
4d4ec087 4004 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 4005 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4006 break;
4007 case 2:
ad312c7c 4008 vcpu->arch.cr2 = val;
8776e519
HB		 4009 break;
4010 case 3:
2d3ad1f4 4011 kvm_set_cr3(vcpu, val);
8776e519
HB		 4012 break;
4013 case 4:
fc78f519 4014 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 4015 break;
152ff9be 4016 case 8:
2d3ad1f4 4017 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 4018 break;
8776e519 4019 default:
b8688d51 4020 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4021 }
4022}
4023
07716717
DK		 4024static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4025{
ad312c7c
ZX		 4026 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4027 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4028
4029 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4030 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4031 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4032 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4033 if (ej->function == e->function) {
4034 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4035 return j;
4036 }
4037 }
4038 return 0; /* silence gcc, even though control never reaches here */
4039}
4040
4041/* find an entry with matching function, matching index (if needed), and that
4042 * should be read next (if it's stateful) */
4043static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4044 u32 function, u32 index)
4045{
4046 if (e->function != function)
4047 return 0;
4048 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4049 return 0;
4050 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4051 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4052 return 0;
4053 return 1;
4054}
4055
d8017474
AG		 4056struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4057 u32 function, u32 index)
8776e519
HB		 4058{
4059 int i;
d8017474 4060 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4061
ad312c7c 4062 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4063 struct kvm_cpuid_entry2 *e;
4064
ad312c7c 4065 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4066 if (is_matching_cpuid_entry(e, function, index)) {
4067 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4068 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4069 best = e;
4070 break;
4071 }
4072 /*
4073 * Both basic or both extended?
4074 */
4075 if (((e->function ^ function) & 0x80000000) == 0)
4076 if (!best || e->function > best->function)
4077 best = e;
4078 }
d8017474
AG		 4079 return best;
4080}
0e851880 4081EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4082
82725b20
DE		 4083int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4084{
4085 struct kvm_cpuid_entry2 *best;
4086
4087 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4088 if (best)
4089 return best->eax & 0xff;
4090 return 36;
4091}
4092
d8017474
AG		 4093void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4094{
4095 u32 function, index;
4096 struct kvm_cpuid_entry2 *best;
4097
4098 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4099 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4100 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4101 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4102 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4103 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4104 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4105 if (best) {
5fdbf976
MT		 4106 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4107 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4108 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4109 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4110 }
8776e519 4111 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4112 trace_kvm_cpuid(function,
4113 kvm_register_read(vcpu, VCPU_REGS_RAX),
4114 kvm_register_read(vcpu, VCPU_REGS_RBX),
4115 kvm_register_read(vcpu, VCPU_REGS_RCX),
4116 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4117}
4118EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4119
b6c7a5dc
HB		 4120/*
4121 * Check if userspace requested an interrupt window, and that the
4122 * interrupt window is open.
4123 *
4124 * No need to exit to userspace if we already have an interrupt queued.
4125 */
851ba692 4126static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4127{
8061823a 4128 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4129 vcpu->run->request_interrupt_window &&
5df56646 4130 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4131}
4132
851ba692 4133static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4134{
851ba692
AK		 4135 struct kvm_run *kvm_run = vcpu->run;
4136
91586a3b 4137 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4138 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4139 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4140 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4141 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4142 else
b6c7a5dc 4143 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4144 kvm_arch_interrupt_allowed(vcpu) &&
4145 !kvm_cpu_has_interrupt(vcpu) &&
4146 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4147}
4148
b93463aa
AK		 4149static void vapic_enter(struct kvm_vcpu *vcpu)
4150{
4151 struct kvm_lapic *apic = vcpu->arch.apic;
4152 struct page *page;
4153
4154 if (!apic || !apic->vapic_addr)
4155 return;
4156
4157 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4158
4159 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4160}
4161
4162static void vapic_exit(struct kvm_vcpu *vcpu)
4163{
4164 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4165 int idx;
b93463aa
AK		 4166
4167 if (!apic || !apic->vapic_addr)
4168 return;
4169
f656ce01 4170 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4171 kvm_release_page_dirty(apic->vapic_page);
4172 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4173 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4174}
4175
95ba8273
GN		 4176static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4177{
4178 int max_irr, tpr;
4179
4180 if (!kvm_x86_ops->update_cr8_intercept)
4181 return;
4182
88c808fd
AK		 4183 if (!vcpu->arch.apic)
4184 return;
4185
8db3baa2
GN		 4186 if (!vcpu->arch.apic->vapic_addr)
4187 max_irr = kvm_lapic_find_highest_irr(vcpu);
4188 else
4189 max_irr = -1;
95ba8273
GN		 4190
4191 if (max_irr != -1)
4192 max_irr >>= 4;
4193
4194 tpr = kvm_lapic_get_cr8(vcpu);
4195
4196 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4197}
4198
851ba692 4199static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4200{
4201 /* try to reinject previous events if any */
b59bb7bd
GN		 4202 if (vcpu->arch.exception.pending) {
4203 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4204 vcpu->arch.exception.has_error_code,
4205 vcpu->arch.exception.error_code);
4206 return;
4207 }
4208
95ba8273
GN		 4209 if (vcpu->arch.nmi_injected) {
4210 kvm_x86_ops->set_nmi(vcpu);
4211 return;
4212 }
4213
4214 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4215 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4216 return;
4217 }
4218
4219 /* try to inject new event if pending */
4220 if (vcpu->arch.nmi_pending) {
4221 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4222 vcpu->arch.nmi_pending = false;
4223 vcpu->arch.nmi_injected = true;
4224 kvm_x86_ops->set_nmi(vcpu);
4225 }
4226 } else if (kvm_cpu_has_interrupt(vcpu)) {
4227 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4228 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4229 false);
4230 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4231 }
4232 }
4233}
4234
851ba692 4235static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4236{
4237 int r;
6a8b1d13 4238 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4239 vcpu->run->request_interrupt_window;
b6c7a5dc 4240
2e53d63a
MT		 4241 if (vcpu->requests)
4242 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4243 kvm_mmu_unload(vcpu);
4244
b6c7a5dc
HB		 4245 r = kvm_mmu_reload(vcpu);
4246 if (unlikely(r))
4247 goto out;
4248
2f52d58c
AK		 4249 if (vcpu->requests) {
4250 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4251 __kvm_migrate_timers(vcpu);
c8076604
GH		 4252 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4253 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4254 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4255 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4256 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4257 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4258 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4259 &vcpu->requests)) {
851ba692 4260 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4261 r = 0;
4262 goto out;
4263 }
71c4dfaf 4264 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4265 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4266 r = 0;
4267 goto out;
4268 }
02daab21
AK		 4269 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4270 vcpu->fpu_active = 0;
4271 kvm_x86_ops->fpu_deactivate(vcpu);
4272 }
2f52d58c 4273 }
b93463aa 4274
b6c7a5dc
HB		 4275 preempt_disable();
4276
4277 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4278 if (vcpu->fpu_active)
4279 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4280
4281 local_irq_disable();
4282
32f88400
MT		 4283 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4284 smp_mb__after_clear_bit();
4285
d7690175 4286 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4287 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4288 local_irq_enable();
4289 preempt_enable();
4290 r = 1;
4291 goto out;
4292 }
4293
851ba692 4294 inject_pending_event(vcpu);
b6c7a5dc 4295
6a8b1d13
GN		 4296 /* enable NMI/IRQ window open exits if needed */
4297 if (vcpu->arch.nmi_pending)
4298 kvm_x86_ops->enable_nmi_window(vcpu);
4299 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4300 kvm_x86_ops->enable_irq_window(vcpu);
4301
95ba8273 4302 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4303 update_cr8_intercept(vcpu);
4304 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4305 }
b93463aa 4306
f656ce01 4307 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4308
b6c7a5dc
HB		 4309 kvm_guest_enter();
4310
42dbaa5a 4311 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4312 set_debugreg(0, 7);
4313 set_debugreg(vcpu->arch.eff_db[0], 0);
4314 set_debugreg(vcpu->arch.eff_db[1], 1);
4315 set_debugreg(vcpu->arch.eff_db[2], 2);
4316 set_debugreg(vcpu->arch.eff_db[3], 3);
4317 }
b6c7a5dc 4318
229456fc 4319 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4320 kvm_x86_ops->run(vcpu);
b6c7a5dc 4321
24f1e32c
FW		 4322 /*
4323 * If the guest has used debug registers, at least dr7
4324 * will be disabled while returning to the host.
4325 * If we don't have active breakpoints in the host, we don't
4326 * care about the messed up debug address registers. But if
4327 * we have some of them active, restore the old state.
4328 */
59d8eb53 4329 if (hw_breakpoint_active())
24f1e32c 4330 hw_breakpoint_restore();
42dbaa5a 4331
32f88400 4332 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4333 local_irq_enable();
4334
4335 ++vcpu->stat.exits;
4336
4337 /*
4338 * We must have an instruction between local_irq_enable() and
4339 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4340 * the interrupt shadow. The stat.exits increment will do nicely.
4341 * But we need to prevent reordering, hence this barrier():
4342 */
4343 barrier();
4344
4345 kvm_guest_exit();
4346
4347 preempt_enable();
4348
f656ce01 4349 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4350
b6c7a5dc
HB		 4351 /*
4352 * Profile KVM exit RIPs:
4353 */
4354 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4355 unsigned long rip = kvm_rip_read(vcpu);
4356 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4357 }
4358
298101da 4359
b93463aa
AK		 4360 kvm_lapic_sync_from_vapic(vcpu);
4361
851ba692 4362 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4363out:
4364 return r;
4365}
b6c7a5dc 4366
09cec754 4367
851ba692 4368static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4369{
4370 int r;
f656ce01 4371 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4372
4373 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4374 pr_debug("vcpu %d received sipi with vector # %x\n",
4375 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4376 kvm_lapic_reset(vcpu);
5f179287 4377 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4378 if (r)
4379 return r;
4380 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4381 }
4382
f656ce01 4383 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4384 vapic_enter(vcpu);
4385
4386 r = 1;
4387 while (r > 0) {
af2152f5 4388 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4389 r = vcpu_enter_guest(vcpu);
d7690175 4390 else {
f656ce01 4391 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4392 kvm_vcpu_block(vcpu);
f656ce01 4393 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4394 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4395 {
4396 switch(vcpu->arch.mp_state) {
4397 case KVM_MP_STATE_HALTED:
d7690175 4398 vcpu->arch.mp_state =
09cec754
GN		 4399 KVM_MP_STATE_RUNNABLE;
4400 case KVM_MP_STATE_RUNNABLE:
4401 break;
4402 case KVM_MP_STATE_SIPI_RECEIVED:
4403 default:
4404 r = -EINTR;
4405 break;
4406 }
4407 }
d7690175
MT		 4408 }
4409
09cec754
GN		 4410 if (r <= 0)
4411 break;
4412
4413 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4414 if (kvm_cpu_has_pending_timer(vcpu))
4415 kvm_inject_pending_timer_irqs(vcpu);
4416
851ba692 4417 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4418 r = -EINTR;
851ba692 4419 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4420 ++vcpu->stat.request_irq_exits;
4421 }
4422 if (signal_pending(current)) {
4423 r = -EINTR;
851ba692 4424 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4425 ++vcpu->stat.signal_exits;
4426 }
4427 if (need_resched()) {
f656ce01 4428 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4429 kvm_resched(vcpu);
f656ce01 4430 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4431 }
b6c7a5dc
HB		 4432 }
4433
f656ce01 4434 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4435 post_kvm_run_save(vcpu);
b6c7a5dc 4436
b93463aa
AK		 4437 vapic_exit(vcpu);
4438
b6c7a5dc
HB		 4439 return r;
4440}
4441
4442int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4443{
4444 int r;
4445 sigset_t sigsaved;
4446
4447 vcpu_load(vcpu);
4448
ac9f6dc0
AK		 4449 if (vcpu->sigset_active)
4450 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4451
a4535290 4452 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4453 kvm_vcpu_block(vcpu);
d7690175 4454 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4455 r = -EAGAIN;
4456 goto out;
b6c7a5dc
HB		 4457 }
4458
b6c7a5dc
HB		 4459 /* re-sync apic's tpr */
4460 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4461 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4462
ad312c7c 4463 if (vcpu->arch.pio.cur_count) {
7567cae1 4464 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
b6c7a5dc 4465 r = complete_pio(vcpu);
7567cae1 4466 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4467 if (r)
4468 goto out;
4469 }
b6c7a5dc
HB		 4470 if (vcpu->mmio_needed) {
4471 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4472 vcpu->mmio_read_completed = 1;
4473 vcpu->mmio_needed = 0;
3200f405 4474
f656ce01 4475 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4476 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4477 EMULTYPE_NO_DECODE);
f656ce01 4478 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4479 if (r == EMULATE_DO_MMIO) {
4480 /*
4481 * Read-modify-write. Back to userspace.
4482 */
4483 r = 0;
4484 goto out;
4485 }
4486 }
5fdbf976
MT		 4487 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4488 kvm_register_write(vcpu, VCPU_REGS_RAX,
4489 kvm_run->hypercall.ret);
b6c7a5dc 4490
851ba692 4491 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4492
4493out:
4494 if (vcpu->sigset_active)
4495 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4496
4497 vcpu_put(vcpu);
4498 return r;
4499}
4500
4501int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4502{
4503 vcpu_load(vcpu);
4504
5fdbf976
MT		 4505 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4506 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4507 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4508 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4509 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4510 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4511 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4512 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4513#ifdef CONFIG_X86_64
5fdbf976
MT		 4514 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4515 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4516 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4517 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4518 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4519 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4520 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4521 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4522#endif
4523
5fdbf976 4524 regs->rip = kvm_rip_read(vcpu);
91586a3b 4525 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4526
4527 vcpu_put(vcpu);
4528
4529 return 0;
4530}
4531
4532int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4533{
4534 vcpu_load(vcpu);
4535
5fdbf976
MT		 4536 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4537 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4538 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4539 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4540 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4541 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4542 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4543 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4544#ifdef CONFIG_X86_64
5fdbf976
MT		 4545 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4546 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4547 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4548 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4549 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4550 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4551 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4552 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4553#endif
4554
5fdbf976 4555 kvm_rip_write(vcpu, regs->rip);
91586a3b 4556 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4557
b4f14abd
JK		 4558 vcpu->arch.exception.pending = false;
4559
b6c7a5dc
HB		 4560 vcpu_put(vcpu);
4561
4562 return 0;
4563}
4564
3e6e0aab
GT		 4565void kvm_get_segment(struct kvm_vcpu *vcpu,
4566 struct kvm_segment *var, int seg)
b6c7a5dc 4567{
14af3f3c 4568 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4569}
4570
4571void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4572{
4573 struct kvm_segment cs;
4574
3e6e0aab 4575 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4576 *db = cs.db;
4577 *l = cs.l;
4578}
4579EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4580
4581int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4582 struct kvm_sregs *sregs)
4583{
89a27f4d 4584 struct desc_ptr dt;
b6c7a5dc
HB		 4585
4586 vcpu_load(vcpu);
4587
3e6e0aab
GT		 4588 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4589 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4590 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4591 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4592 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4593 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4594
3e6e0aab
GT		 4595 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4596 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4597
4598 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4599 sregs->idt.limit = dt.size;
4600 sregs->idt.base = dt.address;
b6c7a5dc 4601 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4602 sregs->gdt.limit = dt.size;
4603 sregs->gdt.base = dt.address;
b6c7a5dc 4604
4d4ec087 4605 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4606 sregs->cr2 = vcpu->arch.cr2;
4607 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4608 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4609 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4610 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4611 sregs->apic_base = kvm_get_apic_base(vcpu);
4612
923c61bb 4613 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4614
36752c9b 4615 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4616 set_bit(vcpu->arch.interrupt.nr,
4617 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4618
b6c7a5dc
HB		 4619 vcpu_put(vcpu);
4620
4621 return 0;
4622}
4623
62d9f0db
MT		 4624int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4625 struct kvm_mp_state *mp_state)
4626{
4627 vcpu_load(vcpu);
4628 mp_state->mp_state = vcpu->arch.mp_state;
4629 vcpu_put(vcpu);
4630 return 0;
4631}
4632
4633int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4634 struct kvm_mp_state *mp_state)
4635{
4636 vcpu_load(vcpu);
4637 vcpu->arch.mp_state = mp_state->mp_state;
4638 vcpu_put(vcpu);
4639 return 0;
4640}
4641
3e6e0aab 4642static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4643 struct kvm_segment *var, int seg)
4644{
14af3f3c 4645 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4646}
4647
37817f29
IE		 4648static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4649 struct kvm_segment *kvm_desct)
4650{
46a359e7
AM		 4651 kvm_desct->base = get_desc_base(seg_desc);
4652 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4653 if (seg_desc->g) {
4654 kvm_desct->limit <<= 12;
4655 kvm_desct->limit |= 0xfff;
4656 }
37817f29
IE		 4657 kvm_desct->selector = selector;
4658 kvm_desct->type = seg_desc->type;
4659 kvm_desct->present = seg_desc->p;
4660 kvm_desct->dpl = seg_desc->dpl;
4661 kvm_desct->db = seg_desc->d;
4662 kvm_desct->s = seg_desc->s;
4663 kvm_desct->l = seg_desc->l;
4664 kvm_desct->g = seg_desc->g;
4665 kvm_desct->avl = seg_desc->avl;
4666 if (!selector)
4667 kvm_desct->unusable = 1;
4668 else
4669 kvm_desct->unusable = 0;
4670 kvm_desct->padding = 0;
4671}
4672
b8222ad2
AS		 4673static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4674 u16 selector,
89a27f4d 4675 struct desc_ptr *dtable)
37817f29
IE		 4676{
4677 if (selector & 1 << 2) {
4678 struct kvm_segment kvm_seg;
4679
3e6e0aab 4680 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4681
4682 if (kvm_seg.unusable)
89a27f4d 4683 dtable->size = 0;
37817f29 4684 else
89a27f4d
GN		 4685 dtable->size = kvm_seg.limit;
4686 dtable->address = kvm_seg.base;
37817f29
IE		 4687 }
4688 else
4689 kvm_x86_ops->get_gdt(vcpu, dtable);
4690}
4691
4692/* allowed just for 8 bytes segments */
4693static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4694 struct desc_struct *seg_desc)
4695{
89a27f4d 4696 struct desc_ptr dtable;
37817f29 4697 u16 index = selector >> 3;
6f550484
TY		 4698 int ret;
4699 u32 err;
4700 gva_t addr;
37817f29 4701
b8222ad2 4702 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4703
89a27f4d 4704 if (dtable.size < index * 8 + 7) {
37817f29 4705 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4706 return X86EMUL_PROPAGATE_FAULT;
37817f29 4707 }
6f550484
TY		 4708 addr = dtable.base + index * 8;
4709 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4710 vcpu, &err);
4711 if (ret == X86EMUL_PROPAGATE_FAULT)
4712 kvm_inject_page_fault(vcpu, addr, err);
4713
4714 return ret;
37817f29
IE		 4715}
4716
4717/* allowed just for 8 bytes segments */
4718static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4719 struct desc_struct *seg_desc)
4720{
89a27f4d 4721 struct desc_ptr dtable;
37817f29
IE		 4722 u16 index = selector >> 3;
4723
b8222ad2 4724 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4725
89a27f4d 4726 if (dtable.size < index * 8 + 7)
37817f29 4727 return 1;
89a27f4d 4728 return kvm_write_guest_virt(dtable.address + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
1871c602
GN		 4729}
4730
4731static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4732 struct desc_struct *seg_desc)
4733{
4734 u32 base_addr = get_desc_base(seg_desc);
4735
4736 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4737}
4738
1871c602 4739static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4740 struct desc_struct *seg_desc)
4741{
46a359e7 4742 u32 base_addr = get_desc_base(seg_desc);
37817f29 4743
1871c602 4744 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4745}
4746
37817f29
IE		 4747static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4748{
4749 struct kvm_segment kvm_seg;
4750
3e6e0aab 4751 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4752 return kvm_seg.selector;
4753}
4754
2259e3a7 4755static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4756{
4757 struct kvm_segment segvar = {
4758 .base = selector << 4,
4759 .limit = 0xffff,
4760 .selector = selector,
4761 .type = 3,
4762 .present = 1,
4763 .dpl = 3,
4764 .db = 0,
4765 .s = 1,
4766 .l = 0,
4767 .g = 0,
4768 .avl = 0,
4769 .unusable = 0,
4770 };
4771 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4772 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4773}
4774
c0c7c04b
AL		 4775static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4776{
4777 return (seg != VCPU_SREG_LDTR) &&
4778 (seg != VCPU_SREG_TR) &&
91586a3b 4779 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4780}
4781
c697518a 4782int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4783{
4784 struct kvm_segment kvm_seg;
e01c2426 4785 struct desc_struct seg_desc;
c697518a
GN		 4786 u8 dpl, rpl, cpl;
4787 unsigned err_vec = GP_VECTOR;
4788 u32 err_code = 0;
4789 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4790 int ret;
37817f29 4791
3eeb3288 4792 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4793 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4794
c697518a
GN		 4795 /* NULL selector is not valid for TR, CS and SS */
4796 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4797 && null_selector)
4798 goto exception;
4799
4800 /* TR should be in GDT only */
4801 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4802 goto exception;
4803
4804 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4805 if (ret)
4806 return ret;
4807
e01c2426 4808 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4809
c697518a
GN		 4810 if (null_selector) { /* for NULL selector skip all following checks */
4811 kvm_seg.unusable = 1;
4812 goto load;
4813 }
37817f29 4814
c697518a
GN		 4815 err_code = selector & 0xfffc;
4816 err_vec = GP_VECTOR;
37817f29 4817
c697518a
GN		 4818 /* can't load system descriptor into segment selecor */
4819 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4820 goto exception;
4821
4822 if (!kvm_seg.present) {
4823 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4824 goto exception;
4825 }
4826
4827 rpl = selector & 3;
4828 dpl = kvm_seg.dpl;
4829 cpl = kvm_x86_ops->get_cpl(vcpu);
4830
4831 switch (seg) {
4832 case VCPU_SREG_SS:
4833 /*
4834 * segment is not a writable data segment or segment
4835 * selector's RPL != CPL or segment selector's RPL != CPL
4836 */
4837 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4838 goto exception;
4839 break;
4840 case VCPU_SREG_CS:
4841 if (!(kvm_seg.type & 8))
4842 goto exception;
4843
4844 if (kvm_seg.type & 4) {
4845 /* conforming */
4846 if (dpl > cpl)
4847 goto exception;
4848 } else {
4849 /* nonconforming */
4850 if (rpl > cpl || dpl != cpl)
4851 goto exception;
4852 }
4853 /* CS(RPL) <- CPL */
4854 selector = (selector & 0xfffc) | cpl;
4855 break;
4856 case VCPU_SREG_TR:
4857 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4858 goto exception;
4859 break;
4860 case VCPU_SREG_LDTR:
4861 if (kvm_seg.s || kvm_seg.type != 2)
4862 goto exception;
4863 break;
4864 default: /* DS, ES, FS, or GS */
4865 /*
4866 * segment is not a data or readable code segment or
4867 * ((segment is a data or nonconforming code segment)
4868 * and (both RPL and CPL > DPL))
4869 */
4870 if ((kvm_seg.type & 0xa) == 0x8 ||
4871 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4872 goto exception;
4873 break;
4874 }
4875
4876 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4877 /* mark segment as accessed */
c697518a 4878 kvm_seg.type |= 1;
e01c2426
GN		 4879 seg_desc.type |= 1;
4880 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4881 }
c697518a
GN		 4882load:
4883 kvm_set_segment(vcpu, &kvm_seg, seg);
4884 return X86EMUL_CONTINUE;
4885exception:
4886 kvm_queue_exception_e(vcpu, err_vec, err_code);
4887 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4888}
4889
4890static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4891 struct tss_segment_32 *tss)
4892{
4893 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4894 tss->eip = kvm_rip_read(vcpu);
91586a3b 4895 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4896 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4897 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4898 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4899 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4900 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4901 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4902 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4903 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4904 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4905 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4906 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4907 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4908 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4909 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4910 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4911}
4912
c697518a
GN		 4913static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4914{
4915 struct kvm_segment kvm_seg;
4916 kvm_get_segment(vcpu, &kvm_seg, seg);
4917 kvm_seg.selector = sel;
4918 kvm_set_segment(vcpu, &kvm_seg, seg);
4919}
4920
37817f29
IE		 4921static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4922 struct tss_segment_32 *tss)
4923{
4924 kvm_set_cr3(vcpu, tss->cr3);
4925
5fdbf976 4926 kvm_rip_write(vcpu, tss->eip);
91586a3b 4927 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4928
5fdbf976
MT		 4929 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4930 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4931 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4932 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4933 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4934 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4935 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4936 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4937
c697518a
GN		 4938 /*
4939 * SDM says that segment selectors are loaded before segment
4940 * descriptors
4941 */
4942 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
4943 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
4944 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
4945 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
4946 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
4947 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
4948 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
4949
4950 /*
4951 * Now load segment descriptors. If fault happenes at this stage
4952 * it is handled in a context of new task
4953 */
4954 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 4955 return 1;
4956
c697518a 4957 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 4958 return 1;
4959
c697518a 4960 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 4961 return 1;
4962
c697518a 4963 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 4964 return 1;
4965
c697518a 4966 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 4967 return 1;
4968
c697518a 4969 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 4970 return 1;
4971
c697518a 4972 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 4973 return 1;
4974 return 0;
4975}
4976
4977static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4978 struct tss_segment_16 *tss)
4979{
5fdbf976 4980 tss->ip = kvm_rip_read(vcpu);
91586a3b 4981 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4982 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4983 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4984 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4985 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4986 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4987 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4988 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4989 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4990
4991 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4992 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4993 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4994 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4995 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4996}
4997
4998static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4999 struct tss_segment_16 *tss)
5000{
5fdbf976 5001 kvm_rip_write(vcpu, tss->ip);
91586a3b 5002 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 5003 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
5004 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5005 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5006 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5007 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5008 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5009 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5010 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5011
c697518a
GN		 5012 /*
5013 * SDM says that segment selectors are loaded before segment
5014 * descriptors
5015 */
5016 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5017 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5018 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5019 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5020 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5021
5022 /*
5023 * Now load segment descriptors. If fault happenes at this stage
5024 * it is handled in a context of new task
5025 */
5026 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5027 return 1;
5028
c697518a 5029 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5030 return 1;
5031
c697518a 5032 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5033 return 1;
5034
c697518a 5035 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5036 return 1;
5037
c697518a 5038 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5039 return 1;
5040 return 0;
5041}
5042
8b2cf73c 5043static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5044 u16 old_tss_sel, u32 old_tss_base,
5045 struct desc_struct *nseg_desc)
37817f29
IE		 5046{
5047 struct tss_segment_16 tss_segment_16;
5048 int ret = 0;
5049
34198bf8
MT		 5050 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5051 sizeof tss_segment_16))
37817f29
IE		 5052 goto out;
5053
5054 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5055
34198bf8
MT		 5056 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5057 sizeof tss_segment_16))
37817f29 5058 goto out;
34198bf8 5059
1871c602 5060 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5061 &tss_segment_16, sizeof tss_segment_16))
5062 goto out;
5063
b237ac37
GN		 5064 if (old_tss_sel != 0xffff) {
5065 tss_segment_16.prev_task_link = old_tss_sel;
5066
5067 if (kvm_write_guest(vcpu->kvm,
1871c602 5068 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5069 &tss_segment_16.prev_task_link,
5070 sizeof tss_segment_16.prev_task_link))
5071 goto out;
5072 }
5073
37817f29
IE		 5074 if (load_state_from_tss16(vcpu, &tss_segment_16))
5075 goto out;
5076
5077 ret = 1;
5078out:
5079 return ret;
5080}
5081
8b2cf73c 5082static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5083 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5084 struct desc_struct *nseg_desc)
5085{
5086 struct tss_segment_32 tss_segment_32;
5087 int ret = 0;
5088
34198bf8
MT		 5089 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5090 sizeof tss_segment_32))
37817f29
IE		 5091 goto out;
5092
5093 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5094
34198bf8
MT		 5095 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5096 sizeof tss_segment_32))
5097 goto out;
5098
1871c602 5099 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5100 &tss_segment_32, sizeof tss_segment_32))
37817f29 5101 goto out;
34198bf8 5102
b237ac37
GN		 5103 if (old_tss_sel != 0xffff) {
5104 tss_segment_32.prev_task_link = old_tss_sel;
5105
5106 if (kvm_write_guest(vcpu->kvm,
1871c602 5107 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5108 &tss_segment_32.prev_task_link,
5109 sizeof tss_segment_32.prev_task_link))
5110 goto out;
5111 }
5112
37817f29
IE		 5113 if (load_state_from_tss32(vcpu, &tss_segment_32))
5114 goto out;
5115
5116 ret = 1;
5117out:
5118 return ret;
5119}
5120
5121int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5122{
5123 struct kvm_segment tr_seg;
5124 struct desc_struct cseg_desc;
5125 struct desc_struct nseg_desc;
5126 int ret = 0;
34198bf8
MT		 5127 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5128 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
e8861cfe 5129 u32 desc_limit;
37817f29 5130
1871c602 5131 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5132
34198bf8
MT		 5133 /* FIXME: Handle errors. Failure to read either TSS or their
5134 * descriptors should generate a pagefault.
5135 */
37817f29
IE		 5136 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5137 goto out;
5138
34198bf8 5139 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5140 goto out;
5141
37817f29
IE		 5142 if (reason != TASK_SWITCH_IRET) {
5143 int cpl;
5144
5145 cpl = kvm_x86_ops->get_cpl(vcpu);
5146 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5147 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5148 return 1;
5149 }
5150 }
5151
e8861cfe
JK		 5152 desc_limit = get_desc_limit(&nseg_desc);
5153 if (!nseg_desc.p ||
5154 ((desc_limit < 0x67 && (nseg_desc.type & 8)) ||
5155 desc_limit < 0x2b)) {
37817f29
IE		 5156 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5157 return 1;
5158 }
5159
5160 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5161 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5162 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5163 }
5164
5165 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5166 u32 eflags = kvm_get_rflags(vcpu);
5167 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5168 }
5169
b237ac37
GN		 5170 /* set back link to prev task only if NT bit is set in eflags
5171 note that old_tss_sel is not used afetr this point */
5172 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5173 old_tss_sel = 0xffff;
5174
37817f29 5175 if (nseg_desc.type & 8)
b237ac37
GN		 5176 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5177 old_tss_base, &nseg_desc);
37817f29 5178 else
b237ac37
GN		 5179 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5180 old_tss_base, &nseg_desc);
37817f29
IE		 5181
5182 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5183 u32 eflags = kvm_get_rflags(vcpu);
5184 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5185 }
5186
5187 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5188 nseg_desc.type |= (1 << 1);
37817f29
IE		 5189 save_guest_segment_descriptor(vcpu, tss_selector,
5190 &nseg_desc);
5191 }
5192
4d4ec087 5193 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5194 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5195 tr_seg.type = 11;
3e6e0aab 5196 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5197out:
37817f29
IE		 5198 return ret;
5199}
5200EXPORT_SYMBOL_GPL(kvm_task_switch);
5201
b6c7a5dc
HB		 5202int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5203 struct kvm_sregs *sregs)
5204{
5205 int mmu_reset_needed = 0;
923c61bb 5206 int pending_vec, max_bits;
89a27f4d 5207 struct desc_ptr dt;
b6c7a5dc
HB		 5208
5209 vcpu_load(vcpu);
5210
89a27f4d
GN		 5211 dt.size = sregs->idt.limit;
5212 dt.address = sregs->idt.base;
b6c7a5dc 5213 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5214 dt.size = sregs->gdt.limit;
5215 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5216 kvm_x86_ops->set_gdt(vcpu, &dt);
5217
ad312c7c
ZX		 5218 vcpu->arch.cr2 = sregs->cr2;
5219 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5220 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5221
2d3ad1f4 5222 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5223
f6801dff 5224 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5225 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5226 kvm_set_apic_base(vcpu, sregs->apic_base);
5227
4d4ec087 5228 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5229 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5230 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5231
fc78f519 5232 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5233 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5234 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5235 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5236 mmu_reset_needed = 1;
5237 }
b6c7a5dc
HB		 5238
5239 if (mmu_reset_needed)
5240 kvm_mmu_reset_context(vcpu);
5241
923c61bb
GN		 5242 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5243 pending_vec = find_first_bit(
5244 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5245 if (pending_vec < max_bits) {
66fd3f7f 5246 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5247 pr_debug("Set back pending irq %d\n", pending_vec);
5248 if (irqchip_in_kernel(vcpu->kvm))
5249 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5250 }
5251
3e6e0aab
GT		 5252 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5253 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5254 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5255 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5256 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5257 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5258
3e6e0aab
GT		 5259 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5260 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5261
5f0269f5
ME		 5262 update_cr8_intercept(vcpu);
5263
9c3e4aab 5264 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5265 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5266 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5267 !is_protmode(vcpu))
9c3e4aab
MT		 5268 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5269
b6c7a5dc
HB		 5270 vcpu_put(vcpu);
5271
5272 return 0;
5273}
5274
d0bfb940
JK		 5275int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5276 struct kvm_guest_debug *dbg)
b6c7a5dc 5277{
355be0b9 5278 unsigned long rflags;
ae675ef0 5279 int i, r;
b6c7a5dc
HB		 5280
5281 vcpu_load(vcpu);
5282
4f926bf2
JK		 5283 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5284 r = -EBUSY;
5285 if (vcpu->arch.exception.pending)
5286 goto unlock_out;
5287 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5288 kvm_queue_exception(vcpu, DB_VECTOR);
5289 else
5290 kvm_queue_exception(vcpu, BP_VECTOR);
5291 }
5292
91586a3b
JK		 5293 /*
5294 * Read rflags as long as potentially injected trace flags are still
5295 * filtered out.
5296 */
5297 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5298
5299 vcpu->guest_debug = dbg->control;
5300 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5301 vcpu->guest_debug = 0;
5302
5303 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5304 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5305 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5306 vcpu->arch.switch_db_regs =
5307 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5308 } else {
5309 for (i = 0; i < KVM_NR_DB_REGS; i++)
5310 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5311 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5312 }
5313
94fe45da
JK		 5314 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5315 vcpu->arch.singlestep_cs =
5316 get_segment_selector(vcpu, VCPU_SREG_CS);
5317 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
5318 }
5319
91586a3b
JK		 5320 /*
5321 * Trigger an rflags update that will inject or remove the trace
5322 * flags.
5323 */
5324 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5325
355be0b9 5326 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5327
4f926bf2 5328 r = 0;
d0bfb940 5329
4f926bf2 5330unlock_out:
b6c7a5dc
HB		 5331 vcpu_put(vcpu);
5332
5333 return r;
5334}
5335
d0752060
HB		 5336/*
5337 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5338 * we have asm/x86/processor.h
5339 */
5340struct fxsave {
5341 u16 cwd;
5342 u16 swd;
5343 u16 twd;
5344 u16 fop;
5345 u64 rip;
5346 u64 rdp;
5347 u32 mxcsr;
5348 u32 mxcsr_mask;
5349 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5350#ifdef CONFIG_X86_64
5351 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5352#else
5353 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5354#endif
5355};
5356
8b006791
ZX		 5357/*
5358 * Translate a guest virtual address to a guest physical address.
5359 */
5360int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5361 struct kvm_translation *tr)
5362{
5363 unsigned long vaddr = tr->linear_address;
5364 gpa_t gpa;
f656ce01 5365 int idx;
8b006791
ZX		 5366
5367 vcpu_load(vcpu);
f656ce01 5368 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5369 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5370 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5371 tr->physical_address = gpa;
5372 tr->valid = gpa != UNMAPPED_GVA;
5373 tr->writeable = 1;
5374 tr->usermode = 0;
8b006791
ZX		 5375 vcpu_put(vcpu);
5376
5377 return 0;
5378}
5379
d0752060
HB		 5380int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5381{
ad312c7c 5382 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5383
5384 vcpu_load(vcpu);
5385
5386 memcpy(fpu->fpr, fxsave->st_space, 128);
5387 fpu->fcw = fxsave->cwd;
5388 fpu->fsw = fxsave->swd;
5389 fpu->ftwx = fxsave->twd;
5390 fpu->last_opcode = fxsave->fop;
5391 fpu->last_ip = fxsave->rip;
5392 fpu->last_dp = fxsave->rdp;
5393 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5394
5395 vcpu_put(vcpu);
5396
5397 return 0;
5398}
5399
5400int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5401{
ad312c7c 5402 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5403
5404 vcpu_load(vcpu);
5405
5406 memcpy(fxsave->st_space, fpu->fpr, 128);
5407 fxsave->cwd = fpu->fcw;
5408 fxsave->swd = fpu->fsw;
5409 fxsave->twd = fpu->ftwx;
5410 fxsave->fop = fpu->last_opcode;
5411 fxsave->rip = fpu->last_ip;
5412 fxsave->rdp = fpu->last_dp;
5413 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5414
5415 vcpu_put(vcpu);
5416
5417 return 0;
5418}
5419
5420void fx_init(struct kvm_vcpu *vcpu)
5421{
5422 unsigned after_mxcsr_mask;
5423
bc1a34f1
AA		 5424 /*
5425 * Touch the fpu the first time in non atomic context as if
5426 * this is the first fpu instruction the exception handler
5427 * will fire before the instruction returns and it'll have to
5428 * allocate ram with GFP_KERNEL.
5429 */
5430 if (!used_math())
d6e88aec 5431 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5432
d0752060
HB		 5433 /* Initialize guest FPU by resetting ours and saving into guest's */
5434 preempt_disable();
d6e88aec
AK		 5435 kvm_fx_save(&vcpu->arch.host_fx_image);
5436 kvm_fx_finit();
5437 kvm_fx_save(&vcpu->arch.guest_fx_image);
5438 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5439 preempt_enable();
5440
ad312c7c 5441 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5442 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5443 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5444 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5445 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5446}
5447EXPORT_SYMBOL_GPL(fx_init);
5448
5449void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5450{
2608d7a1 5451 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5452 return;
5453
5454 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5455 kvm_fx_save(&vcpu->arch.host_fx_image);
5456 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5457 trace_kvm_fpu(1);
d0752060 5458}
d0752060
HB		 5459
5460void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5461{
5462 if (!vcpu->guest_fpu_loaded)
5463 return;
5464
5465 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5466 kvm_fx_save(&vcpu->arch.guest_fx_image);
5467 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5468 ++vcpu->stat.fpu_reload;
02daab21 5469 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5470 trace_kvm_fpu(0);
d0752060 5471}
e9b11c17
ZX		 5472
5473void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5474{
7f1ea208
JR		 5475 if (vcpu->arch.time_page) {
5476 kvm_release_page_dirty(vcpu->arch.time_page);
5477 vcpu->arch.time_page = NULL;
5478 }
5479
e9b11c17
ZX		 5480 kvm_x86_ops->vcpu_free(vcpu);
5481}
5482
5483struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5484 unsigned int id)
5485{
26e5215f
AK		 5486 return kvm_x86_ops->vcpu_create(kvm, id);
5487}
e9b11c17 5488
26e5215f
AK		 5489int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5490{
5491 int r;
e9b11c17
ZX		 5492
5493 /* We do fxsave: this must be aligned. */
ad312c7c 5494 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5495
0bed3b56 5496 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5497 vcpu_load(vcpu);
5498 r = kvm_arch_vcpu_reset(vcpu);
5499 if (r == 0)
5500 r = kvm_mmu_setup(vcpu);
5501 vcpu_put(vcpu);
5502 if (r < 0)
5503 goto free_vcpu;
5504
26e5215f 5505 return 0;
e9b11c17
ZX		 5506free_vcpu:
5507 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5508 return r;
e9b11c17
ZX		 5509}
5510
d40ccc62 5511void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5512{
5513 vcpu_load(vcpu);
5514 kvm_mmu_unload(vcpu);
5515 vcpu_put(vcpu);
5516
5517 kvm_x86_ops->vcpu_free(vcpu);
5518}
5519
5520int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5521{
448fa4a9
JK		 5522 vcpu->arch.nmi_pending = false;
5523 vcpu->arch.nmi_injected = false;
5524
42dbaa5a
JK		 5525 vcpu->arch.switch_db_regs = 0;
5526 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5527 vcpu->arch.dr6 = DR6_FIXED_1;
5528 vcpu->arch.dr7 = DR7_FIXED_1;
5529
e9b11c17
ZX		 5530 return kvm_x86_ops->vcpu_reset(vcpu);
5531}
5532
10474ae8 5533int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5534{
0cca7907
ZA		 5535 /*
5536 * Since this may be called from a hotplug notifcation,
5537 * we can't get the CPU frequency directly.
5538 */
5539 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5540 int cpu = raw_smp_processor_id();
5541 per_cpu(cpu_tsc_khz, cpu) = 0;
5542 }
18863bdd
AK		 5543
5544 kvm_shared_msr_cpu_online();
5545
10474ae8 5546 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5547}
5548
5549void kvm_arch_hardware_disable(void *garbage)
5550{
5551 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5552 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5553}
5554
5555int kvm_arch_hardware_setup(void)
5556{
5557 return kvm_x86_ops->hardware_setup();
5558}
5559
5560void kvm_arch_hardware_unsetup(void)
5561{
5562 kvm_x86_ops->hardware_unsetup();
5563}
5564
5565void kvm_arch_check_processor_compat(void *rtn)
5566{
5567 kvm_x86_ops->check_processor_compatibility(rtn);
5568}
5569
5570int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5571{
5572 struct page *page;
5573 struct kvm *kvm;
5574 int r;
5575
5576 BUG_ON(vcpu->kvm == NULL);
5577 kvm = vcpu->kvm;
5578
ad312c7c 5579 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5580 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5581 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5582 else
a4535290 5583 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5584
5585 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5586 if (!page) {
5587 r = -ENOMEM;
5588 goto fail;
5589 }
ad312c7c 5590 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5591
5592 r = kvm_mmu_create(vcpu);
5593 if (r < 0)
5594 goto fail_free_pio_data;
5595
5596 if (irqchip_in_kernel(kvm)) {
5597 r = kvm_create_lapic(vcpu);
5598 if (r < 0)
5599 goto fail_mmu_destroy;
5600 }
5601
890ca9ae
HY		 5602 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5603 GFP_KERNEL);
5604 if (!vcpu->arch.mce_banks) {
5605 r = -ENOMEM;
443c39bc 5606 goto fail_free_lapic;
890ca9ae
HY		 5607 }
5608 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5609
e9b11c17 5610 return 0;
443c39bc
WY		 5611fail_free_lapic:
5612 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5613fail_mmu_destroy:
5614 kvm_mmu_destroy(vcpu);
5615fail_free_pio_data:
ad312c7c 5616 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5617fail:
5618 return r;
5619}
5620
5621void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5622{
f656ce01
MT		 5623 int idx;
5624
36cb93fd 5625 kfree(vcpu->arch.mce_banks);
e9b11c17 5626 kvm_free_lapic(vcpu);
f656ce01 5627 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5628 kvm_mmu_destroy(vcpu);
f656ce01 5629 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5630 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5631}
d19a9cd2
ZX		 5632
5633struct kvm *kvm_arch_create_vm(void)
5634{
5635 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5636
5637 if (!kvm)
5638 return ERR_PTR(-ENOMEM);
5639
fef9cce0
MT		 5640 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5641 if (!kvm->arch.aliases) {
5642 kfree(kvm);
5643 return ERR_PTR(-ENOMEM);
5644 }
5645
f05e70ac 5646 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5647 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5648
5550af4d
SY		 5649 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5650 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5651
53f658b3
MT		 5652 rdtscll(kvm->arch.vm_init_tsc);
5653
d19a9cd2
ZX		 5654 return kvm;
5655}
5656
5657static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5658{
5659 vcpu_load(vcpu);
5660 kvm_mmu_unload(vcpu);
5661 vcpu_put(vcpu);
5662}
5663
5664static void kvm_free_vcpus(struct kvm *kvm)
5665{
5666 unsigned int i;
988a2cae 5667 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5668
5669 /*
5670 * Unpin any mmu pages first.
5671 */
988a2cae
GN		 5672 kvm_for_each_vcpu(i, vcpu, kvm)
5673 kvm_unload_vcpu_mmu(vcpu);
5674 kvm_for_each_vcpu(i, vcpu, kvm)
5675 kvm_arch_vcpu_free(vcpu);
5676
5677 mutex_lock(&kvm->lock);
5678 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5679 kvm->vcpus[i] = NULL;
d19a9cd2 5680
988a2cae
GN		 5681 atomic_set(&kvm->online_vcpus, 0);
5682 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5683}
5684
ad8ba2cd
SY		 5685void kvm_arch_sync_events(struct kvm *kvm)
5686{
ba4cef31 5687 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5688}
5689
d19a9cd2
ZX		 5690void kvm_arch_destroy_vm(struct kvm *kvm)
5691{
6eb55818 5692 kvm_iommu_unmap_guest(kvm);
7837699f 5693 kvm_free_pit(kvm);
d7deeeb0
ZX		 5694 kfree(kvm->arch.vpic);
5695 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5696 kvm_free_vcpus(kvm);
5697 kvm_free_physmem(kvm);
3d45830c
AK		 5698 if (kvm->arch.apic_access_page)
5699 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5700 if (kvm->arch.ept_identity_pagetable)
5701 put_page(kvm->arch.ept_identity_pagetable);
64749204 5702 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5703 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5704 kfree(kvm);
5705}
0de10343 5706
f7784b8e
MT		 5707int kvm_arch_prepare_memory_region(struct kvm *kvm,
5708 struct kvm_memory_slot *memslot,
0de10343 5709 struct kvm_memory_slot old,
f7784b8e 5710 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5711 int user_alloc)
5712{
f7784b8e 5713 int npages = memslot->npages;
0de10343
ZX		 5714
5715 /*To keep backward compatibility with older userspace,
5716 *x86 needs to hanlde !user_alloc case.
5717 */
5718 if (!user_alloc) {
5719 if (npages && !old.rmap) {
604b38ac
AA		 5720 unsigned long userspace_addr;
5721
72dc67a6 5722 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5723 userspace_addr = do_mmap(NULL, 0,
5724 npages * PAGE_SIZE,
5725 PROT_READ | PROT_WRITE,
acee3c04 5726 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5727 0);
72dc67a6 5728 up_write(&current->mm->mmap_sem);
0de10343 5729
604b38ac
AA		 5730 if (IS_ERR((void *)userspace_addr))
5731 return PTR_ERR((void *)userspace_addr);
5732
604b38ac 5733 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5734 }
5735 }
5736
f7784b8e
MT		 5737
5738 return 0;
5739}
5740
5741void kvm_arch_commit_memory_region(struct kvm *kvm,
5742 struct kvm_userspace_memory_region *mem,
5743 struct kvm_memory_slot old,
5744 int user_alloc)
5745{
5746
5747 int npages = mem->memory_size >> PAGE_SHIFT;
5748
5749 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5750 int ret;
5751
5752 down_write(&current->mm->mmap_sem);
5753 ret = do_munmap(current->mm, old.userspace_addr,
5754 old.npages * PAGE_SIZE);
5755 up_write(&current->mm->mmap_sem);
5756 if (ret < 0)
5757 printk(KERN_WARNING
5758 "kvm_vm_ioctl_set_memory_region: "
5759 "failed to munmap memory\n");
5760 }
5761
7c8a83b7 5762 spin_lock(&kvm->mmu_lock);
f05e70ac 5763 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5764 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5765 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5766 }
5767
5768 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5769 spin_unlock(&kvm->mmu_lock);
0de10343 5770}
1d737c8a 5771
34d4cb8f
MT		 5772void kvm_arch_flush_shadow(struct kvm *kvm)
5773{
5774 kvm_mmu_zap_all(kvm);
8986ecc0 5775 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5776}
5777
1d737c8a
ZX		 5778int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5779{
a4535290 5780 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5781 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5782 || vcpu->arch.nmi_pending ||
5783 (kvm_arch_interrupt_allowed(vcpu) &&
5784 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5785}
5736199a 5786
5736199a
ZX		 5787void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5788{
32f88400
MT		 5789 int me;
5790 int cpu = vcpu->cpu;
5736199a
ZX		 5791
5792 if (waitqueue_active(&vcpu->wq)) {
5793 wake_up_interruptible(&vcpu->wq);
5794 ++vcpu->stat.halt_wakeup;
5795 }
32f88400
MT		 5796
5797 me = get_cpu();
5798 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5799 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5800 smp_send_reschedule(cpu);
e9571ed5 5801 put_cpu();
5736199a 5802}
78646121
GN		 5803
5804int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5805{
5806 return kvm_x86_ops->interrupt_allowed(vcpu);
5807}
229456fc 5808
94fe45da
JK		 5809unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5810{
5811 unsigned long rflags;
5812
5813 rflags = kvm_x86_ops->get_rflags(vcpu);
5814 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5815 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5816 return rflags;
5817}
5818EXPORT_SYMBOL_GPL(kvm_get_rflags);
5819
5820void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5821{
5822 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5823 vcpu->arch.singlestep_cs ==
5824 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5825 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5826 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5827 kvm_x86_ops->set_rflags(vcpu, rflags);
5828}
5829EXPORT_SYMBOL_GPL(kvm_set_rflags);
5830
229456fc
MT		 5831EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5832EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5833EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5834EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5835EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5836EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5837EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5838EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5839EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5840EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5841EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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