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Merge branch 'x86-mem-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
043405e1 58
313a3dc7 59#define MAX_IO_MSRS 256
a03490ed
CO		 60#define CR0_RESERVED_BITS \
61 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
62 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
63 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
64#define CR4_RESERVED_BITS \
65 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
66 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
67 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 68 | X86_CR4_OSXSAVE \
a03490ed
CO		 69 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
70
71#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 72
73#define KVM_MAX_MCE_BANKS 32
74#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
75
50a37eb4
JR		 76/* EFER defaults:
77 * - enable syscall per default because its emulated by KVM
78 * - enable LME and LMA per default on 64 bit KVM
79 */
80#ifdef CONFIG_X86_64
81static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
82#else
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 90static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
91 struct kvm_cpuid_entry2 __user *entries);
92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
ed85c068
AP		 96int ignore_msrs = 0;
97module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
156static inline u32 bit(int bitno)
157{
158 return 1 << (bitno & 31);
159}
160
18863bdd
AK		 161static void kvm_on_user_return(struct user_return_notifier *urn)
162{
163 unsigned slot;
18863bdd
AK		 164 struct kvm_shared_msrs *locals
165 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 166 struct kvm_shared_msr_values *values;
18863bdd
AK		 167
168 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 169 values = &locals->values[slot];
170 if (values->host != values->curr) {
171 wrmsrl(shared_msrs_global.msrs[slot], values->host);
172 values->curr = values->host;
18863bdd
AK		 173 }
174 }
175 locals->registered = false;
176 user_return_notifier_unregister(urn);
177}
178
2bf78fa7 179static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 180{
2bf78fa7 181 struct kvm_shared_msrs *smsr;
18863bdd
AK		 182 u64 value;
183
2bf78fa7
SY		 184 smsr = &__get_cpu_var(shared_msrs);
185 /* only read, and nobody should modify it at this time,
186 * so don't need lock */
187 if (slot >= shared_msrs_global.nr) {
188 printk(KERN_ERR "kvm: invalid MSR slot!");
189 return;
190 }
191 rdmsrl_safe(msr, &value);
192 smsr->values[slot].host = value;
193 smsr->values[slot].curr = value;
194}
195
196void kvm_define_shared_msr(unsigned slot, u32 msr)
197{
18863bdd
AK		 198 if (slot >= shared_msrs_global.nr)
199 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 200 shared_msrs_global.msrs[slot] = msr;
201 /* we need ensured the shared_msr_global have been updated */
202 smp_wmb();
18863bdd
AK		 203}
204EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
205
206static void kvm_shared_msr_cpu_online(void)
207{
208 unsigned i;
18863bdd
AK		 209
210 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 211 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 212}
213
d5696725 214void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 215{
216 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
217
2bf78fa7 218 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 219 return;
2bf78fa7
SY		 220 smsr->values[slot].curr = value;
221 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 222 if (!smsr->registered) {
223 smsr->urn.on_user_return = kvm_on_user_return;
224 user_return_notifier_register(&smsr->urn);
225 smsr->registered = true;
226 }
227}
228EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
229
3548bab5
AK		 230static void drop_user_return_notifiers(void *ignore)
231{
232 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
233
234 if (smsr->registered)
235 kvm_on_user_return(&smsr->urn);
236}
237
6866b83e
CO		 238u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
239{
240 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 241 return vcpu->arch.apic_base;
6866b83e 242 else
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e
CO		 244}
245EXPORT_SYMBOL_GPL(kvm_get_apic_base);
246
247void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
248{
249 /* TODO: reserve bits check */
250 if (irqchip_in_kernel(vcpu->kvm))
251 kvm_lapic_set_base(vcpu, data);
252 else
ad312c7c 253 vcpu->arch.apic_base = data;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_set_apic_base);
256
3fd28fce
ED		 257#define EXCPT_BENIGN 0
258#define EXCPT_CONTRIBUTORY 1
259#define EXCPT_PF 2
260
261static int exception_class(int vector)
262{
263 switch (vector) {
264 case PF_VECTOR:
265 return EXCPT_PF;
266 case DE_VECTOR:
267 case TS_VECTOR:
268 case NP_VECTOR:
269 case SS_VECTOR:
270 case GP_VECTOR:
271 return EXCPT_CONTRIBUTORY;
272 default:
273 break;
274 }
275 return EXCPT_BENIGN;
276}
277
278static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 279 unsigned nr, bool has_error, u32 error_code,
280 bool reinject)
3fd28fce
ED		 281{
282 u32 prev_nr;
283 int class1, class2;
284
285 if (!vcpu->arch.exception.pending) {
286 queue:
287 vcpu->arch.exception.pending = true;
288 vcpu->arch.exception.has_error_code = has_error;
289 vcpu->arch.exception.nr = nr;
290 vcpu->arch.exception.error_code = error_code;
3f0fd292 291 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 292 return;
293 }
294
295 /* to check exception */
296 prev_nr = vcpu->arch.exception.nr;
297 if (prev_nr == DF_VECTOR) {
298 /* triple fault -> shutdown */
a8eeb04a 299 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 300 return;
301 }
302 class1 = exception_class(prev_nr);
303 class2 = exception_class(nr);
304 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
305 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
306 /* generate double fault per SDM Table 5-5 */
307 vcpu->arch.exception.pending = true;
308 vcpu->arch.exception.has_error_code = true;
309 vcpu->arch.exception.nr = DF_VECTOR;
310 vcpu->arch.exception.error_code = 0;
311 } else
312 /* replace previous exception with a new one in a hope
313 that instruction re-execution will regenerate lost
314 exception */
315 goto queue;
316}
317
298101da
AK		 318void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
319{
ce7ddec4 320 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 321}
322EXPORT_SYMBOL_GPL(kvm_queue_exception);
323
ce7ddec4
JR		 324void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
326 kvm_multiple_exception(vcpu, nr, false, 0, true);
327}
328EXPORT_SYMBOL_GPL(kvm_requeue_exception);
329
c3c91fee
AK		 330void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
331 u32 error_code)
332{
333 ++vcpu->stat.pf_guest;
ad312c7c 334 vcpu->arch.cr2 = addr;
c3c91fee
AK		 335 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
336}
337
3419ffc8
SY		 338void kvm_inject_nmi(struct kvm_vcpu *vcpu)
339{
340 vcpu->arch.nmi_pending = 1;
341}
342EXPORT_SYMBOL_GPL(kvm_inject_nmi);
343
298101da
AK		 344void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
345{
ce7ddec4 346 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 347}
348EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
349
ce7ddec4
JR		 350void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
351{
352 kvm_multiple_exception(vcpu, nr, true, error_code, true);
353}
354EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
355
0a79b009
AK		 356/*
357 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
358 * a #GP and return false.
359 */
360bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 361{
0a79b009
AK		 362 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
363 return true;
364 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
365 return false;
298101da 366}
0a79b009 367EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 368
a03490ed
CO		 369/*
370 * Load the pae pdptrs. Return true is they are all valid.
371 */
372int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
373{
374 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
375 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
376 int i;
377 int ret;
ad312c7c 378 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 379
a03490ed
CO		 380 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
381 offset * sizeof(u64), sizeof(pdpte));
382 if (ret < 0) {
383 ret = 0;
384 goto out;
385 }
386 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 387 if (is_present_gpte(pdpte[i]) &&
20c466b5 388 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 389 ret = 0;
390 goto out;
391 }
392 }
393 ret = 1;
394
ad312c7c 395 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 396 __set_bit(VCPU_EXREG_PDPTR,
397 (unsigned long *)&vcpu->arch.regs_avail);
398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 400out:
a03490ed
CO		 401
402 return ret;
403}
cc4b6871 404EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 405
d835dfec
AK		 406static bool pdptrs_changed(struct kvm_vcpu *vcpu)
407{
ad312c7c 408 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 409 bool changed = true;
410 int r;
411
412 if (is_long_mode(vcpu) || !is_pae(vcpu))
413 return false;
414
6de4f3ad
AK		 415 if (!test_bit(VCPU_EXREG_PDPTR,
416 (unsigned long *)&vcpu->arch.regs_avail))
417 return true;
418
ad312c7c 419 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 420 if (r < 0)
421 goto out;
ad312c7c 422 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 423out:
d835dfec
AK		 424
425 return changed;
426}
427
49a9b07e 428int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 429{
aad82703
SY		 430 unsigned long old_cr0 = kvm_read_cr0(vcpu);
431 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
432 X86_CR0_CD | X86_CR0_NW;
433
f9a48e6a
AK		 434 cr0 |= X86_CR0_ET;
435
ab344828 436#ifdef CONFIG_X86_64
0f12244f
GN		 437 if (cr0 & 0xffffffff00000000UL)
438 return 1;
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 442
0f12244f
GN		 443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
444 return 1;
a03490ed 445
0f12244f
GN		 446 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
447 return 1;
a03490ed
CO		 448
449 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
450#ifdef CONFIG_X86_64
f6801dff 451 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 452 int cs_db, cs_l;
453
0f12244f
GN		 454 if (!is_pae(vcpu))
455 return 1;
a03490ed 456 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 457 if (cs_l)
458 return 1;
a03490ed
CO		 459 } else
460#endif
0f12244f
GN		 461 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
462 return 1;
a03490ed
CO		 463 }
464
465 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 466
aad82703
SY		 467 if ((cr0 ^ old_cr0) & update_bits)
468 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 469 return 0;
470}
2d3ad1f4 471EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 472
2d3ad1f4 473void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 474{
49a9b07e 475 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 476}
2d3ad1f4 477EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 478
2acf923e
DC		 479int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
480{
481 u64 xcr0;
482
483 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
484 if (index != XCR_XFEATURE_ENABLED_MASK)
485 return 1;
486 xcr0 = xcr;
487 if (kvm_x86_ops->get_cpl(vcpu) != 0)
488 return 1;
489 if (!(xcr0 & XSTATE_FP))
490 return 1;
491 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
492 return 1;
493 if (xcr0 & ~host_xcr0)
494 return 1;
495 vcpu->arch.xcr0 = xcr0;
496 vcpu->guest_xcr0_loaded = 0;
497 return 0;
498}
499
500int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
501{
502 if (__kvm_set_xcr(vcpu, index, xcr)) {
503 kvm_inject_gp(vcpu, 0);
504 return 1;
505 }
506 return 0;
507}
508EXPORT_SYMBOL_GPL(kvm_set_xcr);
509
510static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
511{
512 struct kvm_cpuid_entry2 *best;
513
514 best = kvm_find_cpuid_entry(vcpu, 1, 0);
515 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
516}
517
518static void update_cpuid(struct kvm_vcpu *vcpu)
519{
520 struct kvm_cpuid_entry2 *best;
521
522 best = kvm_find_cpuid_entry(vcpu, 1, 0);
523 if (!best)
524 return;
525
526 /* Update OSXSAVE bit */
527 if (cpu_has_xsave && best->function == 0x1) {
528 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
529 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
530 best->ecx |= bit(X86_FEATURE_OSXSAVE);
531 }
532}
533
a83b29c6 534int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 535{
fc78f519 536 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 537 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
538
0f12244f
GN		 539 if (cr4 & CR4_RESERVED_BITS)
540 return 1;
a03490ed 541
2acf923e
DC		 542 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
543 return 1;
544
a03490ed 545 if (is_long_mode(vcpu)) {
0f12244f
GN		 546 if (!(cr4 & X86_CR4_PAE))
547 return 1;
a2edf57f
AK		 548 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
549 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 550 && !load_pdptrs(vcpu, vcpu->arch.cr3))
551 return 1;
552
553 if (cr4 & X86_CR4_VMXE)
554 return 1;
a03490ed 555
a03490ed 556 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 557
aad82703
SY		 558 if ((cr4 ^ old_cr4) & pdptr_bits)
559 kvm_mmu_reset_context(vcpu);
0f12244f 560
2acf923e
DC		 561 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
562 update_cpuid(vcpu);
563
0f12244f
GN		 564 return 0;
565}
2d3ad1f4 566EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 567
2390218b 568int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 569{
ad312c7c 570 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 571 kvm_mmu_sync_roots(vcpu);
d835dfec 572 kvm_mmu_flush_tlb(vcpu);
0f12244f 573 return 0;
d835dfec
AK		 574 }
575
a03490ed 576 if (is_long_mode(vcpu)) {
0f12244f
GN		 577 if (cr3 & CR3_L_MODE_RESERVED_BITS)
578 return 1;
a03490ed
CO		 579 } else {
580 if (is_pae(vcpu)) {
0f12244f
GN		 581 if (cr3 & CR3_PAE_RESERVED_BITS)
582 return 1;
583 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
584 return 1;
a03490ed
CO		 585 }
586 /*
587 * We don't check reserved bits in nonpae mode, because
588 * this isn't enforced, and VMware depends on this.
589 */
590 }
591
a03490ed
CO		 592 /*
593 * Does the new cr3 value map to physical memory? (Note, we
594 * catch an invalid cr3 even in real-mode, because it would
595 * cause trouble later on when we turn on paging anyway.)
596 *
597 * A real CPU would silently accept an invalid cr3 and would
598 * attempt to use it - with largely undefined (and often hard
599 * to debug) behavior on the guest side.
600 */
601 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 602 return 1;
603 vcpu->arch.cr3 = cr3;
604 vcpu->arch.mmu.new_cr3(vcpu);
605 return 0;
606}
2d3ad1f4 607EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 608
0f12244f 609int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 610{
0f12244f
GN		 611 if (cr8 & CR8_RESERVED_BITS)
612 return 1;
a03490ed
CO		 613 if (irqchip_in_kernel(vcpu->kvm))
614 kvm_lapic_set_tpr(vcpu, cr8);
615 else
ad312c7c 616 vcpu->arch.cr8 = cr8;
0f12244f
GN		 617 return 0;
618}
619
620void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
621{
622 if (__kvm_set_cr8(vcpu, cr8))
623 kvm_inject_gp(vcpu, 0);
a03490ed 624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 626
2d3ad1f4 627unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 628{
629 if (irqchip_in_kernel(vcpu->kvm))
630 return kvm_lapic_get_cr8(vcpu);
631 else
ad312c7c 632 return vcpu->arch.cr8;
a03490ed 633}
2d3ad1f4 634EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 635
338dbc97 636static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 637{
638 switch (dr) {
639 case 0 ... 3:
640 vcpu->arch.db[dr] = val;
641 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
642 vcpu->arch.eff_db[dr] = val;
643 break;
644 case 4:
338dbc97
GN		 645 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
646 return 1; /* #UD */
020df079
GN		 647 /* fall through */
648 case 6:
338dbc97
GN		 649 if (val & 0xffffffff00000000ULL)
650 return -1; /* #GP */
020df079
GN		 651 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
652 break;
653 case 5:
338dbc97
GN		 654 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
655 return 1; /* #UD */
020df079
GN		 656 /* fall through */
657 default: /* 7 */
338dbc97
GN		 658 if (val & 0xffffffff00000000ULL)
659 return -1; /* #GP */
020df079
GN		 660 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
661 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
662 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
663 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
664 }
665 break;
666 }
667
668 return 0;
669}
338dbc97
GN		 670
671int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
672{
673 int res;
674
675 res = __kvm_set_dr(vcpu, dr, val);
676 if (res > 0)
677 kvm_queue_exception(vcpu, UD_VECTOR);
678 else if (res < 0)
679 kvm_inject_gp(vcpu, 0);
680
681 return res;
682}
020df079
GN		 683EXPORT_SYMBOL_GPL(kvm_set_dr);
684
338dbc97 685static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 686{
687 switch (dr) {
688 case 0 ... 3:
689 *val = vcpu->arch.db[dr];
690 break;
691 case 4:
338dbc97 692 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 693 return 1;
020df079
GN		 694 /* fall through */
695 case 6:
696 *val = vcpu->arch.dr6;
697 break;
698 case 5:
338dbc97 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 700 return 1;
020df079
GN		 701 /* fall through */
702 default: /* 7 */
703 *val = vcpu->arch.dr7;
704 break;
705 }
706
707 return 0;
708}
338dbc97
GN		 709
710int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
711{
712 if (_kvm_get_dr(vcpu, dr, val)) {
713 kvm_queue_exception(vcpu, UD_VECTOR);
714 return 1;
715 }
716 return 0;
717}
020df079
GN		 718EXPORT_SYMBOL_GPL(kvm_get_dr);
719
043405e1
CO		 720/*
721 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
722 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
723 *
724 * This list is modified at module load time to reflect the
e3267cbb
GC		 725 * capabilities of the host cpu. This capabilities test skips MSRs that are
726 * kvm-specific. Those are put in the beginning of the list.
043405e1 727 */
e3267cbb 728
11c6bffa 729#define KVM_SAVE_MSRS_BEGIN 7
043405e1 730static u32 msrs_to_save[] = {
e3267cbb 731 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 732 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 733 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 734 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 735 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 736 MSR_STAR,
043405e1
CO		 737#ifdef CONFIG_X86_64
738 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
739#endif
e3267cbb 740 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 741};
742
743static unsigned num_msrs_to_save;
744
745static u32 emulated_msrs[] = {
746 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 747 MSR_IA32_MCG_STATUS,
748 MSR_IA32_MCG_CTL,
043405e1
CO		 749};
750
b69e8cae 751static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 752{
aad82703
SY		 753 u64 old_efer = vcpu->arch.efer;
754
b69e8cae
RJ		 755 if (efer & efer_reserved_bits)
756 return 1;
15c4a640
CO		 757
758 if (is_paging(vcpu)
b69e8cae
RJ		 759 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
760 return 1;
15c4a640 761
1b2fd70c
AG		 762 if (efer & EFER_FFXSR) {
763 struct kvm_cpuid_entry2 *feat;
764
765 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 766 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
767 return 1;
1b2fd70c
AG		 768 }
769
d8017474
AG		 770 if (efer & EFER_SVME) {
771 struct kvm_cpuid_entry2 *feat;
772
773 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 774 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
775 return 1;
d8017474
AG		 776 }
777
15c4a640 778 efer &= ~EFER_LMA;
f6801dff 779 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 780
a3d204e2
SY		 781 kvm_x86_ops->set_efer(vcpu, efer);
782
9645bb56
AK		 783 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
784 kvm_mmu_reset_context(vcpu);
b69e8cae 785
aad82703
SY		 786 /* Update reserved bits */
787 if ((efer ^ old_efer) & EFER_NX)
788 kvm_mmu_reset_context(vcpu);
789
b69e8cae 790 return 0;
15c4a640
CO		 791}
792
f2b4b7dd
JR		 793void kvm_enable_efer_bits(u64 mask)
794{
795 efer_reserved_bits &= ~mask;
796}
797EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
798
799
15c4a640
CO		 800/*
801 * Writes msr value into into the appropriate "register".
802 * Returns 0 on success, non-0 otherwise.
803 * Assumes vcpu_load() was already called.
804 */
805int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
806{
807 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
808}
809
313a3dc7
CO		 810/*
811 * Adapt set_msr() to msr_io()'s calling convention
812 */
813static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
814{
815 return kvm_set_msr(vcpu, index, *data);
816}
817
18068523
GOC		 818static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
819{
9ed3c444
AK		 820 int version;
821 int r;
50d0a0f9 822 struct pvclock_wall_clock wc;
923de3cf 823 struct timespec boot;
18068523
GOC		 824
825 if (!wall_clock)
826 return;
827
9ed3c444
AK		 828 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
829 if (r)
830 return;
831
832 if (version & 1)
833 ++version; /* first time write, random junk */
834
835 ++version;
18068523 836
18068523
GOC		 837 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
838
50d0a0f9
GH		 839 /*
840 * The guest calculates current wall clock time by adding
841 * system time (updated by kvm_write_guest_time below) to the
842 * wall clock specified here. guest system time equals host
843 * system time for us, thus we must fill in host boot time here.
844 */
923de3cf 845 getboottime(&boot);
50d0a0f9
GH		 846
847 wc.sec = boot.tv_sec;
848 wc.nsec = boot.tv_nsec;
849 wc.version = version;
18068523
GOC		 850
851 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
852
853 version++;
854 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 855}
856
50d0a0f9
GH		 857static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
858{
859 uint32_t quotient, remainder;
860
861 /* Don't try to replace with do_div(), this one calculates
862 * "(dividend << 32) / divisor" */
863 __asm__ ( "divl %4"
864 : "=a" (quotient), "=d" (remainder)
865 : "0" (0), "1" (dividend), "r" (divisor) );
866 return quotient;
867}
868
869static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
870{
871 uint64_t nsecs = 1000000000LL;
872 int32_t shift = 0;
873 uint64_t tps64;
874 uint32_t tps32;
875
876 tps64 = tsc_khz * 1000LL;
877 while (tps64 > nsecs*2) {
878 tps64 >>= 1;
879 shift--;
880 }
881
882 tps32 = (uint32_t)tps64;
883 while (tps32 <= (uint32_t)nsecs) {
884 tps32 <<= 1;
885 shift++;
886 }
887
888 hv_clock->tsc_shift = shift;
889 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
890
891 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 892 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 893 hv_clock->tsc_to_system_mul);
894}
895
c8076604
GH		 896static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
897
18068523
GOC		 898static void kvm_write_guest_time(struct kvm_vcpu *v)
899{
900 struct timespec ts;
901 unsigned long flags;
902 struct kvm_vcpu_arch *vcpu = &v->arch;
903 void *shared_kaddr;
463656c0 904 unsigned long this_tsc_khz;
18068523
GOC		 905
906 if ((!vcpu->time_page))
907 return;
908
463656c0
AK		 909 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
910 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
911 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
912 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 913 }
463656c0 914 put_cpu_var(cpu_tsc_khz);
50d0a0f9 915
18068523
GOC		 916 /* Keep irq disabled to prevent changes to the clock */
917 local_irq_save(flags);
af24a4e4 918 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 919 ktime_get_ts(&ts);
923de3cf 920 monotonic_to_bootbased(&ts);
18068523
GOC		 921 local_irq_restore(flags);
922
923 /* With all the info we got, fill in the values */
924
925 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 926 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
927
371bcf64
GC		 928 vcpu->hv_clock.flags = 0;
929
18068523
GOC		 930 /*
931 * The interface expects us to write an even number signaling that the
932 * update is finished. Since the guest won't see the intermediate
50d0a0f9 933 * state, we just increase by 2 at the end.
18068523 934 */
50d0a0f9 935 vcpu->hv_clock.version += 2;
18068523
GOC		 936
937 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
938
939 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 940 sizeof(vcpu->hv_clock));
18068523
GOC		 941
942 kunmap_atomic(shared_kaddr, KM_USER0);
943
944 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
945}
946
c8076604
GH		 947static int kvm_request_guest_time_update(struct kvm_vcpu *v)
948{
949 struct kvm_vcpu_arch *vcpu = &v->arch;
950
951 if (!vcpu->time_page)
952 return 0;
a8eeb04a 953 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 954 return 1;
955}
956
9ba075a6
AK		 957static bool msr_mtrr_valid(unsigned msr)
958{
959 switch (msr) {
960 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
961 case MSR_MTRRfix64K_00000:
962 case MSR_MTRRfix16K_80000:
963 case MSR_MTRRfix16K_A0000:
964 case MSR_MTRRfix4K_C0000:
965 case MSR_MTRRfix4K_C8000:
966 case MSR_MTRRfix4K_D0000:
967 case MSR_MTRRfix4K_D8000:
968 case MSR_MTRRfix4K_E0000:
969 case MSR_MTRRfix4K_E8000:
970 case MSR_MTRRfix4K_F0000:
971 case MSR_MTRRfix4K_F8000:
972 case MSR_MTRRdefType:
973 case MSR_IA32_CR_PAT:
974 return true;
975 case 0x2f8:
976 return true;
977 }
978 return false;
979}
980
d6289b93
MT		 981static bool valid_pat_type(unsigned t)
982{
983 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
984}
985
986static bool valid_mtrr_type(unsigned t)
987{
988 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
989}
990
991static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
992{
993 int i;
994
995 if (!msr_mtrr_valid(msr))
996 return false;
997
998 if (msr == MSR_IA32_CR_PAT) {
999 for (i = 0; i < 8; i++)
1000 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1001 return false;
1002 return true;
1003 } else if (msr == MSR_MTRRdefType) {
1004 if (data & ~0xcff)
1005 return false;
1006 return valid_mtrr_type(data & 0xff);
1007 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1008 for (i = 0; i < 8 ; i++)
1009 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1010 return false;
1011 return true;
1012 }
1013
1014 /* variable MTRRs */
1015 return valid_mtrr_type(data & 0xff);
1016}
1017
9ba075a6
AK		 1018static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1019{
0bed3b56
SY		 1020 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1021
d6289b93 1022 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1023 return 1;
1024
0bed3b56
SY		 1025 if (msr == MSR_MTRRdefType) {
1026 vcpu->arch.mtrr_state.def_type = data;
1027 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1028 } else if (msr == MSR_MTRRfix64K_00000)
1029 p[0] = data;
1030 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1031 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1032 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1033 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1034 else if (msr == MSR_IA32_CR_PAT)
1035 vcpu->arch.pat = data;
1036 else { /* Variable MTRRs */
1037 int idx, is_mtrr_mask;
1038 u64 *pt;
1039
1040 idx = (msr - 0x200) / 2;
1041 is_mtrr_mask = msr - 0x200 - 2 * idx;
1042 if (!is_mtrr_mask)
1043 pt =
1044 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1045 else
1046 pt =
1047 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1048 *pt = data;
1049 }
1050
1051 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1052 return 0;
1053}
15c4a640 1054
890ca9ae 1055static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1056{
890ca9ae
HY		 1057 u64 mcg_cap = vcpu->arch.mcg_cap;
1058 unsigned bank_num = mcg_cap & 0xff;
1059
15c4a640 1060 switch (msr) {
15c4a640 1061 case MSR_IA32_MCG_STATUS:
890ca9ae 1062 vcpu->arch.mcg_status = data;
15c4a640 1063 break;
c7ac679c 1064 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1065 if (!(mcg_cap & MCG_CTL_P))
1066 return 1;
1067 if (data != 0 && data != ~(u64)0)
1068 return -1;
1069 vcpu->arch.mcg_ctl = data;
1070 break;
1071 default:
1072 if (msr >= MSR_IA32_MC0_CTL &&
1073 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1074 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1075 /* only 0 or all 1s can be written to IA32_MCi_CTL
1076 * some Linux kernels though clear bit 10 in bank 4 to
1077 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1078 * this to avoid an uncatched #GP in the guest
1079 */
890ca9ae 1080 if ((offset & 0x3) == 0 &&
114be429 1081 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1082 return -1;
1083 vcpu->arch.mce_banks[offset] = data;
1084 break;
1085 }
1086 return 1;
1087 }
1088 return 0;
1089}
1090
ffde22ac
ES		 1091static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1092{
1093 struct kvm *kvm = vcpu->kvm;
1094 int lm = is_long_mode(vcpu);
1095 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1096 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1097 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1098 : kvm->arch.xen_hvm_config.blob_size_32;
1099 u32 page_num = data & ~PAGE_MASK;
1100 u64 page_addr = data & PAGE_MASK;
1101 u8 *page;
1102 int r;
1103
1104 r = -E2BIG;
1105 if (page_num >= blob_size)
1106 goto out;
1107 r = -ENOMEM;
1108 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1109 if (!page)
1110 goto out;
1111 r = -EFAULT;
1112 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1113 goto out_free;
1114 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1115 goto out_free;
1116 r = 0;
1117out_free:
1118 kfree(page);
1119out:
1120 return r;
1121}
1122
55cd8e5a
GN		 1123static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1124{
1125 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1126}
1127
1128static bool kvm_hv_msr_partition_wide(u32 msr)
1129{
1130 bool r = false;
1131 switch (msr) {
1132 case HV_X64_MSR_GUEST_OS_ID:
1133 case HV_X64_MSR_HYPERCALL:
1134 r = true;
1135 break;
1136 }
1137
1138 return r;
1139}
1140
1141static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1142{
1143 struct kvm *kvm = vcpu->kvm;
1144
1145 switch (msr) {
1146 case HV_X64_MSR_GUEST_OS_ID:
1147 kvm->arch.hv_guest_os_id = data;
1148 /* setting guest os id to zero disables hypercall page */
1149 if (!kvm->arch.hv_guest_os_id)
1150 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1151 break;
1152 case HV_X64_MSR_HYPERCALL: {
1153 u64 gfn;
1154 unsigned long addr;
1155 u8 instructions[4];
1156
1157 /* if guest os id is not set hypercall should remain disabled */
1158 if (!kvm->arch.hv_guest_os_id)
1159 break;
1160 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1161 kvm->arch.hv_hypercall = data;
1162 break;
1163 }
1164 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1165 addr = gfn_to_hva(kvm, gfn);
1166 if (kvm_is_error_hva(addr))
1167 return 1;
1168 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1169 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1170 if (copy_to_user((void __user *)addr, instructions, 4))
1171 return 1;
1172 kvm->arch.hv_hypercall = data;
1173 break;
1174 }
1175 default:
1176 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1177 "data 0x%llx\n", msr, data);
1178 return 1;
1179 }
1180 return 0;
1181}
1182
1183static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1184{
10388a07
GN		 1185 switch (msr) {
1186 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1187 unsigned long addr;
55cd8e5a 1188
10388a07
GN		 1189 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1190 vcpu->arch.hv_vapic = data;
1191 break;
1192 }
1193 addr = gfn_to_hva(vcpu->kvm, data >>
1194 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1195 if (kvm_is_error_hva(addr))
1196 return 1;
1197 if (clear_user((void __user *)addr, PAGE_SIZE))
1198 return 1;
1199 vcpu->arch.hv_vapic = data;
1200 break;
1201 }
1202 case HV_X64_MSR_EOI:
1203 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1204 case HV_X64_MSR_ICR:
1205 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1206 case HV_X64_MSR_TPR:
1207 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1208 default:
1209 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1210 "data 0x%llx\n", msr, data);
1211 return 1;
1212 }
1213
1214 return 0;
55cd8e5a
GN		 1215}
1216
15c4a640
CO		 1217int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1218{
1219 switch (msr) {
15c4a640 1220 case MSR_EFER:
b69e8cae 1221 return set_efer(vcpu, data);
8f1589d9
AP		 1222 case MSR_K7_HWCR:
1223 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1224 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1225 if (data != 0) {
1226 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1227 data);
1228 return 1;
1229 }
15c4a640 1230 break;
f7c6d140
AP		 1231 case MSR_FAM10H_MMIO_CONF_BASE:
1232 if (data != 0) {
1233 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1234 "0x%llx\n", data);
1235 return 1;
1236 }
15c4a640 1237 break;
c323c0e5 1238 case MSR_AMD64_NB_CFG:
c7ac679c 1239 break;
b5e2fec0
AG		 1240 case MSR_IA32_DEBUGCTLMSR:
1241 if (!data) {
1242 /* We support the non-activated case already */
1243 break;
1244 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1245 /* Values other than LBR and BTF are vendor-specific,
1246 thus reserved and should throw a #GP */
1247 return 1;
1248 }
1249 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1250 __func__, data);
1251 break;
15c4a640
CO		 1252 case MSR_IA32_UCODE_REV:
1253 case MSR_IA32_UCODE_WRITE:
61a6bd67 1254 case MSR_VM_HSAVE_PA:
6098ca93 1255 case MSR_AMD64_PATCH_LOADER:
15c4a640 1256 break;
9ba075a6
AK		 1257 case 0x200 ... 0x2ff:
1258 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1259 case MSR_IA32_APICBASE:
1260 kvm_set_apic_base(vcpu, data);
1261 break;
0105d1a5
GN		 1262 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1263 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1264 case MSR_IA32_MISC_ENABLE:
ad312c7c 1265 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1266 break;
11c6bffa 1267 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1268 case MSR_KVM_WALL_CLOCK:
1269 vcpu->kvm->arch.wall_clock = data;
1270 kvm_write_wall_clock(vcpu->kvm, data);
1271 break;
11c6bffa 1272 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1273 case MSR_KVM_SYSTEM_TIME: {
1274 if (vcpu->arch.time_page) {
1275 kvm_release_page_dirty(vcpu->arch.time_page);
1276 vcpu->arch.time_page = NULL;
1277 }
1278
1279 vcpu->arch.time = data;
1280
1281 /* we verify if the enable bit is set... */
1282 if (!(data & 1))
1283 break;
1284
1285 /* ...but clean it before doing the actual write */
1286 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1287
18068523
GOC		 1288 vcpu->arch.time_page =
1289 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1290
1291 if (is_error_page(vcpu->arch.time_page)) {
1292 kvm_release_page_clean(vcpu->arch.time_page);
1293 vcpu->arch.time_page = NULL;
1294 }
1295
c8076604 1296 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1297 break;
1298 }
890ca9ae
HY		 1299 case MSR_IA32_MCG_CTL:
1300 case MSR_IA32_MCG_STATUS:
1301 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1302 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1303
1304 /* Performance counters are not protected by a CPUID bit,
1305 * so we should check all of them in the generic path for the sake of
1306 * cross vendor migration.
1307 * Writing a zero into the event select MSRs disables them,
1308 * which we perfectly emulate ;-). Any other value should be at least
1309 * reported, some guests depend on them.
1310 */
1311 case MSR_P6_EVNTSEL0:
1312 case MSR_P6_EVNTSEL1:
1313 case MSR_K7_EVNTSEL0:
1314 case MSR_K7_EVNTSEL1:
1315 case MSR_K7_EVNTSEL2:
1316 case MSR_K7_EVNTSEL3:
1317 if (data != 0)
1318 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1319 "0x%x data 0x%llx\n", msr, data);
1320 break;
1321 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1322 * so we ignore writes to make it happy.
1323 */
1324 case MSR_P6_PERFCTR0:
1325 case MSR_P6_PERFCTR1:
1326 case MSR_K7_PERFCTR0:
1327 case MSR_K7_PERFCTR1:
1328 case MSR_K7_PERFCTR2:
1329 case MSR_K7_PERFCTR3:
1330 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1331 "0x%x data 0x%llx\n", msr, data);
1332 break;
55cd8e5a
GN		 1333 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1334 if (kvm_hv_msr_partition_wide(msr)) {
1335 int r;
1336 mutex_lock(&vcpu->kvm->lock);
1337 r = set_msr_hyperv_pw(vcpu, msr, data);
1338 mutex_unlock(&vcpu->kvm->lock);
1339 return r;
1340 } else
1341 return set_msr_hyperv(vcpu, msr, data);
1342 break;
15c4a640 1343 default:
ffde22ac
ES		 1344 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1345 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1346 if (!ignore_msrs) {
1347 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1348 msr, data);
1349 return 1;
1350 } else {
1351 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1352 msr, data);
1353 break;
1354 }
15c4a640
CO		 1355 }
1356 return 0;
1357}
1358EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1359
1360
1361/*
1362 * Reads an msr value (of 'msr_index') into 'pdata'.
1363 * Returns 0 on success, non-0 otherwise.
1364 * Assumes vcpu_load() was already called.
1365 */
1366int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1367{
1368 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1369}
1370
9ba075a6
AK		 1371static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1372{
0bed3b56
SY		 1373 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1374
9ba075a6
AK		 1375 if (!msr_mtrr_valid(msr))
1376 return 1;
1377
0bed3b56
SY		 1378 if (msr == MSR_MTRRdefType)
1379 *pdata = vcpu->arch.mtrr_state.def_type +
1380 (vcpu->arch.mtrr_state.enabled << 10);
1381 else if (msr == MSR_MTRRfix64K_00000)
1382 *pdata = p[0];
1383 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1384 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1385 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1386 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1387 else if (msr == MSR_IA32_CR_PAT)
1388 *pdata = vcpu->arch.pat;
1389 else { /* Variable MTRRs */
1390 int idx, is_mtrr_mask;
1391 u64 *pt;
1392
1393 idx = (msr - 0x200) / 2;
1394 is_mtrr_mask = msr - 0x200 - 2 * idx;
1395 if (!is_mtrr_mask)
1396 pt =
1397 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1398 else
1399 pt =
1400 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1401 *pdata = *pt;
1402 }
1403
9ba075a6
AK		 1404 return 0;
1405}
1406
890ca9ae 1407static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1408{
1409 u64 data;
890ca9ae
HY		 1410 u64 mcg_cap = vcpu->arch.mcg_cap;
1411 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1412
1413 switch (msr) {
15c4a640
CO		 1414 case MSR_IA32_P5_MC_ADDR:
1415 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1416 data = 0;
1417 break;
15c4a640 1418 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1419 data = vcpu->arch.mcg_cap;
1420 break;
c7ac679c 1421 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1422 if (!(mcg_cap & MCG_CTL_P))
1423 return 1;
1424 data = vcpu->arch.mcg_ctl;
1425 break;
1426 case MSR_IA32_MCG_STATUS:
1427 data = vcpu->arch.mcg_status;
1428 break;
1429 default:
1430 if (msr >= MSR_IA32_MC0_CTL &&
1431 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1432 u32 offset = msr - MSR_IA32_MC0_CTL;
1433 data = vcpu->arch.mce_banks[offset];
1434 break;
1435 }
1436 return 1;
1437 }
1438 *pdata = data;
1439 return 0;
1440}
1441
55cd8e5a
GN		 1442static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1443{
1444 u64 data = 0;
1445 struct kvm *kvm = vcpu->kvm;
1446
1447 switch (msr) {
1448 case HV_X64_MSR_GUEST_OS_ID:
1449 data = kvm->arch.hv_guest_os_id;
1450 break;
1451 case HV_X64_MSR_HYPERCALL:
1452 data = kvm->arch.hv_hypercall;
1453 break;
1454 default:
1455 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1456 return 1;
1457 }
1458
1459 *pdata = data;
1460 return 0;
1461}
1462
1463static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1464{
1465 u64 data = 0;
1466
1467 switch (msr) {
1468 case HV_X64_MSR_VP_INDEX: {
1469 int r;
1470 struct kvm_vcpu *v;
1471 kvm_for_each_vcpu(r, v, vcpu->kvm)
1472 if (v == vcpu)
1473 data = r;
1474 break;
1475 }
10388a07
GN		 1476 case HV_X64_MSR_EOI:
1477 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1478 case HV_X64_MSR_ICR:
1479 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1480 case HV_X64_MSR_TPR:
1481 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1482 default:
1483 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1484 return 1;
1485 }
1486 *pdata = data;
1487 return 0;
1488}
1489
890ca9ae
HY		 1490int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1491{
1492 u64 data;
1493
1494 switch (msr) {
890ca9ae 1495 case MSR_IA32_PLATFORM_ID:
15c4a640 1496 case MSR_IA32_UCODE_REV:
15c4a640 1497 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1498 case MSR_IA32_DEBUGCTLMSR:
1499 case MSR_IA32_LASTBRANCHFROMIP:
1500 case MSR_IA32_LASTBRANCHTOIP:
1501 case MSR_IA32_LASTINTFROMIP:
1502 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1503 case MSR_K8_SYSCFG:
1504 case MSR_K7_HWCR:
61a6bd67 1505 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1506 case MSR_P6_PERFCTR0:
1507 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1508 case MSR_P6_EVNTSEL0:
1509 case MSR_P6_EVNTSEL1:
9e699624 1510 case MSR_K7_EVNTSEL0:
1f3ee616 1511 case MSR_K7_PERFCTR0:
1fdbd48c 1512 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1513 case MSR_AMD64_NB_CFG:
f7c6d140 1514 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1515 data = 0;
1516 break;
9ba075a6
AK		 1517 case MSR_MTRRcap:
1518 data = 0x500 | KVM_NR_VAR_MTRR;
1519 break;
1520 case 0x200 ... 0x2ff:
1521 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1522 case 0xcd: /* fsb frequency */
1523 data = 3;
1524 break;
1525 case MSR_IA32_APICBASE:
1526 data = kvm_get_apic_base(vcpu);
1527 break;
0105d1a5
GN		 1528 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1529 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1530 break;
15c4a640 1531 case MSR_IA32_MISC_ENABLE:
ad312c7c 1532 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1533 break;
847f0ad8
AG		 1534 case MSR_IA32_PERF_STATUS:
1535 /* TSC increment by tick */
1536 data = 1000ULL;
1537 /* CPU multiplier */
1538 data |= (((uint64_t)4ULL) << 40);
1539 break;
15c4a640 1540 case MSR_EFER:
f6801dff 1541 data = vcpu->arch.efer;
15c4a640 1542 break;
18068523 1543 case MSR_KVM_WALL_CLOCK:
11c6bffa 1544 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1545 data = vcpu->kvm->arch.wall_clock;
1546 break;
1547 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1548 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1549 data = vcpu->arch.time;
1550 break;
890ca9ae
HY		 1551 case MSR_IA32_P5_MC_ADDR:
1552 case MSR_IA32_P5_MC_TYPE:
1553 case MSR_IA32_MCG_CAP:
1554 case MSR_IA32_MCG_CTL:
1555 case MSR_IA32_MCG_STATUS:
1556 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1557 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1558 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1559 if (kvm_hv_msr_partition_wide(msr)) {
1560 int r;
1561 mutex_lock(&vcpu->kvm->lock);
1562 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1563 mutex_unlock(&vcpu->kvm->lock);
1564 return r;
1565 } else
1566 return get_msr_hyperv(vcpu, msr, pdata);
1567 break;
15c4a640 1568 default:
ed85c068
AP		 1569 if (!ignore_msrs) {
1570 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1571 return 1;
1572 } else {
1573 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1574 data = 0;
1575 }
1576 break;
15c4a640
CO		 1577 }
1578 *pdata = data;
1579 return 0;
1580}
1581EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1582
313a3dc7
CO		 1583/*
1584 * Read or write a bunch of msrs. All parameters are kernel addresses.
1585 *
1586 * @return number of msrs set successfully.
1587 */
1588static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1589 struct kvm_msr_entry *entries,
1590 int (*do_msr)(struct kvm_vcpu *vcpu,
1591 unsigned index, u64 *data))
1592{
f656ce01 1593 int i, idx;
313a3dc7 1594
f656ce01 1595 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1596 for (i = 0; i < msrs->nmsrs; ++i)
1597 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1598 break;
f656ce01 1599 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1600
313a3dc7
CO		 1601 return i;
1602}
1603
1604/*
1605 * Read or write a bunch of msrs. Parameters are user addresses.
1606 *
1607 * @return number of msrs set successfully.
1608 */
1609static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1610 int (*do_msr)(struct kvm_vcpu *vcpu,
1611 unsigned index, u64 *data),
1612 int writeback)
1613{
1614 struct kvm_msrs msrs;
1615 struct kvm_msr_entry *entries;
1616 int r, n;
1617 unsigned size;
1618
1619 r = -EFAULT;
1620 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1621 goto out;
1622
1623 r = -E2BIG;
1624 if (msrs.nmsrs >= MAX_IO_MSRS)
1625 goto out;
1626
1627 r = -ENOMEM;
1628 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1629 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1630 if (!entries)
1631 goto out;
1632
1633 r = -EFAULT;
1634 if (copy_from_user(entries, user_msrs->entries, size))
1635 goto out_free;
1636
1637 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1638 if (r < 0)
1639 goto out_free;
1640
1641 r = -EFAULT;
1642 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1643 goto out_free;
1644
1645 r = n;
1646
1647out_free:
7a73c028 1648 kfree(entries);
313a3dc7
CO		 1649out:
1650 return r;
1651}
1652
018d00d2
ZX		 1653int kvm_dev_ioctl_check_extension(long ext)
1654{
1655 int r;
1656
1657 switch (ext) {
1658 case KVM_CAP_IRQCHIP:
1659 case KVM_CAP_HLT:
1660 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1661 case KVM_CAP_SET_TSS_ADDR:
07716717 1662 case KVM_CAP_EXT_CPUID:
c8076604 1663 case KVM_CAP_CLOCKSOURCE:
7837699f 1664 case KVM_CAP_PIT:
a28e4f5a 1665 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1666 case KVM_CAP_MP_STATE:
ed848624 1667 case KVM_CAP_SYNC_MMU:
52d939a0 1668 case KVM_CAP_REINJECT_CONTROL:
4925663a 1669 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1670 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1671 case KVM_CAP_IRQFD:
d34e6b17 1672 case KVM_CAP_IOEVENTFD:
c5ff41ce 1673 case KVM_CAP_PIT2:
e9f42757 1674 case KVM_CAP_PIT_STATE2:
b927a3ce 1675 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1676 case KVM_CAP_XEN_HVM:
afbcf7ab 1677 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1678 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1679 case KVM_CAP_HYPERV:
10388a07 1680 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1681 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1682 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1683 case KVM_CAP_DEBUGREGS:
d2be1651 1684 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1685 case KVM_CAP_XSAVE:
018d00d2
ZX		 1686 r = 1;
1687 break;
542472b5
LV		 1688 case KVM_CAP_COALESCED_MMIO:
1689 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1690 break;
774ead3a
AK		 1691 case KVM_CAP_VAPIC:
1692 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1693 break;
f725230a
AK		 1694 case KVM_CAP_NR_VCPUS:
1695 r = KVM_MAX_VCPUS;
1696 break;
a988b910
AK		 1697 case KVM_CAP_NR_MEMSLOTS:
1698 r = KVM_MEMORY_SLOTS;
1699 break;
a68a6a72
MT		 1700 case KVM_CAP_PV_MMU: /* obsolete */
1701 r = 0;
2f333bcb 1702 break;
62c476c7 1703 case KVM_CAP_IOMMU:
19de40a8 1704 r = iommu_found();
62c476c7 1705 break;
890ca9ae
HY		 1706 case KVM_CAP_MCE:
1707 r = KVM_MAX_MCE_BANKS;
1708 break;
2d5b5a66
SY		 1709 case KVM_CAP_XCRS:
1710 r = cpu_has_xsave;
1711 break;
018d00d2
ZX		 1712 default:
1713 r = 0;
1714 break;
1715 }
1716 return r;
1717
1718}
1719
043405e1
CO		 1720long kvm_arch_dev_ioctl(struct file *filp,
1721 unsigned int ioctl, unsigned long arg)
1722{
1723 void __user *argp = (void __user *)arg;
1724 long r;
1725
1726 switch (ioctl) {
1727 case KVM_GET_MSR_INDEX_LIST: {
1728 struct kvm_msr_list __user *user_msr_list = argp;
1729 struct kvm_msr_list msr_list;
1730 unsigned n;
1731
1732 r = -EFAULT;
1733 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1734 goto out;
1735 n = msr_list.nmsrs;
1736 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1737 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1738 goto out;
1739 r = -E2BIG;
e125e7b6 1740 if (n < msr_list.nmsrs)
043405e1
CO		 1741 goto out;
1742 r = -EFAULT;
1743 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1744 num_msrs_to_save * sizeof(u32)))
1745 goto out;
e125e7b6 1746 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1747 &emulated_msrs,
1748 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1749 goto out;
1750 r = 0;
1751 break;
1752 }
674eea0f
AK		 1753 case KVM_GET_SUPPORTED_CPUID: {
1754 struct kvm_cpuid2 __user *cpuid_arg = argp;
1755 struct kvm_cpuid2 cpuid;
1756
1757 r = -EFAULT;
1758 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1759 goto out;
1760 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1761 cpuid_arg->entries);
674eea0f
AK		 1762 if (r)
1763 goto out;
1764
1765 r = -EFAULT;
1766 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1767 goto out;
1768 r = 0;
1769 break;
1770 }
890ca9ae
HY		 1771 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1772 u64 mce_cap;
1773
1774 mce_cap = KVM_MCE_CAP_SUPPORTED;
1775 r = -EFAULT;
1776 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1777 goto out;
1778 r = 0;
1779 break;
1780 }
043405e1
CO		 1781 default:
1782 r = -EINVAL;
1783 }
1784out:
1785 return r;
1786}
1787
f5f48ee1
SY		 1788static void wbinvd_ipi(void *garbage)
1789{
1790 wbinvd();
1791}
1792
1793static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
1794{
1795 return vcpu->kvm->arch.iommu_domain &&
1796 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
1797}
1798
313a3dc7
CO		 1799void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1800{
f5f48ee1
SY		 1801 /* Address WBINVD may be executed by guest */
1802 if (need_emulate_wbinvd(vcpu)) {
1803 if (kvm_x86_ops->has_wbinvd_exit())
1804 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
1805 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
1806 smp_call_function_single(vcpu->cpu,
1807 wbinvd_ipi, NULL, 1);
1808 }
1809
313a3dc7 1810 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1811 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1812 unsigned long khz = cpufreq_quick_get(cpu);
1813 if (!khz)
1814 khz = tsc_khz;
1815 per_cpu(cpu_tsc_khz, cpu) = khz;
1816 }
c8076604 1817 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1818}
1819
1820void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1821{
02daab21 1822 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1823 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1824}
1825
07716717 1826static int is_efer_nx(void)
313a3dc7 1827{
e286e86e 1828 unsigned long long efer = 0;
313a3dc7 1829
e286e86e 1830 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1831 return efer & EFER_NX;
1832}
1833
1834static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1835{
1836 int i;
1837 struct kvm_cpuid_entry2 *e, *entry;
1838
313a3dc7 1839 entry = NULL;
ad312c7c
ZX		 1840 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1841 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1842 if (e->function == 0x80000001) {
1843 entry = e;
1844 break;
1845 }
1846 }
07716717 1847 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1848 entry->edx &= ~(1 << 20);
1849 printk(KERN_INFO "kvm: guest NX capability removed\n");
1850 }
1851}
1852
07716717 1853/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1854static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1855 struct kvm_cpuid *cpuid,
1856 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1857{
1858 int r, i;
1859 struct kvm_cpuid_entry *cpuid_entries;
1860
1861 r = -E2BIG;
1862 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1863 goto out;
1864 r = -ENOMEM;
1865 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1866 if (!cpuid_entries)
1867 goto out;
1868 r = -EFAULT;
1869 if (copy_from_user(cpuid_entries, entries,
1870 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1871 goto out_free;
1872 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1873 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1874 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1875 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1876 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1877 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1878 vcpu->arch.cpuid_entries[i].index = 0;
1879 vcpu->arch.cpuid_entries[i].flags = 0;
1880 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1881 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1882 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1883 }
1884 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1885 cpuid_fix_nx_cap(vcpu);
1886 r = 0;
fc61b800 1887 kvm_apic_set_version(vcpu);
0e851880 1888 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 1889 update_cpuid(vcpu);
07716717
DK		 1890
1891out_free:
1892 vfree(cpuid_entries);
1893out:
1894 return r;
1895}
1896
1897static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1898 struct kvm_cpuid2 *cpuid,
1899 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1900{
1901 int r;
1902
1903 r = -E2BIG;
1904 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1905 goto out;
1906 r = -EFAULT;
ad312c7c 1907 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1908 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1909 goto out;
ad312c7c 1910 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1911 kvm_apic_set_version(vcpu);
0e851880 1912 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 1913 update_cpuid(vcpu);
313a3dc7
CO		 1914 return 0;
1915
1916out:
1917 return r;
1918}
1919
07716717 1920static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1921 struct kvm_cpuid2 *cpuid,
1922 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1923{
1924 int r;
1925
1926 r = -E2BIG;
ad312c7c 1927 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1928 goto out;
1929 r = -EFAULT;
ad312c7c 1930 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1931 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1932 goto out;
1933 return 0;
1934
1935out:
ad312c7c 1936 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1937 return r;
1938}
1939
07716717 1940static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1941 u32 index)
07716717
DK		 1942{
1943 entry->function = function;
1944 entry->index = index;
1945 cpuid_count(entry->function, entry->index,
19355475 1946 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1947 entry->flags = 0;
1948}
1949
7faa4ee1
AK		 1950#define F(x) bit(X86_FEATURE_##x)
1951
07716717
DK		 1952static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1953 u32 index, int *nent, int maxnent)
1954{
7faa4ee1 1955 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1956#ifdef CONFIG_X86_64
17cc3935
SY		 1957 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1958 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1959 unsigned f_lm = F(LM);
1960#else
17cc3935 1961 unsigned f_gbpages = 0;
7faa4ee1 1962 unsigned f_lm = 0;
07716717 1963#endif
4e47c7a6 1964 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1965
1966 /* cpuid 1.edx */
1967 const u32 kvm_supported_word0_x86_features =
1968 F(FPU) | F(VME) | F(DE) | F(PSE) |
1969 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1970 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1971 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1972 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1973 0 /* Reserved, DS, ACPI */ | F(MMX) |
1974 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1975 0 /* HTT, TM, Reserved, PBE */;
1976 /* cpuid 0x80000001.edx */
1977 const u32 kvm_supported_word1_x86_features =
1978 F(FPU) | F(VME) | F(DE) | F(PSE) |
1979 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1980 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1981 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1982 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1983 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1984 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1985 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1986 /* cpuid 1.ecx */
1987 const u32 kvm_supported_word4_x86_features =
6c3f6041 1988 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 1989 0 /* DS-CPL, VMX, SMX, EST */ |
1990 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1991 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1992 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1993 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 1994 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
1995 F(F16C);
7faa4ee1 1996 /* cpuid 0x80000001.ecx */
07716717 1997 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1998 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1999 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2000 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2001 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2002
19355475 2003 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2004 get_cpu();
2005 do_cpuid_1_ent(entry, function, index);
2006 ++*nent;
2007
2008 switch (function) {
2009 case 0:
2acf923e 2010 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2011 break;
2012 case 1:
2013 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2014 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2015 /* we support x2apic emulation even if host does not support
2016 * it since we emulate x2apic in software */
2017 entry->ecx |= F(X2APIC);
07716717
DK		 2018 break;
2019 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2020 * may return different values. This forces us to get_cpu() before
2021 * issuing the first command, and also to emulate this annoying behavior
2022 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2023 case 2: {
2024 int t, times = entry->eax & 0xff;
2025
2026 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2027 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2028 for (t = 1; t < times && *nent < maxnent; ++t) {
2029 do_cpuid_1_ent(&entry[t], function, 0);
2030 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2031 ++*nent;
2032 }
2033 break;
2034 }
2035 /* function 4 and 0xb have additional index. */
2036 case 4: {
14af3f3c 2037 int i, cache_type;
07716717
DK		 2038
2039 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2040 /* read more entries until cache_type is zero */
14af3f3c
HH		 2041 for (i = 1; *nent < maxnent; ++i) {
2042 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2043 if (!cache_type)
2044 break;
14af3f3c
HH		 2045 do_cpuid_1_ent(&entry[i], function, i);
2046 entry[i].flags |=
07716717
DK		 2047 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2048 ++*nent;
2049 }
2050 break;
2051 }
2052 case 0xb: {
14af3f3c 2053 int i, level_type;
07716717
DK		 2054
2055 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2056 /* read more entries until level_type is zero */
14af3f3c 2057 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2058 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2059 if (!level_type)
2060 break;
14af3f3c
HH		 2061 do_cpuid_1_ent(&entry[i], function, i);
2062 entry[i].flags |=
07716717
DK		 2063 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2064 ++*nent;
2065 }
2066 break;
2067 }
2acf923e
DC		 2068 case 0xd: {
2069 int i;
2070
2071 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2072 for (i = 1; *nent < maxnent; ++i) {
2073 if (entry[i - 1].eax == 0 && i != 2)
2074 break;
2075 do_cpuid_1_ent(&entry[i], function, i);
2076 entry[i].flags |=
2077 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2078 ++*nent;
2079 }
2080 break;
2081 }
84478c82
GC		 2082 case KVM_CPUID_SIGNATURE: {
2083 char signature[12] = "KVMKVMKVM\0\0";
2084 u32 *sigptr = (u32 *)signature;
2085 entry->eax = 0;
2086 entry->ebx = sigptr[0];
2087 entry->ecx = sigptr[1];
2088 entry->edx = sigptr[2];
2089 break;
2090 }
2091 case KVM_CPUID_FEATURES:
2092 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2093 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2094 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2095 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2096 entry->ebx = 0;
2097 entry->ecx = 0;
2098 entry->edx = 0;
2099 break;
07716717
DK		 2100 case 0x80000000:
2101 entry->eax = min(entry->eax, 0x8000001a);
2102 break;
2103 case 0x80000001:
2104 entry->edx &= kvm_supported_word1_x86_features;
2105 entry->ecx &= kvm_supported_word6_x86_features;
2106 break;
2107 }
d4330ef2
JR		 2108
2109 kvm_x86_ops->set_supported_cpuid(function, entry);
2110
07716717
DK		 2111 put_cpu();
2112}
2113
7faa4ee1
AK		 2114#undef F
2115
674eea0f 2116static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2117 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2118{
2119 struct kvm_cpuid_entry2 *cpuid_entries;
2120 int limit, nent = 0, r = -E2BIG;
2121 u32 func;
2122
2123 if (cpuid->nent < 1)
2124 goto out;
6a544355
AK		 2125 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2126 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2127 r = -ENOMEM;
2128 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2129 if (!cpuid_entries)
2130 goto out;
2131
2132 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2133 limit = cpuid_entries[0].eax;
2134 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2135 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2136 &nent, cpuid->nent);
07716717
DK		 2137 r = -E2BIG;
2138 if (nent >= cpuid->nent)
2139 goto out_free;
2140
2141 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2142 limit = cpuid_entries[nent - 1].eax;
2143 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2144 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2145 &nent, cpuid->nent);
84478c82
GC		 2146
2147
2148
2149 r = -E2BIG;
2150 if (nent >= cpuid->nent)
2151 goto out_free;
2152
2153 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2154 cpuid->nent);
2155
2156 r = -E2BIG;
2157 if (nent >= cpuid->nent)
2158 goto out_free;
2159
2160 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2161 cpuid->nent);
2162
cb007648
MM		 2163 r = -E2BIG;
2164 if (nent >= cpuid->nent)
2165 goto out_free;
2166
07716717
DK		 2167 r = -EFAULT;
2168 if (copy_to_user(entries, cpuid_entries,
19355475 2169 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2170 goto out_free;
2171 cpuid->nent = nent;
2172 r = 0;
2173
2174out_free:
2175 vfree(cpuid_entries);
2176out:
2177 return r;
2178}
2179
313a3dc7
CO		 2180static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2181 struct kvm_lapic_state *s)
2182{
ad312c7c 2183 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2184
2185 return 0;
2186}
2187
2188static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2189 struct kvm_lapic_state *s)
2190{
ad312c7c 2191 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2192 kvm_apic_post_state_restore(vcpu);
cb142eb7 2193 update_cr8_intercept(vcpu);
313a3dc7
CO		 2194
2195 return 0;
2196}
2197
f77bc6a4
ZX		 2198static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2199 struct kvm_interrupt *irq)
2200{
2201 if (irq->irq < 0 || irq->irq >= 256)
2202 return -EINVAL;
2203 if (irqchip_in_kernel(vcpu->kvm))
2204 return -ENXIO;
f77bc6a4 2205
66fd3f7f 2206 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2207
f77bc6a4
ZX		 2208 return 0;
2209}
2210
c4abb7c9
JK		 2211static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2212{
c4abb7c9 2213 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2214
2215 return 0;
2216}
2217
b209749f
AK		 2218static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2219 struct kvm_tpr_access_ctl *tac)
2220{
2221 if (tac->flags)
2222 return -EINVAL;
2223 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2224 return 0;
2225}
2226
890ca9ae
HY		 2227static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2228 u64 mcg_cap)
2229{
2230 int r;
2231 unsigned bank_num = mcg_cap & 0xff, bank;
2232
2233 r = -EINVAL;
a9e38c3e 2234 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2235 goto out;
2236 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2237 goto out;
2238 r = 0;
2239 vcpu->arch.mcg_cap = mcg_cap;
2240 /* Init IA32_MCG_CTL to all 1s */
2241 if (mcg_cap & MCG_CTL_P)
2242 vcpu->arch.mcg_ctl = ~(u64)0;
2243 /* Init IA32_MCi_CTL to all 1s */
2244 for (bank = 0; bank < bank_num; bank++)
2245 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2246out:
2247 return r;
2248}
2249
2250static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2251 struct kvm_x86_mce *mce)
2252{
2253 u64 mcg_cap = vcpu->arch.mcg_cap;
2254 unsigned bank_num = mcg_cap & 0xff;
2255 u64 *banks = vcpu->arch.mce_banks;
2256
2257 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2258 return -EINVAL;
2259 /*
2260 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2261 * reporting is disabled
2262 */
2263 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2264 vcpu->arch.mcg_ctl != ~(u64)0)
2265 return 0;
2266 banks += 4 * mce->bank;
2267 /*
2268 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2269 * reporting is disabled for the bank
2270 */
2271 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2272 return 0;
2273 if (mce->status & MCI_STATUS_UC) {
2274 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2275 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2276 printk(KERN_DEBUG "kvm: set_mce: "
2277 "injects mce exception while "
2278 "previous one is in progress!\n");
a8eeb04a 2279 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2280 return 0;
2281 }
2282 if (banks[1] & MCI_STATUS_VAL)
2283 mce->status |= MCI_STATUS_OVER;
2284 banks[2] = mce->addr;
2285 banks[3] = mce->misc;
2286 vcpu->arch.mcg_status = mce->mcg_status;
2287 banks[1] = mce->status;
2288 kvm_queue_exception(vcpu, MC_VECTOR);
2289 } else if (!(banks[1] & MCI_STATUS_VAL)
2290 || !(banks[1] & MCI_STATUS_UC)) {
2291 if (banks[1] & MCI_STATUS_VAL)
2292 mce->status |= MCI_STATUS_OVER;
2293 banks[2] = mce->addr;
2294 banks[3] = mce->misc;
2295 banks[1] = mce->status;
2296 } else
2297 banks[1] |= MCI_STATUS_OVER;
2298 return 0;
2299}
2300
3cfc3092
JK		 2301static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2302 struct kvm_vcpu_events *events)
2303{
03b82a30
JK		 2304 events->exception.injected =
2305 vcpu->arch.exception.pending &&
2306 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2307 events->exception.nr = vcpu->arch.exception.nr;
2308 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2309 events->exception.error_code = vcpu->arch.exception.error_code;
2310
03b82a30
JK		 2311 events->interrupt.injected =
2312 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2313 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2314 events->interrupt.soft = 0;
48005f64
JK		 2315 events->interrupt.shadow =
2316 kvm_x86_ops->get_interrupt_shadow(vcpu,
2317 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2318
2319 events->nmi.injected = vcpu->arch.nmi_injected;
2320 events->nmi.pending = vcpu->arch.nmi_pending;
2321 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2322
2323 events->sipi_vector = vcpu->arch.sipi_vector;
2324
dab4b911 2325 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2326 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2327 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2328}
2329
2330static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2331 struct kvm_vcpu_events *events)
2332{
dab4b911 2333 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2334 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2335 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2336 return -EINVAL;
2337
3cfc3092
JK		 2338 vcpu->arch.exception.pending = events->exception.injected;
2339 vcpu->arch.exception.nr = events->exception.nr;
2340 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2341 vcpu->arch.exception.error_code = events->exception.error_code;
2342
2343 vcpu->arch.interrupt.pending = events->interrupt.injected;
2344 vcpu->arch.interrupt.nr = events->interrupt.nr;
2345 vcpu->arch.interrupt.soft = events->interrupt.soft;
2346 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2347 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2348 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2349 kvm_x86_ops->set_interrupt_shadow(vcpu,
2350 events->interrupt.shadow);
3cfc3092
JK		 2351
2352 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2353 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2354 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2355 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2356
dab4b911
JK		 2357 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2358 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2359
3cfc3092
JK		 2360 return 0;
2361}
2362
a1efbe77
JK		 2363static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2364 struct kvm_debugregs *dbgregs)
2365{
a1efbe77
JK		 2366 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2367 dbgregs->dr6 = vcpu->arch.dr6;
2368 dbgregs->dr7 = vcpu->arch.dr7;
2369 dbgregs->flags = 0;
a1efbe77
JK		 2370}
2371
2372static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2373 struct kvm_debugregs *dbgregs)
2374{
2375 if (dbgregs->flags)
2376 return -EINVAL;
2377
a1efbe77
JK		 2378 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2379 vcpu->arch.dr6 = dbgregs->dr6;
2380 vcpu->arch.dr7 = dbgregs->dr7;
2381
a1efbe77
JK		 2382 return 0;
2383}
2384
2d5b5a66
SY		 2385static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2386 struct kvm_xsave *guest_xsave)
2387{
2388 if (cpu_has_xsave)
2389 memcpy(guest_xsave->region,
2390 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2391 xstate_size);
2d5b5a66
SY		 2392 else {
2393 memcpy(guest_xsave->region,
2394 &vcpu->arch.guest_fpu.state->fxsave,
2395 sizeof(struct i387_fxsave_struct));
2396 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2397 XSTATE_FPSSE;
2398 }
2399}
2400
2401static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2402 struct kvm_xsave *guest_xsave)
2403{
2404 u64 xstate_bv =
2405 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2406
2407 if (cpu_has_xsave)
2408 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2409 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2410 else {
2411 if (xstate_bv & ~XSTATE_FPSSE)
2412 return -EINVAL;
2413 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2414 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2415 }
2416 return 0;
2417}
2418
2419static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2420 struct kvm_xcrs *guest_xcrs)
2421{
2422 if (!cpu_has_xsave) {
2423 guest_xcrs->nr_xcrs = 0;
2424 return;
2425 }
2426
2427 guest_xcrs->nr_xcrs = 1;
2428 guest_xcrs->flags = 0;
2429 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2430 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2431}
2432
2433static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2434 struct kvm_xcrs *guest_xcrs)
2435{
2436 int i, r = 0;
2437
2438 if (!cpu_has_xsave)
2439 return -EINVAL;
2440
2441 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2442 return -EINVAL;
2443
2444 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2445 /* Only support XCR0 currently */
2446 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2447 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2448 guest_xcrs->xcrs[0].value);
2449 break;
2450 }
2451 if (r)
2452 r = -EINVAL;
2453 return r;
2454}
2455
313a3dc7
CO		 2456long kvm_arch_vcpu_ioctl(struct file *filp,
2457 unsigned int ioctl, unsigned long arg)
2458{
2459 struct kvm_vcpu *vcpu = filp->private_data;
2460 void __user *argp = (void __user *)arg;
2461 int r;
d1ac91d8
AK		 2462 union {
2463 struct kvm_lapic_state *lapic;
2464 struct kvm_xsave *xsave;
2465 struct kvm_xcrs *xcrs;
2466 void *buffer;
2467 } u;
2468
2469 u.buffer = NULL;
313a3dc7
CO		 2470 switch (ioctl) {
2471 case KVM_GET_LAPIC: {
2204ae3c
MT		 2472 r = -EINVAL;
2473 if (!vcpu->arch.apic)
2474 goto out;
d1ac91d8 2475 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2476
b772ff36 2477 r = -ENOMEM;
d1ac91d8 2478 if (!u.lapic)
b772ff36 2479 goto out;
d1ac91d8 2480 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2481 if (r)
2482 goto out;
2483 r = -EFAULT;
d1ac91d8 2484 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2485 goto out;
2486 r = 0;
2487 break;
2488 }
2489 case KVM_SET_LAPIC: {
2204ae3c
MT		 2490 r = -EINVAL;
2491 if (!vcpu->arch.apic)
2492 goto out;
d1ac91d8 2493 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2494 r = -ENOMEM;
d1ac91d8 2495 if (!u.lapic)
b772ff36 2496 goto out;
313a3dc7 2497 r = -EFAULT;
d1ac91d8 2498 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2499 goto out;
d1ac91d8 2500 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2501 if (r)
2502 goto out;
2503 r = 0;
2504 break;
2505 }
f77bc6a4
ZX		 2506 case KVM_INTERRUPT: {
2507 struct kvm_interrupt irq;
2508
2509 r = -EFAULT;
2510 if (copy_from_user(&irq, argp, sizeof irq))
2511 goto out;
2512 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2513 if (r)
2514 goto out;
2515 r = 0;
2516 break;
2517 }
c4abb7c9
JK		 2518 case KVM_NMI: {
2519 r = kvm_vcpu_ioctl_nmi(vcpu);
2520 if (r)
2521 goto out;
2522 r = 0;
2523 break;
2524 }
313a3dc7
CO		 2525 case KVM_SET_CPUID: {
2526 struct kvm_cpuid __user *cpuid_arg = argp;
2527 struct kvm_cpuid cpuid;
2528
2529 r = -EFAULT;
2530 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2531 goto out;
2532 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2533 if (r)
2534 goto out;
2535 break;
2536 }
07716717
DK		 2537 case KVM_SET_CPUID2: {
2538 struct kvm_cpuid2 __user *cpuid_arg = argp;
2539 struct kvm_cpuid2 cpuid;
2540
2541 r = -EFAULT;
2542 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2543 goto out;
2544 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2545 cpuid_arg->entries);
07716717
DK		 2546 if (r)
2547 goto out;
2548 break;
2549 }
2550 case KVM_GET_CPUID2: {
2551 struct kvm_cpuid2 __user *cpuid_arg = argp;
2552 struct kvm_cpuid2 cpuid;
2553
2554 r = -EFAULT;
2555 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2556 goto out;
2557 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2558 cpuid_arg->entries);
07716717
DK		 2559 if (r)
2560 goto out;
2561 r = -EFAULT;
2562 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2563 goto out;
2564 r = 0;
2565 break;
2566 }
313a3dc7
CO		 2567 case KVM_GET_MSRS:
2568 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2569 break;
2570 case KVM_SET_MSRS:
2571 r = msr_io(vcpu, argp, do_set_msr, 0);
2572 break;
b209749f
AK		 2573 case KVM_TPR_ACCESS_REPORTING: {
2574 struct kvm_tpr_access_ctl tac;
2575
2576 r = -EFAULT;
2577 if (copy_from_user(&tac, argp, sizeof tac))
2578 goto out;
2579 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2580 if (r)
2581 goto out;
2582 r = -EFAULT;
2583 if (copy_to_user(argp, &tac, sizeof tac))
2584 goto out;
2585 r = 0;
2586 break;
2587 };
b93463aa
AK		 2588 case KVM_SET_VAPIC_ADDR: {
2589 struct kvm_vapic_addr va;
2590
2591 r = -EINVAL;
2592 if (!irqchip_in_kernel(vcpu->kvm))
2593 goto out;
2594 r = -EFAULT;
2595 if (copy_from_user(&va, argp, sizeof va))
2596 goto out;
2597 r = 0;
2598 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2599 break;
2600 }
890ca9ae
HY		 2601 case KVM_X86_SETUP_MCE: {
2602 u64 mcg_cap;
2603
2604 r = -EFAULT;
2605 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2606 goto out;
2607 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2608 break;
2609 }
2610 case KVM_X86_SET_MCE: {
2611 struct kvm_x86_mce mce;
2612
2613 r = -EFAULT;
2614 if (copy_from_user(&mce, argp, sizeof mce))
2615 goto out;
2616 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2617 break;
2618 }
3cfc3092
JK		 2619 case KVM_GET_VCPU_EVENTS: {
2620 struct kvm_vcpu_events events;
2621
2622 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2623
2624 r = -EFAULT;
2625 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2626 break;
2627 r = 0;
2628 break;
2629 }
2630 case KVM_SET_VCPU_EVENTS: {
2631 struct kvm_vcpu_events events;
2632
2633 r = -EFAULT;
2634 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2635 break;
2636
2637 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2638 break;
2639 }
a1efbe77
JK		 2640 case KVM_GET_DEBUGREGS: {
2641 struct kvm_debugregs dbgregs;
2642
2643 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2644
2645 r = -EFAULT;
2646 if (copy_to_user(argp, &dbgregs,
2647 sizeof(struct kvm_debugregs)))
2648 break;
2649 r = 0;
2650 break;
2651 }
2652 case KVM_SET_DEBUGREGS: {
2653 struct kvm_debugregs dbgregs;
2654
2655 r = -EFAULT;
2656 if (copy_from_user(&dbgregs, argp,
2657 sizeof(struct kvm_debugregs)))
2658 break;
2659
2660 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2661 break;
2662 }
2d5b5a66 2663 case KVM_GET_XSAVE: {
d1ac91d8 2664 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2665 r = -ENOMEM;
d1ac91d8 2666 if (!u.xsave)
2d5b5a66
SY		 2667 break;
2668
d1ac91d8 2669 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2670
2671 r = -EFAULT;
d1ac91d8 2672 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2673 break;
2674 r = 0;
2675 break;
2676 }
2677 case KVM_SET_XSAVE: {
d1ac91d8 2678 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2679 r = -ENOMEM;
d1ac91d8 2680 if (!u.xsave)
2d5b5a66
SY		 2681 break;
2682
2683 r = -EFAULT;
d1ac91d8 2684 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2685 break;
2686
d1ac91d8 2687 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2688 break;
2689 }
2690 case KVM_GET_XCRS: {
d1ac91d8 2691 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2692 r = -ENOMEM;
d1ac91d8 2693 if (!u.xcrs)
2d5b5a66
SY		 2694 break;
2695
d1ac91d8 2696 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2697
2698 r = -EFAULT;
d1ac91d8 2699 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2700 sizeof(struct kvm_xcrs)))
2701 break;
2702 r = 0;
2703 break;
2704 }
2705 case KVM_SET_XCRS: {
d1ac91d8 2706 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2707 r = -ENOMEM;
d1ac91d8 2708 if (!u.xcrs)
2d5b5a66
SY		 2709 break;
2710
2711 r = -EFAULT;
d1ac91d8 2712 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2713 sizeof(struct kvm_xcrs)))
2714 break;
2715
d1ac91d8 2716 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2717 break;
2718 }
313a3dc7
CO		 2719 default:
2720 r = -EINVAL;
2721 }
2722out:
d1ac91d8 2723 kfree(u.buffer);
313a3dc7
CO		 2724 return r;
2725}
2726
1fe779f8
CO		 2727static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2728{
2729 int ret;
2730
2731 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2732 return -1;
2733 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2734 return ret;
2735}
2736
b927a3ce
SY		 2737static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2738 u64 ident_addr)
2739{
2740 kvm->arch.ept_identity_map_addr = ident_addr;
2741 return 0;
2742}
2743
1fe779f8
CO		 2744static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2745 u32 kvm_nr_mmu_pages)
2746{
2747 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2748 return -EINVAL;
2749
79fac95e 2750 mutex_lock(&kvm->slots_lock);
7c8a83b7 2751 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2752
2753 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2754 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2755
7c8a83b7 2756 spin_unlock(&kvm->mmu_lock);
79fac95e 2757 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2758 return 0;
2759}
2760
2761static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2762{
f05e70ac 2763 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2764}
2765
1fe779f8
CO		 2766static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2767{
2768 int r;
2769
2770 r = 0;
2771 switch (chip->chip_id) {
2772 case KVM_IRQCHIP_PIC_MASTER:
2773 memcpy(&chip->chip.pic,
2774 &pic_irqchip(kvm)->pics[0],
2775 sizeof(struct kvm_pic_state));
2776 break;
2777 case KVM_IRQCHIP_PIC_SLAVE:
2778 memcpy(&chip->chip.pic,
2779 &pic_irqchip(kvm)->pics[1],
2780 sizeof(struct kvm_pic_state));
2781 break;
2782 case KVM_IRQCHIP_IOAPIC:
eba0226b 2783 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2784 break;
2785 default:
2786 r = -EINVAL;
2787 break;
2788 }
2789 return r;
2790}
2791
2792static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2793{
2794 int r;
2795
2796 r = 0;
2797 switch (chip->chip_id) {
2798 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2799 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2800 memcpy(&pic_irqchip(kvm)->pics[0],
2801 &chip->chip.pic,
2802 sizeof(struct kvm_pic_state));
fa8273e9 2803 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2804 break;
2805 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2806 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2807 memcpy(&pic_irqchip(kvm)->pics[1],
2808 &chip->chip.pic,
2809 sizeof(struct kvm_pic_state));
fa8273e9 2810 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2811 break;
2812 case KVM_IRQCHIP_IOAPIC:
eba0226b 2813 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2814 break;
2815 default:
2816 r = -EINVAL;
2817 break;
2818 }
2819 kvm_pic_update_irq(pic_irqchip(kvm));
2820 return r;
2821}
2822
e0f63cb9
SY		 2823static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2824{
2825 int r = 0;
2826
894a9c55 2827 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2828 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2829 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2830 return r;
2831}
2832
2833static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2834{
2835 int r = 0;
2836
894a9c55 2837 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2838 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2839 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2840 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2841 return r;
2842}
2843
2844static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2845{
2846 int r = 0;
2847
2848 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2849 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2850 sizeof(ps->channels));
2851 ps->flags = kvm->arch.vpit->pit_state.flags;
2852 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2853 return r;
2854}
2855
2856static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2857{
2858 int r = 0, start = 0;
2859 u32 prev_legacy, cur_legacy;
2860 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2861 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2862 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2863 if (!prev_legacy && cur_legacy)
2864 start = 1;
2865 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2866 sizeof(kvm->arch.vpit->pit_state.channels));
2867 kvm->arch.vpit->pit_state.flags = ps->flags;
2868 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2869 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2870 return r;
2871}
2872
52d939a0
MT		 2873static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2874 struct kvm_reinject_control *control)
2875{
2876 if (!kvm->arch.vpit)
2877 return -ENXIO;
894a9c55 2878 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2879 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2880 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2881 return 0;
2882}
2883
5bb064dc
ZX		 2884/*
2885 * Get (and clear) the dirty memory log for a memory slot.
2886 */
2887int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2888 struct kvm_dirty_log *log)
2889{
87bf6e7d 2890 int r, i;
5bb064dc 2891 struct kvm_memory_slot *memslot;
87bf6e7d 2892 unsigned long n;
b050b015 2893 unsigned long is_dirty = 0;
5bb064dc 2894
79fac95e 2895 mutex_lock(&kvm->slots_lock);
5bb064dc 2896
b050b015
MT		 2897 r = -EINVAL;
2898 if (log->slot >= KVM_MEMORY_SLOTS)
2899 goto out;
2900
2901 memslot = &kvm->memslots->memslots[log->slot];
2902 r = -ENOENT;
2903 if (!memslot->dirty_bitmap)
2904 goto out;
2905
87bf6e7d 2906 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2907
b050b015
MT		 2908 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2909 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2910
2911 /* If nothing is dirty, don't bother messing with page tables. */
2912 if (is_dirty) {
b050b015 2913 struct kvm_memslots *slots, *old_slots;
914ebccd 2914 unsigned long *dirty_bitmap;
b050b015 2915
7c8a83b7 2916 spin_lock(&kvm->mmu_lock);
5bb064dc 2917 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2918 spin_unlock(&kvm->mmu_lock);
b050b015 2919
914ebccd
TY		 2920 r = -ENOMEM;
2921 dirty_bitmap = vmalloc(n);
2922 if (!dirty_bitmap)
2923 goto out;
2924 memset(dirty_bitmap, 0, n);
b050b015 2925
914ebccd
TY		 2926 r = -ENOMEM;
2927 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2928 if (!slots) {
2929 vfree(dirty_bitmap);
2930 goto out;
2931 }
b050b015
MT		 2932 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2933 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2934
2935 old_slots = kvm->memslots;
2936 rcu_assign_pointer(kvm->memslots, slots);
2937 synchronize_srcu_expedited(&kvm->srcu);
2938 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2939 kfree(old_slots);
914ebccd
TY		 2940
2941 r = -EFAULT;
2942 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2943 vfree(dirty_bitmap);
2944 goto out;
2945 }
2946 vfree(dirty_bitmap);
2947 } else {
2948 r = -EFAULT;
2949 if (clear_user(log->dirty_bitmap, n))
2950 goto out;
5bb064dc 2951 }
b050b015 2952
5bb064dc
ZX		 2953 r = 0;
2954out:
79fac95e 2955 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2956 return r;
2957}
2958
1fe779f8
CO		 2959long kvm_arch_vm_ioctl(struct file *filp,
2960 unsigned int ioctl, unsigned long arg)
2961{
2962 struct kvm *kvm = filp->private_data;
2963 void __user *argp = (void __user *)arg;
367e1319 2964 int r = -ENOTTY;
f0d66275
DH		 2965 /*
2966 * This union makes it completely explicit to gcc-3.x
2967 * that these two variables' stack usage should be
2968 * combined, not added together.
2969 */
2970 union {
2971 struct kvm_pit_state ps;
e9f42757 2972 struct kvm_pit_state2 ps2;
c5ff41ce 2973 struct kvm_pit_config pit_config;
f0d66275 2974 } u;
1fe779f8
CO		 2975
2976 switch (ioctl) {
2977 case KVM_SET_TSS_ADDR:
2978 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2979 if (r < 0)
2980 goto out;
2981 break;
b927a3ce
SY		 2982 case KVM_SET_IDENTITY_MAP_ADDR: {
2983 u64 ident_addr;
2984
2985 r = -EFAULT;
2986 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2987 goto out;
2988 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2989 if (r < 0)
2990 goto out;
2991 break;
2992 }
1fe779f8
CO		 2993 case KVM_SET_NR_MMU_PAGES:
2994 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2995 if (r)
2996 goto out;
2997 break;
2998 case KVM_GET_NR_MMU_PAGES:
2999 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3000 break;
3ddea128
MT		 3001 case KVM_CREATE_IRQCHIP: {
3002 struct kvm_pic *vpic;
3003
3004 mutex_lock(&kvm->lock);
3005 r = -EEXIST;
3006 if (kvm->arch.vpic)
3007 goto create_irqchip_unlock;
1fe779f8 3008 r = -ENOMEM;
3ddea128
MT		 3009 vpic = kvm_create_pic(kvm);
3010 if (vpic) {
1fe779f8
CO		 3011 r = kvm_ioapic_init(kvm);
3012 if (r) {
72bb2fcd
WY		 3013 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3014 &vpic->dev);
3ddea128
MT		 3015 kfree(vpic);
3016 goto create_irqchip_unlock;
1fe779f8
CO		 3017 }
3018 } else
3ddea128
MT		 3019 goto create_irqchip_unlock;
3020 smp_wmb();
3021 kvm->arch.vpic = vpic;
3022 smp_wmb();
399ec807
AK		 3023 r = kvm_setup_default_irq_routing(kvm);
3024 if (r) {
3ddea128 3025 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3026 kvm_ioapic_destroy(kvm);
3027 kvm_destroy_pic(kvm);
3ddea128 3028 mutex_unlock(&kvm->irq_lock);
399ec807 3029 }
3ddea128
MT		 3030 create_irqchip_unlock:
3031 mutex_unlock(&kvm->lock);
1fe779f8 3032 break;
3ddea128 3033 }
7837699f 3034 case KVM_CREATE_PIT:
c5ff41ce
JK		 3035 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3036 goto create_pit;
3037 case KVM_CREATE_PIT2:
3038 r = -EFAULT;
3039 if (copy_from_user(&u.pit_config, argp,
3040 sizeof(struct kvm_pit_config)))
3041 goto out;
3042 create_pit:
79fac95e 3043 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3044 r = -EEXIST;
3045 if (kvm->arch.vpit)
3046 goto create_pit_unlock;
7837699f 3047 r = -ENOMEM;
c5ff41ce 3048 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3049 if (kvm->arch.vpit)
3050 r = 0;
269e05e4 3051 create_pit_unlock:
79fac95e 3052 mutex_unlock(&kvm->slots_lock);
7837699f 3053 break;
4925663a 3054 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3055 case KVM_IRQ_LINE: {
3056 struct kvm_irq_level irq_event;
3057
3058 r = -EFAULT;
3059 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3060 goto out;
160d2f6c 3061 r = -ENXIO;
1fe779f8 3062 if (irqchip_in_kernel(kvm)) {
4925663a 3063 __s32 status;
4925663a
GN		 3064 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3065 irq_event.irq, irq_event.level);
4925663a 3066 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3067 r = -EFAULT;
4925663a
GN		 3068 irq_event.status = status;
3069 if (copy_to_user(argp, &irq_event,
3070 sizeof irq_event))
3071 goto out;
3072 }
1fe779f8
CO		 3073 r = 0;
3074 }
3075 break;
3076 }
3077 case KVM_GET_IRQCHIP: {
3078 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3079 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3080
f0d66275
DH		 3081 r = -ENOMEM;
3082 if (!chip)
1fe779f8 3083 goto out;
f0d66275
DH		 3084 r = -EFAULT;
3085 if (copy_from_user(chip, argp, sizeof *chip))
3086 goto get_irqchip_out;
1fe779f8
CO		 3087 r = -ENXIO;
3088 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3089 goto get_irqchip_out;
3090 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3091 if (r)
f0d66275 3092 goto get_irqchip_out;
1fe779f8 3093 r = -EFAULT;
f0d66275
DH		 3094 if (copy_to_user(argp, chip, sizeof *chip))
3095 goto get_irqchip_out;
1fe779f8 3096 r = 0;
f0d66275
DH		 3097 get_irqchip_out:
3098 kfree(chip);
3099 if (r)
3100 goto out;
1fe779f8
CO		 3101 break;
3102 }
3103 case KVM_SET_IRQCHIP: {
3104 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3105 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3106
f0d66275
DH		 3107 r = -ENOMEM;
3108 if (!chip)
1fe779f8 3109 goto out;
f0d66275
DH		 3110 r = -EFAULT;
3111 if (copy_from_user(chip, argp, sizeof *chip))
3112 goto set_irqchip_out;
1fe779f8
CO		 3113 r = -ENXIO;
3114 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3115 goto set_irqchip_out;
3116 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3117 if (r)
f0d66275 3118 goto set_irqchip_out;
1fe779f8 3119 r = 0;
f0d66275
DH		 3120 set_irqchip_out:
3121 kfree(chip);
3122 if (r)
3123 goto out;
1fe779f8
CO		 3124 break;
3125 }
e0f63cb9 3126 case KVM_GET_PIT: {
e0f63cb9 3127 r = -EFAULT;
f0d66275 3128 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3129 goto out;
3130 r = -ENXIO;
3131 if (!kvm->arch.vpit)
3132 goto out;
f0d66275 3133 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3134 if (r)
3135 goto out;
3136 r = -EFAULT;
f0d66275 3137 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3138 goto out;
3139 r = 0;
3140 break;
3141 }
3142 case KVM_SET_PIT: {
e0f63cb9 3143 r = -EFAULT;
f0d66275 3144 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3145 goto out;
3146 r = -ENXIO;
3147 if (!kvm->arch.vpit)
3148 goto out;
f0d66275 3149 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3150 if (r)
3151 goto out;
3152 r = 0;
3153 break;
3154 }
e9f42757
BK		 3155 case KVM_GET_PIT2: {
3156 r = -ENXIO;
3157 if (!kvm->arch.vpit)
3158 goto out;
3159 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3160 if (r)
3161 goto out;
3162 r = -EFAULT;
3163 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3164 goto out;
3165 r = 0;
3166 break;
3167 }
3168 case KVM_SET_PIT2: {
3169 r = -EFAULT;
3170 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3171 goto out;
3172 r = -ENXIO;
3173 if (!kvm->arch.vpit)
3174 goto out;
3175 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3176 if (r)
3177 goto out;
3178 r = 0;
3179 break;
3180 }
52d939a0
MT		 3181 case KVM_REINJECT_CONTROL: {
3182 struct kvm_reinject_control control;
3183 r = -EFAULT;
3184 if (copy_from_user(&control, argp, sizeof(control)))
3185 goto out;
3186 r = kvm_vm_ioctl_reinject(kvm, &control);
3187 if (r)
3188 goto out;
3189 r = 0;
3190 break;
3191 }
ffde22ac
ES		 3192 case KVM_XEN_HVM_CONFIG: {
3193 r = -EFAULT;
3194 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3195 sizeof(struct kvm_xen_hvm_config)))
3196 goto out;
3197 r = -EINVAL;
3198 if (kvm->arch.xen_hvm_config.flags)
3199 goto out;
3200 r = 0;
3201 break;
3202 }
afbcf7ab
GC		 3203 case KVM_SET_CLOCK: {
3204 struct timespec now;
3205 struct kvm_clock_data user_ns;
3206 u64 now_ns;
3207 s64 delta;
3208
3209 r = -EFAULT;
3210 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3211 goto out;
3212
3213 r = -EINVAL;
3214 if (user_ns.flags)
3215 goto out;
3216
3217 r = 0;
3218 ktime_get_ts(&now);
3219 now_ns = timespec_to_ns(&now);
3220 delta = user_ns.clock - now_ns;
3221 kvm->arch.kvmclock_offset = delta;
3222 break;
3223 }
3224 case KVM_GET_CLOCK: {
3225 struct timespec now;
3226 struct kvm_clock_data user_ns;
3227 u64 now_ns;
3228
3229 ktime_get_ts(&now);
3230 now_ns = timespec_to_ns(&now);
3231 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3232 user_ns.flags = 0;
3233
3234 r = -EFAULT;
3235 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3236 goto out;
3237 r = 0;
3238 break;
3239 }
3240
1fe779f8
CO		 3241 default:
3242 ;
3243 }
3244out:
3245 return r;
3246}
3247
a16b043c 3248static void kvm_init_msr_list(void)
043405e1
CO		 3249{
3250 u32 dummy[2];
3251 unsigned i, j;
3252
e3267cbb
GC		 3253 /* skip the first msrs in the list. KVM-specific */
3254 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3255 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3256 continue;
3257 if (j < i)
3258 msrs_to_save[j] = msrs_to_save[i];
3259 j++;
3260 }
3261 num_msrs_to_save = j;
3262}
3263
bda9020e
MT		 3264static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3265 const void *v)
bbd9b64e 3266{
bda9020e
MT		 3267 if (vcpu->arch.apic &&
3268 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3269 return 0;
bbd9b64e 3270
e93f8a0f 3271 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3272}
3273
bda9020e 3274static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3275{
bda9020e
MT		 3276 if (vcpu->arch.apic &&
3277 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3278 return 0;
bbd9b64e 3279
e93f8a0f 3280 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3281}
3282
2dafc6c2
GN		 3283static void kvm_set_segment(struct kvm_vcpu *vcpu,
3284 struct kvm_segment *var, int seg)
3285{
3286 kvm_x86_ops->set_segment(vcpu, var, seg);
3287}
3288
3289void kvm_get_segment(struct kvm_vcpu *vcpu,
3290 struct kvm_segment *var, int seg)
3291{
3292 kvm_x86_ops->get_segment(vcpu, var, seg);
3293}
3294
1871c602
GN		 3295gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3296{
3297 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3298 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3299}
3300
3301 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3302{
3303 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3304 access |= PFERR_FETCH_MASK;
3305 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3306}
3307
3308gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3309{
3310 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3311 access |= PFERR_WRITE_MASK;
3312 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3313}
3314
3315/* uses this to access any guest's mapped memory without checking CPL */
3316gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3317{
3318 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3319}
3320
3321static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3322 struct kvm_vcpu *vcpu, u32 access,
3323 u32 *error)
bbd9b64e
CO		 3324{
3325 void *data = val;
10589a46 3326 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3327
3328 while (bytes) {
1871c602 3329 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3330 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3331 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3332 int ret;
3333
10589a46
MT		 3334 if (gpa == UNMAPPED_GVA) {
3335 r = X86EMUL_PROPAGATE_FAULT;
3336 goto out;
3337 }
77c2002e 3338 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3339 if (ret < 0) {
c3cd7ffa 3340 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3341 goto out;
3342 }
bbd9b64e 3343
77c2002e
IE		 3344 bytes -= toread;
3345 data += toread;
3346 addr += toread;
bbd9b64e 3347 }
10589a46 3348out:
10589a46 3349 return r;
bbd9b64e 3350}
77c2002e 3351
1871c602
GN		 3352/* used for instruction fetching */
3353static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3354 struct kvm_vcpu *vcpu, u32 *error)
3355{
3356 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3357 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3358 access | PFERR_FETCH_MASK, error);
3359}
3360
3361static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3362 struct kvm_vcpu *vcpu, u32 *error)
3363{
3364 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3365 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3366 error);
3367}
3368
3369static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3370 struct kvm_vcpu *vcpu, u32 *error)
3371{
3372 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3373}
3374
7972995b 3375static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3376 unsigned int bytes,
7972995b 3377 struct kvm_vcpu *vcpu,
2dafc6c2 3378 u32 *error)
77c2002e
IE		 3379{
3380 void *data = val;
3381 int r = X86EMUL_CONTINUE;
3382
3383 while (bytes) {
7972995b
GN		 3384 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3385 PFERR_WRITE_MASK, error);
77c2002e
IE		 3386 unsigned offset = addr & (PAGE_SIZE-1);
3387 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3388 int ret;
3389
3390 if (gpa == UNMAPPED_GVA) {
3391 r = X86EMUL_PROPAGATE_FAULT;
3392 goto out;
3393 }
3394 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3395 if (ret < 0) {
c3cd7ffa 3396 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3397 goto out;
3398 }
3399
3400 bytes -= towrite;
3401 data += towrite;
3402 addr += towrite;
3403 }
3404out:
3405 return r;
3406}
3407
bbd9b64e
CO		 3408static int emulator_read_emulated(unsigned long addr,
3409 void *val,
3410 unsigned int bytes,
8fe681e9 3411 unsigned int *error_code,
bbd9b64e
CO		 3412 struct kvm_vcpu *vcpu)
3413{
bbd9b64e
CO		 3414 gpa_t gpa;
3415
3416 if (vcpu->mmio_read_completed) {
3417 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3418 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3419 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3420 vcpu->mmio_read_completed = 0;
3421 return X86EMUL_CONTINUE;
3422 }
3423
8fe681e9 3424 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3425
8fe681e9 3426 if (gpa == UNMAPPED_GVA)
1871c602 3427 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3428
3429 /* For APIC access vmexit */
3430 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3431 goto mmio;
3432
1871c602 3433 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3434 == X86EMUL_CONTINUE)
bbd9b64e 3435 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3436
3437mmio:
3438 /*
3439 * Is this MMIO handled locally?
3440 */
aec51dc4
AK		 3441 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3442 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3443 return X86EMUL_CONTINUE;
3444 }
aec51dc4
AK		 3445
3446 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3447
3448 vcpu->mmio_needed = 1;
411c35b7
GN		 3449 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3450 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3451 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3452 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3453
c3cd7ffa 3454 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3455}
3456
3200f405 3457int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3458 const void *val, int bytes)
bbd9b64e
CO		 3459{
3460 int ret;
3461
3462 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3463 if (ret < 0)
bbd9b64e 3464 return 0;
ad218f85 3465 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3466 return 1;
3467}
3468
3469static int emulator_write_emulated_onepage(unsigned long addr,
3470 const void *val,
3471 unsigned int bytes,
8fe681e9 3472 unsigned int *error_code,
bbd9b64e
CO		 3473 struct kvm_vcpu *vcpu)
3474{
10589a46
MT		 3475 gpa_t gpa;
3476
8fe681e9 3477 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3478
8fe681e9 3479 if (gpa == UNMAPPED_GVA)
bbd9b64e 3480 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3481
3482 /* For APIC access vmexit */
3483 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3484 goto mmio;
3485
3486 if (emulator_write_phys(vcpu, gpa, val, bytes))
3487 return X86EMUL_CONTINUE;
3488
3489mmio:
aec51dc4 3490 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3491 /*
3492 * Is this MMIO handled locally?
3493 */
bda9020e 3494 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3495 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3496
3497 vcpu->mmio_needed = 1;
411c35b7
GN		 3498 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3499 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3500 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3501 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3502 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3503
3504 return X86EMUL_CONTINUE;
3505}
3506
3507int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3508 const void *val,
3509 unsigned int bytes,
8fe681e9 3510 unsigned int *error_code,
8f6abd06 3511 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3512{
3513 /* Crossing a page boundary? */
3514 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3515 int rc, now;
3516
3517 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3518 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3519 vcpu);
bbd9b64e
CO		 3520 if (rc != X86EMUL_CONTINUE)
3521 return rc;
3522 addr += now;
3523 val += now;
3524 bytes -= now;
3525 }
8fe681e9
GN		 3526 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3527 vcpu);
bbd9b64e 3528}
bbd9b64e 3529
daea3e73
AK		 3530#define CMPXCHG_TYPE(t, ptr, old, new) \
3531 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3532
3533#ifdef CONFIG_X86_64
3534# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3535#else
3536# define CMPXCHG64(ptr, old, new) \
9749a6c0 3537 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3538#endif
3539
bbd9b64e
CO		 3540static int emulator_cmpxchg_emulated(unsigned long addr,
3541 const void *old,
3542 const void *new,
3543 unsigned int bytes,
8fe681e9 3544 unsigned int *error_code,
bbd9b64e
CO		 3545 struct kvm_vcpu *vcpu)
3546{
daea3e73
AK		 3547 gpa_t gpa;
3548 struct page *page;
3549 char *kaddr;
3550 bool exchanged;
2bacc55c 3551
daea3e73
AK		 3552 /* guests cmpxchg8b have to be emulated atomically */
3553 if (bytes > 8 || (bytes & (bytes - 1)))
3554 goto emul_write;
10589a46 3555
daea3e73 3556 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3557
daea3e73
AK		 3558 if (gpa == UNMAPPED_GVA ||
3559 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3560 goto emul_write;
2bacc55c 3561
daea3e73
AK		 3562 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3563 goto emul_write;
72dc67a6 3564
daea3e73 3565 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3566 if (is_error_page(page)) {
3567 kvm_release_page_clean(page);
3568 goto emul_write;
3569 }
72dc67a6 3570
daea3e73
AK		 3571 kaddr = kmap_atomic(page, KM_USER0);
3572 kaddr += offset_in_page(gpa);
3573 switch (bytes) {
3574 case 1:
3575 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3576 break;
3577 case 2:
3578 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3579 break;
3580 case 4:
3581 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3582 break;
3583 case 8:
3584 exchanged = CMPXCHG64(kaddr, old, new);
3585 break;
3586 default:
3587 BUG();
2bacc55c 3588 }
daea3e73
AK		 3589 kunmap_atomic(kaddr, KM_USER0);
3590 kvm_release_page_dirty(page);
3591
3592 if (!exchanged)
3593 return X86EMUL_CMPXCHG_FAILED;
3594
8f6abd06
GN		 3595 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3596
3597 return X86EMUL_CONTINUE;
4a5f48f6 3598
3200f405 3599emul_write:
daea3e73 3600 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3601
8fe681e9 3602 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3603}
3604
cf8f70bf
GN		 3605static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3606{
3607 /* TODO: String I/O for in kernel device */
3608 int r;
3609
3610 if (vcpu->arch.pio.in)
3611 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3612 vcpu->arch.pio.size, pd);
3613 else
3614 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3615 vcpu->arch.pio.port, vcpu->arch.pio.size,
3616 pd);
3617 return r;
3618}
3619
3620
3621static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3622 unsigned int count, struct kvm_vcpu *vcpu)
3623{
7972995b 3624 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3625 goto data_avail;
3626
3627 trace_kvm_pio(1, port, size, 1);
3628
3629 vcpu->arch.pio.port = port;
3630 vcpu->arch.pio.in = 1;
7972995b 3631 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3632 vcpu->arch.pio.size = size;
3633
3634 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3635 data_avail:
3636 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3637 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3638 return 1;
3639 }
3640
3641 vcpu->run->exit_reason = KVM_EXIT_IO;
3642 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3643 vcpu->run->io.size = size;
3644 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3645 vcpu->run->io.count = count;
3646 vcpu->run->io.port = port;
3647
3648 return 0;
3649}
3650
3651static int emulator_pio_out_emulated(int size, unsigned short port,
3652 const void *val, unsigned int count,
3653 struct kvm_vcpu *vcpu)
3654{
3655 trace_kvm_pio(0, port, size, 1);
3656
3657 vcpu->arch.pio.port = port;
3658 vcpu->arch.pio.in = 0;
7972995b 3659 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3660 vcpu->arch.pio.size = size;
3661
3662 memcpy(vcpu->arch.pio_data, val, size * count);
3663
3664 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3665 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3666 return 1;
3667 }
3668
3669 vcpu->run->exit_reason = KVM_EXIT_IO;
3670 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3671 vcpu->run->io.size = size;
3672 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3673 vcpu->run->io.count = count;
3674 vcpu->run->io.port = port;
3675
3676 return 0;
3677}
3678
bbd9b64e
CO		 3679static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3680{
3681 return kvm_x86_ops->get_segment_base(vcpu, seg);
3682}
3683
3684int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3685{
a7052897 3686 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3687 return X86EMUL_CONTINUE;
3688}
3689
f5f48ee1
SY		 3690int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3691{
3692 if (!need_emulate_wbinvd(vcpu))
3693 return X86EMUL_CONTINUE;
3694
3695 if (kvm_x86_ops->has_wbinvd_exit()) {
3696 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3697 wbinvd_ipi, NULL, 1);
3698 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3699 }
3700 wbinvd();
3701 return X86EMUL_CONTINUE;
3702}
3703EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3704
bbd9b64e
CO		 3705int emulate_clts(struct kvm_vcpu *vcpu)
3706{
4d4ec087 3707 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3708 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3709 return X86EMUL_CONTINUE;
3710}
3711
35aa5375 3712int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3713{
338dbc97 3714 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3715}
3716
35aa5375 3717int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3718{
338dbc97
GN		 3719
3720 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3721}
3722
52a46617 3723static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3724{
52a46617 3725 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3726}
3727
52a46617 3728static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3729{
52a46617
GN		 3730 unsigned long value;
3731
3732 switch (cr) {
3733 case 0:
3734 value = kvm_read_cr0(vcpu);
3735 break;
3736 case 2:
3737 value = vcpu->arch.cr2;
3738 break;
3739 case 3:
3740 value = vcpu->arch.cr3;
3741 break;
3742 case 4:
3743 value = kvm_read_cr4(vcpu);
3744 break;
3745 case 8:
3746 value = kvm_get_cr8(vcpu);
3747 break;
3748 default:
3749 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3750 return 0;
3751 }
3752
3753 return value;
3754}
3755
0f12244f 3756static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3757{
0f12244f
GN		 3758 int res = 0;
3759
52a46617
GN		 3760 switch (cr) {
3761 case 0:
49a9b07e 3762 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3763 break;
3764 case 2:
3765 vcpu->arch.cr2 = val;
3766 break;
3767 case 3:
2390218b 3768 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3769 break;
3770 case 4:
a83b29c6 3771 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3772 break;
3773 case 8:
0f12244f 3774 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3775 break;
3776 default:
3777 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3778 res = -1;
52a46617 3779 }
0f12244f
GN		 3780
3781 return res;
52a46617
GN		 3782}
3783
9c537244
GN		 3784static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3785{
3786 return kvm_x86_ops->get_cpl(vcpu);
3787}
3788
2dafc6c2
GN		 3789static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3790{
3791 kvm_x86_ops->get_gdt(vcpu, dt);
3792}
3793
5951c442
GN		 3794static unsigned long emulator_get_cached_segment_base(int seg,
3795 struct kvm_vcpu *vcpu)
3796{
3797 return get_segment_base(vcpu, seg);
3798}
3799
2dafc6c2
GN		 3800static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3801 struct kvm_vcpu *vcpu)
3802{
3803 struct kvm_segment var;
3804
3805 kvm_get_segment(vcpu, &var, seg);
3806
3807 if (var.unusable)
3808 return false;
3809
3810 if (var.g)
3811 var.limit >>= 12;
3812 set_desc_limit(desc, var.limit);
3813 set_desc_base(desc, (unsigned long)var.base);
3814 desc->type = var.type;
3815 desc->s = var.s;
3816 desc->dpl = var.dpl;
3817 desc->p = var.present;
3818 desc->avl = var.avl;
3819 desc->l = var.l;
3820 desc->d = var.db;
3821 desc->g = var.g;
3822
3823 return true;
3824}
3825
3826static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3827 struct kvm_vcpu *vcpu)
3828{
3829 struct kvm_segment var;
3830
3831 /* needed to preserve selector */
3832 kvm_get_segment(vcpu, &var, seg);
3833
3834 var.base = get_desc_base(desc);
3835 var.limit = get_desc_limit(desc);
3836 if (desc->g)
3837 var.limit = (var.limit << 12) | 0xfff;
3838 var.type = desc->type;
3839 var.present = desc->p;
3840 var.dpl = desc->dpl;
3841 var.db = desc->d;
3842 var.s = desc->s;
3843 var.l = desc->l;
3844 var.g = desc->g;
3845 var.avl = desc->avl;
3846 var.present = desc->p;
3847 var.unusable = !var.present;
3848 var.padding = 0;
3849
3850 kvm_set_segment(vcpu, &var, seg);
3851 return;
3852}
3853
3854static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3855{
3856 struct kvm_segment kvm_seg;
3857
3858 kvm_get_segment(vcpu, &kvm_seg, seg);
3859 return kvm_seg.selector;
3860}
3861
3862static void emulator_set_segment_selector(u16 sel, int seg,
3863 struct kvm_vcpu *vcpu)
3864{
3865 struct kvm_segment kvm_seg;
3866
3867 kvm_get_segment(vcpu, &kvm_seg, seg);
3868 kvm_seg.selector = sel;
3869 kvm_set_segment(vcpu, &kvm_seg, seg);
3870}
3871
14af3f3c 3872static struct x86_emulate_ops emulate_ops = {
1871c602 3873 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3874 .write_std = kvm_write_guest_virt_system,
1871c602 3875 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3876 .read_emulated = emulator_read_emulated,
3877 .write_emulated = emulator_write_emulated,
3878 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3879 .pio_in_emulated = emulator_pio_in_emulated,
3880 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3881 .get_cached_descriptor = emulator_get_cached_descriptor,
3882 .set_cached_descriptor = emulator_set_cached_descriptor,
3883 .get_segment_selector = emulator_get_segment_selector,
3884 .set_segment_selector = emulator_set_segment_selector,
5951c442 3885 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3886 .get_gdt = emulator_get_gdt,
52a46617
GN		 3887 .get_cr = emulator_get_cr,
3888 .set_cr = emulator_set_cr,
9c537244 3889 .cpl = emulator_get_cpl,
35aa5375
GN		 3890 .get_dr = emulator_get_dr,
3891 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3892 .set_msr = kvm_set_msr,
3893 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3894};
3895
5fdbf976
MT		 3896static void cache_all_regs(struct kvm_vcpu *vcpu)
3897{
3898 kvm_register_read(vcpu, VCPU_REGS_RAX);
3899 kvm_register_read(vcpu, VCPU_REGS_RSP);
3900 kvm_register_read(vcpu, VCPU_REGS_RIP);
3901 vcpu->arch.regs_dirty = ~0;
3902}
3903
95cb2295
GN		 3904static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
3905{
3906 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
3907 /*
3908 * an sti; sti; sequence only disable interrupts for the first
3909 * instruction. So, if the last instruction, be it emulated or
3910 * not, left the system with the INT_STI flag enabled, it
3911 * means that the last instruction is an sti. We should not
3912 * leave the flag on in this case. The same goes for mov ss
3913 */
3914 if (!(int_shadow & mask))
3915 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
3916}
3917
54b8486f
GN		 3918static void inject_emulated_exception(struct kvm_vcpu *vcpu)
3919{
3920 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3921 if (ctxt->exception == PF_VECTOR)
3922 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
3923 else if (ctxt->error_code_valid)
3924 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
3925 else
3926 kvm_queue_exception(vcpu, ctxt->exception);
3927}
3928
6d77dbfc
GN		 3929static int handle_emulation_failure(struct kvm_vcpu *vcpu)
3930{
6d77dbfc
GN		 3931 ++vcpu->stat.insn_emulation_fail;
3932 trace_kvm_emulate_insn_failed(vcpu);
3933 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3934 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3935 vcpu->run->internal.ndata = 0;
3936 kvm_queue_exception(vcpu, UD_VECTOR);
3937 return EMULATE_FAIL;
3938}
3939
a6f177ef
GN		 3940static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
3941{
3942 gpa_t gpa;
3943
68be0803
GN		 3944 if (tdp_enabled)
3945 return false;
3946
a6f177ef
GN		 3947 /*
3948 * if emulation was due to access to shadowed page table
3949 * and it failed try to unshadow page and re-entetr the
3950 * guest to let CPU execute the instruction.
3951 */
3952 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
3953 return true;
3954
3955 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
3956
3957 if (gpa == UNMAPPED_GVA)
3958 return true; /* let cpu generate fault */
3959
3960 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
3961 return true;
3962
3963 return false;
3964}
3965
bbd9b64e 3966int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3967 unsigned long cr2,
3968 u16 error_code,
571008da 3969 int emulation_type)
bbd9b64e 3970{
95cb2295 3971 int r;
4d2179e1 3972 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 3973
26eef70c 3974 kvm_clear_exception_queue(vcpu);
ad312c7c 3975 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3976 /*
56e82318 3977 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3978 * instead of direct ->regs accesses, can save hundred cycles
3979 * on Intel for instructions that don't read/change RSP, for
3980 * for example.
3981 */
3982 cache_all_regs(vcpu);
bbd9b64e 3983
571008da 3984 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3985 int cs_db, cs_l;
3986 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3987
ad312c7c 3988 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3989 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3990 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3991 vcpu->arch.emulate_ctxt.mode =
a0044755 3992 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3993 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3994 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3995 ? X86EMUL_MODE_PROT64 : cs_db
3996 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 3997 memset(c, 0, sizeof(struct decode_cache));
3998 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
95cb2295 3999 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4000 vcpu->arch.emulate_ctxt.exception = -1;
bbd9b64e 4001
ad312c7c 4002 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 4003 trace_kvm_emulate_insn_start(vcpu);
571008da 4004
0cb5762e
AP		 4005 /* Only allow emulation of specific instructions on #UD
4006 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4007 if (emulation_type & EMULTYPE_TRAP_UD) {
4008 if (!c->twobyte)
4009 return EMULATE_FAIL;
4010 switch (c->b) {
4011 case 0x01: /* VMMCALL */
4012 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4013 return EMULATE_FAIL;
4014 break;
4015 case 0x34: /* sysenter */
4016 case 0x35: /* sysexit */
4017 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4018 return EMULATE_FAIL;
4019 break;
4020 case 0x05: /* syscall */
4021 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4022 return EMULATE_FAIL;
4023 break;
4024 default:
4025 return EMULATE_FAIL;
4026 }
4027
4028 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4029 return EMULATE_FAIL;
4030 }
571008da 4031
f2b5756b 4032 ++vcpu->stat.insn_emulation;
bbd9b64e 4033 if (r) {
a6f177ef 4034 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4035 return EMULATE_DONE;
6d77dbfc
GN		 4036 if (emulation_type & EMULTYPE_SKIP)
4037 return EMULATE_FAIL;
4038 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4039 }
4040 }
4041
ba8afb6b
GN		 4042 if (emulation_type & EMULTYPE_SKIP) {
4043 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4044 return EMULATE_DONE;
4045 }
4046
4d2179e1
GN		 4047 /* this is needed for vmware backdor interface to work since it
4048 changes registers values during IO operation */
4049 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4050
5cd21917 4051restart:
ad312c7c 4052 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 4053
c3cd7ffa 4054 if (r) { /* emulation failed */
a6f177ef 4055 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4056 return EMULATE_DONE;
4057
6d77dbfc 4058 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4059 }
4060
95cb2295 4061 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
ef050dc0 4062 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4d2179e1 4063 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 4064 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
3457e419 4065
54b8486f
GN		 4066 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4067 inject_emulated_exception(vcpu);
4068 return EMULATE_DONE;
4069 }
4070
3457e419
GN		 4071 if (vcpu->arch.pio.count) {
4072 if (!vcpu->arch.pio.in)
4073 vcpu->arch.pio.count = 0;
4074 return EMULATE_DO_MMIO;
4075 }
4076
4077 if (vcpu->mmio_needed) {
4078 if (vcpu->mmio_is_write)
4079 vcpu->mmio_needed = 0;
4080 return EMULATE_DO_MMIO;
4081 }
4082
5cd21917
GN		 4083 if (vcpu->arch.emulate_ctxt.restart)
4084 goto restart;
f850e2e6 4085
bbd9b64e 4086 return EMULATE_DONE;
de7d789a 4087}
bbd9b64e 4088EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4089
cf8f70bf 4090int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4091{
cf8f70bf
GN		 4092 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4093 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4094 /* do not return to emulator after return from userspace */
7972995b 4095 vcpu->arch.pio.count = 0;
de7d789a
CO		 4096 return ret;
4097}
cf8f70bf 4098EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4099
c8076604
GH		 4100static void bounce_off(void *info)
4101{
4102 /* nothing */
4103}
4104
c8076604
GH		 4105static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4106 void *data)
4107{
4108 struct cpufreq_freqs *freq = data;
4109 struct kvm *kvm;
4110 struct kvm_vcpu *vcpu;
4111 int i, send_ipi = 0;
4112
c8076604
GH		 4113 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4114 return 0;
4115 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4116 return 0;
0cca7907 4117 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 4118
4119 spin_lock(&kvm_lock);
4120 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4121 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4122 if (vcpu->cpu != freq->cpu)
4123 continue;
4124 if (!kvm_request_guest_time_update(vcpu))
4125 continue;
4126 if (vcpu->cpu != smp_processor_id())
4127 send_ipi++;
4128 }
4129 }
4130 spin_unlock(&kvm_lock);
4131
4132 if (freq->old < freq->new && send_ipi) {
4133 /*
4134 * We upscale the frequency. Must make the guest
4135 * doesn't see old kvmclock values while running with
4136 * the new frequency, otherwise we risk the guest sees
4137 * time go backwards.
4138 *
4139 * In case we update the frequency for another cpu
4140 * (which might be in guest context) send an interrupt
4141 * to kick the cpu out of guest context. Next time
4142 * guest context is entered kvmclock will be updated,
4143 * so the guest will not see stale values.
4144 */
4145 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4146 }
4147 return 0;
4148}
4149
4150static struct notifier_block kvmclock_cpufreq_notifier_block = {
4151 .notifier_call = kvmclock_cpufreq_notifier
4152};
4153
b820cc0c
ZA		 4154static void kvm_timer_init(void)
4155{
4156 int cpu;
4157
b820cc0c 4158 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4159 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4160 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4161 for_each_online_cpu(cpu) {
4162 unsigned long khz = cpufreq_get(cpu);
4163 if (!khz)
4164 khz = tsc_khz;
4165 per_cpu(cpu_tsc_khz, cpu) = khz;
4166 }
0cca7907
ZA		 4167 } else {
4168 for_each_possible_cpu(cpu)
4169 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4170 }
4171}
4172
ff9d07a0
ZY		 4173static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4174
4175static int kvm_is_in_guest(void)
4176{
4177 return percpu_read(current_vcpu) != NULL;
4178}
4179
4180static int kvm_is_user_mode(void)
4181{
4182 int user_mode = 3;
dcf46b94 4183
ff9d07a0
ZY		 4184 if (percpu_read(current_vcpu))
4185 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4186
ff9d07a0
ZY		 4187 return user_mode != 0;
4188}
4189
4190static unsigned long kvm_get_guest_ip(void)
4191{
4192 unsigned long ip = 0;
dcf46b94 4193
ff9d07a0
ZY		 4194 if (percpu_read(current_vcpu))
4195 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4196
ff9d07a0
ZY		 4197 return ip;
4198}
4199
4200static struct perf_guest_info_callbacks kvm_guest_cbs = {
4201 .is_in_guest = kvm_is_in_guest,
4202 .is_user_mode = kvm_is_user_mode,
4203 .get_guest_ip = kvm_get_guest_ip,
4204};
4205
4206void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4207{
4208 percpu_write(current_vcpu, vcpu);
4209}
4210EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4211
4212void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4213{
4214 percpu_write(current_vcpu, NULL);
4215}
4216EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4217
f8c16bba 4218int kvm_arch_init(void *opaque)
043405e1 4219{
b820cc0c 4220 int r;
f8c16bba
ZX		 4221 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4222
f8c16bba
ZX		 4223 if (kvm_x86_ops) {
4224 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4225 r = -EEXIST;
4226 goto out;
f8c16bba
ZX		 4227 }
4228
4229 if (!ops->cpu_has_kvm_support()) {
4230 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4231 r = -EOPNOTSUPP;
4232 goto out;
f8c16bba
ZX		 4233 }
4234 if (ops->disabled_by_bios()) {
4235 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4236 r = -EOPNOTSUPP;
4237 goto out;
f8c16bba
ZX		 4238 }
4239
97db56ce
AK		 4240 r = kvm_mmu_module_init();
4241 if (r)
4242 goto out;
4243
4244 kvm_init_msr_list();
4245
f8c16bba 4246 kvm_x86_ops = ops;
56c6d28a 4247 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4248 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4249 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4250 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4251
b820cc0c 4252 kvm_timer_init();
c8076604 4253
ff9d07a0
ZY		 4254 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4255
2acf923e
DC		 4256 if (cpu_has_xsave)
4257 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4258
f8c16bba 4259 return 0;
56c6d28a
ZX		 4260
4261out:
56c6d28a 4262 return r;
043405e1 4263}
8776e519 4264
f8c16bba
ZX		 4265void kvm_arch_exit(void)
4266{
ff9d07a0
ZY		 4267 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4268
888d256e
JK		 4269 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4270 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4271 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4272 kvm_x86_ops = NULL;
56c6d28a
ZX		 4273 kvm_mmu_module_exit();
4274}
f8c16bba 4275
8776e519
HB		 4276int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4277{
4278 ++vcpu->stat.halt_exits;
4279 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4280 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4281 return 1;
4282 } else {
4283 vcpu->run->exit_reason = KVM_EXIT_HLT;
4284 return 0;
4285 }
4286}
4287EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4288
2f333bcb
MT		 4289static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4290 unsigned long a1)
4291{
4292 if (is_long_mode(vcpu))
4293 return a0;
4294 else
4295 return a0 | ((gpa_t)a1 << 32);
4296}
4297
55cd8e5a
GN		 4298int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4299{
4300 u64 param, ingpa, outgpa, ret;
4301 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4302 bool fast, longmode;
4303 int cs_db, cs_l;
4304
4305 /*
4306 * hypercall generates UD from non zero cpl and real mode
4307 * per HYPER-V spec
4308 */
3eeb3288 4309 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4310 kvm_queue_exception(vcpu, UD_VECTOR);
4311 return 0;
4312 }
4313
4314 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4315 longmode = is_long_mode(vcpu) && cs_l == 1;
4316
4317 if (!longmode) {
ccd46936
GN		 4318 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4319 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4320 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4321 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4322 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4323 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4324 }
4325#ifdef CONFIG_X86_64
4326 else {
4327 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4328 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4329 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4330 }
4331#endif
4332
4333 code = param & 0xffff;
4334 fast = (param >> 16) & 0x1;
4335 rep_cnt = (param >> 32) & 0xfff;
4336 rep_idx = (param >> 48) & 0xfff;
4337
4338 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4339
c25bc163
GN		 4340 switch (code) {
4341 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4342 kvm_vcpu_on_spin(vcpu);
4343 break;
4344 default:
4345 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4346 break;
4347 }
55cd8e5a
GN		 4348
4349 ret = res | (((u64)rep_done & 0xfff) << 32);
4350 if (longmode) {
4351 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4352 } else {
4353 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4354 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4355 }
4356
4357 return 1;
4358}
4359
8776e519
HB		 4360int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4361{
4362 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4363 int r = 1;
8776e519 4364
55cd8e5a
GN		 4365 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4366 return kvm_hv_hypercall(vcpu);
4367
5fdbf976
MT		 4368 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4369 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4370 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4371 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4372 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4373
229456fc 4374 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4375
8776e519
HB		 4376 if (!is_long_mode(vcpu)) {
4377 nr &= 0xFFFFFFFF;
4378 a0 &= 0xFFFFFFFF;
4379 a1 &= 0xFFFFFFFF;
4380 a2 &= 0xFFFFFFFF;
4381 a3 &= 0xFFFFFFFF;
4382 }
4383
07708c4a
JK		 4384 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4385 ret = -KVM_EPERM;
4386 goto out;
4387 }
4388
8776e519 4389 switch (nr) {
b93463aa
AK		 4390 case KVM_HC_VAPIC_POLL_IRQ:
4391 ret = 0;
4392 break;
2f333bcb
MT		 4393 case KVM_HC_MMU_OP:
4394 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4395 break;
8776e519
HB		 4396 default:
4397 ret = -KVM_ENOSYS;
4398 break;
4399 }
07708c4a 4400out:
5fdbf976 4401 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4402 ++vcpu->stat.hypercalls;
2f333bcb 4403 return r;
8776e519
HB		 4404}
4405EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4406
4407int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4408{
4409 char instruction[3];
5fdbf976 4410 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4411
8776e519
HB		 4412 /*
4413 * Blow out the MMU to ensure that no other VCPU has an active mapping
4414 * to ensure that the updated hypercall appears atomically across all
4415 * VCPUs.
4416 */
4417 kvm_mmu_zap_all(vcpu->kvm);
4418
8776e519 4419 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4420
8fe681e9 4421 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4422}
4423
8776e519
HB		 4424void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4425{
89a27f4d 4426 struct desc_ptr dt = { limit, base };
8776e519
HB		 4427
4428 kvm_x86_ops->set_gdt(vcpu, &dt);
4429}
4430
4431void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4432{
89a27f4d 4433 struct desc_ptr dt = { limit, base };
8776e519
HB		 4434
4435 kvm_x86_ops->set_idt(vcpu, &dt);
4436}
4437
07716717
DK		 4438static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4439{
ad312c7c
ZX		 4440 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4441 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4442
4443 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4444 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4445 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4446 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4447 if (ej->function == e->function) {
4448 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4449 return j;
4450 }
4451 }
4452 return 0; /* silence gcc, even though control never reaches here */
4453}
4454
4455/* find an entry with matching function, matching index (if needed), and that
4456 * should be read next (if it's stateful) */
4457static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4458 u32 function, u32 index)
4459{
4460 if (e->function != function)
4461 return 0;
4462 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4463 return 0;
4464 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4465 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4466 return 0;
4467 return 1;
4468}
4469
d8017474
AG		 4470struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4471 u32 function, u32 index)
8776e519
HB		 4472{
4473 int i;
d8017474 4474 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4475
ad312c7c 4476 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4477 struct kvm_cpuid_entry2 *e;
4478
ad312c7c 4479 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4480 if (is_matching_cpuid_entry(e, function, index)) {
4481 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4482 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4483 best = e;
4484 break;
4485 }
4486 /*
4487 * Both basic or both extended?
4488 */
4489 if (((e->function ^ function) & 0x80000000) == 0)
4490 if (!best || e->function > best->function)
4491 best = e;
4492 }
d8017474
AG		 4493 return best;
4494}
0e851880 4495EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4496
82725b20
DE		 4497int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4498{
4499 struct kvm_cpuid_entry2 *best;
4500
f7a71197
AK		 4501 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4502 if (!best || best->eax < 0x80000008)
4503 goto not_found;
82725b20
DE		 4504 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4505 if (best)
4506 return best->eax & 0xff;
f7a71197 4507not_found:
82725b20
DE		 4508 return 36;
4509}
4510
d8017474
AG		 4511void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4512{
4513 u32 function, index;
4514 struct kvm_cpuid_entry2 *best;
4515
4516 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4517 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4518 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4519 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4520 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4521 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4522 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4523 if (best) {
5fdbf976
MT		 4524 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4525 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4526 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4527 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4528 }
8776e519 4529 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4530 trace_kvm_cpuid(function,
4531 kvm_register_read(vcpu, VCPU_REGS_RAX),
4532 kvm_register_read(vcpu, VCPU_REGS_RBX),
4533 kvm_register_read(vcpu, VCPU_REGS_RCX),
4534 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4535}
4536EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4537
b6c7a5dc
HB		 4538/*
4539 * Check if userspace requested an interrupt window, and that the
4540 * interrupt window is open.
4541 *
4542 * No need to exit to userspace if we already have an interrupt queued.
4543 */
851ba692 4544static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4545{
8061823a 4546 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4547 vcpu->run->request_interrupt_window &&
5df56646 4548 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4549}
4550
851ba692 4551static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4552{
851ba692
AK		 4553 struct kvm_run *kvm_run = vcpu->run;
4554
91586a3b 4555 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4556 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4557 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4558 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4559 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4560 else
b6c7a5dc 4561 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4562 kvm_arch_interrupt_allowed(vcpu) &&
4563 !kvm_cpu_has_interrupt(vcpu) &&
4564 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4565}
4566
b93463aa
AK		 4567static void vapic_enter(struct kvm_vcpu *vcpu)
4568{
4569 struct kvm_lapic *apic = vcpu->arch.apic;
4570 struct page *page;
4571
4572 if (!apic || !apic->vapic_addr)
4573 return;
4574
4575 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4576
4577 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4578}
4579
4580static void vapic_exit(struct kvm_vcpu *vcpu)
4581{
4582 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4583 int idx;
b93463aa
AK		 4584
4585 if (!apic || !apic->vapic_addr)
4586 return;
4587
f656ce01 4588 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4589 kvm_release_page_dirty(apic->vapic_page);
4590 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4591 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4592}
4593
95ba8273
GN		 4594static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4595{
4596 int max_irr, tpr;
4597
4598 if (!kvm_x86_ops->update_cr8_intercept)
4599 return;
4600
88c808fd
AK		 4601 if (!vcpu->arch.apic)
4602 return;
4603
8db3baa2
GN		 4604 if (!vcpu->arch.apic->vapic_addr)
4605 max_irr = kvm_lapic_find_highest_irr(vcpu);
4606 else
4607 max_irr = -1;
95ba8273
GN		 4608
4609 if (max_irr != -1)
4610 max_irr >>= 4;
4611
4612 tpr = kvm_lapic_get_cr8(vcpu);
4613
4614 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4615}
4616
851ba692 4617static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4618{
4619 /* try to reinject previous events if any */
b59bb7bd 4620 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4621 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4622 vcpu->arch.exception.has_error_code,
4623 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4624 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4625 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4626 vcpu->arch.exception.error_code,
4627 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4628 return;
4629 }
4630
95ba8273
GN		 4631 if (vcpu->arch.nmi_injected) {
4632 kvm_x86_ops->set_nmi(vcpu);
4633 return;
4634 }
4635
4636 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4637 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4638 return;
4639 }
4640
4641 /* try to inject new event if pending */
4642 if (vcpu->arch.nmi_pending) {
4643 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4644 vcpu->arch.nmi_pending = false;
4645 vcpu->arch.nmi_injected = true;
4646 kvm_x86_ops->set_nmi(vcpu);
4647 }
4648 } else if (kvm_cpu_has_interrupt(vcpu)) {
4649 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4650 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4651 false);
4652 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4653 }
4654 }
4655}
4656
2acf923e
DC		 4657static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4658{
4659 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4660 !vcpu->guest_xcr0_loaded) {
4661 /* kvm_set_xcr() also depends on this */
4662 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4663 vcpu->guest_xcr0_loaded = 1;
4664 }
4665}
4666
4667static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4668{
4669 if (vcpu->guest_xcr0_loaded) {
4670 if (vcpu->arch.xcr0 != host_xcr0)
4671 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4672 vcpu->guest_xcr0_loaded = 0;
4673 }
4674}
4675
851ba692 4676static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4677{
4678 int r;
6a8b1d13 4679 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4680 vcpu->run->request_interrupt_window;
b6c7a5dc 4681
3e007509 4682 if (vcpu->requests) {
a8eeb04a 4683 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4684 kvm_mmu_unload(vcpu);
a8eeb04a 4685 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4686 __kvm_migrate_timers(vcpu);
a8eeb04a 4687 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu))
c8076604 4688 kvm_write_guest_time(vcpu);
a8eeb04a 4689 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4690 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4691 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4692 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4693 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4694 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4695 r = 0;
4696 goto out;
4697 }
a8eeb04a 4698 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 4699 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4700 r = 0;
4701 goto out;
4702 }
a8eeb04a 4703 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 4704 vcpu->fpu_active = 0;
4705 kvm_x86_ops->fpu_deactivate(vcpu);
4706 }
2f52d58c 4707 }
b93463aa 4708
3e007509
AK		 4709 r = kvm_mmu_reload(vcpu);
4710 if (unlikely(r))
4711 goto out;
4712
b6c7a5dc
HB		 4713 preempt_disable();
4714
4715 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4716 if (vcpu->fpu_active)
4717 kvm_load_guest_fpu(vcpu);
2acf923e 4718 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4719
d94e1dc9
AK		 4720 atomic_set(&vcpu->guest_mode, 1);
4721 smp_wmb();
b6c7a5dc 4722
d94e1dc9 4723 local_irq_disable();
32f88400 4724
d94e1dc9
AK		 4725 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4726 || need_resched() || signal_pending(current)) {
4727 atomic_set(&vcpu->guest_mode, 0);
4728 smp_wmb();
6c142801
AK		 4729 local_irq_enable();
4730 preempt_enable();
4731 r = 1;
4732 goto out;
4733 }
4734
851ba692 4735 inject_pending_event(vcpu);
b6c7a5dc 4736
6a8b1d13
GN		 4737 /* enable NMI/IRQ window open exits if needed */
4738 if (vcpu->arch.nmi_pending)
4739 kvm_x86_ops->enable_nmi_window(vcpu);
4740 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4741 kvm_x86_ops->enable_irq_window(vcpu);
4742
95ba8273 4743 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4744 update_cr8_intercept(vcpu);
4745 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4746 }
b93463aa 4747
f656ce01 4748 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4749
b6c7a5dc
HB		 4750 kvm_guest_enter();
4751
42dbaa5a 4752 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4753 set_debugreg(0, 7);
4754 set_debugreg(vcpu->arch.eff_db[0], 0);
4755 set_debugreg(vcpu->arch.eff_db[1], 1);
4756 set_debugreg(vcpu->arch.eff_db[2], 2);
4757 set_debugreg(vcpu->arch.eff_db[3], 3);
4758 }
b6c7a5dc 4759
229456fc 4760 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4761 kvm_x86_ops->run(vcpu);
b6c7a5dc 4762
24f1e32c
FW		 4763 /*
4764 * If the guest has used debug registers, at least dr7
4765 * will be disabled while returning to the host.
4766 * If we don't have active breakpoints in the host, we don't
4767 * care about the messed up debug address registers. But if
4768 * we have some of them active, restore the old state.
4769 */
59d8eb53 4770 if (hw_breakpoint_active())
24f1e32c 4771 hw_breakpoint_restore();
42dbaa5a 4772
d94e1dc9
AK		 4773 atomic_set(&vcpu->guest_mode, 0);
4774 smp_wmb();
b6c7a5dc
HB		 4775 local_irq_enable();
4776
4777 ++vcpu->stat.exits;
4778
4779 /*
4780 * We must have an instruction between local_irq_enable() and
4781 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4782 * the interrupt shadow. The stat.exits increment will do nicely.
4783 * But we need to prevent reordering, hence this barrier():
4784 */
4785 barrier();
4786
4787 kvm_guest_exit();
4788
4789 preempt_enable();
4790
f656ce01 4791 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4792
b6c7a5dc
HB		 4793 /*
4794 * Profile KVM exit RIPs:
4795 */
4796 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4797 unsigned long rip = kvm_rip_read(vcpu);
4798 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4799 }
4800
298101da 4801
b93463aa
AK		 4802 kvm_lapic_sync_from_vapic(vcpu);
4803
851ba692 4804 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4805out:
4806 return r;
4807}
b6c7a5dc 4808
09cec754 4809
851ba692 4810static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4811{
4812 int r;
f656ce01 4813 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4814
4815 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4816 pr_debug("vcpu %d received sipi with vector # %x\n",
4817 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4818 kvm_lapic_reset(vcpu);
5f179287 4819 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4820 if (r)
4821 return r;
4822 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4823 }
4824
f656ce01 4825 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4826 vapic_enter(vcpu);
4827
4828 r = 1;
4829 while (r > 0) {
af2152f5 4830 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4831 r = vcpu_enter_guest(vcpu);
d7690175 4832 else {
f656ce01 4833 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4834 kvm_vcpu_block(vcpu);
f656ce01 4835 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 4836 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 4837 {
4838 switch(vcpu->arch.mp_state) {
4839 case KVM_MP_STATE_HALTED:
d7690175 4840 vcpu->arch.mp_state =
09cec754
GN		 4841 KVM_MP_STATE_RUNNABLE;
4842 case KVM_MP_STATE_RUNNABLE:
4843 break;
4844 case KVM_MP_STATE_SIPI_RECEIVED:
4845 default:
4846 r = -EINTR;
4847 break;
4848 }
4849 }
d7690175
MT		 4850 }
4851
09cec754
GN		 4852 if (r <= 0)
4853 break;
4854
4855 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4856 if (kvm_cpu_has_pending_timer(vcpu))
4857 kvm_inject_pending_timer_irqs(vcpu);
4858
851ba692 4859 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4860 r = -EINTR;
851ba692 4861 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4862 ++vcpu->stat.request_irq_exits;
4863 }
4864 if (signal_pending(current)) {
4865 r = -EINTR;
851ba692 4866 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4867 ++vcpu->stat.signal_exits;
4868 }
4869 if (need_resched()) {
f656ce01 4870 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4871 kvm_resched(vcpu);
f656ce01 4872 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4873 }
b6c7a5dc
HB		 4874 }
4875
f656ce01 4876 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4877
b93463aa
AK		 4878 vapic_exit(vcpu);
4879
b6c7a5dc
HB		 4880 return r;
4881}
4882
4883int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4884{
4885 int r;
4886 sigset_t sigsaved;
4887
ac9f6dc0
AK		 4888 if (vcpu->sigset_active)
4889 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4890
a4535290 4891 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4892 kvm_vcpu_block(vcpu);
d7690175 4893 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4894 r = -EAGAIN;
4895 goto out;
b6c7a5dc
HB		 4896 }
4897
b6c7a5dc
HB		 4898 /* re-sync apic's tpr */
4899 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4900 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4901
92bf9748
GN		 4902 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4903 vcpu->arch.emulate_ctxt.restart) {
4904 if (vcpu->mmio_needed) {
4905 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4906 vcpu->mmio_read_completed = 1;
4907 vcpu->mmio_needed = 0;
b6c7a5dc 4908 }
f656ce01 4909 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4910 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4911 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 4912 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 4913 r = 0;
4914 goto out;
4915 }
4916 }
5fdbf976
MT		 4917 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4918 kvm_register_write(vcpu, VCPU_REGS_RAX,
4919 kvm_run->hypercall.ret);
b6c7a5dc 4920
851ba692 4921 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4922
4923out:
f1d86e46 4924 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4925 if (vcpu->sigset_active)
4926 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4927
b6c7a5dc
HB		 4928 return r;
4929}
4930
4931int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4932{
5fdbf976
MT		 4933 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4934 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4935 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4936 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4937 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4938 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4939 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4940 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4941#ifdef CONFIG_X86_64
5fdbf976
MT		 4942 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4943 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4944 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4945 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4946 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4947 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4948 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4949 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4950#endif
4951
5fdbf976 4952 regs->rip = kvm_rip_read(vcpu);
91586a3b 4953 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 4954
b6c7a5dc
HB		 4955 return 0;
4956}
4957
4958int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4959{
5fdbf976
MT		 4960 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4961 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4962 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4963 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4964 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4965 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4966 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4967 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4968#ifdef CONFIG_X86_64
5fdbf976
MT		 4969 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4970 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4971 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4972 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4973 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4974 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4975 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4976 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4977#endif
4978
5fdbf976 4979 kvm_rip_write(vcpu, regs->rip);
91586a3b 4980 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4981
b4f14abd
JK		 4982 vcpu->arch.exception.pending = false;
4983
b6c7a5dc
HB		 4984 return 0;
4985}
4986
b6c7a5dc
HB		 4987void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4988{
4989 struct kvm_segment cs;
4990
3e6e0aab 4991 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4992 *db = cs.db;
4993 *l = cs.l;
4994}
4995EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4996
4997int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4998 struct kvm_sregs *sregs)
4999{
89a27f4d 5000 struct desc_ptr dt;
b6c7a5dc 5001
3e6e0aab
GT		 5002 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5003 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5004 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5005 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5006 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5007 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5008
3e6e0aab
GT		 5009 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5010 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5011
5012 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5013 sregs->idt.limit = dt.size;
5014 sregs->idt.base = dt.address;
b6c7a5dc 5015 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5016 sregs->gdt.limit = dt.size;
5017 sregs->gdt.base = dt.address;
b6c7a5dc 5018
4d4ec087 5019 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5020 sregs->cr2 = vcpu->arch.cr2;
5021 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5022 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5023 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5024 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5025 sregs->apic_base = kvm_get_apic_base(vcpu);
5026
923c61bb 5027 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5028
36752c9b 5029 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5030 set_bit(vcpu->arch.interrupt.nr,
5031 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5032
b6c7a5dc
HB		 5033 return 0;
5034}
5035
62d9f0db
MT		 5036int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5037 struct kvm_mp_state *mp_state)
5038{
62d9f0db 5039 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5040 return 0;
5041}
5042
5043int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5044 struct kvm_mp_state *mp_state)
5045{
62d9f0db 5046 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5047 return 0;
5048}
5049
e269fb21
JK		 5050int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5051 bool has_error_code, u32 error_code)
b6c7a5dc 5052{
4d2179e1 5053 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
ceffb459
GN		 5054 int cs_db, cs_l, ret;
5055 cache_all_regs(vcpu);
37817f29 5056
ceffb459 5057 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 5058
ceffb459
GN		 5059 vcpu->arch.emulate_ctxt.vcpu = vcpu;
5060 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
5061 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
5062 vcpu->arch.emulate_ctxt.mode =
5063 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5064 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
5065 ? X86EMUL_MODE_VM86 : cs_l
5066 ? X86EMUL_MODE_PROT64 : cs_db
5067 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 5068 memset(c, 0, sizeof(struct decode_cache));
5069 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
c697518a 5070
ceffb459 5071 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 5072 tss_selector, reason, has_error_code,
5073 error_code);
c697518a 5074
c697518a 5075 if (ret)
19d04437 5076 return EMULATE_FAIL;
37817f29 5077
4d2179e1 5078 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5079 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5080 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5081 return EMULATE_DONE;
37817f29
IE		 5082}
5083EXPORT_SYMBOL_GPL(kvm_task_switch);
5084
b6c7a5dc
HB		 5085int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5086 struct kvm_sregs *sregs)
5087{
5088 int mmu_reset_needed = 0;
923c61bb 5089 int pending_vec, max_bits;
89a27f4d 5090 struct desc_ptr dt;
b6c7a5dc 5091
89a27f4d
GN		 5092 dt.size = sregs->idt.limit;
5093 dt.address = sregs->idt.base;
b6c7a5dc 5094 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5095 dt.size = sregs->gdt.limit;
5096 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5097 kvm_x86_ops->set_gdt(vcpu, &dt);
5098
ad312c7c
ZX		 5099 vcpu->arch.cr2 = sregs->cr2;
5100 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5101 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5102
2d3ad1f4 5103 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5104
f6801dff 5105 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5106 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5107 kvm_set_apic_base(vcpu, sregs->apic_base);
5108
4d4ec087 5109 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5110 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5111 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5112
fc78f519 5113 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5114 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5115 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5116 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5117 mmu_reset_needed = 1;
5118 }
b6c7a5dc
HB		 5119
5120 if (mmu_reset_needed)
5121 kvm_mmu_reset_context(vcpu);
5122
923c61bb
GN		 5123 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5124 pending_vec = find_first_bit(
5125 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5126 if (pending_vec < max_bits) {
66fd3f7f 5127 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5128 pr_debug("Set back pending irq %d\n", pending_vec);
5129 if (irqchip_in_kernel(vcpu->kvm))
5130 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5131 }
5132
3e6e0aab
GT		 5133 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5134 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5135 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5136 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5137 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5138 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5139
3e6e0aab
GT		 5140 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5141 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5142
5f0269f5
ME		 5143 update_cr8_intercept(vcpu);
5144
9c3e4aab 5145 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5146 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5147 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5148 !is_protmode(vcpu))
9c3e4aab
MT		 5149 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5150
b6c7a5dc
HB		 5151 return 0;
5152}
5153
d0bfb940
JK		 5154int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5155 struct kvm_guest_debug *dbg)
b6c7a5dc 5156{
355be0b9 5157 unsigned long rflags;
ae675ef0 5158 int i, r;
b6c7a5dc 5159
4f926bf2
JK		 5160 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5161 r = -EBUSY;
5162 if (vcpu->arch.exception.pending)
2122ff5e 5163 goto out;
4f926bf2
JK		 5164 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5165 kvm_queue_exception(vcpu, DB_VECTOR);
5166 else
5167 kvm_queue_exception(vcpu, BP_VECTOR);
5168 }
5169
91586a3b
JK		 5170 /*
5171 * Read rflags as long as potentially injected trace flags are still
5172 * filtered out.
5173 */
5174 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5175
5176 vcpu->guest_debug = dbg->control;
5177 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5178 vcpu->guest_debug = 0;
5179
5180 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5181 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5182 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5183 vcpu->arch.switch_db_regs =
5184 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5185 } else {
5186 for (i = 0; i < KVM_NR_DB_REGS; i++)
5187 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5188 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5189 }
5190
f92653ee
JK		 5191 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5192 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5193 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5194
91586a3b
JK		 5195 /*
5196 * Trigger an rflags update that will inject or remove the trace
5197 * flags.
5198 */
5199 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5200
355be0b9 5201 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5202
4f926bf2 5203 r = 0;
d0bfb940 5204
2122ff5e 5205out:
b6c7a5dc
HB		 5206
5207 return r;
5208}
5209
8b006791
ZX		 5210/*
5211 * Translate a guest virtual address to a guest physical address.
5212 */
5213int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5214 struct kvm_translation *tr)
5215{
5216 unsigned long vaddr = tr->linear_address;
5217 gpa_t gpa;
f656ce01 5218 int idx;
8b006791 5219
f656ce01 5220 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5221 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5222 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5223 tr->physical_address = gpa;
5224 tr->valid = gpa != UNMAPPED_GVA;
5225 tr->writeable = 1;
5226 tr->usermode = 0;
8b006791
ZX		 5227
5228 return 0;
5229}
5230
d0752060
HB		 5231int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5232{
98918833
SY		 5233 struct i387_fxsave_struct *fxsave =
5234 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5235
d0752060
HB		 5236 memcpy(fpu->fpr, fxsave->st_space, 128);
5237 fpu->fcw = fxsave->cwd;
5238 fpu->fsw = fxsave->swd;
5239 fpu->ftwx = fxsave->twd;
5240 fpu->last_opcode = fxsave->fop;
5241 fpu->last_ip = fxsave->rip;
5242 fpu->last_dp = fxsave->rdp;
5243 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5244
d0752060
HB		 5245 return 0;
5246}
5247
5248int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5249{
98918833
SY		 5250 struct i387_fxsave_struct *fxsave =
5251 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5252
d0752060
HB		 5253 memcpy(fxsave->st_space, fpu->fpr, 128);
5254 fxsave->cwd = fpu->fcw;
5255 fxsave->swd = fpu->fsw;
5256 fxsave->twd = fpu->ftwx;
5257 fxsave->fop = fpu->last_opcode;
5258 fxsave->rip = fpu->last_ip;
5259 fxsave->rdp = fpu->last_dp;
5260 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5261
d0752060
HB		 5262 return 0;
5263}
5264
10ab25cd 5265int fx_init(struct kvm_vcpu *vcpu)
d0752060 5266{
10ab25cd
JK		 5267 int err;
5268
5269 err = fpu_alloc(&vcpu->arch.guest_fpu);
5270 if (err)
5271 return err;
5272
98918833 5273 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5274
2acf923e
DC		 5275 /*
5276 * Ensure guest xcr0 is valid for loading
5277 */
5278 vcpu->arch.xcr0 = XSTATE_FP;
5279
ad312c7c 5280 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5281
5282 return 0;
d0752060
HB		 5283}
5284EXPORT_SYMBOL_GPL(fx_init);
5285
98918833
SY		 5286static void fx_free(struct kvm_vcpu *vcpu)
5287{
5288 fpu_free(&vcpu->arch.guest_fpu);
5289}
5290
d0752060
HB		 5291void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5292{
2608d7a1 5293 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5294 return;
5295
2acf923e
DC		 5296 /*
5297 * Restore all possible states in the guest,
5298 * and assume host would use all available bits.
5299 * Guest xcr0 would be loaded later.
5300 */
5301 kvm_put_guest_xcr0(vcpu);
d0752060 5302 vcpu->guest_fpu_loaded = 1;
7cf30855 5303 unlazy_fpu(current);
98918833 5304 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5305 trace_kvm_fpu(1);
d0752060 5306}
d0752060
HB		 5307
5308void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5309{
2acf923e
DC		 5310 kvm_put_guest_xcr0(vcpu);
5311
d0752060
HB		 5312 if (!vcpu->guest_fpu_loaded)
5313 return;
5314
5315 vcpu->guest_fpu_loaded = 0;
98918833 5316 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5317 ++vcpu->stat.fpu_reload;
a8eeb04a 5318 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5319 trace_kvm_fpu(0);
d0752060 5320}
e9b11c17
ZX		 5321
5322void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5323{
7f1ea208
JR		 5324 if (vcpu->arch.time_page) {
5325 kvm_release_page_dirty(vcpu->arch.time_page);
5326 vcpu->arch.time_page = NULL;
5327 }
5328
f5f48ee1 5329 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5330 fx_free(vcpu);
e9b11c17
ZX		 5331 kvm_x86_ops->vcpu_free(vcpu);
5332}
5333
5334struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5335 unsigned int id)
5336{
26e5215f
AK		 5337 return kvm_x86_ops->vcpu_create(kvm, id);
5338}
e9b11c17 5339
26e5215f
AK		 5340int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5341{
5342 int r;
e9b11c17 5343
0bed3b56 5344 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5345 vcpu_load(vcpu);
5346 r = kvm_arch_vcpu_reset(vcpu);
5347 if (r == 0)
5348 r = kvm_mmu_setup(vcpu);
5349 vcpu_put(vcpu);
5350 if (r < 0)
5351 goto free_vcpu;
5352
26e5215f 5353 return 0;
e9b11c17
ZX		 5354free_vcpu:
5355 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5356 return r;
e9b11c17
ZX		 5357}
5358
d40ccc62 5359void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5360{
5361 vcpu_load(vcpu);
5362 kvm_mmu_unload(vcpu);
5363 vcpu_put(vcpu);
5364
98918833 5365 fx_free(vcpu);
e9b11c17
ZX		 5366 kvm_x86_ops->vcpu_free(vcpu);
5367}
5368
5369int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5370{
448fa4a9
JK		 5371 vcpu->arch.nmi_pending = false;
5372 vcpu->arch.nmi_injected = false;
5373
42dbaa5a
JK		 5374 vcpu->arch.switch_db_regs = 0;
5375 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5376 vcpu->arch.dr6 = DR6_FIXED_1;
5377 vcpu->arch.dr7 = DR7_FIXED_1;
5378
e9b11c17
ZX		 5379 return kvm_x86_ops->vcpu_reset(vcpu);
5380}
5381
10474ae8 5382int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5383{
0cca7907
ZA		 5384 /*
5385 * Since this may be called from a hotplug notifcation,
5386 * we can't get the CPU frequency directly.
5387 */
5388 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5389 int cpu = raw_smp_processor_id();
5390 per_cpu(cpu_tsc_khz, cpu) = 0;
5391 }
18863bdd
AK		 5392
5393 kvm_shared_msr_cpu_online();
5394
10474ae8 5395 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5396}
5397
5398void kvm_arch_hardware_disable(void *garbage)
5399{
5400 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5401 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5402}
5403
5404int kvm_arch_hardware_setup(void)
5405{
5406 return kvm_x86_ops->hardware_setup();
5407}
5408
5409void kvm_arch_hardware_unsetup(void)
5410{
5411 kvm_x86_ops->hardware_unsetup();
5412}
5413
5414void kvm_arch_check_processor_compat(void *rtn)
5415{
5416 kvm_x86_ops->check_processor_compatibility(rtn);
5417}
5418
5419int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5420{
5421 struct page *page;
5422 struct kvm *kvm;
5423 int r;
5424
5425 BUG_ON(vcpu->kvm == NULL);
5426 kvm = vcpu->kvm;
5427
ad312c7c 5428 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5429 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5430 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5431 else
a4535290 5432 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5433
5434 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5435 if (!page) {
5436 r = -ENOMEM;
5437 goto fail;
5438 }
ad312c7c 5439 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5440
5441 r = kvm_mmu_create(vcpu);
5442 if (r < 0)
5443 goto fail_free_pio_data;
5444
5445 if (irqchip_in_kernel(kvm)) {
5446 r = kvm_create_lapic(vcpu);
5447 if (r < 0)
5448 goto fail_mmu_destroy;
5449 }
5450
890ca9ae
HY		 5451 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5452 GFP_KERNEL);
5453 if (!vcpu->arch.mce_banks) {
5454 r = -ENOMEM;
443c39bc 5455 goto fail_free_lapic;
890ca9ae
HY		 5456 }
5457 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5458
f5f48ee1
SY		 5459 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5460 goto fail_free_mce_banks;
5461
e9b11c17 5462 return 0;
f5f48ee1
SY		 5463fail_free_mce_banks:
5464 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5465fail_free_lapic:
5466 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5467fail_mmu_destroy:
5468 kvm_mmu_destroy(vcpu);
5469fail_free_pio_data:
ad312c7c 5470 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5471fail:
5472 return r;
5473}
5474
5475void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5476{
f656ce01
MT		 5477 int idx;
5478
36cb93fd 5479 kfree(vcpu->arch.mce_banks);
e9b11c17 5480 kvm_free_lapic(vcpu);
f656ce01 5481 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5482 kvm_mmu_destroy(vcpu);
f656ce01 5483 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5484 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5485}
d19a9cd2
ZX		 5486
5487struct kvm *kvm_arch_create_vm(void)
5488{
5489 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5490
5491 if (!kvm)
5492 return ERR_PTR(-ENOMEM);
5493
f05e70ac 5494 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5495 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5496
5550af4d
SY		 5497 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5498 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5499
53f658b3
MT		 5500 rdtscll(kvm->arch.vm_init_tsc);
5501
d19a9cd2
ZX		 5502 return kvm;
5503}
5504
5505static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5506{
5507 vcpu_load(vcpu);
5508 kvm_mmu_unload(vcpu);
5509 vcpu_put(vcpu);
5510}
5511
5512static void kvm_free_vcpus(struct kvm *kvm)
5513{
5514 unsigned int i;
988a2cae 5515 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5516
5517 /*
5518 * Unpin any mmu pages first.
5519 */
988a2cae
GN		 5520 kvm_for_each_vcpu(i, vcpu, kvm)
5521 kvm_unload_vcpu_mmu(vcpu);
5522 kvm_for_each_vcpu(i, vcpu, kvm)
5523 kvm_arch_vcpu_free(vcpu);
5524
5525 mutex_lock(&kvm->lock);
5526 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5527 kvm->vcpus[i] = NULL;
d19a9cd2 5528
988a2cae
GN		 5529 atomic_set(&kvm->online_vcpus, 0);
5530 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5531}
5532
ad8ba2cd
SY		 5533void kvm_arch_sync_events(struct kvm *kvm)
5534{
ba4cef31 5535 kvm_free_all_assigned_devices(kvm);
aea924f6 5536 kvm_free_pit(kvm);
ad8ba2cd
SY		 5537}
5538
d19a9cd2
ZX		 5539void kvm_arch_destroy_vm(struct kvm *kvm)
5540{
6eb55818 5541 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5542 kfree(kvm->arch.vpic);
5543 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5544 kvm_free_vcpus(kvm);
5545 kvm_free_physmem(kvm);
3d45830c
AK		 5546 if (kvm->arch.apic_access_page)
5547 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5548 if (kvm->arch.ept_identity_pagetable)
5549 put_page(kvm->arch.ept_identity_pagetable);
64749204 5550 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5551 kfree(kvm);
5552}
0de10343 5553
f7784b8e
MT		 5554int kvm_arch_prepare_memory_region(struct kvm *kvm,
5555 struct kvm_memory_slot *memslot,
0de10343 5556 struct kvm_memory_slot old,
f7784b8e 5557 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5558 int user_alloc)
5559{
f7784b8e 5560 int npages = memslot->npages;
7ac77099
AK		 5561 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5562
5563 /* Prevent internal slot pages from being moved by fork()/COW. */
5564 if (memslot->id >= KVM_MEMORY_SLOTS)
5565 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5566
5567 /*To keep backward compatibility with older userspace,
5568 *x86 needs to hanlde !user_alloc case.
5569 */
5570 if (!user_alloc) {
5571 if (npages && !old.rmap) {
604b38ac
AA		 5572 unsigned long userspace_addr;
5573
72dc67a6 5574 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5575 userspace_addr = do_mmap(NULL, 0,
5576 npages * PAGE_SIZE,
5577 PROT_READ | PROT_WRITE,
7ac77099 5578 map_flags,
604b38ac 5579 0);
72dc67a6 5580 up_write(&current->mm->mmap_sem);
0de10343 5581
604b38ac
AA		 5582 if (IS_ERR((void *)userspace_addr))
5583 return PTR_ERR((void *)userspace_addr);
5584
604b38ac 5585 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5586 }
5587 }
5588
f7784b8e
MT		 5589
5590 return 0;
5591}
5592
5593void kvm_arch_commit_memory_region(struct kvm *kvm,
5594 struct kvm_userspace_memory_region *mem,
5595 struct kvm_memory_slot old,
5596 int user_alloc)
5597{
5598
5599 int npages = mem->memory_size >> PAGE_SHIFT;
5600
5601 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5602 int ret;
5603
5604 down_write(&current->mm->mmap_sem);
5605 ret = do_munmap(current->mm, old.userspace_addr,
5606 old.npages * PAGE_SIZE);
5607 up_write(&current->mm->mmap_sem);
5608 if (ret < 0)
5609 printk(KERN_WARNING
5610 "kvm_vm_ioctl_set_memory_region: "
5611 "failed to munmap memory\n");
5612 }
5613
7c8a83b7 5614 spin_lock(&kvm->mmu_lock);
f05e70ac 5615 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5616 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5617 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5618 }
5619
5620 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5621 spin_unlock(&kvm->mmu_lock);
0de10343 5622}
1d737c8a 5623
34d4cb8f
MT		 5624void kvm_arch_flush_shadow(struct kvm *kvm)
5625{
5626 kvm_mmu_zap_all(kvm);
8986ecc0 5627 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5628}
5629
1d737c8a
ZX		 5630int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5631{
a4535290 5632 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5633 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5634 || vcpu->arch.nmi_pending ||
5635 (kvm_arch_interrupt_allowed(vcpu) &&
5636 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5637}
5736199a 5638
5736199a
ZX		 5639void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5640{
32f88400
MT		 5641 int me;
5642 int cpu = vcpu->cpu;
5736199a
ZX		 5643
5644 if (waitqueue_active(&vcpu->wq)) {
5645 wake_up_interruptible(&vcpu->wq);
5646 ++vcpu->stat.halt_wakeup;
5647 }
32f88400
MT		 5648
5649 me = get_cpu();
5650 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5651 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5652 smp_send_reschedule(cpu);
e9571ed5 5653 put_cpu();
5736199a 5654}
78646121
GN		 5655
5656int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5657{
5658 return kvm_x86_ops->interrupt_allowed(vcpu);
5659}
229456fc 5660
f92653ee
JK		 5661bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5662{
5663 unsigned long current_rip = kvm_rip_read(vcpu) +
5664 get_segment_base(vcpu, VCPU_SREG_CS);
5665
5666 return current_rip == linear_rip;
5667}
5668EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5669
94fe45da
JK		 5670unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5671{
5672 unsigned long rflags;
5673
5674 rflags = kvm_x86_ops->get_rflags(vcpu);
5675 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5676 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5677 return rflags;
5678}
5679EXPORT_SYMBOL_GPL(kvm_get_rflags);
5680
5681void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5682{
5683 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5684 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5685 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5686 kvm_x86_ops->set_rflags(vcpu, rflags);
5687}
5688EXPORT_SYMBOL_GPL(kvm_set_rflags);
5689
229456fc
MT		 5690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5692EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5697EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5698EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5699EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5700EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5701EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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