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KVM: Implement dummy values for MSR_PERF_STATUS
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Avi Kivity <avi@qumranet.com>
10 * Yaniv Kamay <yaniv@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
edf88417 17#include <linux/kvm_host.h>
313a3dc7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
313a3dc7 20
18068523 21#include <linux/clocksource.h>
313a3dc7
CO		 22#include <linux/kvm.h>
23#include <linux/fs.h>
24#include <linux/vmalloc.h>
5fb76f9b 25#include <linux/module.h>
0de10343 26#include <linux/mman.h>
2bacc55c 27#include <linux/highmem.h>
043405e1
CO		 28
29#include <asm/uaccess.h>
d825ed0a 30#include <asm/msr.h>
a5f61300 31#include <asm/desc.h>
043405e1 32
313a3dc7 33#define MAX_IO_MSRS 256
a03490ed
CO		 34#define CR0_RESERVED_BITS \
35 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
36 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
37 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
38#define CR4_RESERVED_BITS \
39 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
40 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
41 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
42 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
43
44#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 45/* EFER defaults:
46 * - enable syscall per default because its emulated by KVM
47 * - enable LME and LMA per default on 64 bit KVM
48 */
49#ifdef CONFIG_X86_64
50static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
51#else
52static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
53#endif
313a3dc7 54
ba1389b7
AK		 55#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
56#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 57
674eea0f
AK		 58static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
59 struct kvm_cpuid_entry2 __user *entries);
60
97896d04
ZX		 61struct kvm_x86_ops *kvm_x86_ops;
62
417bc304 63struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 64 { "pf_fixed", VCPU_STAT(pf_fixed) },
65 { "pf_guest", VCPU_STAT(pf_guest) },
66 { "tlb_flush", VCPU_STAT(tlb_flush) },
67 { "invlpg", VCPU_STAT(invlpg) },
68 { "exits", VCPU_STAT(exits) },
69 { "io_exits", VCPU_STAT(io_exits) },
70 { "mmio_exits", VCPU_STAT(mmio_exits) },
71 { "signal_exits", VCPU_STAT(signal_exits) },
72 { "irq_window", VCPU_STAT(irq_window_exits) },
73 { "halt_exits", VCPU_STAT(halt_exits) },
74 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 75 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 76 { "request_irq", VCPU_STAT(request_irq_exits) },
77 { "irq_exits", VCPU_STAT(irq_exits) },
78 { "host_state_reload", VCPU_STAT(host_state_reload) },
79 { "efer_reload", VCPU_STAT(efer_reload) },
80 { "fpu_reload", VCPU_STAT(fpu_reload) },
81 { "insn_emulation", VCPU_STAT(insn_emulation) },
82 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
4cee5764
AK		 83 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
84 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
85 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
86 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
87 { "mmu_flooded", VM_STAT(mmu_flooded) },
88 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 89 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 90 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
417bc304
HB		 91 { NULL }
92};
93
94
5fb76f9b
CO		 95unsigned long segment_base(u16 selector)
96{
97 struct descriptor_table gdt;
a5f61300 98 struct desc_struct *d;
5fb76f9b
CO		 99 unsigned long table_base;
100 unsigned long v;
101
102 if (selector == 0)
103 return 0;
104
105 asm("sgdt %0" : "=m"(gdt));
106 table_base = gdt.base;
107
108 if (selector & 4) { /* from ldt */
109 u16 ldt_selector;
110
111 asm("sldt %0" : "=g"(ldt_selector));
112 table_base = segment_base(ldt_selector);
113 }
a5f61300
AK		 114 d = (struct desc_struct *)(table_base + (selector & ~7));
115 v = d->base0 | ((unsigned long)d->base1 << 16) |
116 ((unsigned long)d->base2 << 24);
5fb76f9b 117#ifdef CONFIG_X86_64
a5f61300
AK		 118 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
119 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 120#endif
121 return v;
122}
123EXPORT_SYMBOL_GPL(segment_base);
124
6866b83e
CO		 125u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
126{
127 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 128 return vcpu->arch.apic_base;
6866b83e 129 else
ad312c7c 130 return vcpu->arch.apic_base;
6866b83e
CO		 131}
132EXPORT_SYMBOL_GPL(kvm_get_apic_base);
133
134void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
135{
136 /* TODO: reserve bits check */
137 if (irqchip_in_kernel(vcpu->kvm))
138 kvm_lapic_set_base(vcpu, data);
139 else
ad312c7c 140 vcpu->arch.apic_base = data;
6866b83e
CO		 141}
142EXPORT_SYMBOL_GPL(kvm_set_apic_base);
143
298101da
AK		 144void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
145{
ad312c7c
ZX		 146 WARN_ON(vcpu->arch.exception.pending);
147 vcpu->arch.exception.pending = true;
148 vcpu->arch.exception.has_error_code = false;
149 vcpu->arch.exception.nr = nr;
298101da
AK		 150}
151EXPORT_SYMBOL_GPL(kvm_queue_exception);
152
c3c91fee
AK		 153void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
154 u32 error_code)
155{
156 ++vcpu->stat.pf_guest;
ad312c7c 157 if (vcpu->arch.exception.pending && vcpu->arch.exception.nr == PF_VECTOR) {
c3c91fee
AK		 158 printk(KERN_DEBUG "kvm: inject_page_fault:"
159 " double fault 0x%lx\n", addr);
ad312c7c
ZX		 160 vcpu->arch.exception.nr = DF_VECTOR;
161 vcpu->arch.exception.error_code = 0;
c3c91fee
AK		 162 return;
163 }
ad312c7c 164 vcpu->arch.cr2 = addr;
c3c91fee
AK		 165 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
166}
167
298101da
AK		 168void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
169{
ad312c7c
ZX		 170 WARN_ON(vcpu->arch.exception.pending);
171 vcpu->arch.exception.pending = true;
172 vcpu->arch.exception.has_error_code = true;
173 vcpu->arch.exception.nr = nr;
174 vcpu->arch.exception.error_code = error_code;
298101da
AK		 175}
176EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
177
178static void __queue_exception(struct kvm_vcpu *vcpu)
179{
ad312c7c
ZX		 180 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
181 vcpu->arch.exception.has_error_code,
182 vcpu->arch.exception.error_code);
298101da
AK		 183}
184
a03490ed
CO		 185/*
186 * Load the pae pdptrs. Return true is they are all valid.
187 */
188int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
189{
190 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
191 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
192 int i;
193 int ret;
ad312c7c 194 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 195
72dc67a6 196 down_read(&vcpu->kvm->slots_lock);
a03490ed
CO		 197 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
198 offset * sizeof(u64), sizeof(pdpte));
199 if (ret < 0) {
200 ret = 0;
201 goto out;
202 }
203 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
204 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
205 ret = 0;
206 goto out;
207 }
208 }
209 ret = 1;
210
ad312c7c 211 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 212out:
72dc67a6 213 up_read(&vcpu->kvm->slots_lock);
a03490ed
CO		 214
215 return ret;
216}
cc4b6871 217EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 218
d835dfec
AK		 219static bool pdptrs_changed(struct kvm_vcpu *vcpu)
220{
ad312c7c 221 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 222 bool changed = true;
223 int r;
224
225 if (is_long_mode(vcpu) || !is_pae(vcpu))
226 return false;
227
72dc67a6 228 down_read(&vcpu->kvm->slots_lock);
ad312c7c 229 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 230 if (r < 0)
231 goto out;
ad312c7c 232 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 233out:
72dc67a6 234 up_read(&vcpu->kvm->slots_lock);
d835dfec
AK		 235
236 return changed;
237}
238
a03490ed
CO		 239void set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
240{
241 if (cr0 & CR0_RESERVED_BITS) {
242 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 243 cr0, vcpu->arch.cr0);
c1a5d4f9 244 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 245 return;
246 }
247
248 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
249 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 250 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 251 return;
252 }
253
254 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
255 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
256 "and a clear PE flag\n");
c1a5d4f9 257 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 258 return;
259 }
260
261 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
262#ifdef CONFIG_X86_64
ad312c7c 263 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 264 int cs_db, cs_l;
265
266 if (!is_pae(vcpu)) {
267 printk(KERN_DEBUG "set_cr0: #GP, start paging "
268 "in long mode while PAE is disabled\n");
c1a5d4f9 269 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 270 return;
271 }
272 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
273 if (cs_l) {
274 printk(KERN_DEBUG "set_cr0: #GP, start paging "
275 "in long mode while CS.L == 1\n");
c1a5d4f9 276 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 277 return;
278
279 }
280 } else
281#endif
ad312c7c 282 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 283 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
284 "reserved bits\n");
c1a5d4f9 285 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 286 return;
287 }
288
289 }
290
291 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 292 vcpu->arch.cr0 = cr0;
a03490ed 293
a03490ed 294 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 295 return;
296}
297EXPORT_SYMBOL_GPL(set_cr0);
298
299void lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
300{
ad312c7c 301 set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed
CO		 302}
303EXPORT_SYMBOL_GPL(lmsw);
304
305void set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
306{
307 if (cr4 & CR4_RESERVED_BITS) {
308 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 309 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 310 return;
311 }
312
313 if (is_long_mode(vcpu)) {
314 if (!(cr4 & X86_CR4_PAE)) {
315 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
316 "in long mode\n");
c1a5d4f9 317 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 318 return;
319 }
320 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 321 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 322 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 323 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 324 return;
325 }
326
327 if (cr4 & X86_CR4_VMXE) {
328 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 329 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 330 return;
331 }
332 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 333 vcpu->arch.cr4 = cr4;
a03490ed 334 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 335}
336EXPORT_SYMBOL_GPL(set_cr4);
337
338void set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
339{
ad312c7c 340 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
d835dfec
AK		 341 kvm_mmu_flush_tlb(vcpu);
342 return;
343 }
344
a03490ed
CO		 345 if (is_long_mode(vcpu)) {
346 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
347 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 348 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 349 return;
350 }
351 } else {
352 if (is_pae(vcpu)) {
353 if (cr3 & CR3_PAE_RESERVED_BITS) {
354 printk(KERN_DEBUG
355 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
360 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
361 "reserved bits\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365 }
366 /*
367 * We don't check reserved bits in nonpae mode, because
368 * this isn't enforced, and VMware depends on this.
369 */
370 }
371
72dc67a6 372 down_read(&vcpu->kvm->slots_lock);
a03490ed
CO		 373 /*
374 * Does the new cr3 value map to physical memory? (Note, we
375 * catch an invalid cr3 even in real-mode, because it would
376 * cause trouble later on when we turn on paging anyway.)
377 *
378 * A real CPU would silently accept an invalid cr3 and would
379 * attempt to use it - with largely undefined (and often hard
380 * to debug) behavior on the guest side.
381 */
382 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 383 kvm_inject_gp(vcpu, 0);
a03490ed 384 else {
ad312c7c
ZX		 385 vcpu->arch.cr3 = cr3;
386 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 387 }
72dc67a6 388 up_read(&vcpu->kvm->slots_lock);
a03490ed
CO		 389}
390EXPORT_SYMBOL_GPL(set_cr3);
391
392void set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
393{
394 if (cr8 & CR8_RESERVED_BITS) {
395 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 396 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 397 return;
398 }
399 if (irqchip_in_kernel(vcpu->kvm))
400 kvm_lapic_set_tpr(vcpu, cr8);
401 else
ad312c7c 402 vcpu->arch.cr8 = cr8;
a03490ed
CO		 403}
404EXPORT_SYMBOL_GPL(set_cr8);
405
406unsigned long get_cr8(struct kvm_vcpu *vcpu)
407{
408 if (irqchip_in_kernel(vcpu->kvm))
409 return kvm_lapic_get_cr8(vcpu);
410 else
ad312c7c 411 return vcpu->arch.cr8;
a03490ed
CO		 412}
413EXPORT_SYMBOL_GPL(get_cr8);
414
043405e1
CO		 415/*
416 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
417 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
418 *
419 * This list is modified at module load time to reflect the
420 * capabilities of the host cpu.
421 */
422static u32 msrs_to_save[] = {
423 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
424 MSR_K6_STAR,
425#ifdef CONFIG_X86_64
426 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
427#endif
18068523 428 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 429 MSR_IA32_PERF_STATUS,
043405e1
CO		 430};
431
432static unsigned num_msrs_to_save;
433
434static u32 emulated_msrs[] = {
435 MSR_IA32_MISC_ENABLE,
436};
437
15c4a640
CO		 438static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
439{
f2b4b7dd 440 if (efer & efer_reserved_bits) {
15c4a640
CO		 441 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
442 efer);
c1a5d4f9 443 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 444 return;
445 }
446
447 if (is_paging(vcpu)
ad312c7c 448 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 449 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 450 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 451 return;
452 }
453
454 kvm_x86_ops->set_efer(vcpu, efer);
455
456 efer &= ~EFER_LMA;
ad312c7c 457 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 458
ad312c7c 459 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 460}
461
f2b4b7dd
JR		 462void kvm_enable_efer_bits(u64 mask)
463{
464 efer_reserved_bits &= ~mask;
465}
466EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
467
468
15c4a640
CO		 469/*
470 * Writes msr value into into the appropriate "register".
471 * Returns 0 on success, non-0 otherwise.
472 * Assumes vcpu_load() was already called.
473 */
474int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
475{
476 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
477}
478
313a3dc7
CO		 479/*
480 * Adapt set_msr() to msr_io()'s calling convention
481 */
482static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
483{
484 return kvm_set_msr(vcpu, index, *data);
485}
486
18068523
GOC		 487static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
488{
489 static int version;
490 struct kvm_wall_clock wc;
491 struct timespec wc_ts;
492
493 if (!wall_clock)
494 return;
495
496 version++;
497
498 down_read(&kvm->slots_lock);
499 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
500
501 wc_ts = current_kernel_time();
502 wc.wc_sec = wc_ts.tv_sec;
503 wc.wc_nsec = wc_ts.tv_nsec;
504 wc.wc_version = version;
505
506 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
507
508 version++;
509 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
510 up_read(&kvm->slots_lock);
511}
512
513static void kvm_write_guest_time(struct kvm_vcpu *v)
514{
515 struct timespec ts;
516 unsigned long flags;
517 struct kvm_vcpu_arch *vcpu = &v->arch;
518 void *shared_kaddr;
519
520 if ((!vcpu->time_page))
521 return;
522
523 /* Keep irq disabled to prevent changes to the clock */
524 local_irq_save(flags);
525 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
526 &vcpu->hv_clock.tsc_timestamp);
527 ktime_get_ts(&ts);
528 local_irq_restore(flags);
529
530 /* With all the info we got, fill in the values */
531
532 vcpu->hv_clock.system_time = ts.tv_nsec +
533 (NSEC_PER_SEC * (u64)ts.tv_sec);
534 /*
535 * The interface expects us to write an even number signaling that the
536 * update is finished. Since the guest won't see the intermediate
537 * state, we just write "2" at the end
538 */
539 vcpu->hv_clock.version = 2;
540
541 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
542
543 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
544 sizeof(vcpu->hv_clock));
545
546 kunmap_atomic(shared_kaddr, KM_USER0);
547
548 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
549}
550
15c4a640
CO		 551
552int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
553{
554 switch (msr) {
15c4a640
CO		 555 case MSR_EFER:
556 set_efer(vcpu, data);
557 break;
15c4a640
CO		 558 case MSR_IA32_MC0_STATUS:
559 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
560 __FUNCTION__, data);
561 break;
562 case MSR_IA32_MCG_STATUS:
563 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
564 __FUNCTION__, data);
565 break;
c7ac679c
JR		 566 case MSR_IA32_MCG_CTL:
567 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
568 __FUNCTION__, data);
569 break;
15c4a640
CO		 570 case MSR_IA32_UCODE_REV:
571 case MSR_IA32_UCODE_WRITE:
572 case 0x200 ... 0x2ff: /* MTRRs */
573 break;
574 case MSR_IA32_APICBASE:
575 kvm_set_apic_base(vcpu, data);
576 break;
577 case MSR_IA32_MISC_ENABLE:
ad312c7c 578 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 579 break;
18068523
GOC		 580 case MSR_KVM_WALL_CLOCK:
581 vcpu->kvm->arch.wall_clock = data;
582 kvm_write_wall_clock(vcpu->kvm, data);
583 break;
584 case MSR_KVM_SYSTEM_TIME: {
585 if (vcpu->arch.time_page) {
586 kvm_release_page_dirty(vcpu->arch.time_page);
587 vcpu->arch.time_page = NULL;
588 }
589
590 vcpu->arch.time = data;
591
592 /* we verify if the enable bit is set... */
593 if (!(data & 1))
594 break;
595
596 /* ...but clean it before doing the actual write */
597 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
598
599 vcpu->arch.hv_clock.tsc_to_system_mul =
600 clocksource_khz2mult(tsc_khz, 22);
601 vcpu->arch.hv_clock.tsc_shift = 22;
602
603 down_read(&current->mm->mmap_sem);
604 down_read(&vcpu->kvm->slots_lock);
605 vcpu->arch.time_page =
606 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
607 up_read(&vcpu->kvm->slots_lock);
608 up_read(&current->mm->mmap_sem);
609
610 if (is_error_page(vcpu->arch.time_page)) {
611 kvm_release_page_clean(vcpu->arch.time_page);
612 vcpu->arch.time_page = NULL;
613 }
614
615 kvm_write_guest_time(vcpu);
616 break;
617 }
15c4a640 618 default:
565f1fbd 619 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 620 return 1;
621 }
622 return 0;
623}
624EXPORT_SYMBOL_GPL(kvm_set_msr_common);
625
626
627/*
628 * Reads an msr value (of 'msr_index') into 'pdata'.
629 * Returns 0 on success, non-0 otherwise.
630 * Assumes vcpu_load() was already called.
631 */
632int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
633{
634 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
635}
636
637int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
638{
639 u64 data;
640
641 switch (msr) {
642 case 0xc0010010: /* SYSCFG */
643 case 0xc0010015: /* HWCR */
644 case MSR_IA32_PLATFORM_ID:
645 case MSR_IA32_P5_MC_ADDR:
646 case MSR_IA32_P5_MC_TYPE:
647 case MSR_IA32_MC0_CTL:
648 case MSR_IA32_MCG_STATUS:
649 case MSR_IA32_MCG_CAP:
c7ac679c 650 case MSR_IA32_MCG_CTL:
15c4a640
CO		 651 case MSR_IA32_MC0_MISC:
652 case MSR_IA32_MC0_MISC+4:
653 case MSR_IA32_MC0_MISC+8:
654 case MSR_IA32_MC0_MISC+12:
655 case MSR_IA32_MC0_MISC+16:
656 case MSR_IA32_UCODE_REV:
15c4a640
CO		 657 case MSR_IA32_EBL_CR_POWERON:
658 /* MTRR registers */
659 case 0xfe:
660 case 0x200 ... 0x2ff:
661 data = 0;
662 break;
663 case 0xcd: /* fsb frequency */
664 data = 3;
665 break;
666 case MSR_IA32_APICBASE:
667 data = kvm_get_apic_base(vcpu);
668 break;
669 case MSR_IA32_MISC_ENABLE:
ad312c7c 670 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 671 break;
847f0ad8
AG		 672 case MSR_IA32_PERF_STATUS:
673 /* TSC increment by tick */
674 data = 1000ULL;
675 /* CPU multiplier */
676 data |= (((uint64_t)4ULL) << 40);
677 break;
15c4a640 678 case MSR_EFER:
ad312c7c 679 data = vcpu->arch.shadow_efer;
15c4a640 680 break;
18068523
GOC		 681 case MSR_KVM_WALL_CLOCK:
682 data = vcpu->kvm->arch.wall_clock;
683 break;
684 case MSR_KVM_SYSTEM_TIME:
685 data = vcpu->arch.time;
686 break;
15c4a640
CO		 687 default:
688 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
689 return 1;
690 }
691 *pdata = data;
692 return 0;
693}
694EXPORT_SYMBOL_GPL(kvm_get_msr_common);
695
313a3dc7
CO		 696/*
697 * Read or write a bunch of msrs. All parameters are kernel addresses.
698 *
699 * @return number of msrs set successfully.
700 */
701static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
702 struct kvm_msr_entry *entries,
703 int (*do_msr)(struct kvm_vcpu *vcpu,
704 unsigned index, u64 *data))
705{
706 int i;
707
708 vcpu_load(vcpu);
709
710 for (i = 0; i < msrs->nmsrs; ++i)
711 if (do_msr(vcpu, entries[i].index, &entries[i].data))
712 break;
713
714 vcpu_put(vcpu);
715
716 return i;
717}
718
719/*
720 * Read or write a bunch of msrs. Parameters are user addresses.
721 *
722 * @return number of msrs set successfully.
723 */
724static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
725 int (*do_msr)(struct kvm_vcpu *vcpu,
726 unsigned index, u64 *data),
727 int writeback)
728{
729 struct kvm_msrs msrs;
730 struct kvm_msr_entry *entries;
731 int r, n;
732 unsigned size;
733
734 r = -EFAULT;
735 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
736 goto out;
737
738 r = -E2BIG;
739 if (msrs.nmsrs >= MAX_IO_MSRS)
740 goto out;
741
742 r = -ENOMEM;
743 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
744 entries = vmalloc(size);
745 if (!entries)
746 goto out;
747
748 r = -EFAULT;
749 if (copy_from_user(entries, user_msrs->entries, size))
750 goto out_free;
751
752 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
753 if (r < 0)
754 goto out_free;
755
756 r = -EFAULT;
757 if (writeback && copy_to_user(user_msrs->entries, entries, size))
758 goto out_free;
759
760 r = n;
761
762out_free:
763 vfree(entries);
764out:
765 return r;
766}
767
e9b11c17
ZX		 768/*
769 * Make sure that a cpu that is being hot-unplugged does not have any vcpus
770 * cached on it.
771 */
772void decache_vcpus_on_cpu(int cpu)
773{
774 struct kvm *vm;
775 struct kvm_vcpu *vcpu;
776 int i;
777
778 spin_lock(&kvm_lock);
779 list_for_each_entry(vm, &vm_list, vm_list)
780 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
781 vcpu = vm->vcpus[i];
782 if (!vcpu)
783 continue;
784 /*
785 * If the vcpu is locked, then it is running on some
786 * other cpu and therefore it is not cached on the
787 * cpu in question.
788 *
789 * If it's not locked, check the last cpu it executed
790 * on.
791 */
792 if (mutex_trylock(&vcpu->mutex)) {
793 if (vcpu->cpu == cpu) {
794 kvm_x86_ops->vcpu_decache(vcpu);
795 vcpu->cpu = -1;
796 }
797 mutex_unlock(&vcpu->mutex);
798 }
799 }
800 spin_unlock(&kvm_lock);
801}
802
018d00d2
ZX		 803int kvm_dev_ioctl_check_extension(long ext)
804{
805 int r;
806
807 switch (ext) {
808 case KVM_CAP_IRQCHIP:
809 case KVM_CAP_HLT:
810 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
811 case KVM_CAP_USER_MEMORY:
812 case KVM_CAP_SET_TSS_ADDR:
07716717 813 case KVM_CAP_EXT_CPUID:
18068523 814 case KVM_CAP_CLOCKSOURCE:
018d00d2
ZX		 815 r = 1;
816 break;
774ead3a
AK		 817 case KVM_CAP_VAPIC:
818 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
819 break;
f725230a
AK		 820 case KVM_CAP_NR_VCPUS:
821 r = KVM_MAX_VCPUS;
822 break;
a988b910
AK		 823 case KVM_CAP_NR_MEMSLOTS:
824 r = KVM_MEMORY_SLOTS;
825 break;
018d00d2
ZX		 826 default:
827 r = 0;
828 break;
829 }
830 return r;
831
832}
833
043405e1
CO		 834long kvm_arch_dev_ioctl(struct file *filp,
835 unsigned int ioctl, unsigned long arg)
836{
837 void __user *argp = (void __user *)arg;
838 long r;
839
840 switch (ioctl) {
841 case KVM_GET_MSR_INDEX_LIST: {
842 struct kvm_msr_list __user *user_msr_list = argp;
843 struct kvm_msr_list msr_list;
844 unsigned n;
845
846 r = -EFAULT;
847 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
848 goto out;
849 n = msr_list.nmsrs;
850 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
851 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
852 goto out;
853 r = -E2BIG;
854 if (n < num_msrs_to_save)
855 goto out;
856 r = -EFAULT;
857 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
858 num_msrs_to_save * sizeof(u32)))
859 goto out;
860 if (copy_to_user(user_msr_list->indices
861 + num_msrs_to_save * sizeof(u32),
862 &emulated_msrs,
863 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
864 goto out;
865 r = 0;
866 break;
867 }
674eea0f
AK		 868 case KVM_GET_SUPPORTED_CPUID: {
869 struct kvm_cpuid2 __user *cpuid_arg = argp;
870 struct kvm_cpuid2 cpuid;
871
872 r = -EFAULT;
873 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
874 goto out;
875 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
876 cpuid_arg->entries);
877 if (r)
878 goto out;
879
880 r = -EFAULT;
881 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
882 goto out;
883 r = 0;
884 break;
885 }
043405e1
CO		 886 default:
887 r = -EINVAL;
888 }
889out:
890 return r;
891}
892
313a3dc7
CO		 893void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
894{
895 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 896 kvm_write_guest_time(vcpu);
313a3dc7
CO		 897}
898
899void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
900{
901 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 902 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 903}
904
07716717 905static int is_efer_nx(void)
313a3dc7
CO		 906{
907 u64 efer;
313a3dc7
CO		 908
909 rdmsrl(MSR_EFER, efer);
07716717
DK		 910 return efer & EFER_NX;
911}
912
913static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
914{
915 int i;
916 struct kvm_cpuid_entry2 *e, *entry;
917
313a3dc7 918 entry = NULL;
ad312c7c
ZX		 919 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
920 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 921 if (e->function == 0x80000001) {
922 entry = e;
923 break;
924 }
925 }
07716717 926 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 927 entry->edx &= ~(1 << 20);
928 printk(KERN_INFO "kvm: guest NX capability removed\n");
929 }
930}
931
07716717 932/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 933static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
934 struct kvm_cpuid *cpuid,
935 struct kvm_cpuid_entry __user *entries)
07716717
DK		 936{
937 int r, i;
938 struct kvm_cpuid_entry *cpuid_entries;
939
940 r = -E2BIG;
941 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
942 goto out;
943 r = -ENOMEM;
944 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
945 if (!cpuid_entries)
946 goto out;
947 r = -EFAULT;
948 if (copy_from_user(cpuid_entries, entries,
949 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
950 goto out_free;
951 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 952 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
953 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
954 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
955 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
956 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
957 vcpu->arch.cpuid_entries[i].index = 0;
958 vcpu->arch.cpuid_entries[i].flags = 0;
959 vcpu->arch.cpuid_entries[i].padding[0] = 0;
960 vcpu->arch.cpuid_entries[i].padding[1] = 0;
961 vcpu->arch.cpuid_entries[i].padding[2] = 0;
962 }
963 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 964 cpuid_fix_nx_cap(vcpu);
965 r = 0;
966
967out_free:
968 vfree(cpuid_entries);
969out:
970 return r;
971}
972
973static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
974 struct kvm_cpuid2 *cpuid,
975 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 976{
977 int r;
978
979 r = -E2BIG;
980 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
981 goto out;
982 r = -EFAULT;
ad312c7c 983 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 984 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 985 goto out;
ad312c7c 986 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 987 return 0;
988
989out:
990 return r;
991}
992
07716717
DK		 993static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
994 struct kvm_cpuid2 *cpuid,
995 struct kvm_cpuid_entry2 __user *entries)
996{
997 int r;
998
999 r = -E2BIG;
ad312c7c 1000 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1001 goto out;
1002 r = -EFAULT;
ad312c7c
ZX		 1003 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1004 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1005 goto out;
1006 return 0;
1007
1008out:
ad312c7c 1009 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1010 return r;
1011}
1012
1013static inline u32 bit(int bitno)
1014{
1015 return 1 << (bitno & 31);
1016}
1017
1018static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1019 u32 index)
1020{
1021 entry->function = function;
1022 entry->index = index;
1023 cpuid_count(entry->function, entry->index,
1024 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1025 entry->flags = 0;
1026}
1027
1028static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1029 u32 index, int *nent, int maxnent)
1030{
1031 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1032 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1033 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1034 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1035 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1036 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1037 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1038 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1039 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1040 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1041 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1042 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1043 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1044 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1045 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1046 bit(X86_FEATURE_PGE) |
1047 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1048 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1049 bit(X86_FEATURE_SYSCALL) |
1050 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1051#ifdef CONFIG_X86_64
1052 bit(X86_FEATURE_LM) |
1053#endif
1054 bit(X86_FEATURE_MMXEXT) |
1055 bit(X86_FEATURE_3DNOWEXT) |
1056 bit(X86_FEATURE_3DNOW);
1057 const u32 kvm_supported_word3_x86_features =
1058 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1059 const u32 kvm_supported_word6_x86_features =
1060 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1061
1062 /* all func 2 cpuid_count() should be called on the same cpu */
1063 get_cpu();
1064 do_cpuid_1_ent(entry, function, index);
1065 ++*nent;
1066
1067 switch (function) {
1068 case 0:
1069 entry->eax = min(entry->eax, (u32)0xb);
1070 break;
1071 case 1:
1072 entry->edx &= kvm_supported_word0_x86_features;
1073 entry->ecx &= kvm_supported_word3_x86_features;
1074 break;
1075 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1076 * may return different values. This forces us to get_cpu() before
1077 * issuing the first command, and also to emulate this annoying behavior
1078 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1079 case 2: {
1080 int t, times = entry->eax & 0xff;
1081
1082 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1083 for (t = 1; t < times && *nent < maxnent; ++t) {
1084 do_cpuid_1_ent(&entry[t], function, 0);
1085 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1086 ++*nent;
1087 }
1088 break;
1089 }
1090 /* function 4 and 0xb have additional index. */
1091 case 4: {
14af3f3c 1092 int i, cache_type;
07716717
DK		 1093
1094 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1095 /* read more entries until cache_type is zero */
14af3f3c
HH		 1096 for (i = 1; *nent < maxnent; ++i) {
1097 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1098 if (!cache_type)
1099 break;
14af3f3c
HH		 1100 do_cpuid_1_ent(&entry[i], function, i);
1101 entry[i].flags |=
07716717
DK		 1102 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1103 ++*nent;
1104 }
1105 break;
1106 }
1107 case 0xb: {
14af3f3c 1108 int i, level_type;
07716717
DK		 1109
1110 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1111 /* read more entries until level_type is zero */
14af3f3c
HH		 1112 for (i = 1; *nent < maxnent; ++i) {
1113 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1114 if (!level_type)
1115 break;
14af3f3c
HH		 1116 do_cpuid_1_ent(&entry[i], function, i);
1117 entry[i].flags |=
07716717
DK		 1118 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1119 ++*nent;
1120 }
1121 break;
1122 }
1123 case 0x80000000:
1124 entry->eax = min(entry->eax, 0x8000001a);
1125 break;
1126 case 0x80000001:
1127 entry->edx &= kvm_supported_word1_x86_features;
1128 entry->ecx &= kvm_supported_word6_x86_features;
1129 break;
1130 }
1131 put_cpu();
1132}
1133
674eea0f 1134static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1135 struct kvm_cpuid_entry2 __user *entries)
1136{
1137 struct kvm_cpuid_entry2 *cpuid_entries;
1138 int limit, nent = 0, r = -E2BIG;
1139 u32 func;
1140
1141 if (cpuid->nent < 1)
1142 goto out;
1143 r = -ENOMEM;
1144 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1145 if (!cpuid_entries)
1146 goto out;
1147
1148 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1149 limit = cpuid_entries[0].eax;
1150 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1151 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1152 &nent, cpuid->nent);
1153 r = -E2BIG;
1154 if (nent >= cpuid->nent)
1155 goto out_free;
1156
1157 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1158 limit = cpuid_entries[nent - 1].eax;
1159 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1160 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1161 &nent, cpuid->nent);
1162 r = -EFAULT;
1163 if (copy_to_user(entries, cpuid_entries,
1164 nent * sizeof(struct kvm_cpuid_entry2)))
1165 goto out_free;
1166 cpuid->nent = nent;
1167 r = 0;
1168
1169out_free:
1170 vfree(cpuid_entries);
1171out:
1172 return r;
1173}
1174
313a3dc7
CO		 1175static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1176 struct kvm_lapic_state *s)
1177{
1178 vcpu_load(vcpu);
ad312c7c 1179 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1180 vcpu_put(vcpu);
1181
1182 return 0;
1183}
1184
1185static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1186 struct kvm_lapic_state *s)
1187{
1188 vcpu_load(vcpu);
ad312c7c 1189 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1190 kvm_apic_post_state_restore(vcpu);
1191 vcpu_put(vcpu);
1192
1193 return 0;
1194}
1195
f77bc6a4
ZX		 1196static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1197 struct kvm_interrupt *irq)
1198{
1199 if (irq->irq < 0 || irq->irq >= 256)
1200 return -EINVAL;
1201 if (irqchip_in_kernel(vcpu->kvm))
1202 return -ENXIO;
1203 vcpu_load(vcpu);
1204
ad312c7c
ZX		 1205 set_bit(irq->irq, vcpu->arch.irq_pending);
1206 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1207
1208 vcpu_put(vcpu);
1209
1210 return 0;
1211}
1212
b209749f
AK		 1213static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1214 struct kvm_tpr_access_ctl *tac)
1215{
1216 if (tac->flags)
1217 return -EINVAL;
1218 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1219 return 0;
1220}
1221
313a3dc7
CO		 1222long kvm_arch_vcpu_ioctl(struct file *filp,
1223 unsigned int ioctl, unsigned long arg)
1224{
1225 struct kvm_vcpu *vcpu = filp->private_data;
1226 void __user *argp = (void __user *)arg;
1227 int r;
1228
1229 switch (ioctl) {
1230 case KVM_GET_LAPIC: {
1231 struct kvm_lapic_state lapic;
1232
1233 memset(&lapic, 0, sizeof lapic);
1234 r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic);
1235 if (r)
1236 goto out;
1237 r = -EFAULT;
1238 if (copy_to_user(argp, &lapic, sizeof lapic))
1239 goto out;
1240 r = 0;
1241 break;
1242 }
1243 case KVM_SET_LAPIC: {
1244 struct kvm_lapic_state lapic;
1245
1246 r = -EFAULT;
1247 if (copy_from_user(&lapic, argp, sizeof lapic))
1248 goto out;
1249 r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);;
1250 if (r)
1251 goto out;
1252 r = 0;
1253 break;
1254 }
f77bc6a4
ZX		 1255 case KVM_INTERRUPT: {
1256 struct kvm_interrupt irq;
1257
1258 r = -EFAULT;
1259 if (copy_from_user(&irq, argp, sizeof irq))
1260 goto out;
1261 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1262 if (r)
1263 goto out;
1264 r = 0;
1265 break;
1266 }
313a3dc7
CO		 1267 case KVM_SET_CPUID: {
1268 struct kvm_cpuid __user *cpuid_arg = argp;
1269 struct kvm_cpuid cpuid;
1270
1271 r = -EFAULT;
1272 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1273 goto out;
1274 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1275 if (r)
1276 goto out;
1277 break;
1278 }
07716717
DK		 1279 case KVM_SET_CPUID2: {
1280 struct kvm_cpuid2 __user *cpuid_arg = argp;
1281 struct kvm_cpuid2 cpuid;
1282
1283 r = -EFAULT;
1284 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1285 goto out;
1286 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1287 cpuid_arg->entries);
1288 if (r)
1289 goto out;
1290 break;
1291 }
1292 case KVM_GET_CPUID2: {
1293 struct kvm_cpuid2 __user *cpuid_arg = argp;
1294 struct kvm_cpuid2 cpuid;
1295
1296 r = -EFAULT;
1297 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1298 goto out;
1299 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1300 cpuid_arg->entries);
1301 if (r)
1302 goto out;
1303 r = -EFAULT;
1304 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1305 goto out;
1306 r = 0;
1307 break;
1308 }
313a3dc7
CO		 1309 case KVM_GET_MSRS:
1310 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1311 break;
1312 case KVM_SET_MSRS:
1313 r = msr_io(vcpu, argp, do_set_msr, 0);
1314 break;
b209749f
AK		 1315 case KVM_TPR_ACCESS_REPORTING: {
1316 struct kvm_tpr_access_ctl tac;
1317
1318 r = -EFAULT;
1319 if (copy_from_user(&tac, argp, sizeof tac))
1320 goto out;
1321 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1322 if (r)
1323 goto out;
1324 r = -EFAULT;
1325 if (copy_to_user(argp, &tac, sizeof tac))
1326 goto out;
1327 r = 0;
1328 break;
1329 };
b93463aa
AK		 1330 case KVM_SET_VAPIC_ADDR: {
1331 struct kvm_vapic_addr va;
1332
1333 r = -EINVAL;
1334 if (!irqchip_in_kernel(vcpu->kvm))
1335 goto out;
1336 r = -EFAULT;
1337 if (copy_from_user(&va, argp, sizeof va))
1338 goto out;
1339 r = 0;
1340 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1341 break;
1342 }
313a3dc7
CO		 1343 default:
1344 r = -EINVAL;
1345 }
1346out:
1347 return r;
1348}
1349
1fe779f8
CO		 1350static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1351{
1352 int ret;
1353
1354 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1355 return -1;
1356 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1357 return ret;
1358}
1359
1360static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1361 u32 kvm_nr_mmu_pages)
1362{
1363 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1364 return -EINVAL;
1365
72dc67a6 1366 down_write(&kvm->slots_lock);
1fe779f8
CO		 1367
1368 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1369 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1370
72dc67a6 1371 up_write(&kvm->slots_lock);
1fe779f8
CO		 1372 return 0;
1373}
1374
1375static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1376{
f05e70ac 1377 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1378}
1379
e9f85cde
ZX		 1380gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1381{
1382 int i;
1383 struct kvm_mem_alias *alias;
1384
d69fb81f
ZX		 1385 for (i = 0; i < kvm->arch.naliases; ++i) {
1386 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1387 if (gfn >= alias->base_gfn
1388 && gfn < alias->base_gfn + alias->npages)
1389 return alias->target_gfn + gfn - alias->base_gfn;
1390 }
1391 return gfn;
1392}
1393
1fe779f8
CO		 1394/*
1395 * Set a new alias region. Aliases map a portion of physical memory into
1396 * another portion. This is useful for memory windows, for example the PC
1397 * VGA region.
1398 */
1399static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1400 struct kvm_memory_alias *alias)
1401{
1402 int r, n;
1403 struct kvm_mem_alias *p;
1404
1405 r = -EINVAL;
1406 /* General sanity checks */
1407 if (alias->memory_size & (PAGE_SIZE - 1))
1408 goto out;
1409 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1410 goto out;
1411 if (alias->slot >= KVM_ALIAS_SLOTS)
1412 goto out;
1413 if (alias->guest_phys_addr + alias->memory_size
1414 < alias->guest_phys_addr)
1415 goto out;
1416 if (alias->target_phys_addr + alias->memory_size
1417 < alias->target_phys_addr)
1418 goto out;
1419
72dc67a6 1420 down_write(&kvm->slots_lock);
1fe779f8 1421
d69fb81f 1422 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1423 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1424 p->npages = alias->memory_size >> PAGE_SHIFT;
1425 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1426
1427 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1428 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1429 break;
d69fb81f 1430 kvm->arch.naliases = n;
1fe779f8
CO		 1431
1432 kvm_mmu_zap_all(kvm);
1433
72dc67a6 1434 up_write(&kvm->slots_lock);
1fe779f8
CO		 1435
1436 return 0;
1437
1438out:
1439 return r;
1440}
1441
1442static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1443{
1444 int r;
1445
1446 r = 0;
1447 switch (chip->chip_id) {
1448 case KVM_IRQCHIP_PIC_MASTER:
1449 memcpy(&chip->chip.pic,
1450 &pic_irqchip(kvm)->pics[0],
1451 sizeof(struct kvm_pic_state));
1452 break;
1453 case KVM_IRQCHIP_PIC_SLAVE:
1454 memcpy(&chip->chip.pic,
1455 &pic_irqchip(kvm)->pics[1],
1456 sizeof(struct kvm_pic_state));
1457 break;
1458 case KVM_IRQCHIP_IOAPIC:
1459 memcpy(&chip->chip.ioapic,
1460 ioapic_irqchip(kvm),
1461 sizeof(struct kvm_ioapic_state));
1462 break;
1463 default:
1464 r = -EINVAL;
1465 break;
1466 }
1467 return r;
1468}
1469
1470static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1471{
1472 int r;
1473
1474 r = 0;
1475 switch (chip->chip_id) {
1476 case KVM_IRQCHIP_PIC_MASTER:
1477 memcpy(&pic_irqchip(kvm)->pics[0],
1478 &chip->chip.pic,
1479 sizeof(struct kvm_pic_state));
1480 break;
1481 case KVM_IRQCHIP_PIC_SLAVE:
1482 memcpy(&pic_irqchip(kvm)->pics[1],
1483 &chip->chip.pic,
1484 sizeof(struct kvm_pic_state));
1485 break;
1486 case KVM_IRQCHIP_IOAPIC:
1487 memcpy(ioapic_irqchip(kvm),
1488 &chip->chip.ioapic,
1489 sizeof(struct kvm_ioapic_state));
1490 break;
1491 default:
1492 r = -EINVAL;
1493 break;
1494 }
1495 kvm_pic_update_irq(pic_irqchip(kvm));
1496 return r;
1497}
1498
5bb064dc
ZX		 1499/*
1500 * Get (and clear) the dirty memory log for a memory slot.
1501 */
1502int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1503 struct kvm_dirty_log *log)
1504{
1505 int r;
1506 int n;
1507 struct kvm_memory_slot *memslot;
1508 int is_dirty = 0;
1509
72dc67a6 1510 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1511
1512 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1513 if (r)
1514 goto out;
1515
1516 /* If nothing is dirty, don't bother messing with page tables. */
1517 if (is_dirty) {
1518 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1519 kvm_flush_remote_tlbs(kvm);
1520 memslot = &kvm->memslots[log->slot];
1521 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1522 memset(memslot->dirty_bitmap, 0, n);
1523 }
1524 r = 0;
1525out:
72dc67a6 1526 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1527 return r;
1528}
1529
1fe779f8
CO		 1530long kvm_arch_vm_ioctl(struct file *filp,
1531 unsigned int ioctl, unsigned long arg)
1532{
1533 struct kvm *kvm = filp->private_data;
1534 void __user *argp = (void __user *)arg;
1535 int r = -EINVAL;
1536
1537 switch (ioctl) {
1538 case KVM_SET_TSS_ADDR:
1539 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1540 if (r < 0)
1541 goto out;
1542 break;
1543 case KVM_SET_MEMORY_REGION: {
1544 struct kvm_memory_region kvm_mem;
1545 struct kvm_userspace_memory_region kvm_userspace_mem;
1546
1547 r = -EFAULT;
1548 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1549 goto out;
1550 kvm_userspace_mem.slot = kvm_mem.slot;
1551 kvm_userspace_mem.flags = kvm_mem.flags;
1552 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1553 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1554 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1555 if (r)
1556 goto out;
1557 break;
1558 }
1559 case KVM_SET_NR_MMU_PAGES:
1560 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1561 if (r)
1562 goto out;
1563 break;
1564 case KVM_GET_NR_MMU_PAGES:
1565 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1566 break;
1567 case KVM_SET_MEMORY_ALIAS: {
1568 struct kvm_memory_alias alias;
1569
1570 r = -EFAULT;
1571 if (copy_from_user(&alias, argp, sizeof alias))
1572 goto out;
1573 r = kvm_vm_ioctl_set_memory_alias(kvm, &alias);
1574 if (r)
1575 goto out;
1576 break;
1577 }
1578 case KVM_CREATE_IRQCHIP:
1579 r = -ENOMEM;
d7deeeb0
ZX		 1580 kvm->arch.vpic = kvm_create_pic(kvm);
1581 if (kvm->arch.vpic) {
1fe779f8
CO		 1582 r = kvm_ioapic_init(kvm);
1583 if (r) {
d7deeeb0
ZX		 1584 kfree(kvm->arch.vpic);
1585 kvm->arch.vpic = NULL;
1fe779f8
CO		 1586 goto out;
1587 }
1588 } else
1589 goto out;
1590 break;
1591 case KVM_IRQ_LINE: {
1592 struct kvm_irq_level irq_event;
1593
1594 r = -EFAULT;
1595 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1596 goto out;
1597 if (irqchip_in_kernel(kvm)) {
1598 mutex_lock(&kvm->lock);
1599 if (irq_event.irq < 16)
1600 kvm_pic_set_irq(pic_irqchip(kvm),
1601 irq_event.irq,
1602 irq_event.level);
d7deeeb0 1603 kvm_ioapic_set_irq(kvm->arch.vioapic,
1fe779f8
CO		 1604 irq_event.irq,
1605 irq_event.level);
1606 mutex_unlock(&kvm->lock);
1607 r = 0;
1608 }
1609 break;
1610 }
1611 case KVM_GET_IRQCHIP: {
1612 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1613 struct kvm_irqchip chip;
1614
1615 r = -EFAULT;
1616 if (copy_from_user(&chip, argp, sizeof chip))
1617 goto out;
1618 r = -ENXIO;
1619 if (!irqchip_in_kernel(kvm))
1620 goto out;
1621 r = kvm_vm_ioctl_get_irqchip(kvm, &chip);
1622 if (r)
1623 goto out;
1624 r = -EFAULT;
1625 if (copy_to_user(argp, &chip, sizeof chip))
1626 goto out;
1627 r = 0;
1628 break;
1629 }
1630 case KVM_SET_IRQCHIP: {
1631 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1632 struct kvm_irqchip chip;
1633
1634 r = -EFAULT;
1635 if (copy_from_user(&chip, argp, sizeof chip))
1636 goto out;
1637 r = -ENXIO;
1638 if (!irqchip_in_kernel(kvm))
1639 goto out;
1640 r = kvm_vm_ioctl_set_irqchip(kvm, &chip);
1641 if (r)
1642 goto out;
1643 r = 0;
1644 break;
1645 }
1646 default:
1647 ;
1648 }
1649out:
1650 return r;
1651}
1652
a16b043c 1653static void kvm_init_msr_list(void)
043405e1
CO		 1654{
1655 u32 dummy[2];
1656 unsigned i, j;
1657
1658 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1659 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1660 continue;
1661 if (j < i)
1662 msrs_to_save[j] = msrs_to_save[i];
1663 j++;
1664 }
1665 num_msrs_to_save = j;
1666}
1667
bbd9b64e
CO		 1668/*
1669 * Only apic need an MMIO device hook, so shortcut now..
1670 */
1671static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
1672 gpa_t addr)
1673{
1674 struct kvm_io_device *dev;
1675
ad312c7c
ZX		 1676 if (vcpu->arch.apic) {
1677 dev = &vcpu->arch.apic->dev;
bbd9b64e
CO		 1678 if (dev->in_range(dev, addr))
1679 return dev;
1680 }
1681 return NULL;
1682}
1683
1684
1685static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
1686 gpa_t addr)
1687{
1688 struct kvm_io_device *dev;
1689
1690 dev = vcpu_find_pervcpu_dev(vcpu, addr);
1691 if (dev == NULL)
1692 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr);
1693 return dev;
1694}
1695
1696int emulator_read_std(unsigned long addr,
1697 void *val,
1698 unsigned int bytes,
1699 struct kvm_vcpu *vcpu)
1700{
1701 void *data = val;
10589a46 1702 int r = X86EMUL_CONTINUE;
bbd9b64e 1703
72dc67a6 1704 down_read(&vcpu->kvm->slots_lock);
bbd9b64e 1705 while (bytes) {
ad312c7c 1706 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1707 unsigned offset = addr & (PAGE_SIZE-1);
1708 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1709 int ret;
1710
10589a46
MT		 1711 if (gpa == UNMAPPED_GVA) {
1712 r = X86EMUL_PROPAGATE_FAULT;
1713 goto out;
1714 }
bbd9b64e 1715 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1716 if (ret < 0) {
1717 r = X86EMUL_UNHANDLEABLE;
1718 goto out;
1719 }
bbd9b64e
CO		 1720
1721 bytes -= tocopy;
1722 data += tocopy;
1723 addr += tocopy;
1724 }
10589a46 1725out:
72dc67a6 1726 up_read(&vcpu->kvm->slots_lock);
10589a46 1727 return r;
bbd9b64e
CO		 1728}
1729EXPORT_SYMBOL_GPL(emulator_read_std);
1730
bbd9b64e
CO		 1731static int emulator_read_emulated(unsigned long addr,
1732 void *val,
1733 unsigned int bytes,
1734 struct kvm_vcpu *vcpu)
1735{
1736 struct kvm_io_device *mmio_dev;
1737 gpa_t gpa;
1738
1739 if (vcpu->mmio_read_completed) {
1740 memcpy(val, vcpu->mmio_data, bytes);
1741 vcpu->mmio_read_completed = 0;
1742 return X86EMUL_CONTINUE;
1743 }
1744
72dc67a6 1745 down_read(&vcpu->kvm->slots_lock);
ad312c7c 1746 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
72dc67a6 1747 up_read(&vcpu->kvm->slots_lock);
bbd9b64e
CO		 1748
1749 /* For APIC access vmexit */
1750 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1751 goto mmio;
1752
1753 if (emulator_read_std(addr, val, bytes, vcpu)
1754 == X86EMUL_CONTINUE)
1755 return X86EMUL_CONTINUE;
1756 if (gpa == UNMAPPED_GVA)
1757 return X86EMUL_PROPAGATE_FAULT;
1758
1759mmio:
1760 /*
1761 * Is this MMIO handled locally?
1762 */
10589a46 1763 mutex_lock(&vcpu->kvm->lock);
bbd9b64e
CO		 1764 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa);
1765 if (mmio_dev) {
1766 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 1767 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1768 return X86EMUL_CONTINUE;
1769 }
10589a46 1770 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1771
1772 vcpu->mmio_needed = 1;
1773 vcpu->mmio_phys_addr = gpa;
1774 vcpu->mmio_size = bytes;
1775 vcpu->mmio_is_write = 0;
1776
1777 return X86EMUL_UNHANDLEABLE;
1778}
1779
1780static int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
1781 const void *val, int bytes)
1782{
1783 int ret;
1784
72dc67a6 1785 down_read(&vcpu->kvm->slots_lock);
bbd9b64e 1786 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
10589a46 1787 if (ret < 0) {
72dc67a6 1788 up_read(&vcpu->kvm->slots_lock);
bbd9b64e 1789 return 0;
10589a46 1790 }
bbd9b64e 1791 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
72dc67a6 1792 up_read(&vcpu->kvm->slots_lock);
bbd9b64e
CO		 1793 return 1;
1794}
1795
1796static int emulator_write_emulated_onepage(unsigned long addr,
1797 const void *val,
1798 unsigned int bytes,
1799 struct kvm_vcpu *vcpu)
1800{
1801 struct kvm_io_device *mmio_dev;
10589a46
MT		 1802 gpa_t gpa;
1803
72dc67a6 1804 down_read(&vcpu->kvm->slots_lock);
10589a46 1805 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
72dc67a6 1806 up_read(&vcpu->kvm->slots_lock);
bbd9b64e
CO		 1807
1808 if (gpa == UNMAPPED_GVA) {
c3c91fee 1809 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 1810 return X86EMUL_PROPAGATE_FAULT;
1811 }
1812
1813 /* For APIC access vmexit */
1814 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1815 goto mmio;
1816
1817 if (emulator_write_phys(vcpu, gpa, val, bytes))
1818 return X86EMUL_CONTINUE;
1819
1820mmio:
1821 /*
1822 * Is this MMIO handled locally?
1823 */
10589a46 1824 mutex_lock(&vcpu->kvm->lock);
bbd9b64e
CO		 1825 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa);
1826 if (mmio_dev) {
1827 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 1828 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1829 return X86EMUL_CONTINUE;
1830 }
10589a46 1831 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1832
1833 vcpu->mmio_needed = 1;
1834 vcpu->mmio_phys_addr = gpa;
1835 vcpu->mmio_size = bytes;
1836 vcpu->mmio_is_write = 1;
1837 memcpy(vcpu->mmio_data, val, bytes);
1838
1839 return X86EMUL_CONTINUE;
1840}
1841
1842int emulator_write_emulated(unsigned long addr,
1843 const void *val,
1844 unsigned int bytes,
1845 struct kvm_vcpu *vcpu)
1846{
1847 /* Crossing a page boundary? */
1848 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
1849 int rc, now;
1850
1851 now = -addr & ~PAGE_MASK;
1852 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
1853 if (rc != X86EMUL_CONTINUE)
1854 return rc;
1855 addr += now;
1856 val += now;
1857 bytes -= now;
1858 }
1859 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
1860}
1861EXPORT_SYMBOL_GPL(emulator_write_emulated);
1862
1863static int emulator_cmpxchg_emulated(unsigned long addr,
1864 const void *old,
1865 const void *new,
1866 unsigned int bytes,
1867 struct kvm_vcpu *vcpu)
1868{
1869 static int reported;
1870
1871 if (!reported) {
1872 reported = 1;
1873 printk(KERN_WARNING "kvm: emulating exchange as write\n");
1874 }
2bacc55c
MT		 1875#ifndef CONFIG_X86_64
1876 /* guests cmpxchg8b have to be emulated atomically */
1877 if (bytes == 8) {
10589a46 1878 gpa_t gpa;
2bacc55c 1879 struct page *page;
c0b49b0d 1880 char *kaddr;
2bacc55c
MT		 1881 u64 val;
1882
72dc67a6 1883 down_read(&vcpu->kvm->slots_lock);
10589a46
MT		 1884 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
1885
2bacc55c
MT		 1886 if (gpa == UNMAPPED_GVA ||
1887 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1888 goto emul_write;
1889
1890 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
1891 goto emul_write;
1892
1893 val = *(u64 *)new;
72dc67a6
IE		 1894
1895 down_read(&current->mm->mmap_sem);
2bacc55c 1896 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1897 up_read(&current->mm->mmap_sem);
1898
c0b49b0d
AM		 1899 kaddr = kmap_atomic(page, KM_USER0);
1900 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
1901 kunmap_atomic(kaddr, KM_USER0);
2bacc55c 1902 kvm_release_page_dirty(page);
10589a46 1903 emul_write:
72dc67a6 1904 up_read(&vcpu->kvm->slots_lock);
2bacc55c 1905 }
2bacc55c
MT		 1906#endif
1907
bbd9b64e
CO		 1908 return emulator_write_emulated(addr, new, bytes, vcpu);
1909}
1910
1911static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
1912{
1913 return kvm_x86_ops->get_segment_base(vcpu, seg);
1914}
1915
1916int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
1917{
1918 return X86EMUL_CONTINUE;
1919}
1920
1921int emulate_clts(struct kvm_vcpu *vcpu)
1922{
ad312c7c 1923 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 1924 return X86EMUL_CONTINUE;
1925}
1926
1927int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
1928{
1929 struct kvm_vcpu *vcpu = ctxt->vcpu;
1930
1931 switch (dr) {
1932 case 0 ... 3:
1933 *dest = kvm_x86_ops->get_dr(vcpu, dr);
1934 return X86EMUL_CONTINUE;
1935 default:
1936 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __FUNCTION__, dr);
1937 return X86EMUL_UNHANDLEABLE;
1938 }
1939}
1940
1941int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
1942{
1943 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
1944 int exception;
1945
1946 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
1947 if (exception) {
1948 /* FIXME: better handling */
1949 return X86EMUL_UNHANDLEABLE;
1950 }
1951 return X86EMUL_CONTINUE;
1952}
1953
1954void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
1955{
1956 static int reported;
1957 u8 opcodes[4];
ad312c7c 1958 unsigned long rip = vcpu->arch.rip;
bbd9b64e
CO		 1959 unsigned long rip_linear;
1960
1961 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
1962
1963 if (reported)
1964 return;
1965
1966 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
1967
1968 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
1969 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
1970 reported = 1;
1971}
1972EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
1973
14af3f3c 1974static struct x86_emulate_ops emulate_ops = {
bbd9b64e 1975 .read_std = emulator_read_std,
bbd9b64e
CO		 1976 .read_emulated = emulator_read_emulated,
1977 .write_emulated = emulator_write_emulated,
1978 .cmpxchg_emulated = emulator_cmpxchg_emulated,
1979};
1980
1981int emulate_instruction(struct kvm_vcpu *vcpu,
1982 struct kvm_run *run,
1983 unsigned long cr2,
1984 u16 error_code,
571008da 1985 int emulation_type)
bbd9b64e
CO		 1986{
1987 int r;
571008da 1988 struct decode_cache *c;
bbd9b64e 1989
ad312c7c 1990 vcpu->arch.mmio_fault_cr2 = cr2;
bbd9b64e
CO		 1991 kvm_x86_ops->cache_regs(vcpu);
1992
1993 vcpu->mmio_is_write = 0;
ad312c7c 1994 vcpu->arch.pio.string = 0;
bbd9b64e 1995
571008da 1996 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 1997 int cs_db, cs_l;
1998 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
1999
ad312c7c
ZX		 2000 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2001 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2002 vcpu->arch.emulate_ctxt.mode =
2003 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2004 ? X86EMUL_MODE_REAL : cs_l
2005 ? X86EMUL_MODE_PROT64 : cs_db
2006 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2007
ad312c7c
ZX		 2008 if (vcpu->arch.emulate_ctxt.mode == X86EMUL_MODE_PROT64) {
2009 vcpu->arch.emulate_ctxt.cs_base = 0;
2010 vcpu->arch.emulate_ctxt.ds_base = 0;
2011 vcpu->arch.emulate_ctxt.es_base = 0;
2012 vcpu->arch.emulate_ctxt.ss_base = 0;
bbd9b64e 2013 } else {
ad312c7c 2014 vcpu->arch.emulate_ctxt.cs_base =
bbd9b64e 2015 get_segment_base(vcpu, VCPU_SREG_CS);
ad312c7c 2016 vcpu->arch.emulate_ctxt.ds_base =
bbd9b64e 2017 get_segment_base(vcpu, VCPU_SREG_DS);
ad312c7c 2018 vcpu->arch.emulate_ctxt.es_base =
bbd9b64e 2019 get_segment_base(vcpu, VCPU_SREG_ES);
ad312c7c 2020 vcpu->arch.emulate_ctxt.ss_base =
bbd9b64e
CO		 2021 get_segment_base(vcpu, VCPU_SREG_SS);
2022 }
2023
ad312c7c 2024 vcpu->arch.emulate_ctxt.gs_base =
bbd9b64e 2025 get_segment_base(vcpu, VCPU_SREG_GS);
ad312c7c 2026 vcpu->arch.emulate_ctxt.fs_base =
bbd9b64e
CO		 2027 get_segment_base(vcpu, VCPU_SREG_FS);
2028
ad312c7c 2029 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2030
2031 /* Reject the instructions other than VMCALL/VMMCALL when
2032 * try to emulate invalid opcode */
2033 c = &vcpu->arch.emulate_ctxt.decode;
2034 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2035 (!(c->twobyte && c->b == 0x01 &&
2036 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2037 c->modrm_mod == 3 && c->modrm_rm == 1)))
2038 return EMULATE_FAIL;
2039
f2b5756b 2040 ++vcpu->stat.insn_emulation;
bbd9b64e 2041 if (r) {
f2b5756b 2042 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2043 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2044 return EMULATE_DONE;
2045 return EMULATE_FAIL;
2046 }
2047 }
2048
ad312c7c 2049 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2050
ad312c7c 2051 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2052 return EMULATE_DO_MMIO;
2053
2054 if ((r || vcpu->mmio_is_write) && run) {
2055 run->exit_reason = KVM_EXIT_MMIO;
2056 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2057 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2058 run->mmio.len = vcpu->mmio_size;
2059 run->mmio.is_write = vcpu->mmio_is_write;
2060 }
2061
2062 if (r) {
2063 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2064 return EMULATE_DONE;
2065 if (!vcpu->mmio_needed) {
2066 kvm_report_emulation_failure(vcpu, "mmio");
2067 return EMULATE_FAIL;
2068 }
2069 return EMULATE_DO_MMIO;
2070 }
2071
2072 kvm_x86_ops->decache_regs(vcpu);
ad312c7c 2073 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2074
2075 if (vcpu->mmio_is_write) {
2076 vcpu->mmio_needed = 0;
2077 return EMULATE_DO_MMIO;
2078 }
2079
2080 return EMULATE_DONE;
2081}
2082EXPORT_SYMBOL_GPL(emulate_instruction);
2083
de7d789a
CO		 2084static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2085{
2086 int i;
2087
ad312c7c
ZX		 2088 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2089 if (vcpu->arch.pio.guest_pages[i]) {
2090 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2091 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2092 }
2093}
2094
2095static int pio_copy_data(struct kvm_vcpu *vcpu)
2096{
ad312c7c 2097 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2098 void *q;
2099 unsigned bytes;
ad312c7c 2100 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2101
ad312c7c 2102 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2103 PAGE_KERNEL);
2104 if (!q) {
2105 free_pio_guest_pages(vcpu);
2106 return -ENOMEM;
2107 }
ad312c7c
ZX		 2108 q += vcpu->arch.pio.guest_page_offset;
2109 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2110 if (vcpu->arch.pio.in)
de7d789a
CO		 2111 memcpy(q, p, bytes);
2112 else
2113 memcpy(p, q, bytes);
ad312c7c 2114 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2115 vunmap(q);
2116 free_pio_guest_pages(vcpu);
2117 return 0;
2118}
2119
2120int complete_pio(struct kvm_vcpu *vcpu)
2121{
ad312c7c 2122 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2123 long delta;
2124 int r;
2125
2126 kvm_x86_ops->cache_regs(vcpu);
2127
2128 if (!io->string) {
2129 if (io->in)
ad312c7c 2130 memcpy(&vcpu->arch.regs[VCPU_REGS_RAX], vcpu->arch.pio_data,
de7d789a
CO		 2131 io->size);
2132 } else {
2133 if (io->in) {
2134 r = pio_copy_data(vcpu);
2135 if (r) {
2136 kvm_x86_ops->cache_regs(vcpu);
2137 return r;
2138 }
2139 }
2140
2141 delta = 1;
2142 if (io->rep) {
2143 delta *= io->cur_count;
2144 /*
2145 * The size of the register should really depend on
2146 * current address size.
2147 */
ad312c7c 2148 vcpu->arch.regs[VCPU_REGS_RCX] -= delta;
de7d789a
CO		 2149 }
2150 if (io->down)
2151 delta = -delta;
2152 delta *= io->size;
2153 if (io->in)
ad312c7c 2154 vcpu->arch.regs[VCPU_REGS_RDI] += delta;
de7d789a 2155 else
ad312c7c 2156 vcpu->arch.regs[VCPU_REGS_RSI] += delta;
de7d789a
CO		 2157 }
2158
2159 kvm_x86_ops->decache_regs(vcpu);
2160
2161 io->count -= io->cur_count;
2162 io->cur_count = 0;
2163
2164 return 0;
2165}
2166
2167static void kernel_pio(struct kvm_io_device *pio_dev,
2168 struct kvm_vcpu *vcpu,
2169 void *pd)
2170{
2171 /* TODO: String I/O for in kernel device */
2172
2173 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2174 if (vcpu->arch.pio.in)
2175 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2176 vcpu->arch.pio.size,
de7d789a
CO		 2177 pd);
2178 else
ad312c7c
ZX		 2179 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2180 vcpu->arch.pio.size,
de7d789a
CO		 2181 pd);
2182 mutex_unlock(&vcpu->kvm->lock);
2183}
2184
2185static void pio_string_write(struct kvm_io_device *pio_dev,
2186 struct kvm_vcpu *vcpu)
2187{
ad312c7c
ZX		 2188 struct kvm_pio_request *io = &vcpu->arch.pio;
2189 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2190 int i;
2191
2192 mutex_lock(&vcpu->kvm->lock);
2193 for (i = 0; i < io->cur_count; i++) {
2194 kvm_iodevice_write(pio_dev, io->port,
2195 io->size,
2196 pd);
2197 pd += io->size;
2198 }
2199 mutex_unlock(&vcpu->kvm->lock);
2200}
2201
2202static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
2203 gpa_t addr)
2204{
2205 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr);
2206}
2207
2208int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2209 int size, unsigned port)
2210{
2211 struct kvm_io_device *pio_dev;
2212
2213 vcpu->run->exit_reason = KVM_EXIT_IO;
2214 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2215 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2216 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2217 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2218 vcpu->run->io.port = vcpu->arch.pio.port = port;
2219 vcpu->arch.pio.in = in;
2220 vcpu->arch.pio.string = 0;
2221 vcpu->arch.pio.down = 0;
2222 vcpu->arch.pio.guest_page_offset = 0;
2223 vcpu->arch.pio.rep = 0;
de7d789a
CO		 2224
2225 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2226 memcpy(vcpu->arch.pio_data, &vcpu->arch.regs[VCPU_REGS_RAX], 4);
de7d789a
CO		 2227 kvm_x86_ops->decache_regs(vcpu);
2228
2229 kvm_x86_ops->skip_emulated_instruction(vcpu);
2230
2231 pio_dev = vcpu_find_pio_dev(vcpu, port);
2232 if (pio_dev) {
ad312c7c 2233 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2234 complete_pio(vcpu);
2235 return 1;
2236 }
2237 return 0;
2238}
2239EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2240
2241int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2242 int size, unsigned long count, int down,
2243 gva_t address, int rep, unsigned port)
2244{
2245 unsigned now, in_page;
2246 int i, ret = 0;
2247 int nr_pages = 1;
2248 struct page *page;
2249 struct kvm_io_device *pio_dev;
2250
2251 vcpu->run->exit_reason = KVM_EXIT_IO;
2252 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2253 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2254 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2255 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2256 vcpu->run->io.port = vcpu->arch.pio.port = port;
2257 vcpu->arch.pio.in = in;
2258 vcpu->arch.pio.string = 1;
2259 vcpu->arch.pio.down = down;
2260 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2261 vcpu->arch.pio.rep = rep;
de7d789a
CO		 2262
2263 if (!count) {
2264 kvm_x86_ops->skip_emulated_instruction(vcpu);
2265 return 1;
2266 }
2267
2268 if (!down)
2269 in_page = PAGE_SIZE - offset_in_page(address);
2270 else
2271 in_page = offset_in_page(address) + size;
2272 now = min(count, (unsigned long)in_page / size);
2273 if (!now) {
2274 /*
2275 * String I/O straddles page boundary. Pin two guest pages
2276 * so that we satisfy atomicity constraints. Do just one
2277 * transaction to avoid complexity.
2278 */
2279 nr_pages = 2;
2280 now = 1;
2281 }
2282 if (down) {
2283 /*
2284 * String I/O in reverse. Yuck. Kill the guest, fix later.
2285 */
2286 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2287 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2288 return 1;
2289 }
2290 vcpu->run->io.count = now;
ad312c7c 2291 vcpu->arch.pio.cur_count = now;
de7d789a 2292
ad312c7c 2293 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2294 kvm_x86_ops->skip_emulated_instruction(vcpu);
2295
2296 for (i = 0; i < nr_pages; ++i) {
72dc67a6 2297 down_read(&vcpu->kvm->slots_lock);
de7d789a 2298 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2299 vcpu->arch.pio.guest_pages[i] = page;
72dc67a6 2300 up_read(&vcpu->kvm->slots_lock);
de7d789a 2301 if (!page) {
c1a5d4f9 2302 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2303 free_pio_guest_pages(vcpu);
2304 return 1;
2305 }
2306 }
2307
2308 pio_dev = vcpu_find_pio_dev(vcpu, port);
ad312c7c 2309 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2310 /* string PIO write */
2311 ret = pio_copy_data(vcpu);
2312 if (ret >= 0 && pio_dev) {
2313 pio_string_write(pio_dev, vcpu);
2314 complete_pio(vcpu);
ad312c7c 2315 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2316 ret = 1;
2317 }
2318 } else if (pio_dev)
2319 pr_unimpl(vcpu, "no string pio read support yet, "
2320 "port %x size %d count %ld\n",
2321 port, size, count);
2322
2323 return ret;
2324}
2325EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2326
f8c16bba 2327int kvm_arch_init(void *opaque)
043405e1 2328{
56c6d28a 2329 int r;
f8c16bba
ZX		 2330 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2331
f8c16bba
ZX		 2332 if (kvm_x86_ops) {
2333 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2334 r = -EEXIST;
2335 goto out;
f8c16bba
ZX		 2336 }
2337
2338 if (!ops->cpu_has_kvm_support()) {
2339 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2340 r = -EOPNOTSUPP;
2341 goto out;
f8c16bba
ZX		 2342 }
2343 if (ops->disabled_by_bios()) {
2344 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2345 r = -EOPNOTSUPP;
2346 goto out;
f8c16bba
ZX		 2347 }
2348
97db56ce
AK		 2349 r = kvm_mmu_module_init();
2350 if (r)
2351 goto out;
2352
2353 kvm_init_msr_list();
2354
f8c16bba 2355 kvm_x86_ops = ops;
56c6d28a 2356 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
f8c16bba 2357 return 0;
56c6d28a
ZX		 2358
2359out:
56c6d28a 2360 return r;
043405e1 2361}
8776e519 2362
f8c16bba
ZX		 2363void kvm_arch_exit(void)
2364{
2365 kvm_x86_ops = NULL;
56c6d28a
ZX		 2366 kvm_mmu_module_exit();
2367}
f8c16bba 2368
8776e519
HB		 2369int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2370{
2371 ++vcpu->stat.halt_exits;
2372 if (irqchip_in_kernel(vcpu->kvm)) {
ad312c7c 2373 vcpu->arch.mp_state = VCPU_MP_STATE_HALTED;
8776e519 2374 kvm_vcpu_block(vcpu);
ad312c7c 2375 if (vcpu->arch.mp_state != VCPU_MP_STATE_RUNNABLE)
8776e519
HB		 2376 return -EINTR;
2377 return 1;
2378 } else {
2379 vcpu->run->exit_reason = KVM_EXIT_HLT;
2380 return 0;
2381 }
2382}
2383EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2384
2385int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2386{
2387 unsigned long nr, a0, a1, a2, a3, ret;
2388
2389 kvm_x86_ops->cache_regs(vcpu);
2390
ad312c7c
ZX		 2391 nr = vcpu->arch.regs[VCPU_REGS_RAX];
2392 a0 = vcpu->arch.regs[VCPU_REGS_RBX];
2393 a1 = vcpu->arch.regs[VCPU_REGS_RCX];
2394 a2 = vcpu->arch.regs[VCPU_REGS_RDX];
2395 a3 = vcpu->arch.regs[VCPU_REGS_RSI];
8776e519
HB		 2396
2397 if (!is_long_mode(vcpu)) {
2398 nr &= 0xFFFFFFFF;
2399 a0 &= 0xFFFFFFFF;
2400 a1 &= 0xFFFFFFFF;
2401 a2 &= 0xFFFFFFFF;
2402 a3 &= 0xFFFFFFFF;
2403 }
2404
2405 switch (nr) {
b93463aa
AK		 2406 case KVM_HC_VAPIC_POLL_IRQ:
2407 ret = 0;
2408 break;
8776e519
HB		 2409 default:
2410 ret = -KVM_ENOSYS;
2411 break;
2412 }
ad312c7c 2413 vcpu->arch.regs[VCPU_REGS_RAX] = ret;
8776e519 2414 kvm_x86_ops->decache_regs(vcpu);
f11c3a8d 2415 ++vcpu->stat.hypercalls;
8776e519
HB		 2416 return 0;
2417}
2418EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2419
2420int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2421{
2422 char instruction[3];
2423 int ret = 0;
2424
8776e519
HB		 2425
2426 /*
2427 * Blow out the MMU to ensure that no other VCPU has an active mapping
2428 * to ensure that the updated hypercall appears atomically across all
2429 * VCPUs.
2430 */
2431 kvm_mmu_zap_all(vcpu->kvm);
2432
2433 kvm_x86_ops->cache_regs(vcpu);
2434 kvm_x86_ops->patch_hypercall(vcpu, instruction);
ad312c7c 2435 if (emulator_write_emulated(vcpu->arch.rip, instruction, 3, vcpu)
8776e519
HB		 2436 != X86EMUL_CONTINUE)
2437 ret = -EFAULT;
2438
8776e519
HB		 2439 return ret;
2440}
2441
2442static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2443{
2444 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2445}
2446
2447void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2448{
2449 struct descriptor_table dt = { limit, base };
2450
2451 kvm_x86_ops->set_gdt(vcpu, &dt);
2452}
2453
2454void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2455{
2456 struct descriptor_table dt = { limit, base };
2457
2458 kvm_x86_ops->set_idt(vcpu, &dt);
2459}
2460
2461void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2462 unsigned long *rflags)
2463{
2464 lmsw(vcpu, msw);
2465 *rflags = kvm_x86_ops->get_rflags(vcpu);
2466}
2467
2468unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2469{
2470 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2471 switch (cr) {
2472 case 0:
ad312c7c 2473 return vcpu->arch.cr0;
8776e519 2474 case 2:
ad312c7c 2475 return vcpu->arch.cr2;
8776e519 2476 case 3:
ad312c7c 2477 return vcpu->arch.cr3;
8776e519 2478 case 4:
ad312c7c 2479 return vcpu->arch.cr4;
152ff9be
JR		 2480 case 8:
2481 return get_cr8(vcpu);
8776e519
HB		 2482 default:
2483 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __FUNCTION__, cr);
2484 return 0;
2485 }
2486}
2487
2488void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2489 unsigned long *rflags)
2490{
2491 switch (cr) {
2492 case 0:
ad312c7c 2493 set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2494 *rflags = kvm_x86_ops->get_rflags(vcpu);
2495 break;
2496 case 2:
ad312c7c 2497 vcpu->arch.cr2 = val;
8776e519
HB		 2498 break;
2499 case 3:
2500 set_cr3(vcpu, val);
2501 break;
2502 case 4:
ad312c7c 2503 set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2504 break;
152ff9be
JR		 2505 case 8:
2506 set_cr8(vcpu, val & 0xfUL);
2507 break;
8776e519
HB		 2508 default:
2509 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __FUNCTION__, cr);
2510 }
2511}
2512
07716717
DK		 2513static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2514{
ad312c7c
ZX		 2515 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2516 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2517
2518 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2519 /* when no next entry is found, the current entry[i] is reselected */
2520 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2521 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2522 if (ej->function == e->function) {
2523 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2524 return j;
2525 }
2526 }
2527 return 0; /* silence gcc, even though control never reaches here */
2528}
2529
2530/* find an entry with matching function, matching index (if needed), and that
2531 * should be read next (if it's stateful) */
2532static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2533 u32 function, u32 index)
2534{
2535 if (e->function != function)
2536 return 0;
2537 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2538 return 0;
2539 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2540 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2541 return 0;
2542 return 1;
2543}
2544
8776e519
HB		 2545void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2546{
2547 int i;
07716717
DK		 2548 u32 function, index;
2549 struct kvm_cpuid_entry2 *e, *best;
8776e519
HB		 2550
2551 kvm_x86_ops->cache_regs(vcpu);
ad312c7c
ZX		 2552 function = vcpu->arch.regs[VCPU_REGS_RAX];
2553 index = vcpu->arch.regs[VCPU_REGS_RCX];
2554 vcpu->arch.regs[VCPU_REGS_RAX] = 0;
2555 vcpu->arch.regs[VCPU_REGS_RBX] = 0;
2556 vcpu->arch.regs[VCPU_REGS_RCX] = 0;
2557 vcpu->arch.regs[VCPU_REGS_RDX] = 0;
8776e519 2558 best = NULL;
ad312c7c
ZX		 2559 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2560 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2561 if (is_matching_cpuid_entry(e, function, index)) {
2562 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2563 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2564 best = e;
2565 break;
2566 }
2567 /*
2568 * Both basic or both extended?
2569 */
2570 if (((e->function ^ function) & 0x80000000) == 0)
2571 if (!best || e->function > best->function)
2572 best = e;
2573 }
2574 if (best) {
ad312c7c
ZX		 2575 vcpu->arch.regs[VCPU_REGS_RAX] = best->eax;
2576 vcpu->arch.regs[VCPU_REGS_RBX] = best->ebx;
2577 vcpu->arch.regs[VCPU_REGS_RCX] = best->ecx;
2578 vcpu->arch.regs[VCPU_REGS_RDX] = best->edx;
8776e519
HB		 2579 }
2580 kvm_x86_ops->decache_regs(vcpu);
2581 kvm_x86_ops->skip_emulated_instruction(vcpu);
2582}
2583EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2584
b6c7a5dc
HB		 2585/*
2586 * Check if userspace requested an interrupt window, and that the
2587 * interrupt window is open.
2588 *
2589 * No need to exit to userspace if we already have an interrupt queued.
2590 */
2591static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2592 struct kvm_run *kvm_run)
2593{
ad312c7c 2594 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2595 kvm_run->request_interrupt_window &&
ad312c7c 2596 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2597 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2598}
2599
2600static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2601 struct kvm_run *kvm_run)
2602{
2603 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2604 kvm_run->cr8 = get_cr8(vcpu);
2605 kvm_run->apic_base = kvm_get_apic_base(vcpu);
2606 if (irqchip_in_kernel(vcpu->kvm))
2607 kvm_run->ready_for_interrupt_injection = 1;
2608 else
2609 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2610 (vcpu->arch.interrupt_window_open &&
2611 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2612}
2613
b93463aa
AK		 2614static void vapic_enter(struct kvm_vcpu *vcpu)
2615{
2616 struct kvm_lapic *apic = vcpu->arch.apic;
2617 struct page *page;
2618
2619 if (!apic || !apic->vapic_addr)
2620 return;
2621
10589a46 2622 down_read(&current->mm->mmap_sem);
b93463aa 2623 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
10589a46 2624 up_read(&current->mm->mmap_sem);
72dc67a6
IE		 2625
2626 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2627}
2628
2629static void vapic_exit(struct kvm_vcpu *vcpu)
2630{
2631 struct kvm_lapic *apic = vcpu->arch.apic;
2632
2633 if (!apic || !apic->vapic_addr)
2634 return;
2635
2636 kvm_release_page_dirty(apic->vapic_page);
2637 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
2638}
2639
b6c7a5dc
HB		 2640static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2641{
2642 int r;
2643
ad312c7c 2644 if (unlikely(vcpu->arch.mp_state == VCPU_MP_STATE_SIPI_RECEIVED)) {
b6c7a5dc 2645 pr_debug("vcpu %d received sipi with vector # %x\n",
ad312c7c 2646 vcpu->vcpu_id, vcpu->arch.sipi_vector);
b6c7a5dc
HB		 2647 kvm_lapic_reset(vcpu);
2648 r = kvm_x86_ops->vcpu_reset(vcpu);
2649 if (r)
2650 return r;
ad312c7c 2651 vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 2652 }
2653
b93463aa
AK		 2654 vapic_enter(vcpu);
2655
b6c7a5dc
HB		 2656preempted:
2657 if (vcpu->guest_debug.enabled)
2658 kvm_x86_ops->guest_debug_pre(vcpu);
2659
2660again:
2661 r = kvm_mmu_reload(vcpu);
2662 if (unlikely(r))
2663 goto out;
2664
2f52d58c
AK		 2665 if (vcpu->requests) {
2666 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2667 __kvm_migrate_apic_timer(vcpu);
b93463aa
AK		 2668 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2669 &vcpu->requests)) {
2670 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2671 r = 0;
2672 goto out;
2673 }
2f52d58c 2674 }
b93463aa 2675
b6c7a5dc
HB		 2676 kvm_inject_pending_timer_irqs(vcpu);
2677
2678 preempt_disable();
2679
2680 kvm_x86_ops->prepare_guest_switch(vcpu);
2681 kvm_load_guest_fpu(vcpu);
2682
2683 local_irq_disable();
2684
6c142801
AK		 2685 if (need_resched()) {
2686 local_irq_enable();
2687 preempt_enable();
2688 r = 1;
2689 goto out;
2690 }
2691
b6c7a5dc
HB		 2692 if (signal_pending(current)) {
2693 local_irq_enable();
2694 preempt_enable();
2695 r = -EINTR;
2696 kvm_run->exit_reason = KVM_EXIT_INTR;
2697 ++vcpu->stat.signal_exits;
2698 goto out;
2699 }
2700
ad312c7c 2701 if (vcpu->arch.exception.pending)
298101da
AK		 2702 __queue_exception(vcpu);
2703 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2704 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2705 else
b6c7a5dc
HB		 2706 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2707
b93463aa
AK		 2708 kvm_lapic_sync_to_vapic(vcpu);
2709
b6c7a5dc
HB		 2710 vcpu->guest_mode = 1;
2711 kvm_guest_enter();
2712
2713 if (vcpu->requests)
2714 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2715 kvm_x86_ops->tlb_flush(vcpu);
2716
2717 kvm_x86_ops->run(vcpu, kvm_run);
2718
2719 vcpu->guest_mode = 0;
2720 local_irq_enable();
2721
2722 ++vcpu->stat.exits;
2723
2724 /*
2725 * We must have an instruction between local_irq_enable() and
2726 * kvm_guest_exit(), so the timer interrupt isn't delayed by
2727 * the interrupt shadow. The stat.exits increment will do nicely.
2728 * But we need to prevent reordering, hence this barrier():
2729 */
2730 barrier();
2731
2732 kvm_guest_exit();
2733
2734 preempt_enable();
2735
2736 /*
2737 * Profile KVM exit RIPs:
2738 */
2739 if (unlikely(prof_on == KVM_PROFILING)) {
2740 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2741 profile_hit(KVM_PROFILING, (void *)vcpu->arch.rip);
b6c7a5dc
HB		 2742 }
2743
ad312c7c
ZX		 2744 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
2745 vcpu->arch.exception.pending = false;
298101da 2746
b93463aa
AK		 2747 kvm_lapic_sync_from_vapic(vcpu);
2748
b6c7a5dc
HB		 2749 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
2750
2751 if (r > 0) {
2752 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2753 r = -EINTR;
2754 kvm_run->exit_reason = KVM_EXIT_INTR;
2755 ++vcpu->stat.request_irq_exits;
2756 goto out;
2757 }
e1beb1d3 2758 if (!need_resched())
b6c7a5dc 2759 goto again;
b6c7a5dc
HB		 2760 }
2761
2762out:
2763 if (r > 0) {
2764 kvm_resched(vcpu);
2765 goto preempted;
2766 }
2767
2768 post_kvm_run_save(vcpu, kvm_run);
2769
b93463aa
AK		 2770 vapic_exit(vcpu);
2771
b6c7a5dc
HB		 2772 return r;
2773}
2774
2775int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2776{
2777 int r;
2778 sigset_t sigsaved;
2779
2780 vcpu_load(vcpu);
2781
ad312c7c 2782 if (unlikely(vcpu->arch.mp_state == VCPU_MP_STATE_UNINITIALIZED)) {
b6c7a5dc
HB		 2783 kvm_vcpu_block(vcpu);
2784 vcpu_put(vcpu);
2785 return -EAGAIN;
2786 }
2787
2788 if (vcpu->sigset_active)
2789 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
2790
2791 /* re-sync apic's tpr */
2792 if (!irqchip_in_kernel(vcpu->kvm))
2793 set_cr8(vcpu, kvm_run->cr8);
2794
ad312c7c 2795 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 2796 r = complete_pio(vcpu);
2797 if (r)
2798 goto out;
2799 }
2800#if CONFIG_HAS_IOMEM
2801 if (vcpu->mmio_needed) {
2802 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
2803 vcpu->mmio_read_completed = 1;
2804 vcpu->mmio_needed = 0;
2805 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 2806 vcpu->arch.mmio_fault_cr2, 0,
2807 EMULTYPE_NO_DECODE);
b6c7a5dc
HB		 2808 if (r == EMULATE_DO_MMIO) {
2809 /*
2810 * Read-modify-write. Back to userspace.
2811 */
2812 r = 0;
2813 goto out;
2814 }
2815 }
2816#endif
2817 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) {
2818 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2819 vcpu->arch.regs[VCPU_REGS_RAX] = kvm_run->hypercall.ret;
b6c7a5dc
HB		 2820 kvm_x86_ops->decache_regs(vcpu);
2821 }
2822
2823 r = __vcpu_run(vcpu, kvm_run);
2824
2825out:
2826 if (vcpu->sigset_active)
2827 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
2828
2829 vcpu_put(vcpu);
2830 return r;
2831}
2832
2833int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
2834{
2835 vcpu_load(vcpu);
2836
2837 kvm_x86_ops->cache_regs(vcpu);
2838
ad312c7c
ZX		 2839 regs->rax = vcpu->arch.regs[VCPU_REGS_RAX];
2840 regs->rbx = vcpu->arch.regs[VCPU_REGS_RBX];
2841 regs->rcx = vcpu->arch.regs[VCPU_REGS_RCX];
2842 regs->rdx = vcpu->arch.regs[VCPU_REGS_RDX];
2843 regs->rsi = vcpu->arch.regs[VCPU_REGS_RSI];
2844 regs->rdi = vcpu->arch.regs[VCPU_REGS_RDI];
2845 regs->rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2846 regs->rbp = vcpu->arch.regs[VCPU_REGS_RBP];
b6c7a5dc 2847#ifdef CONFIG_X86_64
ad312c7c
ZX		 2848 regs->r8 = vcpu->arch.regs[VCPU_REGS_R8];
2849 regs->r9 = vcpu->arch.regs[VCPU_REGS_R9];
2850 regs->r10 = vcpu->arch.regs[VCPU_REGS_R10];
2851 regs->r11 = vcpu->arch.regs[VCPU_REGS_R11];
2852 regs->r12 = vcpu->arch.regs[VCPU_REGS_R12];
2853 regs->r13 = vcpu->arch.regs[VCPU_REGS_R13];
2854 regs->r14 = vcpu->arch.regs[VCPU_REGS_R14];
2855 regs->r15 = vcpu->arch.regs[VCPU_REGS_R15];
b6c7a5dc
HB		 2856#endif
2857
ad312c7c 2858 regs->rip = vcpu->arch.rip;
b6c7a5dc
HB		 2859 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
2860
2861 /*
2862 * Don't leak debug flags in case they were set for guest debugging
2863 */
2864 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
2865 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2866
2867 vcpu_put(vcpu);
2868
2869 return 0;
2870}
2871
2872int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
2873{
2874 vcpu_load(vcpu);
2875
ad312c7c
ZX		 2876 vcpu->arch.regs[VCPU_REGS_RAX] = regs->rax;
2877 vcpu->arch.regs[VCPU_REGS_RBX] = regs->rbx;
2878 vcpu->arch.regs[VCPU_REGS_RCX] = regs->rcx;
2879 vcpu->arch.regs[VCPU_REGS_RDX] = regs->rdx;
2880 vcpu->arch.regs[VCPU_REGS_RSI] = regs->rsi;
2881 vcpu->arch.regs[VCPU_REGS_RDI] = regs->rdi;
2882 vcpu->arch.regs[VCPU_REGS_RSP] = regs->rsp;
2883 vcpu->arch.regs[VCPU_REGS_RBP] = regs->rbp;
b6c7a5dc 2884#ifdef CONFIG_X86_64
ad312c7c
ZX		 2885 vcpu->arch.regs[VCPU_REGS_R8] = regs->r8;
2886 vcpu->arch.regs[VCPU_REGS_R9] = regs->r9;
2887 vcpu->arch.regs[VCPU_REGS_R10] = regs->r10;
2888 vcpu->arch.regs[VCPU_REGS_R11] = regs->r11;
2889 vcpu->arch.regs[VCPU_REGS_R12] = regs->r12;
2890 vcpu->arch.regs[VCPU_REGS_R13] = regs->r13;
2891 vcpu->arch.regs[VCPU_REGS_R14] = regs->r14;
2892 vcpu->arch.regs[VCPU_REGS_R15] = regs->r15;
b6c7a5dc
HB		 2893#endif
2894
ad312c7c 2895 vcpu->arch.rip = regs->rip;
b6c7a5dc
HB		 2896 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
2897
2898 kvm_x86_ops->decache_regs(vcpu);
2899
2900 vcpu_put(vcpu);
2901
2902 return 0;
2903}
2904
2905static void get_segment(struct kvm_vcpu *vcpu,
2906 struct kvm_segment *var, int seg)
2907{
14af3f3c 2908 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 2909}
2910
2911void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2912{
2913 struct kvm_segment cs;
2914
2915 get_segment(vcpu, &cs, VCPU_SREG_CS);
2916 *db = cs.db;
2917 *l = cs.l;
2918}
2919EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
2920
2921int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
2922 struct kvm_sregs *sregs)
2923{
2924 struct descriptor_table dt;
2925 int pending_vec;
2926
2927 vcpu_load(vcpu);
2928
2929 get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
2930 get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
2931 get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
2932 get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
2933 get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
2934 get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
2935
2936 get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
2937 get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
2938
2939 kvm_x86_ops->get_idt(vcpu, &dt);
2940 sregs->idt.limit = dt.limit;
2941 sregs->idt.base = dt.base;
2942 kvm_x86_ops->get_gdt(vcpu, &dt);
2943 sregs->gdt.limit = dt.limit;
2944 sregs->gdt.base = dt.base;
2945
2946 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 2947 sregs->cr0 = vcpu->arch.cr0;
2948 sregs->cr2 = vcpu->arch.cr2;
2949 sregs->cr3 = vcpu->arch.cr3;
2950 sregs->cr4 = vcpu->arch.cr4;
b6c7a5dc 2951 sregs->cr8 = get_cr8(vcpu);
ad312c7c 2952 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 2953 sregs->apic_base = kvm_get_apic_base(vcpu);
2954
2955 if (irqchip_in_kernel(vcpu->kvm)) {
2956 memset(sregs->interrupt_bitmap, 0,
2957 sizeof sregs->interrupt_bitmap);
2958 pending_vec = kvm_x86_ops->get_irq(vcpu);
2959 if (pending_vec >= 0)
2960 set_bit(pending_vec,
2961 (unsigned long *)sregs->interrupt_bitmap);
2962 } else
ad312c7c 2963 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 2964 sizeof sregs->interrupt_bitmap);
2965
2966 vcpu_put(vcpu);
2967
2968 return 0;
2969}
2970
2971static void set_segment(struct kvm_vcpu *vcpu,
2972 struct kvm_segment *var, int seg)
2973{
14af3f3c 2974 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 2975}
2976
2977int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
2978 struct kvm_sregs *sregs)
2979{
2980 int mmu_reset_needed = 0;
2981 int i, pending_vec, max_bits;
2982 struct descriptor_table dt;
2983
2984 vcpu_load(vcpu);
2985
2986 dt.limit = sregs->idt.limit;
2987 dt.base = sregs->idt.base;
2988 kvm_x86_ops->set_idt(vcpu, &dt);
2989 dt.limit = sregs->gdt.limit;
2990 dt.base = sregs->gdt.base;
2991 kvm_x86_ops->set_gdt(vcpu, &dt);
2992
ad312c7c
ZX		 2993 vcpu->arch.cr2 = sregs->cr2;
2994 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
2995 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc
HB		 2996
2997 set_cr8(vcpu, sregs->cr8);
2998
ad312c7c 2999 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3000 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3001 kvm_set_apic_base(vcpu, sregs->apic_base);
3002
3003 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3004
ad312c7c 3005 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3006 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3007 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3008
ad312c7c 3009 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3010 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3011 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3012 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3013
3014 if (mmu_reset_needed)
3015 kvm_mmu_reset_context(vcpu);
3016
3017 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3018 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3019 sizeof vcpu->arch.irq_pending);
3020 vcpu->arch.irq_summary = 0;
3021 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3022 if (vcpu->arch.irq_pending[i])
3023 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3024 } else {
3025 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3026 pending_vec = find_first_bit(
3027 (const unsigned long *)sregs->interrupt_bitmap,
3028 max_bits);
3029 /* Only pending external irq is handled here */
3030 if (pending_vec < max_bits) {
3031 kvm_x86_ops->set_irq(vcpu, pending_vec);
3032 pr_debug("Set back pending irq %d\n",
3033 pending_vec);
3034 }
3035 }
3036
3037 set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3038 set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3039 set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3040 set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3041 set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3042 set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3043
3044 set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3045 set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3046
3047 vcpu_put(vcpu);
3048
3049 return 0;
3050}
3051
3052int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3053 struct kvm_debug_guest *dbg)
3054{
3055 int r;
3056
3057 vcpu_load(vcpu);
3058
3059 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3060
3061 vcpu_put(vcpu);
3062
3063 return r;
3064}
3065
d0752060
HB		 3066/*
3067 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3068 * we have asm/x86/processor.h
3069 */
3070struct fxsave {
3071 u16 cwd;
3072 u16 swd;
3073 u16 twd;
3074 u16 fop;
3075 u64 rip;
3076 u64 rdp;
3077 u32 mxcsr;
3078 u32 mxcsr_mask;
3079 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3080#ifdef CONFIG_X86_64
3081 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3082#else
3083 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3084#endif
3085};
3086
8b006791
ZX		 3087/*
3088 * Translate a guest virtual address to a guest physical address.
3089 */
3090int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3091 struct kvm_translation *tr)
3092{
3093 unsigned long vaddr = tr->linear_address;
3094 gpa_t gpa;
3095
3096 vcpu_load(vcpu);
72dc67a6 3097 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3098 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3099 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3100 tr->physical_address = gpa;
3101 tr->valid = gpa != UNMAPPED_GVA;
3102 tr->writeable = 1;
3103 tr->usermode = 0;
8b006791
ZX		 3104 vcpu_put(vcpu);
3105
3106 return 0;
3107}
3108
d0752060
HB		 3109int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3110{
ad312c7c 3111 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3112
3113 vcpu_load(vcpu);
3114
3115 memcpy(fpu->fpr, fxsave->st_space, 128);
3116 fpu->fcw = fxsave->cwd;
3117 fpu->fsw = fxsave->swd;
3118 fpu->ftwx = fxsave->twd;
3119 fpu->last_opcode = fxsave->fop;
3120 fpu->last_ip = fxsave->rip;
3121 fpu->last_dp = fxsave->rdp;
3122 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3123
3124 vcpu_put(vcpu);
3125
3126 return 0;
3127}
3128
3129int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3130{
ad312c7c 3131 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3132
3133 vcpu_load(vcpu);
3134
3135 memcpy(fxsave->st_space, fpu->fpr, 128);
3136 fxsave->cwd = fpu->fcw;
3137 fxsave->swd = fpu->fsw;
3138 fxsave->twd = fpu->ftwx;
3139 fxsave->fop = fpu->last_opcode;
3140 fxsave->rip = fpu->last_ip;
3141 fxsave->rdp = fpu->last_dp;
3142 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3143
3144 vcpu_put(vcpu);
3145
3146 return 0;
3147}
3148
3149void fx_init(struct kvm_vcpu *vcpu)
3150{
3151 unsigned after_mxcsr_mask;
3152
3153 /* Initialize guest FPU by resetting ours and saving into guest's */
3154 preempt_disable();
ad312c7c 3155 fx_save(&vcpu->arch.host_fx_image);
d0752060 3156 fpu_init();
ad312c7c
ZX		 3157 fx_save(&vcpu->arch.guest_fx_image);
3158 fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3159 preempt_enable();
3160
ad312c7c 3161 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3162 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3163 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3164 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3165 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3166}
3167EXPORT_SYMBOL_GPL(fx_init);
3168
3169void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3170{
3171 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3172 return;
3173
3174 vcpu->guest_fpu_loaded = 1;
ad312c7c
ZX		 3175 fx_save(&vcpu->arch.host_fx_image);
3176 fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3177}
3178EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3179
3180void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3181{
3182 if (!vcpu->guest_fpu_loaded)
3183 return;
3184
3185 vcpu->guest_fpu_loaded = 0;
ad312c7c
ZX		 3186 fx_save(&vcpu->arch.guest_fx_image);
3187 fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3188 ++vcpu->stat.fpu_reload;
d0752060
HB		 3189}
3190EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3191
3192void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3193{
3194 kvm_x86_ops->vcpu_free(vcpu);
3195}
3196
3197struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3198 unsigned int id)
3199{
26e5215f
AK		 3200 return kvm_x86_ops->vcpu_create(kvm, id);
3201}
e9b11c17 3202
26e5215f
AK		 3203int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3204{
3205 int r;
e9b11c17
ZX		 3206
3207 /* We do fxsave: this must be aligned. */
ad312c7c 3208 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 3209
3210 vcpu_load(vcpu);
3211 r = kvm_arch_vcpu_reset(vcpu);
3212 if (r == 0)
3213 r = kvm_mmu_setup(vcpu);
3214 vcpu_put(vcpu);
3215 if (r < 0)
3216 goto free_vcpu;
3217
26e5215f 3218 return 0;
e9b11c17
ZX		 3219free_vcpu:
3220 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3221 return r;
e9b11c17
ZX		 3222}
3223
d40ccc62 3224void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3225{
3226 vcpu_load(vcpu);
3227 kvm_mmu_unload(vcpu);
3228 vcpu_put(vcpu);
3229
3230 kvm_x86_ops->vcpu_free(vcpu);
3231}
3232
3233int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
3234{
3235 return kvm_x86_ops->vcpu_reset(vcpu);
3236}
3237
3238void kvm_arch_hardware_enable(void *garbage)
3239{
3240 kvm_x86_ops->hardware_enable(garbage);
3241}
3242
3243void kvm_arch_hardware_disable(void *garbage)
3244{
3245 kvm_x86_ops->hardware_disable(garbage);
3246}
3247
3248int kvm_arch_hardware_setup(void)
3249{
3250 return kvm_x86_ops->hardware_setup();
3251}
3252
3253void kvm_arch_hardware_unsetup(void)
3254{
3255 kvm_x86_ops->hardware_unsetup();
3256}
3257
3258void kvm_arch_check_processor_compat(void *rtn)
3259{
3260 kvm_x86_ops->check_processor_compatibility(rtn);
3261}
3262
3263int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
3264{
3265 struct page *page;
3266 struct kvm *kvm;
3267 int r;
3268
3269 BUG_ON(vcpu->kvm == NULL);
3270 kvm = vcpu->kvm;
3271
ad312c7c 3272 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 3273 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
ad312c7c 3274 vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
e9b11c17 3275 else
ad312c7c 3276 vcpu->arch.mp_state = VCPU_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 3277
3278 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
3279 if (!page) {
3280 r = -ENOMEM;
3281 goto fail;
3282 }
ad312c7c 3283 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 3284
3285 r = kvm_mmu_create(vcpu);
3286 if (r < 0)
3287 goto fail_free_pio_data;
3288
3289 if (irqchip_in_kernel(kvm)) {
3290 r = kvm_create_lapic(vcpu);
3291 if (r < 0)
3292 goto fail_mmu_destroy;
3293 }
3294
3295 return 0;
3296
3297fail_mmu_destroy:
3298 kvm_mmu_destroy(vcpu);
3299fail_free_pio_data:
ad312c7c 3300 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 3301fail:
3302 return r;
3303}
3304
3305void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
3306{
3307 kvm_free_lapic(vcpu);
3308 kvm_mmu_destroy(vcpu);
ad312c7c 3309 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 3310}
d19a9cd2
ZX		 3311
3312struct kvm *kvm_arch_create_vm(void)
3313{
3314 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
3315
3316 if (!kvm)
3317 return ERR_PTR(-ENOMEM);
3318
f05e70ac 3319 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
d19a9cd2
ZX		 3320
3321 return kvm;
3322}
3323
3324static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
3325{
3326 vcpu_load(vcpu);
3327 kvm_mmu_unload(vcpu);
3328 vcpu_put(vcpu);
3329}
3330
3331static void kvm_free_vcpus(struct kvm *kvm)
3332{
3333 unsigned int i;
3334
3335 /*
3336 * Unpin any mmu pages first.
3337 */
3338 for (i = 0; i < KVM_MAX_VCPUS; ++i)
3339 if (kvm->vcpus[i])
3340 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
3341 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
3342 if (kvm->vcpus[i]) {
3343 kvm_arch_vcpu_free(kvm->vcpus[i]);
3344 kvm->vcpus[i] = NULL;
3345 }
3346 }
3347
3348}
3349
3350void kvm_arch_destroy_vm(struct kvm *kvm)
3351{
d7deeeb0
ZX		 3352 kfree(kvm->arch.vpic);
3353 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 3354 kvm_free_vcpus(kvm);
3355 kvm_free_physmem(kvm);
3356 kfree(kvm);
3357}
0de10343
ZX		 3358
3359int kvm_arch_set_memory_region(struct kvm *kvm,
3360 struct kvm_userspace_memory_region *mem,
3361 struct kvm_memory_slot old,
3362 int user_alloc)
3363{
3364 int npages = mem->memory_size >> PAGE_SHIFT;
3365 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
3366
3367 /*To keep backward compatibility with older userspace,
3368 *x86 needs to hanlde !user_alloc case.
3369 */
3370 if (!user_alloc) {
3371 if (npages && !old.rmap) {
72dc67a6 3372 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3373 memslot->userspace_addr = do_mmap(NULL, 0,
3374 npages * PAGE_SIZE,
3375 PROT_READ | PROT_WRITE,
3376 MAP_SHARED | MAP_ANONYMOUS,
3377 0);
72dc67a6 3378 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3379
3380 if (IS_ERR((void *)memslot->userspace_addr))
3381 return PTR_ERR((void *)memslot->userspace_addr);
3382 } else {
3383 if (!old.user_alloc && old.rmap) {
3384 int ret;
3385
72dc67a6 3386 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3387 ret = do_munmap(current->mm, old.userspace_addr,
3388 old.npages * PAGE_SIZE);
72dc67a6 3389 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3390 if (ret < 0)
3391 printk(KERN_WARNING
3392 "kvm_vm_ioctl_set_memory_region: "
3393 "failed to munmap memory\n");
3394 }
3395 }
3396 }
3397
f05e70ac 3398 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 3399 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
3400 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
3401 }
3402
3403 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3404 kvm_flush_remote_tlbs(kvm);
3405
3406 return 0;
3407}
1d737c8a
ZX		 3408
3409int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
3410{
3411 return vcpu->arch.mp_state == VCPU_MP_STATE_RUNNABLE
3412 || vcpu->arch.mp_state == VCPU_MP_STATE_SIPI_RECEIVED;
3413}
5736199a
ZX		 3414
3415static void vcpu_kick_intr(void *info)
3416{
3417#ifdef DEBUG
3418 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
3419 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
3420#endif
3421}
3422
3423void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
3424{
3425 int ipi_pcpu = vcpu->cpu;
3426
3427 if (waitqueue_active(&vcpu->wq)) {
3428 wake_up_interruptible(&vcpu->wq);
3429 ++vcpu->stat.halt_wakeup;
3430 }
3431 if (vcpu->guest_mode)
3432 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0, 0);
3433}
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